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Fri, 17 Apr 2026 07:49:58 -0700 (PDT) From: Chao Liu To: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Paolo Savini , Nicholas Piggin , Eric Biggers , Daniel Henrique Barboza Subject: [PATCH v10 1/2] target/riscv: Use tcg nodes for strided vector ld/st generation Date: Fri, 17 Apr 2026 22:49:31 +0800 Message-ID: <8ab885ce490cede31b8e9e7f6a67295c1aa353f7.1776437127.git.chao.liu.zevorn@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::a41; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-vk1-xa41.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1776437435620158500 Content-Type: text/plain; charset="utf-8" This commit improves the performance of QEMU when emulating strided vector loads and stores by substituting the call for the helper function with the generation of equivalent TCG operations. PS: An implementation is permitted to cause an illegal instruction if vstart is not 0 and it is set to a value that can not be produced implicitly by the implementation, but memory accesses will generally always need to deal with page faults. So, if a strided vector memory access instruction has non-zero vstart, check it through vlse/vsse helpers function. Signed-off-by: Paolo Savini Signed-off-by: Chao Liu Signed-off-by: Nicholas Piggin Tested-by: Eric Biggers Reviewed-by: Daniel Henrique Barboza --- target/riscv/insn_trans/trans_rvv.c.inc | 354 ++++++++++++++++++++++-- 1 file changed, 337 insertions(+), 17 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 5b72926b3c..4cf3643cbd 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -16,6 +16,7 @@ */ #include "tcg/tcg-op-gvec.h" #include "tcg/tcg-gvec-desc.h" +#include "tcg/tcg-temp-internal.h" #include "internals.h" =20 static inline bool is_overlapped(const int8_t astart, int8_t asize, @@ -872,15 +873,290 @@ static bool st_us_mask_check(DisasContext *s, arg_vs= m_v *a, uint8_t eew) GEN_VEXT_TRANS(vlm_v, MO_8, vlm_v, ld_us_mask_op, ld_us_mask_check) GEN_VEXT_TRANS(vsm_v, MO_8, vsm_v, st_us_mask_op, st_us_mask_check) =20 +/* + * MAXSZ returns the maximum vector size can be operated in bytes, + * which is used in GVEC IR when vl_eq_vlmax flag is set to true + * to accelerate vector operation. + */ +static inline uint32_t MAXSZ(DisasContext *s) +{ + int max_sz =3D s->cfg_ptr->vlenb << 3; + return max_sz >> (3 - s->lmul); +} + +static inline uint32_t get_log2(uint32_t a) +{ + assert(is_power_of_2(a)); + return ctz32(a); +} + +typedef void gen_tl_ldst(TCGv, TCGv_ptr, tcg_target_long); + +static void gen_ldst_vreg(DisasContext *s, TCGv_i64 dest_offs, TCGv_i64 ad= dr, + gen_tl_ldst *ld_fn, gen_tl_ldst *st_fn, bool is_= load) +{ + MemOp atomicity =3D (s->sew =3D=3D 0) ? MO_ATOM_NONE : MO_ATOM_IFALIGN= _PAIR; + TCGv_ptr dest_ptr =3D tcg_temp_new_ptr(); + TCGv_i64 vreg =3D tcg_temp_new_i64(); + tcg_gen_trunc_i64_ptr(dest_ptr, dest_offs); + + if (is_load) { + tcg_gen_qemu_ld_tl(vreg, addr, s->mem_idx, MO_LE | s->sew | atomic= ity); + st_fn(vreg, dest_ptr, 0); + } else { + ld_fn(vreg, dest_ptr, 0); + tcg_gen_qemu_st_tl(vreg, addr, s->mem_idx, MO_LE | s->sew | atomic= ity); + } + tcg_temp_free_ptr(dest_ptr); + tcg_temp_free_i64(vreg); +} + +/* + * Check whether the i bit of the mask is 0 or 1. + * + * static inline int vext_elem_mask(void *v0, int index) + * { + * int idx =3D index / 64; + * int pos =3D index % 64; + * return (((uint64_t *)v0)[idx] >> pos) & 1; + * } + * + * And + * + * if (vext_elem_mask(v0, i) !=3D 0) { + * goto label; + * } + */ +static void gen_check_vext_elem_mask(DisasContext *s, TCGLabel *label, + TCGv_i64 mask_offs) +{ + TCGv_i64 temp =3D tcg_temp_new_i64(); + TCGv_ptr ptr =3D tcg_temp_new_ptr(); + TCGv_i64 elem =3D tcg_temp_new_i64(); + + tcg_gen_shri_tl(temp, mask_offs, 3); + tcg_gen_trunc_i64_ptr(ptr, temp); + tcg_gen_add_ptr(ptr, ptr, tcg_env); + + tcg_gen_ld8u_i64(elem, ptr, 0); + tcg_gen_andi_tl(temp, mask_offs, 7); + tcg_gen_shr_tl(elem, elem, temp); + tcg_gen_brcond_i64(TCG_COND_TSTNE, elem, tcg_constant_i64(1), label); + + tcg_temp_free_i64(temp); + tcg_temp_free_ptr(ptr); + tcg_temp_free_i64(elem); +} + +static void gen_vext_set_elems_1s(TCGv dest, TCGv_i64 mask_offs, int sew, + gen_tl_ldst *st_fn, bool is_load) +{ + if (is_load) { + TCGv_ptr ptr =3D tcg_temp_new_ptr(); + tcg_gen_shli_tl(mask_offs, mask_offs, sew); + tcg_gen_add_tl(mask_offs, mask_offs, dest); + tcg_gen_trunc_i64_ptr(ptr, mask_offs); + st_fn(tcg_constant_tl(-1), ptr, 0); + tcg_temp_free_ptr(ptr); + } +} + +/* + * Simulate the strided load/store main loop: + * + * for (i =3D env->vstart; i < env->vl; env->vstart =3D ++i) { + * k =3D 0; + * while (k < nf) { + * if (!vm && !vext_elem_mask(v0, i)) { + * vext_set_elems_1s(vd, vma, (i + k * max_elems) * esz, + * (i + k * max_elems + 1) * esz); + * k++; + * continue; + * } + * target_ulong addr =3D base + stride * i + (k << log2_esz); + * ldst(env, adjust_addr(env, addr), i + k * max_elems, vd, ra); + * k++; + * } + * } + */ +static void gen_ldst_stride_main_loop(DisasContext *s, TCGv dest, uint32_t= rs1, + uint32_t rs2, uint32_t vm, uint32_t = nf, + gen_tl_ldst *ld_fn, gen_tl_ldst *st_= fn, + bool is_load) +{ + TCGv_i64 addr =3D tcg_temp_new_i64(); + TCGv base =3D get_gpr(s, rs1, EXT_NONE); + TCGv stride =3D get_gpr(s, rs2, EXT_NONE); + + TCGv i =3D tcg_temp_new(); + TCGv i_esz =3D tcg_temp_new(); + TCGv k =3D tcg_temp_new(); + TCGv k_esz =3D tcg_temp_new(); + TCGv k_max =3D tcg_temp_new(); + TCGv_i64 mask_offs =3D tcg_temp_new_i64(); + TCGv_i64 dest_offs =3D tcg_temp_new_i64(); + TCGv_i64 stride_offs =3D tcg_temp_new_i64(); + + uint32_t max_elems =3D MAXSZ(s) >> s->sew; + + TCGLabel *start =3D gen_new_label(); + TCGLabel *end =3D gen_new_label(); + TCGLabel *start_k =3D gen_new_label(); + TCGLabel *inc_k =3D gen_new_label(); + TCGLabel *end_k =3D gen_new_label(); + + /* Start of outer loop. */ + tcg_gen_mov_tl(i, cpu_vstart); + gen_set_label(start); + tcg_gen_brcond_tl(TCG_COND_GE, i, cpu_vl, end); + tcg_gen_shli_tl(i_esz, i, s->sew); + + /* Start of inner loop. */ + tcg_gen_movi_tl(k, 0); + gen_set_label(start_k); + tcg_gen_brcond_tl(TCG_COND_GE, k, tcg_constant_tl(nf), end_k); + + /* + * If we are in mask agnostic regime and the operation is not unmasked= we + * set the inactive elements to 1. + */ + if (!vm && s->vma) { + TCGLabel *active_element =3D gen_new_label(); + /* (i + k * max_elems) * esz */ + tcg_gen_shli_tl(mask_offs, k, get_log2(max_elems << s->sew)); + tcg_gen_add_tl(mask_offs, mask_offs, i_esz); + + /* + * Check whether the i bit of the mask is 0 or 1. + * If it is 0, set masked-off elements; + * otherwise, directly load/store the vector register. + */ + gen_check_vext_elem_mask(s, active_element, mask_offs); + + /* + * Set masked-off elements in the destination vector register to 1= s. + * Store instructions simply skip this bit as memory ops access me= mory + * only for active elements. + */ + gen_vext_set_elems_1s(dest, mask_offs, s->sew, st_fn, is_load); + + tcg_gen_br(inc_k); + gen_set_label(active_element); + } + + /* + * The element is active, calculate the address with stride: + * target_ulong addr =3D base + stride * i + (k << log2_esz); + */ + tcg_gen_mul_tl(stride_offs, stride, i); + tcg_gen_shli_tl(k_esz, k, s->sew); + tcg_gen_add_tl(stride_offs, stride_offs, k_esz); + tcg_gen_add_tl(addr, base, stride_offs); + + /* Calculate the offset in the dst/src vector register. */ + tcg_gen_shli_tl(k_max, k, get_log2(max_elems)); + tcg_gen_add_tl(dest_offs, i, k_max); + tcg_gen_shli_tl(dest_offs, dest_offs, s->sew); + tcg_gen_add_tl(dest_offs, dest_offs, dest); + + /* Load/Store vector register. */ + gen_ldst_vreg(s, dest_offs, addr, ld_fn, st_fn, is_load); + + /* + * We don't execute the load/store above if the element was inactive. + * We jump instead directly to incrementing k and continuing the loop. + */ + if (!vm && s->vma) { + gen_set_label(inc_k); + } + tcg_gen_addi_tl(k, k, 1); + tcg_gen_br(start_k); + + /* End of the inner loop. */ + gen_set_label(end_k); + + tcg_gen_addi_tl(i, i, 1); + tcg_gen_mov_tl(cpu_vstart, i); + tcg_gen_br(start); + + /* End of the outer loop. */ + gen_set_label(end); + + return; +} + +/* + * Set the tail bytes of the strided loads/stores to 1: + * + * for (k =3D 0; k < nf; ++k) { + * cnt =3D (k * max_elems + vl) * esz; + * tot =3D (k * max_elems + max_elems) * esz; + * for (i =3D cnt; i < tot; i +=3D esz) { + * store_1s(-1, vd[vl+i]); + * } + * } + */ +static void gen_ldst_stride_tail_loop(DisasContext *s, TCGv dest, uint32_t= nf, + gen_tl_ldst *st_fn) +{ + TCGv i =3D tcg_temp_new(); + TCGv k =3D tcg_temp_new(); + TCGv tail_cnt =3D tcg_temp_new(); + TCGv tail_tot =3D tcg_temp_new(); + TCGv tail_addr =3D tcg_temp_new(); + + TCGLabel *start =3D gen_new_label(); + TCGLabel *end =3D gen_new_label(); + TCGLabel *start_i =3D gen_new_label(); + TCGLabel *end_i =3D gen_new_label(); + + uint32_t max_elems_b =3D MAXSZ(s); + uint32_t esz =3D 1 << s->sew; + + /* Start of the outer loop. */ + tcg_gen_movi_tl(k, 0); + tcg_gen_shli_tl(tail_cnt, cpu_vl, s->sew); + tcg_gen_movi_tl(tail_tot, max_elems_b); + tcg_gen_add_tl(tail_addr, dest, tail_cnt); + gen_set_label(start); + tcg_gen_brcond_tl(TCG_COND_GE, k, tcg_constant_tl(nf), end); + + /* Start of the inner loop. */ + tcg_gen_mov_tl(i, tail_cnt); + gen_set_label(start_i); + tcg_gen_brcond_tl(TCG_COND_GE, i, tail_tot, end_i); + + /* store_1s(-1, vd[vl+i]); */ + st_fn(tcg_constant_tl(-1), (TCGv_ptr)tail_addr, 0); + tcg_gen_addi_tl(tail_addr, tail_addr, esz); + tcg_gen_addi_tl(i, i, esz); + tcg_gen_br(start_i); + + /* End of the inner loop. */ + gen_set_label(end_i); + + /* Update the counts */ + tcg_gen_addi_tl(tail_cnt, tail_cnt, max_elems_b); + tcg_gen_addi_tl(tail_tot, tail_cnt, max_elems_b); + tcg_gen_addi_tl(k, k, 1); + tcg_gen_br(start); + + /* End of the outer loop. */ + gen_set_label(end); + + return; +} + /* *** stride load and store */ typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv, TCGv, TCGv_env, TCGv_i32); =20 -static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, - uint32_t data, gen_helper_ldst_stride *fn, - DisasContext *s) +static +bool gen_call_helper_ldst_stride(uint32_t vd, uint32_t rs1, uint32_t rs2, + uint32_t data, gen_helper_ldst_stride *fn, + DisasContext *s) { TCGv_ptr dest, mask; TCGv base, stride; @@ -904,11 +1180,66 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t = rs1, uint32_t rs2, return true; } =20 +static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, + uint32_t data, gen_helper_ldst_stride *fn, + DisasContext *s, bool is_load) +{ + if (!s->vstart_eq_zero) { + /* vstart !=3D 0 helper slowpath */ + return gen_call_helper_ldst_stride(vd, rs1, rs2, data, fn, s); + } + + TCGv dest =3D tcg_temp_new(); + + uint32_t nf =3D FIELD_EX32(data, VDATA, NF); + uint32_t vm =3D FIELD_EX32(data, VDATA, VM); + + /* Destination register and mask register */ + tcg_gen_addi_tl(dest, (TCGv)tcg_env, vreg_ofs(s, vd)); + + /* + * Select the appropriate load/store to retrieve data from the vector + * register given a specific sew. + */ + static gen_tl_ldst * const ld_fns[4] =3D { + tcg_gen_ld8u_tl, tcg_gen_ld16u_tl, + tcg_gen_ld32u_tl, tcg_gen_ld_tl + }; + + static gen_tl_ldst * const st_fns[4] =3D { + tcg_gen_st8_tl, tcg_gen_st16_tl, + tcg_gen_st32_tl, tcg_gen_st_tl + }; + + gen_tl_ldst *ld_fn =3D ld_fns[s->sew]; + gen_tl_ldst *st_fn =3D st_fns[s->sew]; + + if (ld_fn =3D=3D NULL || st_fn =3D=3D NULL) { + return false; + } + + mark_vs_dirty(s); + + gen_ldst_stride_main_loop(s, dest, rs1, rs2, vm, nf, ld_fn, st_fn, is_= load); + + tcg_gen_movi_tl(cpu_vstart, 0); + + /* + * Set the tail bytes to 1 if tail agnostic: + */ + if (s->vta !=3D 0 && is_load) { + gen_ldst_stride_tail_loop(s, dest, nf, st_fn); + } + + finalize_rvv_inst(s); + return true; +} + static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) { uint32_t data =3D 0; gen_helper_ldst_stride *fn; - static gen_helper_ldst_stride * const fns[4] =3D { + static gen_helper_ldst_stride *const fns[4] =3D { gen_helper_vlse8_v, gen_helper_vlse16_v, gen_helper_vlse32_v, gen_helper_vlse64_v }; @@ -924,7 +1255,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a= , uint8_t eew) data =3D FIELD_DP32(data, VDATA, NF, a->nf); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); data =3D FIELD_DP32(data, VDATA, VMA, s->vma); - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); } =20 static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) @@ -958,7 +1289,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a= , uint8_t eew) return false; } =20 - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } =20 static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) @@ -1281,17 +1612,6 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, int8_t, 8, false) *** Vector Integer Arithmetic Instructions */ =20 -/* - * MAXSZ returns the maximum vector size can be operated in bytes, - * which is used in GVEC IR when vl_eq_vlmax flag is set to true - * to accelerate vector operation. - */ -static inline uint32_t MAXSZ(DisasContext *s) -{ - int max_sz =3D s->cfg_ptr->vlenb * 8; - return max_sz >> (3 - s->lmul); -} - static bool opivv_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && --=20 2.53.0 From nobody Tue Apr 21 14:36:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 17 Apr 2026 07:50:04 -0700 (PDT) From: Chao Liu To: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Nicholas Piggin , Eric Biggers Subject: [PATCH v10 2/2] tests/tcg/riscv64: Add test for vlsseg8e32 instruction Date: Fri, 17 Apr 2026 22:49:32 +0800 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::a44; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-vk1-xa44.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FREEMAIL_REPLY=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1776437507375154100 Content-Type: text/plain; charset="utf-8" This case, it copied 64 bytes from a0 to a1 with vlsseg8e32. Signed-off-by: Chao Liu Signed-off-by: Nicholas Piggin Tested-by: Eric Biggers --- tests/tcg/riscv64/Makefile.softmmu-target | 7 +- tests/tcg/riscv64/test-vlsseg8e32.S | 107 ++++++++++++++++++++++ 2 files changed, 113 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/riscv64/test-vlsseg8e32.S diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/= Makefile.softmmu-target index 82be8a2c91..05c8f851e0 100644 --- a/tests/tcg/riscv64/Makefile.softmmu-target +++ b/tests/tcg/riscv64/Makefile.softmmu-target @@ -7,7 +7,7 @@ VPATH +=3D $(TEST_SRC) =20 LINK_SCRIPT =3D $(TEST_SRC)/semihost.ld LDFLAGS =3D -T $(LINK_SCRIPT) -CFLAGS +=3D -g -Og +CFLAGS +=3D -march=3Drv64gcv -mabi=3Dlp64d -g -Og =20 %.o: %.S $(CC) $(CFLAGS) $< -Wa,--noexecstack -c -o $@ @@ -41,5 +41,10 @@ comma:=3D , run-test-crc32: test-crc32 $(call run-test, $<, $(QEMU) -cpu rv64$(comma)xlrbr=3Dtrue $(QEMU_OPTS)$<) =20 +EXTRA_RUNS +=3D run-vlsseg8e32 +run-vlsseg8e32: QEMU_OPTS :=3D -cpu rv64,v=3Dtrue $(QEMU_OPTS) +run-vlsseg8e32: test-vlsseg8e32 + $(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<) + # We don't currently support the multiarch system tests undefine MULTIARCH_TESTS diff --git a/tests/tcg/riscv64/test-vlsseg8e32.S b/tests/tcg/riscv64/test-v= lsseg8e32.S new file mode 100644 index 0000000000..bbc79d5e8d --- /dev/null +++ b/tests/tcg/riscv64/test-vlsseg8e32.S @@ -0,0 +1,107 @@ +# +# QEMU RISC-V Vector Strided Load Instruction testcase +# +# Copyright (c) 2025 Chao Liu chao.liu@yeah.net +# +# SPDX-License-Identifier: GPL-2.0-or-later +# + .option norvc + + .section .data + .align 4 +source_data: + .asciz "Test the vssseg8e32 insn by copy 64b and verifying correctness." + .equ source_len, 64 + + .text + .global _start +_start: + lla t0, trap + csrw mtvec, t0 + +enable_rvv: + + li x15, 0x800000000024112d + csrw 0x301, x15 + li x1, 0x2200 + csrr x2, mstatus + or x2, x2, x1 + csrw mstatus, x2 + +rvv_test_func: + la a0, source_data + li a1, 0x80020000 + vsetivli zero, 1, e32, m1, ta, ma + li t0, 64 + + vlsseg8e32.v v0, (a0), t0 + addi a0, a0, 32 + vlsseg8e32.v v8, (a0), t0 + + vssseg8e32.v v0, (a1), t0 + addi a1, a1, 32 + vssseg8e32.v v8, (a1), t0 + +compare_start: + la a0, source_data + li a1, 0x80020000 + li t0, 0 + li t1, source_len + +compare_loop: + # when t0 >=3D len, compare end + bge t0, t1, compare_done + + lb t2, 0(a0) + lb t3, 0(a1) + bne t2, t3, compare_fail + + addi a0, a0, 1 + addi a1, a1, 1 + addi t0, t0, 1 + j compare_loop + +compare_done: + # compare ok, return 0 + li a0, 0 + j _exit + +compare_fail: + # compare failed, return 2 + li a0, 2 + j _exit + +trap: + # When an instruction traps, compare it to the insn in memory. + csrr t0, mepc + csrr t1, mtval + lwu t2, 0(t0) + bne t1, t2, fail + + # Skip the insn and continue. + addi t0, t0, 4 + csrw mepc, t0 + mret + +fail: + li a0, 1 + +# Exit code in a0 +_exit: + lla a1, semiargs + li t0, 0x20026 # ADP_Stopped_ApplicationExit + sd t0, 0(a1) + sd a0, 8(a1) + li a0, 0x20 # TARGET_SYS_EXIT_EXTENDED + + # Semihosting call sequence + .balign 16 + slli zero, zero, 0x1f + ebreak + srai zero, zero, 0x7 + j . + + .data + .balign 16 +semiargs: + .space 16 --=20 2.53.0