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Fri, 10 Apr 2026 10:56:08 -0700 (PDT) X-Received: by 2002:a05:7022:6282:b0:12a:796b:7cf1 with SMTP id a92af1059eb24-12c34edb8f8mr2729669c88.23.1775843767887; Fri, 10 Apr 2026 10:56:07 -0700 (PDT) From: Matheus Tavares Bernardino To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng, brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com, marco.liebel@oss.qualcomm.com, philmd@linaro.org, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com, Pierrick Bouvier , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v4 01/16] tests/docker: Update hexagon cross toolchain to 22.1.0 Date: Fri, 10 Apr 2026 10:55:49 -0700 Message-Id: <1440dd86da7dfcf88037049a8868cbcd05947ec9.1775843299.git.matheus.bernardino@oss.qualcomm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: 0GC-aE4hFtjoVQWrb_jwPvNcPhuBEn18 X-Authority-Analysis: v=2.4 cv=b9aCJNGx c=1 sm=1 tr=0 ts=69d939b9 cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=ovJmrJClAAAA:8 a=qC_FGOx9AAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=q7X4_axEi9qJq2Gpr8MA:9 a=Fk4IpSoW4aLDllm1B1p-:22 a=brTEhlvMp4NY0_u118I2:22 a=fsdK_YakeE02zTmptMdW:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 0GC-aE4hFtjoVQWrb_jwPvNcPhuBEn18 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDE2OCBTYWx0ZWRfX2sfPvGOksyon LKm8K4L0urg5EHJ3LBctK/PN6fTx/Qe6Hs2j3voeItqvQ3UPQEVhuci5qQp5L6FpVXMICAHMGea 2bGScK0zNdJnNRce2pZLEoeHAVk3KvVSJjnGi7bl7mr7yBkVth1XxamztIDopVlpG0b7F2Ztbzm +6DaAm+dzWp3D7K7CKkFMEQ4pG0JYE546MrwqjvzTqKSSo7AVb/rNSLbdJygZjCne23ukuGiAuT VWaDcRhPM9FvnCQvFF2sHaDzYIXAkL8Xax4NDKYEylRgpMAoAelI59LZa1ICF6U/U0xaXYe8u5Y 0uzKgUtv/5oeT+QOsaQeIt1Cz60MqgCMDb6gTHoKblecH8Z7nOe+RzsMsdYD2q1NwD4T7lekzSa in/YeTPRfRMvc+rgjSA3e2Tmh6Co34ZsGWJy88EuLBI4dmsJ6tAXquq6PkZuCOkilUMWmS47v0q 5vhArZRobe9K7WR06dA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_05,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 impostorscore=0 adultscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100168 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775843913143154100 Content-Type: text/plain; charset="utf-8" From: Brian Cain Update the hexagon cross-compiler Docker container to use toolchain version 22.1.0, replacing the previous 12.Dec.2023 release. Changes to accommodate the new toolchain: - Add libc++1, libc++abi1, libunwind-19 runtime deps for the new LLVM-based toolchain - Add zstd for the new .tar.zst archive format - Update artifact URL domain to artifacts.codelinaro.org Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/docker/dockerfiles/debian-hexagon-cross.docker | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/tests/docker/dockerfiles/debian-hexagon-cross.docker b/tests/d= ocker/dockerfiles/debian-hexagon-cross.docker index 91d4b71ac9..636d0ca8a0 100644 --- a/tests/docker/dockerfiles/debian-hexagon-cross.docker +++ b/tests/docker/dockerfiles/debian-hexagon-cross.docker @@ -19,7 +19,11 @@ RUN apt-get update && \ curl \ ccache \ xz-utils \ + zstd \ ca-certificates \ + libc++1 \ + libc++abi1 \ + libunwind-19 \ bison \ flex \ git \ @@ -40,12 +44,12 @@ RUN apt-get update && \ dpkg-query --showformat '${Package}_${Version}_${Architecture}\n' --sh= ow > /packages.txt =20 ENV TOOLCHAIN_INSTALL /opt -ENV TOOLCHAIN_RELEASE 12.Dec.2023 +ENV TOOLCHAIN_RELEASE 22.1.0 ENV TOOLCHAIN_BASENAME "clang+llvm-${TOOLCHAIN_RELEASE}-cross-hexagon-unkn= own-linux-musl" -ENV TOOLCHAIN_URL https://codelinaro.jfrog.io/artifactory/codelinaro-toolc= hain-for-hexagon/${TOOLCHAIN_RELEASE}/${TOOLCHAIN_BASENAME}.tar.xz +ENV TOOLCHAIN_URL https://artifacts.codelinaro.org/artifactory/codelinaro-= toolchain-for-hexagon/${TOOLCHAIN_RELEASE}_/${TOOLCHAIN_BASENAME}.tar.zst ENV CCACHE_WRAPPERSDIR "/usr/libexec/ccache-wrappers" =20 -RUN curl -#SL "$TOOLCHAIN_URL" | tar -xJC "$TOOLCHAIN_INSTALL" +RUN curl -#SL "$TOOLCHAIN_URL" | tar --zstd -xC "$TOOLCHAIN_INSTALL" ENV PATH $PATH:${TOOLCHAIN_INSTALL}/${TOOLCHAIN_BASENAME}/x86_64-linux-gnu= /bin ENV MAKE /usr/bin/make # As a final step configure the user (if env is defined) --=20 2.37.2 From nobody Sat Apr 11 17:07:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1775843826; cv=none; d=zohomail.com; s=zohoarc; b=axUMdRr4l15de68VZJwWlo+njZV006qPI4gRcAsG+/v6UYBLZV7JA80Yj0Go+39OU/Jcgt73cDKKcl+gfH4Fc/C/FY26RDTO/a8eiVcCEgYHwcCCesUnWKIZYXQ3B9iQJoTQD8gM6dZWlSZN8FsnZxtXaxTmuuvV09gOhtkpmDs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775843826; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nOvzeWfo1gzMP3it2e0DgF8ZBLHR2ZVPC9oC1yks6l8=; b=VbqfzXgVpzPDsDGh3AIC+QbFcrc1epXw3qyjRrxOHjwZMdqRC8AXLnANr8MVERjO7Lato5Gj40tigJAiAwzrekv7xRZY0znmdFvo/8UxuIdtS8g02tdufULiHDhBLKeR8A+XiLD72GXXJeC0Pt2zPQkR1oXdHffmxpwQCHMUKf8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1775843826111439.80886769012375; Fri, 10 Apr 2026 10:57:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wBG5a-0006nW-Qy; Fri, 10 Apr 2026 13:56:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wBG5Y-0006mW-Hg for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:16 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wBG5V-0001Xb-DO for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:16 -0400 Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 63AAKDwV2698454 for ; Fri, 10 Apr 2026 17:56:10 GMT Received: from mail-dl1-f72.google.com (mail-dl1-f72.google.com [74.125.82.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4degt9v4hj-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 10 Apr 2026 17:56:10 +0000 (GMT) Received: by mail-dl1-f72.google.com with SMTP id a92af1059eb24-127133794b6so13615424c88.1 for ; Fri, 10 Apr 2026 10:56:10 -0700 (PDT) Received: from hu-mathbern-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775843828778158500 Content-Type: text/plain; charset="utf-8" The following encodings have become stricter since v68: - V6_vunpackob, V6_vunpackoh: ---00 -> --000 - V6_vaddbq/hq/wq, V6_vaddbnq/hnq/wnq: ---01 -> --001 - V6_vsubbq/hq, V6_vsubwq/bnq/hnq/wnq: ---01/---10 -> --001/--010 - V6_vhist, V6_vwhist128/256, V6_vwhist128/256_sat: ---00 -> --000 - V6_vhistq, V6_vwhist128/256q, V6_vwhist128/256q_sat: ---10 -> --010 Pre v68 compilers, by default, already use "0" for the non-specified bit that changed in v68, so unless someone is manually writing the binary encoding, this should not cause any backwards incompatibility with pre-v68 binaries. Reviewed-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/imported/mmvec/encode_ext.def | 48 ++++++++++---------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/= imported/mmvec/encode_ext.def index 402438f566..6d70086b5f 100644 --- a/target/hexagon/imported/mmvec/encode_ext.def +++ b/target/hexagon/imported/mmvec/encode_ext.def @@ -647,36 +647,36 @@ DEF_ENC(V6_vsubububb_sat, ICLASS_CJ" 1 110 101 vvv= vv PP 0 uuuuu 101 ddddd") DEF_ENC(V6_vmpyewuh_64, ICLASS_CJ" 1 110 101 vvvvv PP 0 uuuuu 110 d= dddd") =20 DEF_FIELDROW_DESC32( ICLASS_CJ" 1 110 --0 ----- PP 1 ----- ----- --= -","Vx32=3DVu32") -DEF_ENC(V6_vunpackob, ICLASS_CJ" 1 110 --0 ---00 PP 1 uuuuu 000 xx= xxx") // -DEF_ENC(V6_vunpackoh, ICLASS_CJ" 1 110 --0 ---00 PP 1 uuuuu 001 xx= xxx") // +DEF_ENC(V6_vunpackob, ICLASS_CJ" 1 110 --0 --000 PP 1 uuuuu 000 xx= xxx") // +DEF_ENC(V6_vunpackoh, ICLASS_CJ" 1 110 --0 --000 PP 1 uuuuu 001 xx= xxx") // //DEF_ENC(V6_vunpackow, ICLASS_CJ" 1 110 --0 ---00 PP 1 uuuuu 010 xxxx= x") // =20 -DEF_ENC(V6_vhist, ICLASS_CJ" 1 110 --0 ---00 PP 1 -000- 100 ---= --") -DEF_ENC(V6_vwhist256, ICLASS_CJ" 1 110 --0 ---00 PP 1 -0010 100 ---= --") -DEF_ENC(V6_vwhist256_sat, ICLASS_CJ" 1 110 --0 ---00 PP 1 -0011 100 ---= --") -DEF_ENC(V6_vwhist128, ICLASS_CJ" 1 110 --0 ---00 PP 1 -010- 100 ---= --") -DEF_ENC(V6_vwhist128m, ICLASS_CJ" 1 110 --0 ---00 PP 1 -011i 100 --= ---") +DEF_ENC(V6_vhist, ICLASS_CJ" 1 110 --0 --000 PP 1 -000- 100 ---= --") +DEF_ENC(V6_vwhist256, ICLASS_CJ" 1 110 --0 --000 PP 1 -0010 100 ---= --") +DEF_ENC(V6_vwhist256_sat, ICLASS_CJ" 1 110 --0 --000 PP 1 -0011 100 ---= --") +DEF_ENC(V6_vwhist128, ICLASS_CJ" 1 110 --0 --000 PP 1 -010- 100 ---= --") +DEF_ENC(V6_vwhist128m, ICLASS_CJ" 1 110 --0 --000 PP 1 -011i 100 --= ---") =20 DEF_FIELDROW_DESC32( ICLASS_CJ" 1 110 --0 ----- PP 1 ----- ----- --= -","if (Qv4) Vx32=3DVu32") -DEF_ENC(V6_vaddbq, ICLASS_CJ" 1 110 vv0 ---01 PP 1 uuuuu 000 x= xxxx") // -DEF_ENC(V6_vaddhq, ICLASS_CJ" 1 110 vv0 ---01 PP 1 uuuuu 001 x= xxxx") // -DEF_ENC(V6_vaddwq, ICLASS_CJ" 1 110 vv0 ---01 PP 1 uuuuu 010 x= xxxx") // -DEF_ENC(V6_vaddbnq, ICLASS_CJ" 1 110 vv0 ---01 PP 1 uuuuu 011 xxxx= x") // -DEF_ENC(V6_vaddhnq, ICLASS_CJ" 1 110 vv0 ---01 PP 1 uuuuu 100 xxxx= x") // -DEF_ENC(V6_vaddwnq, ICLASS_CJ" 1 110 vv0 ---01 PP 1 uuuuu 101 xxxx= x") // -DEF_ENC(V6_vsubbq, ICLASS_CJ" 1 110 vv0 ---01 PP 1 uuuuu 110 x= xxxx") // -DEF_ENC(V6_vsubhq, ICLASS_CJ" 1 110 vv0 ---01 PP 1 uuuuu 111 x= xxxx") // +DEF_ENC(V6_vaddbq, ICLASS_CJ" 1 110 vv0 --001 PP 1 uuuuu 000 x= xxxx") // +DEF_ENC(V6_vaddhq, ICLASS_CJ" 1 110 vv0 --001 PP 1 uuuuu 001 x= xxxx") // +DEF_ENC(V6_vaddwq, ICLASS_CJ" 1 110 vv0 --001 PP 1 uuuuu 010 x= xxxx") // +DEF_ENC(V6_vaddbnq, ICLASS_CJ" 1 110 vv0 --001 PP 1 uuuuu 011 xxxx= x") // +DEF_ENC(V6_vaddhnq, ICLASS_CJ" 1 110 vv0 --001 PP 1 uuuuu 100 xxxx= x") // +DEF_ENC(V6_vaddwnq, ICLASS_CJ" 1 110 vv0 --001 PP 1 uuuuu 101 xxxx= x") // +DEF_ENC(V6_vsubbq, ICLASS_CJ" 1 110 vv0 --001 PP 1 uuuuu 110 x= xxxx") // +DEF_ENC(V6_vsubhq, ICLASS_CJ" 1 110 vv0 --001 PP 1 uuuuu 111 x= xxxx") // =20 -DEF_ENC(V6_vsubwq, ICLASS_CJ" 1 110 vv0 ---10 PP 1 uuuuu 000 x= xxxx") // -DEF_ENC(V6_vsubbnq, ICLASS_CJ" 1 110 vv0 ---10 PP 1 uuuuu 001 xxxx= x") // -DEF_ENC(V6_vsubhnq, ICLASS_CJ" 1 110 vv0 ---10 PP 1 uuuuu 010 xxxx= x") // -DEF_ENC(V6_vsubwnq, ICLASS_CJ" 1 110 vv0 ---10 PP 1 uuuuu 011 xxxx= x") // +DEF_ENC(V6_vsubwq, ICLASS_CJ" 1 110 vv0 --010 PP 1 uuuuu 000 x= xxxx") // +DEF_ENC(V6_vsubbnq, ICLASS_CJ" 1 110 vv0 --010 PP 1 uuuuu 001 xxxx= x") // +DEF_ENC(V6_vsubhnq, ICLASS_CJ" 1 110 vv0 --010 PP 1 uuuuu 010 xxxx= x") // +DEF_ENC(V6_vsubwnq, ICLASS_CJ" 1 110 vv0 --010 PP 1 uuuuu 011 xxxx= x") // =20 -DEF_ENC(V6_vhistq, ICLASS_CJ" 1 110 vv0 ---10 PP 1 --00- 100 --= ---") -DEF_ENC(V6_vwhist256q, ICLASS_CJ" 1 110 vv0 ---10 PP 1 --010 100 --= ---") -DEF_ENC(V6_vwhist256q_sat, ICLASS_CJ" 1 110 vv0 ---10 PP 1 --011 100 --= ---") -DEF_ENC(V6_vwhist128q, ICLASS_CJ" 1 110 vv0 ---10 PP 1 --10- 100 --= ---") -DEF_ENC(V6_vwhist128qm, ICLASS_CJ" 1 110 vv0 ---10 PP 1 --11i 100 -= ----") +DEF_ENC(V6_vhistq, ICLASS_CJ" 1 110 vv0 --010 PP 1 --00- 100 --= ---") +DEF_ENC(V6_vwhist256q, ICLASS_CJ" 1 110 vv0 --010 PP 1 --010 100 --= ---") +DEF_ENC(V6_vwhist256q_sat, ICLASS_CJ" 1 110 vv0 --010 PP 1 --011 100 --= ---") +DEF_ENC(V6_vwhist128q, ICLASS_CJ" 1 110 vv0 --010 PP 1 --10- 100 --= ---") +DEF_ENC(V6_vwhist128qm, ICLASS_CJ" 1 110 vv0 --010 PP 1 --11i 100 -= ----") =20 =20 DEF_ENC(V6_vandvqv, ICLASS_CJ" 1 110 vv0 ---11 PP 1 uuuuu 000 d= dddd") --=20 2.37.2 From nobody Sat Apr 11 17:07:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775843844978154100 Content-Type: text/plain; charset="utf-8" This flag will be used to control the HVX IEEE float instructions, which are only available at some Hexagon cores. When unavailable, the instruction effectively only set the destination registers to 0. Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/cpu.h | 1 + target/hexagon/translate.h | 1 + target/hexagon/attribs_def.h.inc | 3 +++ target/hexagon/cpu.c | 1 + target/hexagon/translate.c | 1 + target/hexagon/gen_tcg_funcs.py | 11 +++++++++++ target/hexagon/hex_common.py | 25 +++++++++++++++++++++++++ 7 files changed, 43 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 85afd59277..77822a48b6 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -127,6 +127,7 @@ struct ArchCPU { bool lldb_compat; target_ulong lldb_stack_adjust; bool short_circuit; + bool ieee_fp_extension; }; =20 #include "cpu_bits.h" diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index b37cb49238..516aab7038 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -70,6 +70,7 @@ typedef struct DisasContext { target_ulong branch_dest; bool is_tight_loop; bool short_circuit; + bool ieee_fp_extension; bool read_after_write; bool has_hvx_overlap; TCGv new_value[TOTAL_PER_THREAD_REGS]; diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.= h.inc index 9e3a05f882..c85cd5d17c 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -173,5 +173,8 @@ DEF_ATTRIB(NOTE_SHIFT_RESOURCE, "Uses the HVX shift res= ource.", "", "") DEF_ATTRIB(RESTRICT_NOSLOT1_STORE, "Packet must not have slot 1 store", ""= , "") DEF_ATTRIB(RESTRICT_LATEPRED, "Predicate can not be used as a .new.", "", = "") =20 +/* HVX IEEE FP extension attributes */ +DEF_ATTRIB(HVX_IEEE_FP, "HVX IEEE FP extension instruction", "", "") + /* Keep this as the last attribute: */ DEF_ATTRIB(ZZ_LASTATTRIB, "Last attribute in the file", "", "") diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index ffd14bb467..8b72a5d3c8 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -54,6 +54,7 @@ static const Property hexagon_cpu_properties[] =3D { DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjus= t, 0, qdev_prop_uint32, target_ulong), DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true), + DEFINE_PROP_BOOL("ieee-fp", HexagonCPU, ieee_fp_extension, true), }; =20 const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] =3D { diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 633401451d..fa8f615a9e 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -988,6 +988,7 @@ static void hexagon_tr_init_disas_context(DisasContextB= ase *dcbase, ctx->branch_cond =3D TCG_COND_NEVER; ctx->is_tight_loop =3D FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP); ctx->short_circuit =3D hex_cpu->short_circuit; + ctx->ieee_fp_extension =3D hex_cpu->ieee_fp_extension; } =20 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index 87b7f10d7f..b752ec883c 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -22,6 +22,14 @@ import string import hex_common =20 +def gen_disabled_ieee_insn(f, tag, regs): + f.write(" if (!ctx->ieee_fp_extension) {\n") + for regtype, regid in regs: + reg =3D hex_common.get_register(tag, regtype, regid) + if reg.is_hvx_reg() and reg.is_written(): + reg.gen_zero(f) + f.write(" return;\n") + f.write(" }\n") =20 ## ## Generate the TCG code to call the helper @@ -62,6 +70,9 @@ def gen_tcg_func(f, tag, regs, imms): i =3D 1 if immlett.isupper() else 0 f.write(f" int {hex_common.imm_name(immlett)} =3D insn->immed[{= i}];\n") =20 + if "A_HVX_IEEE_FP" in hex_common.attribdict[tag]: + gen_disabled_ieee_insn(f, tag, regs) + if hex_common.is_idef_parser_enabled(tag): declared =3D [] ## Handle registers diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index c0e9f26aeb..e82a3da1e4 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -723,6 +723,11 @@ def decl_tcg(self, f, tag, regno): TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); """)) + def gen_zero(self, f): + f.write(code_fmt(f"""\ + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()}, + sizeof(MMVector), sizeof(MMVector), 0); + """)) def gen_write(self, f, tag): pass def helper_hvx_desc(self, f): @@ -789,6 +794,11 @@ def decl_tcg(self, f, tag, regno): TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); """)) + def gen_zero(self, f): + f.write(code_fmt(f"""\ + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()}, + sizeof(MMVector), sizeof(MMVector), 0); + """)) def gen_write(self, f, tag): pass def helper_hvx_desc(self, f): @@ -821,6 +831,11 @@ def decl_tcg(self, f, tag, regno): vreg_src_off(ctx, {self.reg_num}), sizeof(MMVector), sizeof(MMVector)); """)) + def gen_zero(self, f): + f.write(code_fmt(f"""\ + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()}, + sizeof(MMVector), sizeof(MMVector), 0); + """)) def gen_write(self, f, tag): f.write(code_fmt(f"""\ gen_vreg_write(ctx, {self.hvx_off()}, {self.reg_num}, @@ -854,6 +869,11 @@ def decl_tcg(self, f, tag, regno): TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); """)) + def gen_zero(self, f): + f.write(code_fmt(f"""\ + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()}, + sizeof(MMVectorPair), sizeof(MMVectorPair), 0); + """)) def gen_write(self, f, tag): pass def helper_hvx_desc(self, f): @@ -913,6 +933,11 @@ def decl_tcg(self, f, tag, regno): TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); """)) + def gen_zero(self, f): + f.write(code_fmt(f"""\ + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()}, + sizeof(MMVectorPair), sizeof(MMVectorPair), 0); + """)) def gen_write(self, f, tag): f.write(code_fmt(f"""\ gen_vreg_write_pair(ctx, {self.hvx_off()}, {self.reg_num}, --=20 2.37.2 From nobody Sat Apr 11 17:07:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Reviewed-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/cpu.h | 10 +++------- target/hexagon/cpu_bits.h | 7 +++++++ target/hexagon/cpu.c | 14 +++++++------- target/hexagon/translate.c | 6 +++--- 4 files changed, 20 insertions(+), 17 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 77822a48b6..d28beaa92f 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -119,19 +119,15 @@ typedef struct HexagonCPUClass { ResettablePhases parent_phases; } HexagonCPUClass; =20 +#include "cpu_bits.h" + struct ArchCPU { CPUState parent_obj; =20 CPUHexagonState env; - - bool lldb_compat; - target_ulong lldb_stack_adjust; - bool short_circuit; - bool ieee_fp_extension; + HexagonCPUConfig cfg; }; =20 -#include "cpu_bits.h" - FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) =20 G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index 19beca81c0..83d13de569 100644 --- a/target/hexagon/cpu_bits.h +++ b/target/hexagon/cpu_bits.h @@ -20,6 +20,13 @@ =20 #include "qemu/bitops.h" =20 +typedef struct HexagonCPUConfig { + bool lldb_compat; + uint32_t lldb_stack_adjust; + bool short_circuit; + bool ieee_fp_extension; +} HexagonCPUConfig; + #define PCALIGN 4 #define PCALIGN_MASK (PCALIGN - 1) =20 diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 8b72a5d3c8..5470d9c7ce 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -50,11 +50,11 @@ static ObjectClass *hexagon_cpu_class_by_name(const cha= r *cpu_model) } =20 static const Property hexagon_cpu_properties[] =3D { - DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false), - DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjus= t, 0, - qdev_prop_uint32, target_ulong), - DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true), - DEFINE_PROP_BOOL("ieee-fp", HexagonCPU, ieee_fp_extension, true), + DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, cfg.lldb_compat, false), + DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, cfg.lldb_stack_a= djust, + 0, qdev_prop_uint32, target_ulong), + DEFINE_PROP_BOOL("short-circuit", HexagonCPU, cfg.short_circuit, true), + DEFINE_PROP_BOOL("ieee-fp", HexagonCPU, cfg.ieee_fp_extension, true), }; =20 const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] =3D { @@ -77,7 +77,7 @@ const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS= ] =3D { static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong a= ddr) { HexagonCPU *cpu =3D env_archcpu(env); - target_ulong stack_adjust =3D cpu->lldb_stack_adjust; + target_ulong stack_adjust =3D cpu->cfg.lldb_stack_adjust; target_ulong stack_start =3D env->stack_start; target_ulong stack_size =3D 0x10000; =20 @@ -181,7 +181,7 @@ static void hexagon_dump(CPUHexagonState *env, FILE *f,= int flags) { HexagonCPU *cpu =3D env_archcpu(env); =20 - if (cpu->lldb_compat) { + if (cpu->cfg.lldb_compat) { /* * When comparing with LLDB, it doesn't step through single-cycle * hardware loops the same way. So, we just skip them here diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index fa8f615a9e..ce3af96675 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -987,8 +987,8 @@ static void hexagon_tr_init_disas_context(DisasContextB= ase *dcbase, ctx->num_hvx_insns =3D 0; ctx->branch_cond =3D TCG_COND_NEVER; ctx->is_tight_loop =3D FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP); - ctx->short_circuit =3D hex_cpu->short_circuit; - ctx->ieee_fp_extension =3D hex_cpu->ieee_fp_extension; + ctx->short_circuit =3D hex_cpu->cfg.short_circuit; + ctx->ieee_fp_extension =3D hex_cpu->cfg.ieee_fp_extension; } =20 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) @@ -1041,7 +1041,7 @@ static void hexagon_tr_translate_packet(DisasContextB= ase *dcbase, CPUState *cpu) * so end the TLB after every packet. */ HexagonCPU *hex_cpu =3D env_archcpu(env); - if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) { + if (hex_cpu->cfg.lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)= ) { ctx->base.is_jmp =3D DISAS_TOO_MANY; } } --=20 2.37.2 From nobody Sat Apr 11 17:07:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1775843846; cv=none; d=zohomail.com; s=zohoarc; b=kh6n5PWEneGtQoUPv4vz5wCkEA4/zI7IWR6ypZYw7AvXm116xtZ4p9X7WiJ7ZIQPZIVZbAkjugK6UG3bYb5WFgB3U8itJKyxae9Nk9KjqTGvJM0XslXo5cFSxwaIgswkEMAEx9fjTaGnT8dpxF12EePynVynBjDn8zrjeUUXAcM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775843846; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ybwCHZLfhnyCfuN9WWdAhCLFmoos/vVMcKHV+YU2Zd4=; b=lfZA4IY/PxhMo3qgLFULmXkNDFQJV/04YiNHb8959WKVrEz9ZXJE15awakX+yAOj3uUgoASdkZZpvq/zUa5LIE1XVEQLOWdW2cUgnvlXA+umM46LMm1euaSgKl78cGBkRcftsH/AcCC7A5V+mxbSLSdsGJCMAPZhhzPgp81Tip8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1775843846746292.6222549005422; Fri, 10 Apr 2026 10:57:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wBG5c-0006od-9Q; Fri, 10 Apr 2026 13:56:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wBG5Y-0006ml-SY for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:16 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wBG5W-0001Yp-DM for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:16 -0400 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 63AFJAJi3118235 for ; Fri, 10 Apr 2026 17:56:13 GMT Received: from mail-dl1-f69.google.com (mail-dl1-f69.google.com [74.125.82.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4df3rarexg-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 10 Apr 2026 17:56:13 +0000 (GMT) Received: by mail-dl1-f69.google.com with SMTP id a92af1059eb24-12c28353912so1965438c88.1 for ; Fri, 10 Apr 2026 10:56:13 -0700 (PDT) Received: from hu-mathbern-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775843849852158500 Content-Type: text/plain; charset="utf-8" When cpu->cfg.ieee_fp_extension is off, IEEE FP instructions don't get executed. Let's print that info on the "-d in_asm" output to help users. This will generate an output like the following: 0x00020e30: 0x1f82e1c0 { V0.sf =3D vadd(V1.sf,V2.sf) (disabled: no i= eee_fp) } Reviewed-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/cpu_bits.h | 3 ++- target/hexagon/printinsn.h | 2 +- disas/hexagon.c | 3 ++- target/hexagon/cpu.c | 2 ++ target/hexagon/decode.c | 4 ++-- target/hexagon/printinsn.c | 7 ++++++- 6 files changed, 15 insertions(+), 6 deletions(-) diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index 83d13de569..1f9e617d72 100644 --- a/target/hexagon/cpu_bits.h +++ b/target/hexagon/cpu_bits.h @@ -72,6 +72,7 @@ static inline bool is_packet_end(uint32_t endocing) return ((bits =3D=3D 0x3) || (bits =3D=3D 0x0)); } =20 -int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc, GString *= buf); +int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc, + GString *buf, const HexagonCPUConfig *cfg); =20 #endif diff --git a/target/hexagon/printinsn.h b/target/hexagon/printinsn.h index 2ecd1731d0..6a45ec571f 100644 --- a/target/hexagon/printinsn.h +++ b/target/hexagon/printinsn.h @@ -21,7 +21,7 @@ #include "insn.h" =20 void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words, - target_ulong pc); + target_ulong pc, const HexagonCPUConfig *cfg); void snprint_a_pkt_debug(GString *buf, Packet *pkt); =20 #endif diff --git a/disas/hexagon.c b/disas/hexagon.c index c1a4ffc5f6..e2d3804606 100644 --- a/disas/hexagon.c +++ b/disas/hexagon.c @@ -57,8 +57,9 @@ int print_insn_hexagon(bfd_vma memaddr, struct disassembl= e_info *info) return PACKET_WORDS_MAX * sizeof(uint32_t); } =20 + const HexagonCPUConfig *cfg =3D info->target_info; buf =3D g_string_sized_new(PACKET_BUFFER_LEN); - len =3D disassemble_hexagon(words, i, memaddr, buf); + len =3D disassemble_hexagon(words, i, memaddr, buf, cfg); (*info->fprintf_func)(info->stream, "%s", buf->str); g_string_free(buf, true); =20 diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 5470d9c7ce..d7f4df5f96 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -307,6 +307,8 @@ static void hexagon_cpu_disas_set_info(const CPUState *= cs, { info->print_insn =3D print_insn_hexagon; info->endian =3D BFD_ENDIAN_LITTLE; + HexagonCPU *cpu =3D HEXAGON_CPU(cs); + info->target_info =3D &cpu->cfg; } =20 static void hexagon_cpu_realize(DeviceState *dev, Error **errp) diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c index dbc9c630e8..d7ce8c8e1b 100644 --- a/target/hexagon/decode.c +++ b/target/hexagon/decode.c @@ -801,7 +801,7 @@ int decode_packet(DisasContext *ctx, int max_words, con= st uint32_t *words, =20 /* Used for "-d in_asm" logging */ int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc, - GString *buf) + GString *buf, const HexagonCPUConfig *cfg) { DisasContext ctx; Packet pkt; @@ -810,7 +810,7 @@ int disassemble_hexagon(uint32_t *words, int nwords, bf= d_vma pc, ctx.pkt =3D &pkt; =20 if (decode_packet(&ctx, nwords, words, &pkt, true) > 0) { - snprint_a_pkt_disas(buf, &pkt, words, pc); + snprint_a_pkt_disas(buf, &pkt, words, pc, cfg); return pkt.encod_pkt_size_in_bytes; } else { g_string_assign(buf, ""); diff --git a/target/hexagon/printinsn.c b/target/hexagon/printinsn.c index 4865cdd133..85527f56e2 100644 --- a/target/hexagon/printinsn.c +++ b/target/hexagon/printinsn.c @@ -51,7 +51,7 @@ static void snprintinsn(GString *buf, Insn *insn) } =20 void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words, - target_ulong pc) + target_ulong pc, const HexagonCPUConfig *cfg) { bool has_endloop0 =3D false; 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DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775843877882158500 Content-Type: text/plain; charset="utf-8" Add HVX IEEE floating-point arithmetic instructions: - vmpy_sf_sf, vmpy_sf_hf, vmpy_hf_hf: multiply operations - vdmpy_sf_hf: dot-product multiply - vmpy_sf_hf_acc, vmpy_hf_hf_acc, vdmpy_sf_hf_acc: multiply-accumulate - vadd_sf_sf, vsub_sf_sf, vadd_sf_hf, vsub_sf_hf: add/sub with sf output - vadd_hf_hf, vsub_hf_hf: add/sub with hf output Reviewed-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/cpu.h | 1 + target/hexagon/mmvec/hvx_ieee_fp.h | 18 ++++ target/hexagon/mmvec/macros.h | 1 + target/hexagon/mmvec/mmvec.h | 2 + target/hexagon/attribs_def.h.inc | 4 + target/hexagon/arch.c | 8 ++ target/hexagon/cpu.c | 3 + target/hexagon/mmvec/hvx_ieee_fp.c | 21 ++++ target/hexagon/hex_common.py | 1 + target/hexagon/imported/mmvec/encode_ext.def | 18 ++++ target/hexagon/imported/mmvec/ext.idef | 101 +++++++++++++++++++ target/hexagon/meson.build | 1 + 12 files changed, 179 insertions(+) create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.h create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.c diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index d28beaa92f..5a008d1949 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -87,6 +87,7 @@ typedef struct CPUArchState { MemLog mem_log_stores[STORES_MAX]; =20 float_status fp_status; + float_status hvx_fp_status; =20 target_ulong llsc_addr; target_ulong llsc_val; diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_= ieee_fp.h new file mode 100644 index 0000000000..75008deb3b --- /dev/null +++ b/target/hexagon/mmvec/hvx_ieee_fp.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HEXAGON_HVX_IEEE_H +#define HEXAGON_HVX_IEEE_H + +#include "fpu/softfloat.h" + +#define f16_to_f32(A) float16_to_float32((A), true, &env->hvx_fp_status) + +float32 fp_mult_sf_hf(float16 a1, float16 a2, float_status *fp_status); +float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4, + float_status *fp_status); + +#endif diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index c7840fbf2e..ac709d8993 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -23,6 +23,7 @@ #include "mmvec/system_ext_mmvec.h" #include "accel/tcg/getpc.h" #include "accel/tcg/probe.h" +#include "mmvec/hvx_ieee_fp.h" =20 #ifndef QEMU_GENERATE #define VdV (*(MMVector *restrict)(VdV_void)) diff --git a/target/hexagon/mmvec/mmvec.h b/target/hexagon/mmvec/mmvec.h index 52d470709c..31909303b5 100644 --- a/target/hexagon/mmvec/mmvec.h +++ b/target/hexagon/mmvec/mmvec.h @@ -38,6 +38,8 @@ typedef union { int16_t h[MAX_VEC_SIZE_BYTES / 2]; uint8_t ub[MAX_VEC_SIZE_BYTES / 1]; int8_t b[MAX_VEC_SIZE_BYTES / 1]; + float32 sf[MAX_VEC_SIZE_BYTES / 4]; + float16 hf[MAX_VEC_SIZE_BYTES / 2]; } MMVector; =20 typedef union { diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.= h.inc index c85cd5d17c..d3c4bf6301 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -175,6 +175,10 @@ DEF_ATTRIB(RESTRICT_LATEPRED, "Predicate can not be us= ed as a .new.", "", "") =20 /* HVX IEEE FP extension attributes */ DEF_ATTRIB(HVX_IEEE_FP, "HVX IEEE FP extension instruction", "", "") +DEF_ATTRIB(HVX_IEEE_FP_ACC, "HVX IEEE FP accumulate instruction", "", "") +DEF_ATTRIB(HVX_IEEE_FP_OUT_16, "HVX IEEE FP 16-bit output", "", "") +DEF_ATTRIB(HVX_IEEE_FP_OUT_32, "HVX IEEE FP 32-bit output", "", "") +DEF_ATTRIB(CVI_VX_NO_TMP_LD, "HVX multiply without tmp load", "", "") =20 /* Keep this as the last attribute: */ DEF_ATTRIB(ZZ_LASTATTRIB, "Last attribute in the file", "", "") diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c index e17e714a6a..358aa71e03 100644 --- a/target/hexagon/arch.c +++ b/target/hexagon/arch.c @@ -199,6 +199,10 @@ void arch_fpop_start(CPUHexagonState *env) set_float_rounding_mode( softfloat_roundingmodes[fREAD_REG_FIELD(USR, USR_FPRND)], &env->fp_status); + /* + * No need to check env->hvx_fp_status, these instructions don't + * raise exceptions nor interact with usr fields. + */ } =20 #ifdef CONFIG_USER_ONLY @@ -232,6 +236,10 @@ void arch_fpop_end(CPUHexagonState *env, bool pkt_need= _commit) SOFTFLOAT_TEST_FLAG(float_flag_overflow, FPOVFF, FPOVFE); SOFTFLOAT_TEST_FLAG(float_flag_underflow, FPUNFF, FPUNFE); } + /* + * No need to check env->hvx_fp_status, these instructions don't + * raise exceptions nor interact with usr fields. + */ } =20 int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjus= t, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index d7f4df5f96..d6ca51f175 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -300,6 +300,9 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetTy= pe type) set_float_detect_tininess(float_tininess_before_rounding, &env->fp_sta= tus); /* Default NaN value: sign bit set, all frac bits set */ set_float_default_nan_pattern(0b11111111, &env->fp_status); + + set_default_nan_mode(1, &env->hvx_fp_status); + set_float_default_nan_pattern(0b01111111, &env->hvx_fp_status); } =20 static void hexagon_cpu_disas_set_info(const CPUState *cs, diff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_= ieee_fp.c new file mode 100644 index 0000000000..3367226998 --- /dev/null +++ b/target/hexagon/mmvec/hvx_ieee_fp.c @@ -0,0 +1,21 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hvx_ieee_fp.h" + +float32 fp_mult_sf_hf(float16 a1, float16 a2, float_status *fp_status) +{ + return float32_mul(float16_to_float32(a1, true, fp_status), + float16_to_float32(a2, true, fp_status), fp_status); +} + +float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4, + float_status *fp_status) +{ + return float32_add(fp_mult_sf_hf(a1, a3, fp_status), + fp_mult_sf_hf(a2, a4, fp_status), fp_status); +} diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index e82a3da1e4..9819201b50 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -215,6 +215,7 @@ def need_env(tag): "A_LOAD" in attribdict[tag] or "A_CVI_GATHER" in attribdict[tag] or "A_CVI_SCATTER" in attribdict[tag] or + "A_HVX_IEEE_FP" in attribdict[tag] or "A_IMPLICIT_WRITES_USR" in attribdict[tag]) =20 =20 diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/= imported/mmvec/encode_ext.def index 6d70086b5f..4ce87d09fd 100644 --- a/target/hexagon/imported/mmvec/encode_ext.def +++ b/target/hexagon/imported/mmvec/encode_ext.def @@ -804,5 +804,23 @@ DEF_ENC(V6_vmpyewuh, ICLASS_CJ" 1 111 111 vvvvv PP = 0 uuuuu 101 ddddd") DEF_ENC(V6_vmpyowh, ICLASS_CJ" 1 111 111 vvvvv PP 0 uuuuu 111 ddddd= ") DEF_ENC(V6_vmpyuhvs,"00011111110vvvvvPP1uuuuu111ddddd") =20 +/* IEEE FP multiply instructions */ +DEF_ENC(V6_vmpy_sf_sf,"00011111100vvvvvPP1uuuuu001ddddd") +DEF_ENC(V6_vmpy_sf_hf,"00011111100vvvvvPP1uuuuu010ddddd") +DEF_ENC(V6_vmpy_hf_hf,"00011111100vvvvvPP1uuuuu011ddddd") +DEF_ENC(V6_vdmpy_sf_hf,"00011111101vvvvvPP1uuuuu110ddddd") + +/* IEEE FP multiply-accumulate instructions */ +DEF_ENC(V6_vmpy_sf_hf_acc,"00011100010vvvvvPP1uuuuu001xxxxx") +DEF_ENC(V6_vmpy_hf_hf_acc,"00011100010vvvvvPP1uuuuu010xxxxx") +DEF_ENC(V6_vdmpy_sf_hf_acc,"00011100010vvvvvPP1uuuuu011xxxxx") + +/* IEEE FP add/sub instructions */ +DEF_ENC(V6_vadd_sf_sf,"00011111100vvvvvPP1uuuuu110ddddd") +DEF_ENC(V6_vsub_sf_sf,"00011111100vvvvvPP1uuuuu111ddddd") +DEF_ENC(V6_vadd_sf_hf,"00011111100vvvvvPP1uuuuu100ddddd") +DEF_ENC(V6_vsub_sf_hf,"00011111100vvvvvPP1uuuuu101ddddd") +DEF_ENC(V6_vadd_hf_hf,"00011111101vvvvvPP1uuuuu111ddddd") +DEF_ENC(V6_vsub_hf_hf,"00011111011vvvvvPP1uuuuu000ddddd") =20 #endif /* NO MMVEC */ diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/import= ed/mmvec/ext.idef index 03d31f6181..14df8e4790 100644 --- a/target/hexagon/imported/mmvec/ext.idef +++ b/target/hexagon/imported/mmvec/ext.idef @@ -2895,9 +2895,110 @@ EXTINSN(V6_vprefixqw,"Vd32.w=3Dprefixsum(Qv4)", A= TTRIBS(A_EXTENSION,A_CVI,A_CVI_ } } ) =20 +/* KVX - IEEE FP Instructions */ =20 +/* Single pipe, 32-bit output */ +#define ITERATOR_INSN_IEEE_FP_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ +ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_32), \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) =20 +/* Single pipe, 16-bit output */ +#define ITERATOR_INSN_IEEE_FP_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ +ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16), \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) =20 +/* Two pipes: P2 & P3, single output: P2, 32-bit output */ +#define ITERATOR_INSN_IEEE_FP_DOUBLE_SINGLE_32(WIDTH,TAG,SYNTAX,DESCR,CODE= ) \ +EXTINSN(V6_##TAG, SYNTAX, \ +ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_32),= \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* Two pipes: P2 & P3, two outputs, 32-bit output */ +#define ITERATOR_INSN_IEEE_FP_DOUBLE_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ +ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_32),= \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* + * single pipe, accumulate instruction, produces 16-bit output, requires 1= 6-bit + * accumulate input + */ +#define ITERATOR_INSN_IEEE_FP_ACC_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ +ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_ACC,A_HVX_I= EEE_FP_OUT_16,A_CVI_VX_NO_TMP_LD), \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* + * single pipe, accumulate instruction, produces 32-bit output, requires 3= 2-bit + * accumulate input + */ +#define ITERATOR_INSN_IEEE_FP_ACC_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ +ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_ACC,A_HVX_I= EEE_FP_OUT_32,A_CVI_VX_NO_TMP_LD), \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* IEEE FP multiply instructions */ +ITERATOR_INSN_IEEE_FP_DOUBLE_SINGLE_32(32, vmpy_sf_sf, + "Vd32.sf=3Dvmpy(Vu32.sf,Vv32.sf)", "Vector IEEE mul: sf", + VdV.sf[i] =3D float32_mul(VuV.sf[i], VvV.sf[i], &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_hf, + "Vdd32.sf=3Dvmpy(Vu32.hf,Vv32.hf)", "Vector IEEE mul: hf widen to sf", + VddV.v[0].sf[i] =3D fp_mult_sf_hf(VuV.hf[2*i], VvV.hf[2*i], &env->hvx_= fp_status); + VddV.v[1].sf[i] =3D fp_mult_sf_hf(VuV.hf[2*i+1], VvV.hf[2*i+1], &env->= hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16(16, vmpy_hf_hf, "Vd32.hf=3Dvmpy(Vu32.hf,Vv32.= hf)", + "Vector IEEE mul: hf", + VdV.hf[i] =3D float16_mul(VuV.hf[i], VvV.hf[i], &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_32(32, vdmpy_sf_hf, "Vd32.sf=3Dvdmpy(Vu32.hf,Vv3= 2.hf)", + "Vector IEEE mul reduction: hf widen to sf", + VdV.sf[i] =3D fp_vdmpy(VuV.hf[2*i+1], VuV.hf[2*i], VvV.hf[2*i+1], + VvV.hf[2*i], &env->hvx_fp_status)) + +/* IEEE FP multiply-accumulate instructions */ +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_hf_acc, + "Vxx32.sf+=3Dvmpy(Vu32.hf,Vv32.hf)", "Vector IEEE fma: hf widen to sf", + VxxV.v[0].sf[i] =3D float32_muladd(f16_to_f32(VuV.hf[2*i]), + f16_to_f32(VvV.hf[2*i]), + VxxV.v[0].sf[i], 0, &env->hvx_fp_stat= us); + VxxV.v[1].sf[i] =3D float32_muladd(f16_to_f32(VuV.hf[2*i+1]), + f16_to_f32(VvV.hf[2*i+1]), + VxxV.v[1].sf[i], 0, &env->hvx_fp_stat= us)) +ITERATOR_INSN_IEEE_FP_ACC_16(16, vmpy_hf_hf_acc, + "Vx32.hf+=3Dvmpy(Vu32.hf,Vv32.hf)", "Vector IEEE fma: hf", + VxV.hf[i] =3D float16_muladd(VuV.hf[i], VvV.hf[i], VxV.hf[i], 0, &env-= >hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_ACC_32(32, vdmpy_sf_hf_acc, + "Vx32.sf+=3Dvdmpy(Vu32.hf,Vv32.hf)", "Vector IEEE fma reduce: hf widen= to sf", + VxV.sf[i] =3D float32_add(fp_vdmpy(VuV.hf[2*i+1], VuV.hf[2*i], + VvV.hf[2*i+1], VvV.hf[2*i], + &env->hvx_fp_status), + VxV.sf[i], &env->hvx_fp_status)) + +/* IEEE FP add/sub instructions */ +ITERATOR_INSN_IEEE_FP_32(32, vadd_sf_sf, "Vd32.sf=3Dvadd(Vu32.sf,Vv32.sf)", + "Vector IEEE add: sf", + VdV.sf[i] =3D float32_add(VuV.sf[i], VvV.sf[i], &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_32(32, vsub_sf_sf, "Vd32.sf=3Dvsub(Vu32.sf,Vv32.sf)", + "Vector IEEE sub: sf", + VdV.sf[i] =3D float32_sub(VuV.sf[i], VvV.sf[i], &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16(16, vadd_hf_hf, "Vd32.hf=3Dvadd(Vu32.hf,Vv32.hf)", + "Vector IEEE add: hf", + VdV.hf[i] =3D float16_add(VuV.hf[i], VvV.hf[i], &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16(16, vsub_hf_hf, "Vd32.hf=3Dvsub(Vu32.hf,Vv32.hf)", + "Vector IEEE sub: hf", + VdV.hf[i] =3D float16_sub(VuV.hf[i], VvV.hf[i], &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vadd_sf_hf, + "Vdd32.sf=3Dvadd(Vu32.hf,Vv32.hf)", "Vector IEEE add: hf widen to sf", + VddV.v[0].sf[i] =3D float32_add(f16_to_f32(VuV.hf[2*i]), + f16_to_f32(VvV.hf[2*i]), &env->hvx_fp_st= atus); + VddV.v[1].sf[i] =3D float32_add(f16_to_f32(VuV.hf[2*i+1]), + f16_to_f32(VvV.hf[2*i+1]), &env->hvx_fp_= status)) +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vsub_sf_hf, + "Vdd32.sf=3Dvsub(Vu32.hf,Vv32.hf)", "Vector IEEE sub: hf widen to sf", + VddV.v[0].sf[i] =3D float32_sub(f16_to_f32(VuV.hf[2*i]), + f16_to_f32(VvV.hf[2*i]), &env->hvx_fp_st= atus); + VddV.v[1].sf[i] =3D float32_sub(f16_to_f32(VuV.hf[2*i+1]), + f16_to_f32(VvV.hf[2*i+1]), &env->hvx_fp_= status)) =20 /*************************************************************************= ***** DEBUG Vector/Register Printing diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index d169cf71b2..9195014821 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -250,6 +250,7 @@ hexagon_ss.add(files( 'fma_emu.c', 'mmvec/decode_ext_mmvec.c', 'mmvec/system_ext_mmvec.c', + 'mmvec/hvx_ieee_fp.c', )) =20 # --=20 2.37.2 From nobody Sat Apr 11 17:07:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1775843880; cv=none; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775843882856154100 Content-Type: text/plain; charset="utf-8" Add HVX IEEE floating-point min/max instructions: - vfmin_hf, vfmin_sf: IEEE floating-point minimum - vfmax_hf, vfmax_sf: IEEE floating-point maximum - vmax_hf, vmax_sf: qfloat IEEE maximum - vmin_hf, vmin_sf: qfloat IEEE minimum The Hexagon qfloat variants are similar to the IEEE-754 ones, but they handle NaN slightly differently. See comment on hvx_ieee_fp.h Reviewed-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/mmvec/hvx_ieee_fp.h | 6 +++ target/hexagon/attribs_def.h.inc | 2 + target/hexagon/mmvec/hvx_ieee_fp.c | 50 ++++++++++++++++++++ target/hexagon/hex_common.py | 1 + target/hexagon/imported/mmvec/encode_ext.def | 10 ++++ target/hexagon/imported/mmvec/ext.idef | 36 +++++++++++++- 6 files changed, 104 insertions(+), 1 deletion(-) diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_= ieee_fp.h index 75008deb3b..dff2fab14c 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.h +++ b/target/hexagon/mmvec/hvx_ieee_fp.h @@ -15,4 +15,10 @@ float32 fp_mult_sf_hf(float16 a1, float16 a2, float_stat= us *fp_status); float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4, float_status *fp_status); =20 +/* Qfloat min/max treat +NaN as greater than +INF and -NaN as smaller than= -INF */ +float32 qf_max_sf(float32 a1, float32 a2, float_status *fp_status); +float32 qf_min_sf(float32 a1, float32 a2, float_status *fp_status); +float16 qf_max_hf(float16 a1, float16 a2, float_status *fp_status); +float16 qf_min_hf(float16 a1, float16 a2, float_status *fp_status); + #endif diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.= h.inc index d3c4bf6301..2d0fc7e9c0 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -81,6 +81,7 @@ DEF_ATTRIB(CVI_SCATTER, "CVI Scatter operation", "", "") DEF_ATTRIB(CVI_SCATTER_RELEASE, "CVI Store Release for scatter", "", "") DEF_ATTRIB(CVI_TMP_DST, "CVI instruction that doesn't write a register", "= ", "") DEF_ATTRIB(CVI_SLOT23, "Can execute in slot 2 or slot 3 (HVX)", "", "") +DEF_ATTRIB(CVI_VA_2SRC, "Execs on multimedia vector engine; requires two s= rcs", "", "") =20 DEF_ATTRIB(VTCM_ALLBANK_ACCESS, "Allocates in all VTCM schedulers.", "", "= ") =20 @@ -179,6 +180,7 @@ DEF_ATTRIB(HVX_IEEE_FP_ACC, "HVX IEEE FP accumulate ins= truction", "", "") DEF_ATTRIB(HVX_IEEE_FP_OUT_16, "HVX IEEE FP 16-bit output", "", "") DEF_ATTRIB(HVX_IEEE_FP_OUT_32, "HVX IEEE FP 32-bit output", "", "") DEF_ATTRIB(CVI_VX_NO_TMP_LD, "HVX multiply without tmp load", "", "") +DEF_ATTRIB(HVX_FLT, "This a floating point HVX instruction.", "", "") =20 /* Keep this as the last attribute: */ DEF_ATTRIB(ZZ_LASTATTRIB, "Last attribute in the file", "", "") diff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_= ieee_fp.c index 3367226998..2ae79a485a 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.c +++ b/target/hexagon/mmvec/hvx_ieee_fp.c @@ -19,3 +19,53 @@ float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, flo= at16 a4, return float32_add(fp_mult_sf_hf(a1, a3, fp_status), fp_mult_sf_hf(a2, a4, fp_status), fp_status); } + +#define float32_is_pos_nan(X) (float32_is_any_nan(X) && !float32_is_neg(X)) +#define float32_is_neg_nan(X) (float32_is_any_nan(X) && float32_is_neg(X)) +#define float16_is_pos_nan(X) (float16_is_any_nan(X) && !float16_is_neg(X)) +#define float16_is_neg_nan(X) (float16_is_any_nan(X) && float16_is_neg(X)) + +/* Qfloat min/max treat +NaN as greater than +INF and -NaN as smaller than= -INF */ +float32 qf_max_sf(float32 a1, float32 a2, float_status *fp_status) +{ + if (float32_is_pos_nan(a1) || float32_is_neg_nan(a2)) { + return a1; + } + if (float32_is_pos_nan(a2) || float32_is_neg_nan(a1)) { + return a2; + } + return float32_max(a1, a2, fp_status); +} + +float32 qf_min_sf(float32 a1, float32 a2, float_status *fp_status) +{ + if (float32_is_pos_nan(a1) || float32_is_neg_nan(a2)) { + return a2; + } + if (float32_is_pos_nan(a2) || float32_is_neg_nan(a1)) { + return a1; + } + return float32_min(a1, a2, fp_status); +} + +float16 qf_max_hf(float16 a1, float16 a2, float_status *fp_status) +{ + if (float16_is_pos_nan(a1) || float16_is_neg_nan(a2)) { + return a1; + } + if (float16_is_pos_nan(a2) || float16_is_neg_nan(a1)) { + return a2; + } + return float16_max(a1, a2, fp_status); +} + +float16 qf_min_hf(float16 a1, float16 a2, float_status *fp_status) +{ + if (float16_is_pos_nan(a1) || float16_is_neg_nan(a2)) { + return a2; + } + if (float16_is_pos_nan(a2) || float16_is_neg_nan(a1)) { + return a1; + } + return float16_min(a1, a2, fp_status); +} diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 9819201b50..168112c66f 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -216,6 +216,7 @@ def need_env(tag): "A_CVI_GATHER" in attribdict[tag] or "A_CVI_SCATTER" in attribdict[tag] or "A_HVX_IEEE_FP" in attribdict[tag] or + "A_HVX_FLT" in attribdict[tag] or "A_IMPLICIT_WRITES_USR" in attribdict[tag]) =20 =20 diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/= imported/mmvec/encode_ext.def index 4ce87d09fd..d7f50db778 100644 --- a/target/hexagon/imported/mmvec/encode_ext.def +++ b/target/hexagon/imported/mmvec/encode_ext.def @@ -823,4 +823,14 @@ DEF_ENC(V6_vsub_sf_hf,"00011111100vvvvvPP1uuuuu101dddd= d") DEF_ENC(V6_vadd_hf_hf,"00011111101vvvvvPP1uuuuu111ddddd") DEF_ENC(V6_vsub_hf_hf,"00011111011vvvvvPP1uuuuu000ddddd") =20 +/* IEEE FP min/max instructions */ +DEF_ENC(V6_vfmin_hf,"00011100011vvvvvPP1uuuuu000ddddd") +DEF_ENC(V6_vfmin_sf,"00011100011vvvvvPP1uuuuu001ddddd") +DEF_ENC(V6_vfmax_hf,"00011100011vvvvvPP1uuuuu010ddddd") +DEF_ENC(V6_vfmax_sf,"00011100011vvvvvPP1uuuuu011ddddd") +DEF_ENC(V6_vmax_sf,"00011111110vvvvvPP1uuuuu001ddddd") +DEF_ENC(V6_vmin_sf,"00011111110vvvvvPP1uuuuu010ddddd") +DEF_ENC(V6_vmax_hf,"00011111110vvvvvPP1uuuuu011ddddd") +DEF_ENC(V6_vmin_hf,"00011111110vvvvvPP1uuuuu100ddddd") + #endif /* NO MMVEC */ diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/import= ed/mmvec/ext.idef index 14df8e4790..0e9cace203 100644 --- a/target/hexagon/imported/mmvec/ext.idef +++ b/target/hexagon/imported/mmvec/ext.idef @@ -43,7 +43,9 @@ EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA), \ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) =20 - +#define ITERATOR_INSN_ANY_SLOT_2SRC(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC= ,A_HVX_FLT), \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) =20 #define ITERATOR_INSN2_ANY_SLOT(WIDTH,TAG,SYNTAX,SYNTAX2,DESCR,CODE) \ ITERATOR_INSN_ANY_SLOT(WIDTH,TAG,SYNTAX2,DESCR,CODE) @@ -3000,6 +3002,38 @@ ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vsub_sf_hf, VddV.v[1].sf[i] =3D float32_sub(f16_to_f32(VuV.hf[2*i+1]), f16_to_f32(VvV.hf[2*i+1]), &env->hvx_fp_= status)) =20 +#define ITERATOR_INSN_IEEE_FP_16_32_LATE(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ + ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT= _16,A_HVX_IEEE_FP_OUT_32), \ + DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* IEEE FP min/max instructions */ +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vfmin_hf, "Vd32.hf=3Dvfmin(Vu32.hf,Vv= 32.hf)", \ + "Vector IEEE min: hf", VdV.hf[i] =3D float16_min(VuV.hf[i], VvV.hf[i]= , \ + &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vfmin_sf, "Vd32.sf=3Dvfmin(Vu32.sf,Vv= 32.sf)", \ + "Vector IEEE min: sf", VdV.sf[i] =3D float32_min(VuV.sf[i], VvV.sf[i]= , \ + &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vfmax_hf, "Vd32.hf=3Dvfmax(Vu32.hf,V= v32.hf)", \ + "Vector IEEE max: hf", VdV.hf[i] =3D float16_max(VuV.hf[i], VvV.hf[i],= \ + &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vfmax_sf, "Vd32.sf=3Dvfmax(Vu32.sf,V= v32.sf)", \ + "Vector IEEE max: sf", VdV.sf[i] =3D float32_max(VuV.sf[i], VvV.sf[i],= \ + &env->hvx_fp_status)) + +ITERATOR_INSN_ANY_SLOT_2SRC(32,vmax_sf,"Vd32.sf=3Dvmax(Vu32.sf,Vv32.sf)", \ + "Vector max of sf input", VdV.sf[i] =3D qf_max_sf(VuV.sf[i], VvV.sf[i]= , \ + &env->hvx_fp_status)) +ITERATOR_INSN_ANY_SLOT_2SRC(32,vmin_sf,"Vd32.sf=3Dvmin(Vu32.sf,Vv32.sf)", \ + "Vector min of sf input", VdV.sf[i] =3D qf_min_sf(VuV.sf[i], VvV.sf[i]= , \ + &env->hvx_fp_status)) +ITERATOR_INSN_ANY_SLOT_2SRC(16,vmax_hf,"Vd32.hf=3Dvmax(Vu32.hf,Vv32.hf)", \ + "Vector max of hf input", VdV.hf[i] =3D qf_max_hf(VuV.hf[i], VvV.hf[i]= , \ + &env->hvx_fp_status)) +ITERATOR_INSN_ANY_SLOT_2SRC(16,vmin_hf,"Vd32.hf=3Dvmin(Vu32.hf,Vv32.hf)", \ + "Vector min of hf input", VdV.hf[i] =3D qf_min_hf(VuV.hf[i], VvV.hf[i]= , \ + &env->hvx_fp_status)) + /*************************************************************************= ***** DEBUG Vector/Register Printing *************************************************************************= *****/ --=20 2.37.2 From nobody Sat Apr 11 17:07:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775843854487154100 Content-Type: text/plain; charset="utf-8" Add HVX IEEE floating-point miscellaneous instructions: - vassign_fp (vfmv): vector move - vfneg_hf, vfneg_sf: vector floating-point negate - vabs_hf, vabs_sf: vector absolute value Reviewed-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/imported/mmvec/encode_ext.def | 7 +++++++ target/hexagon/imported/mmvec/ext.idef | 12 ++++++++++++ 2 files changed, 19 insertions(+) diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/= imported/mmvec/encode_ext.def index d7f50db778..72daf8724c 100644 --- a/target/hexagon/imported/mmvec/encode_ext.def +++ b/target/hexagon/imported/mmvec/encode_ext.def @@ -833,4 +833,11 @@ DEF_ENC(V6_vmin_sf,"00011111110vvvvvPP1uuuuu010ddddd") DEF_ENC(V6_vmax_hf,"00011111110vvvvvPP1uuuuu011ddddd") DEF_ENC(V6_vmin_hf,"00011111110vvvvvPP1uuuuu100ddddd") =20 +/* IEEE FP move, negate, abs instructions */ +DEF_ENC(V6_vassign_fp,"00011110--0-0110PP1uuuuu001ddddd") +DEF_ENC(V6_vfneg_hf,"00011110--0-0110PP1uuuuu010ddddd") +DEF_ENC(V6_vfneg_sf,"00011110--0-0110PP1uuuuu011ddddd") +DEF_ENC(V6_vabs_hf,"00011110--0-0110PP1uuuuu100ddddd") +DEF_ENC(V6_vabs_sf,"00011110--0-0110PP1uuuuu101ddddd") + #endif /* NO MMVEC */ diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/import= ed/mmvec/ext.idef index 0e9cace203..1b16ed0628 100644 --- a/target/hexagon/imported/mmvec/ext.idef +++ b/target/hexagon/imported/mmvec/ext.idef @@ -3034,6 +3034,18 @@ ITERATOR_INSN_ANY_SLOT_2SRC(16,vmin_hf,"Vd32.hf=3Dvm= in(Vu32.hf,Vv32.hf)", \ "Vector min of hf input", VdV.hf[i] =3D qf_min_hf(VuV.hf[i], VvV.hf[i]= , \ &env->hvx_fp_status)) =20 +/* IEEE FP move, negate, abs instructions */ +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vassign_fp, "Vd32.w=3Dvfmv(Vu32.w)", \ + "Vector IEEE move", VdV.w[i] =3D VuV.w[i]) +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vfneg_hf, "Vd32.hf=3Dvfneg(Vu32.hf)",= \ + "Vector IEEE neg: hf", VdV.hf[i] =3D float16_chs(VuV.hf[i])) +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vfneg_sf, "Vd32.sf=3Dvfneg(Vu32.sf)",= \ + "Vector IEEE neg: sf", VdV.sf[i] =3D float32_chs(VuV.sf[i])) +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vabs_hf, "Vd32.hf=3Dvabs(Vu32.hf)", \ + "Vector IEEE abs: hf", VdV.hf[i] =3D float16_abs(VuV.hf[i])) +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vabs_sf, "Vd32.sf=3Dvabs(Vu32.sf)", \ + "Vector IEEE abs: sf", VdV.sf[i] =3D float32_abs(VuV.sf[i])) + /*************************************************************************= ***** DEBUG Vector/Register Printing *************************************************************************= *****/ --=20 2.37.2 From nobody Sat Apr 11 17:07:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775843865062154100 Content-Type: text/plain; charset="utf-8" Add HVX IEEE floating-point conversion instructions: - vconv_hf_h, vconv_h_hf, vconv_sf_w, vconv_w_sf: vconv operations - vcvt_hf_sf, vcvt_sf_hf: float <-> half float conversions - vcvt_hf_b, vcvt_hf_h, vcvt_hf_ub, vcvt_hf_uh: int to half float - vcvt_b_hf, vcvt_h_hf, vcvt_ub_hf, vcvt_uh_hf: half float to int Reviewed-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/mmvec/hvx_ieee_fp.h | 4 + target/hexagon/mmvec/hvx_ieee_fp.c | 18 ++++ target/hexagon/imported/mmvec/encode_ext.def | 18 ++++ target/hexagon/imported/mmvec/ext.idef | 97 ++++++++++++++++++++ 4 files changed, 137 insertions(+) diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_= ieee_fp.h index dff2fab14c..bdc21e08f0 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.h +++ b/target/hexagon/mmvec/hvx_ieee_fp.h @@ -10,6 +10,7 @@ #include "fpu/softfloat.h" =20 #define f16_to_f32(A) float16_to_float32((A), true, &env->hvx_fp_status) +#define f32_to_f16(A) float32_to_float16((A), true, &env->hvx_fp_status) =20 float32 fp_mult_sf_hf(float16 a1, float16 a2, float_status *fp_status); float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4, @@ -21,4 +22,7 @@ float32 qf_min_sf(float32 a1, float32 a2, float_status *f= p_status); float16 qf_max_hf(float16 a1, float16 a2, float_status *fp_status); float16 qf_min_hf(float16 a1, float16 a2, float_status *fp_status); =20 +int32_t conv_w_sf(float32 a, float_status *fp_status); +int16_t conv_h_hf(float16 a, float_status *fp_status); + #endif diff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_= ieee_fp.c index 2ae79a485a..697f35b5ed 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.c +++ b/target/hexagon/mmvec/hvx_ieee_fp.c @@ -69,3 +69,21 @@ float16 qf_min_hf(float16 a1, float16 a2, float_status *= fp_status) } return float16_min(a1, a2, fp_status); } + +int32_t conv_w_sf(float32 a, float_status *fp_status) +{ + /* float32_to_int32 converts any NaN to MAX, hexagon looks at the sign= . */ + if (float32_is_any_nan(a)) { + return float32_is_neg(a) ? INT32_MIN : INT32_MAX; + } + return float32_to_int32_round_to_zero(a, fp_status); +} + +int16_t conv_h_hf(float16 a, float_status *fp_status) +{ + /* float16_to_int16 converts any NaN to MAX, hexagon looks at the sign= . */ + if (float16_is_any_nan(a)) { + return float16_is_neg(a) ? INT16_MIN : INT16_MAX; + } + return float16_to_int16_round_to_zero(a, fp_status); +} diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/= imported/mmvec/encode_ext.def index 72daf8724c..c1ed1b6c23 100644 --- a/target/hexagon/imported/mmvec/encode_ext.def +++ b/target/hexagon/imported/mmvec/encode_ext.def @@ -840,4 +840,22 @@ DEF_ENC(V6_vfneg_sf,"00011110--0-0110PP1uuuuu011ddddd") DEF_ENC(V6_vabs_hf,"00011110--0-0110PP1uuuuu100ddddd") DEF_ENC(V6_vabs_sf,"00011110--0-0110PP1uuuuu101ddddd") =20 +/* IEEE FP vcvt instructions */ +DEF_ENC(V6_vcvt_sf_hf,"00011110--0-0100PP1uuuuu100ddddd") +DEF_ENC(V6_vcvt_hf_sf,"00011111011vvvvvPP1uuuuu001ddddd") +DEF_ENC(V6_vcvt_hf_ub,"00011110--0-0100PP1uuuuu001ddddd") +DEF_ENC(V6_vcvt_hf_b,"00011110--0-0100PP1uuuuu010ddddd") +DEF_ENC(V6_vcvt_hf_uh,"00011110--0-0100PP1uuuuu101ddddd") +DEF_ENC(V6_vcvt_hf_h,"00011110--0-0100PP1uuuuu111ddddd") +DEF_ENC(V6_vcvt_uh_hf,"00011110--0--101PP1uuuuu000ddddd") +DEF_ENC(V6_vcvt_h_hf,"00011110--0-0110PP1uuuuu000ddddd") +DEF_ENC(V6_vcvt_ub_hf,"00011111110vvvvvPP1uuuuu101ddddd") +DEF_ENC(V6_vcvt_b_hf,"00011111110vvvvvPP1uuuuu110ddddd") + +/* IEEE FP vconv instructions */ +DEF_ENC(V6_vconv_sf_w,"00011110--0--101PP1uuuuu011ddddd") +DEF_ENC(V6_vconv_w_sf,"00011110--0--101PP1uuuuu001ddddd") +DEF_ENC(V6_vconv_hf_h,"00011110--0--101PP1uuuuu100ddddd") +DEF_ENC(V6_vconv_h_hf,"00011110--0--101PP1uuuuu010ddddd") + #endif /* NO MMVEC */ diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/import= ed/mmvec/ext.idef index 1b16ed0628..788ce1d2ae 100644 --- a/target/hexagon/imported/mmvec/ext.idef +++ b/target/hexagon/imported/mmvec/ext.idef @@ -63,6 +63,9 @@ ITERATOR_INSN_ANY_SLOT_DOUBLE_VEC(WIDTH,TAG,SYNTAX2,DESCR= ,CODE) EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS), \ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) =20 +#define ITERATOR_INSN_SHIFT_SLOT_FLT(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS,A_HVX_FLT), \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) =20 #define ITERATOR_INSN_SHIFT3_SLOT(WIDTH,TAG,SYNTAX,DESCR,CODE) \ EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS,A_CVI_VS_3SRC= ,A_NOTE_SHIFT_RESOURCE,A_NOTE_NOVP,A_NOTE_VA_UNARY), \ @@ -3046,6 +3049,100 @@ ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vabs_hf, "Vd3= 2.hf=3Dvabs(Vu32.hf)", \ ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vabs_sf, "Vd32.sf=3Dvabs(Vu32.sf)", \ "Vector IEEE abs: sf", VdV.sf[i] =3D float32_abs(VuV.sf[i])) =20 +/* Two pipes: P2 & P3, two outputs, 16-bit */ +#define ITERATOR_INSN_IEEE_FP_DOUBLE_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ +ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_16),= \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* Two pipes: P2 & P3, two outputs, 32-bit output */ +#define ITERATOR_INSN_IEEE_FP_DOUBLE_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ + ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_= 32), \ + DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* Single pipe, 16-bit output */ +#define ITERATOR_INSN_IEEE_FP_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ + ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16)= , \ + DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* single pipe, output can feed 16- or 32-bit accumulate */ +#define ITERATOR_INSN_IEEE_FP_16_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ + ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16,= A_HVX_IEEE_FP_OUT_32), \ + DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/*************************************************************************= ***** + * IEEE FP convert instructions + *************************************************************************= *****/ + +ITERATOR_INSN_IEEE_FP_DOUBLE_16(32, vcvt_hf_ub, "Vdd32.hf=3Dvcvt(Vu32.ub)= ", + "Vector IEEE cvt from int: ub widen to hf", + VddV.v[0].hf[2*i] =3D uint64_to_float16_scalbn(VuV.ub[4*i], float_ro= und_nearest_even, 0); + VddV.v[0].hf[2*i+1] =3D uint64_to_float16_scalbn(VuV.ub[4*i+1], float_= round_nearest_even, 0); + VddV.v[1].hf[2*i] =3D uint64_to_float16_scalbn(VuV.ub[4*i+2], float_= round_nearest_even, 0); + VddV.v[1].hf[2*i+1] =3D uint64_to_float16_scalbn(VuV.ub[4*i+3], float_= round_nearest_even, 0)) + +ITERATOR_INSN_IEEE_FP_DOUBLE_16(32, vcvt_hf_b, "Vdd32.hf=3Dvcvt(Vu32.b)", + "Vector IEEE cvt from int: b widen to hf", + VddV.v[0].hf[2*i] =3D int64_to_float16_scalbn(VuV.b[4*i], float_roun= d_nearest_even, 0); + VddV.v[0].hf[2*i+1] =3D int64_to_float16_scalbn(VuV.b[4*i+1], float_ro= und_nearest_even, 0); + VddV.v[1].hf[2*i] =3D int64_to_float16_scalbn(VuV.b[4*i+2], float_ro= und_nearest_even, 0); + VddV.v[1].hf[2*i+1] =3D int64_to_float16_scalbn(VuV.b[4*i+3], float_ro= und_nearest_even, 0)) + +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vcvt_sf_hf, "Vdd32.sf=3Dvcvt(Vu32.hf)", + "Vector IEEE cvt: hf widen to sf", + VddV.v[0].sf[i] =3D f16_to_f32(VuV.hf[2*i]); + VddV.v[1].sf[i] =3D f16_to_f32(VuV.hf[2*i+1])) + +ITERATOR_INSN_IEEE_FP_16(16, vcvt_hf_uh, "Vd32.hf=3Dvcvt(Vu32.uh)", + "Vector IEEE cvt from int: uh to hf", + VdV.hf[i] =3D uint64_to_float16_scalbn(VuV.uh[i], float_round_nearest_= even, 0)) +ITERATOR_INSN_IEEE_FP_16(16, vcvt_hf_h, "Vd32.hf=3Dvcvt(Vu32.h)", + "Vector IEEE cvt from int: h to hf", + VdV.hf[i] =3D int64_to_float16_scalbn(VuV.h[i], float_round_nearest_ev= en, 0)) +ITERATOR_INSN_IEEE_FP_16_32(16, vcvt_uh_hf, "Vd32.uh=3Dvcvt(Vu32.hf)", + "Vector IEEE cvt to int: hf to uh", + VdV.uh[i] =3D float16_to_uint16_scalbn(VuV.hf[i], float_round_nearest_= even, 0, &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16_32(16, vcvt_h_hf, "Vd32.h=3Dvcvt(Vu32.hf)", + "Vector IEEE cvt to int: hf to h", + VdV.h[i] =3D float16_to_int16_scalbn(VuV.hf[i], float_round_nearest_e= ven, 0, &env->hvx_fp_status)) + +ITERATOR_INSN_IEEE_FP_16(32, vcvt_hf_sf, "Vd32.hf=3Dvcvt(Vu32.sf,Vv32.sf)", + "Vector IEEE cvt: sf to hf", + VdV.hf[2*i] =3D f32_to_f16(VuV.sf[i]); + VdV.hf[2*i+1] =3D f32_to_f16(VvV.sf[i])) + +ITERATOR_INSN_IEEE_FP_16_32(32, vcvt_ub_hf, "Vd32.ub=3Dvcvt(Vu32.hf,Vv32.h= f)", "Vector cvt to int: hf narrow to ub", + VdV.ub[4*i] =3D float16_to_uint8_scalbn(VuV.hf[2*i], float_round_nea= rest_even, 0, &env->hvx_fp_status); + VdV.ub[4*i+1] =3D float16_to_uint8_scalbn(VuV.hf[2*i+1], float_round_n= earest_even, 0, &env->hvx_fp_status); + VdV.ub[4*i+2] =3D float16_to_uint8_scalbn(VvV.hf[2*i], float_round_nea= rest_even, 0, &env->hvx_fp_status); + VdV.ub[4*i+3] =3D float16_to_uint8_scalbn(VvV.hf[2*i+1], float_round_n= earest_even, 0, &env->hvx_fp_status)) + +ITERATOR_INSN_IEEE_FP_16_32(32, vcvt_b_hf, "Vd32.b=3Dvcvt(Vu32.hf,Vv32.hf= )", + "Vector cvt to int: hf narrow to b", + VdV.b[4*i] =3D float16_to_int8_scalbn(VuV.hf[2*i], float_round_neare= st_even, 0, &env->hvx_fp_status); + VdV.b[4*i+1] =3D float16_to_int8_scalbn(VuV.hf[2*i+1], float_round_nea= rest_even, 0, &env->hvx_fp_status); + VdV.b[4*i+2] =3D float16_to_int8_scalbn(VvV.hf[2*i], float_round_neare= st_even, 0, &env->hvx_fp_status); + VdV.b[4*i+3] =3D float16_to_int8_scalbn(VvV.hf[2*i+1], float_round_nea= rest_even, 0, &env->hvx_fp_status)) + +ITERATOR_INSN_SHIFT_SLOT_FLT(32, vconv_w_sf,"Vd32.w=3DVu32.sf", + "Vector conversion of sf32 format to int w", + VdV.w[i] =3D conv_w_sf(VuV.sf[i], &env->hvx_fp_status)) + +ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_h_hf,"Vd32.h=3DVu32.hf", + "Vector conversion of hf16 format to int hw", + VdV.h[i] =3D conv_h_hf(VuV.hf[i], &env->hvx_fp_status)) + +ITERATOR_INSN_SHIFT_SLOT_FLT(32, vconv_sf_w,"Vd32.sf=3DVu32.w", + "Vector conversion of int w format to sf32", + VdV.sf[i] =3D int32_to_float32(VuV.w[i], &env->hvx_fp_status)) + +ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_hf_h,"Vd32.hf=3DVu32.h", + "Vector conversion of int hw format to hf16", + VdV.hf[i] =3D float16_val(int16_to_float16(VuV.h[i], &env->hvx_fp_stat= us))) + /*************************************************************************= ***** DEBUG Vector/Register Printing *************************************************************************= *****/ --=20 2.37.2 From nobody Sat Apr 11 17:07:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775843923380154100 Content-Type: text/plain; charset="utf-8" Add HVX IEEE floating-point compare instructions: - V6_vgthf, V6_vgtsf: greater-than compare - V6_vgthf_and, V6_vgtsf_and: greater-than with predicate-and - V6_vgthf_or, V6_vgtsf_or: greater-than with predicate-or - V6_vgthf_xor, V6_vgtsf_xor: greater-than with predicate-xor Reviewed-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/mmvec/hvx_ieee_fp.h | 4 ++ target/hexagon/mmvec/macros.h | 3 + target/hexagon/mmvec/hvx_ieee_fp.c | 48 +++++++++++++++ target/hexagon/imported/mmvec/encode_ext.def | 10 ++++ target/hexagon/imported/mmvec/ext.idef | 61 ++++++++++++++++++++ 5 files changed, 126 insertions(+) diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_= ieee_fp.h index bdc21e08f0..01728121eb 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.h +++ b/target/hexagon/mmvec/hvx_ieee_fp.h @@ -25,4 +25,8 @@ float16 qf_min_hf(float16 a1, float16 a2, float_status *f= p_status); int32_t conv_w_sf(float32 a, float_status *fp_status); int16_t conv_h_hf(float16 a, float_status *fp_status); =20 +/* IEEE - FP compare instructions */ +uint32_t cmpgt_sf(float32 a1, float32 a2, float_status *fp_status); +uint16_t cmpgt_hf(float16 a1, float16 a2, float_status *fp_status); + #endif diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index ac709d8993..318d44efb7 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -356,4 +356,7 @@ extract32(VAL, POS * 8, 8); \ } while (0); =20 +#define fCMPGT_SF(A, B) cmpgt_sf(A, B, &env->hvx_fp_status) +#define fCMPGT_HF(A, B) cmpgt_hf(A, B, &env->hvx_fp_status) + #endif diff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_= ieee_fp.c index 697f35b5ed..d7751adbe2 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.c +++ b/target/hexagon/mmvec/hvx_ieee_fp.c @@ -87,3 +87,51 @@ int16_t conv_h_hf(float16 a, float_status *fp_status) } return float16_to_int16_round_to_zero(a, fp_status); } + +/* + * Returns true if f1 > f2, where at least one of the elements is guarante= ed + * to be NaN. + * Up to v73, Hexagon HVX IEEE FP follows this order: + * QNaN > SNaN > +Inf > numbers > -Inf > SNaN_neg > QNaN_neg + */ +static bool float32_nan_compare(float32 f1, float32 f2, float_status *fp_s= tatus) +{ + /* opposite signs case */ + if (float32_is_neg(f1) !=3D float32_is_neg(f2)) { + return !float32_is_neg(f1); + } + + /* same sign case */ + bool result =3D (float32_is_any_nan(f1) && !float32_is_any_nan(f2)) || + (float32_is_quiet_nan(f1, fp_status) && !float32_is_quiet_nan(f2, = fp_status)); + return float32_is_neg(f1) ? !result : result; +} + +static bool float16_nan_compare(float16 f1, float16 f2, float_status *fp_s= tatus) +{ + /* opposite signs case */ + if (float16_is_neg(f1) !=3D float16_is_neg(f2)) { + return !float16_is_neg(f1); + } + + /* same sign case */ + bool result =3D (float16_is_any_nan(f1) && !float16_is_any_nan(f2)) || + (float16_is_quiet_nan(f1, fp_status) && !float16_is_quiet_nan(f2, = fp_status)); + return float16_is_neg(f1) ? !result : result; +} + +uint32_t cmpgt_sf(float32 a1, float32 a2, float_status *fp_status) +{ + if (float32_is_any_nan(a1) || float32_is_any_nan(a2)) { + return float32_nan_compare(a1, a2, fp_status); + } + return float32_compare(a1, a2, fp_status) =3D=3D float_relation_greate= r; +} + +uint16_t cmpgt_hf(float16 a1, float16 a2, float_status *fp_status) +{ + if (float16_is_any_nan(a1) || float16_is_any_nan(a2)) { + return float16_nan_compare(a1, a2, fp_status); + } + return float16_compare(a1, a2, fp_status) =3D=3D float_relation_greate= r; +} diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/= imported/mmvec/encode_ext.def index c1ed1b6c23..3572e4de4c 100644 --- a/target/hexagon/imported/mmvec/encode_ext.def +++ b/target/hexagon/imported/mmvec/encode_ext.def @@ -858,4 +858,14 @@ DEF_ENC(V6_vconv_w_sf,"00011110--0--101PP1uuuuu001dddd= d") DEF_ENC(V6_vconv_hf_h,"00011110--0--101PP1uuuuu100ddddd") DEF_ENC(V6_vconv_h_hf,"00011110--0--101PP1uuuuu010ddddd") =20 +/* IEEE FP compare instructions */ +DEF_ENC(V6_vgtsf,"00011100100vvvvvPP1uuuuu011100dd") +DEF_ENC(V6_vgthf,"00011100100vvvvvPP1uuuuu011101dd") +DEF_ENC(V6_vgtsf_and,"00011100100vvvvvPP1uuuuu110010xx") +DEF_ENC(V6_vgthf_and,"00011100100vvvvvPP1uuuuu110011xx") +DEF_ENC(V6_vgtsf_or,"00011100100vvvvvPP1uuuuu001100xx") +DEF_ENC(V6_vgthf_or,"00011100100vvvvvPP1uuuuu001101xx") +DEF_ENC(V6_vgtsf_xor,"00011100100vvvvvPP1uuuuu111010xx") +DEF_ENC(V6_vgthf_xor,"00011100100vvvvvPP1uuuuu111011xx") + #endif /* NO MMVEC */ diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/import= ed/mmvec/ext.idef index 788ce1d2ae..a7043d598c 100644 --- a/target/hexagon/imported/mmvec/ext.idef +++ b/target/hexagon/imported/mmvec/ext.idef @@ -3143,6 +3143,67 @@ ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_hf_h,"Vd32.hf= =3DVu32.h", "Vector conversion of int hw format to hf16", VdV.hf[i] =3D float16_val(int16_to_float16(VuV.h[i], &env->hvx_fp_stat= us))) =20 +/*************************************************************************= ***** + * IEEE FP compare instructions + *************************************************************************= *****/ + +#define VCMPGT_SF(DEST, ASRC, ASRCOP, CMP, N, SRC, MASK, WIDTH) \ +{ \ + for (fHIDE(int) i =3D 0; i < fVBYTES(); i +=3D WIDTH) { \ + fHIDE(int) VAL =3D fCMPGT_SF(VuV.SRC[i/WIDTH],VvV.SRC[i/WIDTH]) ? = MASK : 0; \ + fSETQBITS(DEST,WIDTH,MASK,i,ASRC ASRCOP VAL); \ + } \ +} + +#define VCMPGT_HF(DEST, ASRC, ASRCOP, CMP, N, SRC, MASK, WIDTH) \ +{ \ + for (fHIDE(int) i =3D 0; i < fVBYTES(); i +=3D WIDTH) { \ + fHIDE(int) VAL =3D fCMPGT_HF(VuV.SRC[i/WIDTH],VvV.SRC[i/WIDTH]) ? = MASK : 0; \ + fSETQBITS(DEST,WIDTH,MASK,i,ASRC ASRCOP VAL); \ + } \ +} + +/* Vector SF compare */ +#define MMVEC_CMPGT_SF(TYPE,TYPE2,DESCR,N,MASK,WIDTH,SRC) \ + EXTINSN(V6_vgt##TYPE##_and, "Qx4&=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE= 2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than with predicate-and", \ + VCMPGT_SF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), &, ">", N, SRC, MASK, = WIDTH)) \ + EXTINSN(V6_vgt##TYPE##_xor, "Qx4^=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE= 2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than with predicate-xor", \ + VCMPGT_SF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), ^, ">", N, SRC, MASK, = WIDTH)) \ + EXTINSN(V6_vgt##TYPE##_or, "Qx4|=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE2= ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than with predicate-or", \ + VCMPGT_SF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), |, ">", N, SRC, MASK, = WIDTH)) \ + EXTINSN(V6_vgt##TYPE, "Qd4=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than", \ + VCMPGT_SF(QdV, , , ">", N, SRC, MASK, WIDTH)) + +/* Vector HF compare */ +#define MMVEC_CMPGT_HF(TYPE,TYPE2,DESCR,N,MASK,WIDTH,SRC) \ + EXTINSN(V6_vgt##TYPE##_and, "Qx4&=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE= 2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than with predicate-and", \ + VCMPGT_HF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), &, ">", N, SRC, MASK, = WIDTH)) \ + EXTINSN(V6_vgt##TYPE##_xor, "Qx4^=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE= 2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than with predicate-xor", \ + VCMPGT_HF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), ^, ">", N, SRC, MASK, = WIDTH)) \ + EXTINSN(V6_vgt##TYPE##_or, "Qx4|=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE2= ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than with predicate-or", \ + VCMPGT_HF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), |, ">", N, SRC, MASK, = WIDTH)) \ + EXTINSN(V6_vgt##TYPE, "Qd4=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than", \ + VCMPGT_HF(QdV, , , ">", N, SRC, MASK, WIDTH)) + +MMVEC_CMPGT_SF(sf,"sf","Vector sf Compare ", fVELEM(32), 0xF, 4, sf) +MMVEC_CMPGT_HF(hf,"hf","Vector hf Compare ", fVELEM(16), 0x3, 2, hf) + /*************************************************************************= ***** DEBUG Vector/Register Printing *************************************************************************= *****/ --=20 2.37.2 From nobody Sat Apr 11 17:07:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1775843868; cv=none; d=zohomail.com; s=zohoarc; b=N2sAi5zy/TcpRDsyWQQHhLKOci29OV3oqizUf3yKimKc6KkOmV/EsppG15SrAgn/xFpvSeeth8WihfpeiSkpf2EIxJf0J4XSWfMWZ02GBwVFuHDFB8gD+RLH5gNLtMpjyMxLjjgsgI+RgJJvr+Ec5Bmz7MQdz+nkAYrrfdGB1Zo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775843868; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=GGG/Zp81i+Z5zJgP834y0mXGrz5J69B+j8Rbi2MoPwg=; b=KrzexbZwSOQiMPV/SJ87exo7AqbAKO23MaeDrTeJVjVLCFCN9n8IMEm86tjHDd3NrneMjtiDbutTbMT+c3193joLHBrMSBBOv0FsW7LIfVIxVjqLfV+fdp6rYLNXE79Xnq66OaSCsvcFpC3hU5P14KJifutVptIEdmkX5BoR8Js= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1775843868866170.14719082904878; Fri, 10 Apr 2026 10:57:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wBG65-0006uS-SI; Fri, 10 Apr 2026 13:56:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wBG5y-0006u0-66 for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:42 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wBG5v-0001ft-UW for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:41 -0400 Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 63AB13LJ438888 for ; Fri, 10 Apr 2026 17:56:20 GMT Received: from mail-dl1-f69.google.com (mail-dl1-f69.google.com [74.125.82.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4deyy9s9uq-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 10 Apr 2026 17:56:20 +0000 (GMT) Received: by mail-dl1-f69.google.com with SMTP id a92af1059eb24-1275c6fc58aso2785951c88.0 for ; Fri, 10 Apr 2026 10:56:20 -0700 (PDT) Received: from hu-mathbern-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775843871805158500 Content-Type: text/plain; charset="utf-8" Add HVX IEEE bfloat16 (bf16) instructions: Arithmetic operations: - V6_vadd_sf_bf, V6_vsub_sf_bf: add/sub bf16 widening to sf output - V6_vmpy_sf_bf: multiply bf16 widening to sf output - V6_vmpy_sf_bf_acc: multiply-accumulate bf16 widening to sf output Min/Max operations: - V6_vmin_bf, V6_vmax_bf: bf16 min/max Comparison operations: - V6_vgtbf: greater-than compare - V6_vgtbf_and, V6_vgtbf_or, V6_vgtbf_xor: predicate variants Conversion operations: - V6_vcvt_bf_sf: convert sf to bf16 Reviewed-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/mmvec/hvx_ieee_fp.h | 37 ++++++++++++ target/hexagon/mmvec/macros.h | 4 ++ target/hexagon/mmvec/mmvec.h | 1 + target/hexagon/imported/mmvec/encode_ext.def | 15 +++++ target/hexagon/imported/mmvec/ext.idef | 62 ++++++++++++++++++++ 5 files changed, 119 insertions(+) diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_= ieee_fp.h index 01728121eb..b7e379b089 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.h +++ b/target/hexagon/mmvec/hvx_ieee_fp.h @@ -9,8 +9,11 @@ =20 #include "fpu/softfloat.h" =20 +#define FP32_DEF_NAN 0x7FFFFFFF + #define f16_to_f32(A) float16_to_float32((A), true, &env->hvx_fp_status) #define f32_to_f16(A) float32_to_float16((A), true, &env->hvx_fp_status) +#define bf16_to_f32(A) bfloat16_to_float32(A, &env->hvx_fp_status) =20 float32 fp_mult_sf_hf(float16 a1, float16 a2, float_status *fp_status); float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4, @@ -29,4 +32,38 @@ int16_t conv_h_hf(float16 a, float_status *fp_status); uint32_t cmpgt_sf(float32 a1, float32 a2, float_status *fp_status); uint16_t cmpgt_hf(float16 a1, float16 a2, float_status *fp_status); =20 +/* IEEE BFloat instructions */ + +#define fp_mult_sf_bf(A, B) \ + float32_mul(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status) + +#define fp_add_sf_bf(A, B) \ + float32_add(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status) + +#define fp_sub_sf_bf(A, B) \ + float32_sub(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status) + +#define fp_mult_sf_bf_acc(f1, f2, f3) \ + float32_muladd(bf16_to_f32(f1), bf16_to_f32(f2), f3, 0, &env->hvx_fp_s= tatus) + +static inline bfloat16 f32_to_bf16(float32 A, float_status *fp_status) +{ + uint32_t rslt =3D A; + if ((rslt & 0x1FFFF) =3D=3D 0x08000) { + /* do not round up if exactly .5 and even already */ + } else if ((rslt & 0x8000) =3D=3D 0x8000) { + rslt +=3D 0x8000; /* rounding to nearest number */ + } + rslt =3D float32_is_any_nan(A) ? FP32_DEF_NAN : rslt; + return float32_to_bfloat16(rslt, fp_status); +} + +#define fp_min_bf(A, B) \ + f32_to_bf16(float32_min(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_s= tatus), \ + &env->hvx_fp_status); + +#define fp_max_bf(A, B) \ + f32_to_bf16(float32_max(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_s= tatus), \ + &env->hvx_fp_status); + #endif diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index 318d44efb7..4945a61194 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -25,6 +25,9 @@ #include "accel/tcg/probe.h" #include "mmvec/hvx_ieee_fp.h" =20 +#define fBFLOAT() +#define fCVI_VX_NO_TMP_LD() + #ifndef QEMU_GENERATE #define VdV (*(MMVector *restrict)(VdV_void)) #define VsV (*(MMVector *restrict)(VsV_void)) @@ -358,5 +361,6 @@ =20 #define fCMPGT_SF(A, B) cmpgt_sf(A, B, &env->hvx_fp_status) #define fCMPGT_HF(A, B) cmpgt_hf(A, B, &env->hvx_fp_status) +#define fCMPGT_BF(A, B) fCMPGT_SF((uint32_t)(A) << 16, (uint32_t)(B) << 16) =20 #endif diff --git a/target/hexagon/mmvec/mmvec.h b/target/hexagon/mmvec/mmvec.h index 31909303b5..ab991471b1 100644 --- a/target/hexagon/mmvec/mmvec.h +++ b/target/hexagon/mmvec/mmvec.h @@ -40,6 +40,7 @@ typedef union { int8_t b[MAX_VEC_SIZE_BYTES / 1]; float32 sf[MAX_VEC_SIZE_BYTES / 4]; float16 hf[MAX_VEC_SIZE_BYTES / 2]; + bfloat16 bf[MAX_VEC_SIZE_BYTES / 2]; } MMVector; =20 typedef union { diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/= imported/mmvec/encode_ext.def index 3572e4de4c..16f043b77d 100644 --- a/target/hexagon/imported/mmvec/encode_ext.def +++ b/target/hexagon/imported/mmvec/encode_ext.def @@ -868,4 +868,19 @@ DEF_ENC(V6_vgthf_or,"00011100100vvvvvPP1uuuuu001101xx") DEF_ENC(V6_vgtsf_xor,"00011100100vvvvvPP1uuuuu111010xx") DEF_ENC(V6_vgthf_xor,"00011100100vvvvvPP1uuuuu111011xx") =20 +/* BFLOAT instructions */ +DEF_ENC(V6_vmpy_sf_bf,"00011101010vvvvvPP1uuuuu100ddddd") +DEF_ENC(V6_vmpy_sf_bf_acc,"00011101000vvvvvPP1uuuuu000xxxxx") +DEF_ENC(V6_vadd_sf_bf,"00011101010vvvvvPP1uuuuu110ddddd") +DEF_ENC(V6_vsub_sf_bf,"00011101010vvvvvPP1uuuuu101ddddd") +DEF_ENC(V6_vmax_bf,"00011101010vvvvvPP1uuuuu111ddddd") +DEF_ENC(V6_vmin_bf,"00011101010vvvvvPP1uuuuu000ddddd") +DEF_ENC(V6_vcvt_bf_sf,"00011101010vvvvvPP1uuuuu011ddddd") + +/* BFLOAT compare instructions */ +DEF_ENC(V6_vgtbf,"00011100100vvvvvPP1uuuuu011110dd") +DEF_ENC(V6_vgtbf_and,"00011100100vvvvvPP1uuuuu110100xx") +DEF_ENC(V6_vgtbf_or,"00011100100vvvvvPP1uuuuu001110xx") +DEF_ENC(V6_vgtbf_xor,"00011100100vvvvvPP1uuuuu111100xx") + #endif /* NO MMVEC */ diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/import= ed/mmvec/ext.idef index a7043d598c..44135a8eea 100644 --- a/target/hexagon/imported/mmvec/ext.idef +++ b/target/hexagon/imported/mmvec/ext.idef @@ -3163,6 +3163,15 @@ ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_hf_h,"Vd32.hf= =3DVu32.h", } \ } =20 +#define VCMPGT_BF(DEST, ASRC, ASRCOP, CMP, N, SRC, MASK, WIDTH) \ +{ \ + fBFLOAT(); \ + for (fHIDE(int) i =3D 0; i < fVBYTES(); i +=3D WIDTH) { \ + fHIDE(int) VAL =3D fCMPGT_BF(VuV.SRC[i/WIDTH],VvV.SRC[i/WIDTH]) ? = MASK : 0; \ + fSETQBITS(DEST,WIDTH,MASK,i,ASRC ASRCOP VAL); \ + } \ +} + /* Vector SF compare */ #define MMVEC_CMPGT_SF(TYPE,TYPE2,DESCR,N,MASK,WIDTH,SRC) \ EXTINSN(V6_vgt##TYPE##_and, "Qx4&=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE= 2 ")", \ @@ -3201,8 +3210,61 @@ ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_hf_h,"Vd32.hf= =3DVu32.h", DESCR" greater than", \ VCMPGT_HF(QdV, , , ">", N, SRC, MASK, WIDTH)) =20 +/* Vector BF compare */ +#define MMVEC_CMPGT_BF(TYPE,TYPE2,DESCR,N,MASK,WIDTH,SRC) \ + EXTINSN(V6_vgt##TYPE##_and, "Qx4&=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE= 2 ")",\ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than with predicate-and", \ + VCMPGT_BF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), &, ">", N, SRC, MASK, = WIDTH)) \ + EXTINSN(V6_vgt##TYPE##_xor, "Qx4^=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE= 2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than with predicate-xor", \ + VCMPGT_BF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), ^, ">", N, SRC, MASK, = WIDTH)) \ + EXTINSN(V6_vgt##TYPE##_or, "Qx4|=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE2= ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than with predicate-or", \ + VCMPGT_BF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), |, ">", N, SRC, MASK, = WIDTH)) \ + EXTINSN(V6_vgt##TYPE, "Qd4=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than", \ + VCMPGT_BF(QdV, , , ">", N, SRC, MASK, WIDTH)) + MMVEC_CMPGT_SF(sf,"sf","Vector sf Compare ", fVELEM(32), 0xF, 4, sf) MMVEC_CMPGT_HF(hf,"hf","Vector hf Compare ", fVELEM(16), 0x3, 2, hf) +MMVEC_CMPGT_BF(bf,"bf","Vector bf Compare ", fVELEM(16), 0x3, 2, bf) + +/*************************************************************************= ***** + BFloat arithmetic and max/min instructions + *************************************************************************= *****/ + +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vadd_sf_bf, + "Vdd32.sf=3Dvadd(Vu32.bf,Vv32.bf)", "Vector IEEE add: bf widen to sf", + VddV.v[0].sf[i] =3D fp_add_sf_bf(VuV.bf[2*i], VvV.bf[2*i]); + VddV.v[1].sf[i] =3D fp_add_sf_bf(VuV.bf[2*i+1], VvV.bf[2*i+1]); fBFLOA= T()) +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vsub_sf_bf, + "Vdd32.sf=3Dvsub(Vu32.bf,Vv32.bf)", "Vector IEEE sub: bf widen to sf", + VddV.v[0].sf[i] =3D fp_sub_sf_bf(VuV.bf[2*i], VvV.bf[2*i]); + VddV.v[1].sf[i] =3D fp_sub_sf_bf(VuV.bf[2*i+1], VvV.bf[2*i+1]); fBFLOA= T()) +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_bf, + "Vdd32.sf=3Dvmpy(Vu32.bf,Vv32.bf)", "Vector IEEE mul: hf widen to sf", + VddV.v[0].sf[i] =3D fp_mult_sf_bf(VuV.bf[2*i], VvV.bf[2*i]); + VddV.v[1].sf[i] =3D fp_mult_sf_bf(VuV.bf[2*i+1], VvV.bf[2*i+1]); fBFLO= AT()) +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_bf_acc, + "Vxx32.sf+=3Dvmpy(Vu32.bf,Vv32.bf)", "Vector IEEE fma: hf widen to sf", + VxxV.v[0].sf[i] =3D fp_mult_sf_bf_acc(VuV.bf[2*i], VvV.bf[2*i], VxxV.v= [0].sf[i]); + VxxV.v[1].sf[i] =3D fp_mult_sf_bf_acc(VuV.bf[2*i+1], VvV.bf[2*i+1], Vx= xV.v[1].sf[i]); + fCVI_VX_NO_TMP_LD(); fBFLOAT()) +ITERATOR_INSN_IEEE_FP_16(32, vcvt_bf_sf, + "Vd32.bf=3Dvcvt(Vu32.sf,Vv32.sf)", "Vector IEEE cvt: sf to bf", + VdV.bf[2*i] =3D f32_to_bf16(VuV.sf[i], &env->hvx_fp_status); + VdV.bf[2*i+1] =3D f32_to_bf16(VvV.sf[i], &env->hvx_fp_status); fBFLOAT= ()) + +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vmax_bf, "Vd32.bf=3Dvmax(Vu32.bf,Vv32= .bf)", + "Vector IEEE max: bf", VdV.bf[i] =3D fp_max_bf(VuV.bf[i], VvV.bf[i]); + fBFLOAT()) +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vmin_bf, "Vd32.bf=3Dvmin(Vu32.bf,Vv32= .bf)", + "Vector IEEE max: bf", VdV.bf[i] =3D fp_min_bf(VuV.bf[i], VvV.bf[i]); + fBFLOAT()) =20 /*************************************************************************= ***** DEBUG Vector/Register Printing --=20 2.37.2 From nobody Sat Apr 11 17:07:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1775843998; cv=none; d=zohomail.com; s=zohoarc; b=a/Cs0hYb1AZwWoqFVKT87Y2rfyFv2cVciwy+Huy0H//tBXfTO6ugYlO9ggSt8UiFCM7avE3IHsY+WlF65hPitoJpXP3Dv7CKRb3Dc0g0kUtj9I9qt3O7Lsxolt8Gcq3bv8HCQgxs7be1ZNPMYLJ/XonJZJyond4kKlEMqMXa+SE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775843998; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775844000274158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino --- tests/tcg/hexagon/hex_test.h | 4 + tests/tcg/hexagon/hvx_misc.h | 41 ++++++++ tests/tcg/hexagon/fp_hvx.c | 155 ++++++++++++++++++++++++++++ tests/tcg/hexagon/fp_hvx_disabled.c | 57 ++++++++++ tests/tcg/hexagon/Makefile.target | 8 ++ 5 files changed, 265 insertions(+) create mode 100644 tests/tcg/hexagon/fp_hvx.c create mode 100644 tests/tcg/hexagon/fp_hvx_disabled.c diff --git a/tests/tcg/hexagon/hex_test.h b/tests/tcg/hexagon/hex_test.h index cfed06a58b..e7a6644d41 100644 --- a/tests/tcg/hexagon/hex_test.h +++ b/tests/tcg/hexagon/hex_test.h @@ -19,6 +19,8 @@ #ifndef HEX_TEST_H #define HEX_TEST_H =20 +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + static inline void __check32(int line, uint32_t val, uint32_t expect) { if (val !=3D expect) { @@ -110,6 +112,7 @@ static inline void __check64_ne(int line, uint64_t val,= uint64_t expect) =20 /* Some useful floating point values */ const uint32_t SF_INF =3D 0x7f800000; +const uint32_t SF_INF_neg =3D 0xff800000; const uint32_t SF_QNaN =3D 0x7fc00000; const uint32_t SF_QNaN_special =3D 0x7f800001; const uint32_t SF_SNaN =3D 0x7fb00000; @@ -128,6 +131,7 @@ const uint32_t SF_large_pos =3D 0x5afa572e; const uint32_t SF_any =3D 0x3f800000; const uint32_t SF_denorm =3D 0x00000001; const uint32_t SF_random =3D 0x346001d6; +const uint32_t SF_neg_two =3D 0xc0000000; =20 const uint64_t DF_QNaN =3D 0x7ff8000000000000ULL; const uint64_t DF_SNaN =3D 0x7ff7000000000000ULL; diff --git a/tests/tcg/hexagon/hvx_misc.h b/tests/tcg/hexagon/hvx_misc.h index 2e868340fd..0330cb289d 100644 --- a/tests/tcg/hexagon/hvx_misc.h +++ b/tests/tcg/hexagon/hvx_misc.h @@ -18,6 +18,8 @@ #ifndef HVX_MISC_H #define HVX_MISC_H =20 +#include "hex_test.h" + static inline void check(int line, int i, int j, uint64_t result, uint64_t expect) { @@ -34,8 +36,10 @@ typedef union { uint64_t ud[MAX_VEC_SIZE_BYTES / 8]; int64_t d[MAX_VEC_SIZE_BYTES / 8]; uint32_t uw[MAX_VEC_SIZE_BYTES / 4]; + uint32_t sf[MAX_VEC_SIZE_BYTES / 4]; /* convenience alias */ int32_t w[MAX_VEC_SIZE_BYTES / 4]; uint16_t uh[MAX_VEC_SIZE_BYTES / 2]; + uint16_t hf[MAX_VEC_SIZE_BYTES / 2]; /* convenience alias */ int16_t h[MAX_VEC_SIZE_BYTES / 2]; uint8_t ub[MAX_VEC_SIZE_BYTES / 1]; int8_t b[MAX_VEC_SIZE_BYTES / 1]; @@ -63,7 +67,9 @@ static inline void check_output_##FIELD(int line, size_t = num_vectors) \ =20 CHECK_OUTPUT_FUNC(d, 8) CHECK_OUTPUT_FUNC(w, 4) +CHECK_OUTPUT_FUNC(sf, 4) CHECK_OUTPUT_FUNC(h, 2) +CHECK_OUTPUT_FUNC(hf, 2) CHECK_OUTPUT_FUNC(b, 1) =20 static inline void init_buffers(void) @@ -81,6 +87,33 @@ static inline void init_buffers(void) } } =20 +static const uint32_t FP_VALUES[] =3D { + SF_INF, SF_INF_neg, SF_QNaN, SF_QNaN_special, SF_SNaN, SF_QNaN_neg, + SF_SNaN_neg, SF_HEX_NaN, SF_zero, SF_zero_neg, SF_one, SF_one_recip, + SF_one_invsqrta, SF_two, SF_four, SF_small_neg, SF_large_pos, SF_any, + SF_denorm, SF_random, SF_neg_two, +}; +#define FP_VALUES_MAX ARRAY_SIZE(FP_VALUES) + +static inline void init_buffers_fp(void) +{ + _Static_assert(BUFSIZE * (MAX_VEC_SIZE_BYTES / 4) > + FP_VALUES_MAX * FP_VALUES_MAX, + "test arrays can't fit all FP_VALUES combinations"); + int counter1 =3D 0, counter2 =3D 0; + for (int i =3D 0; i < BUFSIZE; i++) { + for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / 4; j++) { + buffer0[i].sf[j] =3D FP_VALUES[counter1]; + buffer1[i].sf[j] =3D FP_VALUES[counter2]; + counter2++; + if (counter2 =3D=3D FP_VALUES_MAX) { + counter2 =3D 0; + counter1 =3D (counter1 + 1) % FP_VALUES_MAX; + } + } + } +} + #define VEC_OP1(ASM, EL, IN, OUT) \ asm("v2 =3D vmem(%0 + #0)\n\t" \ "v2" #EL " =3D " #ASM "(v2" #EL ")\n\t" \ @@ -175,4 +208,12 @@ static inline void test_##NAME(bool invert) \ check_output_b(__LINE__, BUFSIZE); \ } =20 +#define float_sf(x) ({ typeof(x) _x =3D (x); *((float *)&(_x)); }) +#define float_hf(x) ({ typeof(x) _x =3D (x); *((_Float16 *) &(_x)); }) +#define raw_sf(x) ({ typeof(x) _x =3D (x); *((uint32_t *)&(_x)); }) +#define raw_hf(x) ({ typeof(x) _x =3D (x); *((uint16_t *)&(_x)); }) +#define float_hf_to_sf(x) ((float)x) +#define bytes_hf 2 +#define bytes_sf 4 + #endif diff --git a/tests/tcg/hexagon/fp_hvx.c b/tests/tcg/hexagon/fp_hvx.c new file mode 100644 index 0000000000..a309654ed7 --- /dev/null +++ b/tests/tcg/hexagon/fp_hvx.c @@ -0,0 +1,155 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include + +int err; +#include "hvx_misc.h" + +#if __HEXAGON_ARCH__ > 75 +#error "After v75, compiler will replace some FP HVX instructions." +#endif + +/*************************************************************************= ***** + * NAN handling + *************************************************************************= ****/ + +#define isnan(X) \ + (sizeof(X) =3D=3D bytes_hf ? ((raw_hf(X) & ~0x8000) > 0x7c00) : \ + ((raw_sf(X) & ~(1 << 31)) > 0x7f800000UL)) + +#define CHECK_NAN(A, DEF_NAN) (isnan(A) ? DEF_NAN : (A)) +#define NAN_SF float_sf(0x7FFFFFFF) +#define NAN_HF float_hf(0x7FFF) + +/*************************************************************************= ***** + * Binary operations + *************************************************************************= ****/ + +#define DEF_TEST_OP_2(vop, op, type_res, type_arg) \ + static void test_##vop##_##type_res##_##type_arg(void) \ + { \ + memset(expect, 0xff, sizeof(expect)); \ + memset(output, 0xff, sizeof(output)); \ + for (int i =3D 0; i < BUFSIZE; i++) { \ + HVX_Vector *hvx_output =3D (HVX_Vector *)&output[i]; \ + HVX_Vector hvx_buffer0 =3D *(HVX_Vector *)&buffer0[i]; \ + HVX_Vector hvx_buffer1 =3D *(HVX_Vector *)&buffer1[i]; \ + *hvx_output =3D \ + Q6_V##type_res##_##vop##_V##type_arg##V##type_arg(hvx_buff= er0, \ + hvx_buff= er1); \ + for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / bytes_##type_res; j= ++) { \ + expect[i].type_res[j] =3D \ + raw_##type_res(op(float_##type_arg(buffer0[i].type_arg= [j]), \ + float_##type_arg(buffer1[i].type_arg= [j]))); \ + } \ + } \ + check_output_##type_res(__LINE__, BUFSIZE); \ + } + +#define SUM(X, Y, DEF_NAN) CHECK_NAN((X) + (Y), DEF_NAN) +#define SUB(X, Y, DEF_NAN) CHECK_NAN((X) - (Y), DEF_NAN) +#define MULT(X, Y, DEF_NAN) CHECK_NAN((X) * (Y), DEF_NAN) + +#define SUM_SF(X, Y) SUM(X, Y, NAN_SF) +#define SUM_HF(X, Y) SUM(X, Y, NAN_HF) +#define SUB_SF(X, Y) SUB(X, Y, NAN_SF) +#define SUB_HF(X, Y) SUB(X, Y, NAN_HF) +#define MULT_SF(X, Y) MULT(X, Y, NAN_SF) +#define MULT_HF(X, Y) MULT(X, Y, NAN_HF) + +DEF_TEST_OP_2(vadd, SUM_SF, sf, sf); +DEF_TEST_OP_2(vadd, SUM_HF, hf, hf); +DEF_TEST_OP_2(vsub, SUB_SF, sf, sf); +DEF_TEST_OP_2(vsub, SUB_HF, hf, hf); +DEF_TEST_OP_2(vmpy, MULT_SF, sf, sf); +DEF_TEST_OP_2(vmpy, MULT_HF, hf, hf); + +/*************************************************************************= ***** + * Other tests + *************************************************************************= ****/ + +static void test_vdmpy_sf_hf(bool acc) +{ + memset(expect, 0xff, sizeof(expect)); + + for (int i =3D 0; i < BUFSIZE; i++) { + HVX_Vector hvx_buffer0 =3D *(HVX_Vector *)&buffer0[i]; + HVX_Vector hvx_buffer1 =3D *(HVX_Vector *)&buffer1[i]; + HVX_Vector *hvx_output =3D (HVX_Vector *)&output[i]; + + uint32_t PREFIL_VAL =3D 0x111222; + *hvx_output =3D Q6_V_vsplat_R(PREFIL_VAL); + + if (!acc) { + *hvx_output =3D Q6_Vsf_vdmpy_VhfVhf(hvx_buffer0, hvx_buffer1); + } else { + *hvx_output =3D Q6_Vsf_vdmpyacc_VsfVhfVhf(*hvx_output, hvx_buf= fer0, + hvx_buffer1); + } + + for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / 4; j++) { + float a1 =3D float_hf_to_sf(float_hf(buffer0[i].hf[2 * j + 1])= ); + float a2 =3D float_hf_to_sf(float_hf(buffer0[i].hf[2 * j])); + float a3 =3D float_hf_to_sf(float_hf(buffer1[i].hf[2 * j + 1])= ); + float a4 =3D float_hf_to_sf(float_hf(buffer1[i].hf[2 * j])); + /* + * Note, IEEE FP specifies +0.0 + -0.0 =3D=3D +0.0. So we use = -0.0 in + * the default case to preserve the zero sign. + */ + float prev =3D acc ? float_sf(PREFIL_VAL) : -0.0; + expect[i].sf[j] =3D raw_sf(CHECK_NAN((a1 * a3) + (a2 * a4) + p= rev, NAN_SF)); + } + } + check_output_sf(__LINE__, BUFSIZE); +} + +static void test_new(void) +{ + asm volatile("r0 =3D #%2\n" + "v0 =3D vsplat(r0)\n" + "vmem(%1 + #0) =3D v0\n" + "r1 =3D #%3\n" + "v1 =3D vsplat(r1)\n" + "v2 =3D vsplat(r1)\n" + "{\n" + " v0.sf =3D vadd(v1.sf, v2.sf)\n" + " vmem(%0 + #0) =3D v0.new\n" + "}\n" + : + : "r"(output), "r"(expect), "i"(SF_two), "i"(SF_one) + : "r0", "r1", "v0", "v1", "v2", "memory"); + check_output_w(__LINE__, 1); +} + +int main(void) +{ + init_buffers_fp(); + + /* add/sub */ + test_vadd_sf_sf(); + test_vadd_hf_hf(); + test_vsub_sf_sf(); + test_vsub_hf_hf(); + + /* multiply */ + test_vmpy_sf_sf(); + test_vmpy_hf_hf(); + + /* dot product */ + test_vdmpy_sf_hf(false); + test_vdmpy_sf_hf(true); + + test_new(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/fp_hvx_disabled.c b/tests/tcg/hexagon/fp_hvx= _disabled.c new file mode 100644 index 0000000000..388a42e2b7 --- /dev/null +++ b/tests/tcg/hexagon/fp_hvx_disabled.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include + +int err; +#include "hvx_misc.h" + +static void test_disabled(void) +{ + memset(output, 0xAA, sizeof(output)); + memset(expect, 0, sizeof(expect)); + asm volatile("r0 =3D #0xff\n" + "v0 =3D vsplat(r0)\n" + "r1 =3D #0x1\n" + "v1 =3D vsplat(r1)\n" + "v2 =3D vsplat(r1)\n" + "v0.sf =3D vadd(v1.sf, v2.sf)\n" + "vmem(%0 + #0) =3D v0\n" + : + : "r"(output) + : "r0", "r1", "v0", "v1", "v2", "memory"); + check_output_w(__LINE__, 1); +} + +static void test_disabled_with_new(void) +{ + memset(output, 0xAA, sizeof(output)); + memset(expect, 0, sizeof(expect)); + asm volatile("r0 =3D #0xff\n" + "v0 =3D vsplat(r0)\n" + "r1 =3D #0x1\n" + "v1 =3D vsplat(r1)\n" + "v2 =3D vsplat(r1)\n" + "{\n" + " v0.sf =3D vadd(v1.sf, v2.sf)\n" + " vmem(%0 + #0) =3D v0.new\n" + "}\n" + : + : "r"(output) + : "r0", "r1", "v0", "v1", "v2", "memory"); + check_output_w(__LINE__, 1); +} + +int main(void) +{ + test_disabled(); + test_disabled_with_new(); + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile= .target index 549c95082f..afd3dd6d19 100644 --- a/tests/tcg/hexagon/Makefile.target +++ b/tests/tcg/hexagon/Makefile.target @@ -50,6 +50,8 @@ HEX_TESTS +=3D vector_add_int HEX_TESTS +=3D scatter_gather HEX_TESTS +=3D hvx_misc HEX_TESTS +=3D hvx_histogram +HEX_TESTS +=3D fp_hvx +HEX_TESTS +=3D fp_hvx_disabled HEX_TESTS +=3D invalid-slots HEX_TESTS +=3D invalid-encoding HEX_TESTS +=3D multiple-writes @@ -126,6 +128,12 @@ v68_hvx: CFLAGS +=3D -mhvx -Wno-unused-function v69_hvx: v69_hvx.c hvx_misc.h v69_hvx: CFLAGS +=3D -mhvx -Wno-unused-function v73_scalar: CFLAGS +=3D -Wno-unused-function +fp_hvx: fp_hvx.c hvx_misc.h hex_test.h +fp_hvx: CFLAGS +=3D -mhvx -mhvx-ieee-fp +fp_hvx_disabled: fp_hvx_disabled.c hvx_misc.h hex_test.h +fp_hvx_disabled: CFLAGS +=3D -mhvx -mhvx-ieee-fp + +run-fp_hvx_disabled: QEMU_OPTS +=3D -cpu v73,ieee-fp=3Dfalse =20 hvx_histogram: hvx_histogram.c hvx_histogram_row.S $(CC) $(CFLAGS) $(CROSS_CC_GUEST_CFLAGS) $^ -o $@ $(LDFLAGS) --=20 2.37.2 From nobody Sat Apr 11 17:07:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1775843871; cv=none; d=zohomail.com; s=zohoarc; b=RcJ36Gbt64Vla/pOgSSIt7Bwc7XEvt9YjLBhX5A6rT9l66HcG+WVjuMGFAj6X4AZl2Bz1tYB4jSZWFBfJuwcvoEsdKb9wHUloeuANVLasPw3z1Jq0P1nsnUfc2GkXy29YS+U90+FC91Wp98HjfpcJ1yNNm3qNytqSPyt5HqbPzE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775843871; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6rsaGe+qyX7aGhkX5jlvph/v3y8P3SaLT96OgXBeU9M=; b=R/Z+HZNQqR3xUzPQBHZh4vn5mdz50xOuG68FF3dWx+Z6KN7U4MYZQ8TWbN4nGRBETJvdqpkFH9AY9pHjeGqhZh3GuJMCBtw5rQoty0Rtw46v+kpp4DYcLbRr2Lg44vut0H9foDDtdSeS6bsjklswdXTUDdqoez8a4XMhJU6BKvI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1775843871336109.35774348759321; Fri, 10 Apr 2026 10:57:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wBG5t-0006sk-DB; Fri, 10 Apr 2026 13:56:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wBG5p-0006qs-TV for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:33 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wBG5l-0001g0-TT for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:32 -0400 Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 63AHCYeG1498589 for ; Fri, 10 Apr 2026 17:56:22 GMT Received: from mail-dl1-f70.google.com (mail-dl1-f70.google.com [74.125.82.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dey5b1ctg-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 10 Apr 2026 17:56:21 +0000 (GMT) Received: by mail-dl1-f70.google.com with SMTP id a92af1059eb24-12c20a91932so4749161c88.1 for ; Fri, 10 Apr 2026 10:56:21 -0700 (PDT) Received: from hu-mathbern-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775843871705158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino --- tests/tcg/hexagon/fp_hvx.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/tests/tcg/hexagon/fp_hvx.c b/tests/tcg/hexagon/fp_hvx.c index a309654ed7..dee0781bd7 100644 --- a/tests/tcg/hexagon/fp_hvx.c +++ b/tests/tcg/hexagon/fp_hvx.c @@ -73,6 +73,30 @@ DEF_TEST_OP_2(vsub, SUB_HF, hf, hf); DEF_TEST_OP_2(vmpy, MULT_SF, sf, sf); DEF_TEST_OP_2(vmpy, MULT_HF, hf, hf); =20 +#define signbit_fp(X) \ + (sizeof(X) =3D=3D bytes_hf ? ((raw_hf(X) & 0x8000) !=3D 0) : \ + ((raw_sf(X) & 0x80000000) !=3D 0)) + +#define STD_MIN(X, Y) ((X) < (Y) ? (X) : (Y)) +#define STD_MAX(X, Y) ((X) > (Y) ? (X) : (Y)) + +#define MIN(X, Y, DEF_NAN) \ + ((isnan(X) || isnan(Y)) ? DEF_NAN : \ + ((X) !=3D (Y)) ? STD_MIN(X, Y) : (signbit_fp(X) ? (X) : (Y))) /* -0 <= +0 */ +#define MAX(X, Y, DEF_NAN) \ + ((isnan(X) || isnan(Y)) ? DEF_NAN : \ + ((X) !=3D (Y)) ? STD_MAX(X, Y) : (signbit_fp(X) ? (Y) : (X))) /* -0 <= +0 */ + +#define MIN_HF(X, Y) MIN(X, Y, NAN_HF) +#define MAX_HF(X, Y) MAX(X, Y, NAN_HF) +#define MIN_SF(X, Y) MIN(X, Y, NAN_SF) +#define MAX_SF(X, Y) MAX(X, Y, NAN_SF) + +DEF_TEST_OP_2(vfmin, MIN_SF, sf, sf); +DEF_TEST_OP_2(vfmax, MAX_SF, sf, sf); +DEF_TEST_OP_2(vfmin, MIN_HF, hf, hf); +DEF_TEST_OP_2(vfmax, MAX_HF, hf, hf); + /*************************************************************************= ***** * Other tests *************************************************************************= ****/ @@ -150,6 +174,12 @@ int main(void) =20 test_new(); =20 + /* min/max */ + test_vfmin_sf_sf(); + test_vfmin_hf_hf(); + test_vfmax_sf_sf(); + test_vfmax_hf_hf(); + puts(err ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775844004569154101 Content-Type: text/plain; charset="utf-8" Reviewed-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino --- tests/tcg/hexagon/hex_test.h | 14 +++ tests/tcg/hexagon/hvx_misc.h | 2 + tests/tcg/hexagon/fp_hvx_cvt.c | 188 ++++++++++++++++++++++++++++++ tests/tcg/hexagon/Makefile.target | 3 + 4 files changed, 207 insertions(+) create mode 100644 tests/tcg/hexagon/fp_hvx_cvt.c diff --git a/tests/tcg/hexagon/hex_test.h b/tests/tcg/hexagon/hex_test.h index e7a6644d41..d5da8ad240 100644 --- a/tests/tcg/hexagon/hex_test.h +++ b/tests/tcg/hexagon/hex_test.h @@ -111,6 +111,20 @@ static inline void __check64_ne(int line, uint64_t val= , uint64_t expect) "usr =3D r2\n\t" =20 /* Some useful floating point values */ +const uint16_t HF_INF =3D 0x7c00; +const uint16_t HF_INF_neg =3D 0xfc00; +const uint16_t HF_QNaN =3D 0x7e00; +const uint16_t HF_SNaN =3D 0x7d00; +const uint16_t HF_QNaN_neg =3D 0xfe00; +const uint16_t HF_zero =3D 0x0000; +const uint16_t HF_zero_neg =3D 0x8000; +const uint16_t HF_one =3D 0x3c00; +const uint16_t HF_one_recip =3D 0x3bf9; +const uint16_t HF_two =3D 0x4000; +const uint16_t HF_small_neg =3D 0x8010; +const uint16_t HF_any =3D 0x3c00; +const uint16_t HF_neg_two =3D 0xc000; + const uint32_t SF_INF =3D 0x7f800000; const uint32_t SF_INF_neg =3D 0xff800000; const uint32_t SF_QNaN =3D 0x7fc00000; diff --git a/tests/tcg/hexagon/hvx_misc.h b/tests/tcg/hexagon/hvx_misc.h index 0330cb289d..43de20da6a 100644 --- a/tests/tcg/hexagon/hvx_misc.h +++ b/tests/tcg/hexagon/hvx_misc.h @@ -69,7 +69,9 @@ CHECK_OUTPUT_FUNC(d, 8) CHECK_OUTPUT_FUNC(w, 4) CHECK_OUTPUT_FUNC(sf, 4) CHECK_OUTPUT_FUNC(h, 2) +CHECK_OUTPUT_FUNC(uh, 2) CHECK_OUTPUT_FUNC(hf, 2) +CHECK_OUTPUT_FUNC(ub, 1) CHECK_OUTPUT_FUNC(b, 1) =20 static inline void init_buffers(void) diff --git a/tests/tcg/hexagon/fp_hvx_cvt.c b/tests/tcg/hexagon/fp_hvx_cvt.c new file mode 100644 index 0000000000..71c3f0fd4f --- /dev/null +++ b/tests/tcg/hexagon/fp_hvx_cvt.c @@ -0,0 +1,188 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include + +#if __HEXAGON_ARCH__ > 75 +#error "After v75, compiler will replace some FP HVX instructions." +#endif + +int err; +#include "hvx_misc.h" +#include "hex_test.h" + +#define TEST_EXP(TO, FROM, VAL, EXP) do { \ + ((MMVector *)&buffer)->FROM[index] =3D VAL; \ + expect[0].TO[index] =3D EXP; \ + index++; \ +} while (0) + +#define DEF_TEST_CVT(TO, FROM, TESTS) \ + static void test_vcvt_##TO##_##FROM(void) \ + { \ + HVX_Vector *hvx_output =3D (HVX_Vector *)&output[0]; \ + HVX_Vector buffer; \ + int index =3D 0; \ + memset(&buffer, 0, sizeof(buffer)); \ + memset(expect, 0, sizeof(expect)); \ + TESTS \ + *hvx_output =3D Q6_V##TO##_vcvt_V##FROM(buffer); \ + check_output_##TO(__LINE__, 1); \ + } + +DEF_TEST_CVT(uh, hf, { \ + TEST_EXP(uh, hf, HF_QNaN, UINT16_MAX); \ + TEST_EXP(uh, hf, HF_SNaN, UINT16_MAX); \ + TEST_EXP(uh, hf, HF_QNaN_neg, UINT16_MAX); \ + TEST_EXP(uh, hf, HF_INF, UINT16_MAX); \ + TEST_EXP(uh, hf, HF_INF_neg, 0); \ + TEST_EXP(uh, hf, HF_neg_two, 0); \ + TEST_EXP(uh, hf, HF_zero_neg, 0); \ + TEST_EXP(uh, hf, raw_hf((_Float16)2.1), 2); \ + TEST_EXP(uh, hf, HF_one_recip, 1); \ +}) + +DEF_TEST_CVT(h, hf, { \ + TEST_EXP(h, hf, HF_QNaN, INT16_MAX); \ + TEST_EXP(h, hf, HF_SNaN, INT16_MAX); \ + TEST_EXP(h, hf, HF_QNaN_neg, INT16_MAX); \ + TEST_EXP(h, hf, HF_INF, INT16_MAX); \ + TEST_EXP(h, hf, HF_INF_neg, INT16_MIN); \ + TEST_EXP(h, hf, HF_neg_two, -2); \ + TEST_EXP(h, hf, HF_zero_neg, 0); \ + TEST_EXP(h, hf, raw_hf((_Float16)2.1), 2); \ + TEST_EXP(h, hf, HF_one_recip, 1); \ +}) + +/* + * Some cvt operations take two vectors as input and perform the following: + * VdV.TO[4*i] =3D OP(VuV.FROM[2*i]); + * VdV.TO[4*i+1] =3D OP(VuV.FROM[2*i+1]); + * VdV.TO[4*i+2] =3D OP(VvV.FROM[2*i]); + * VdV.TO[4*i+3] =3D OP(VvV.FROM[2*i+1])) + * We use bf_index and index in a way that the tests are always done either + * using the first or third line of the above snippet. + */ +#define TEST_EXP_2(TO, FROM, VAL, EXP) do { \ + ((MMVector *)&buffers[bf_index])->FROM[2 * index] =3D VAL; \ + expect[0].TO[(4 * index) + (2 * bf_index)] =3D EXP; \ + index++; \ + bf_index =3D (bf_index + 1) % 2; \ +} while (0) + +#define DEF_TEST_CVT_2(TO, FROM, TESTS) \ + static void test_vcvt_##TO##_##FROM(void) \ + { \ + HVX_Vector *hvx_output =3D (HVX_Vector *)&output[0]; \ + HVX_Vector buffers[2]; \ + int index =3D 0, bf_index =3D 0; \ + memset(&buffers, 0, sizeof(buffers)); \ + memset(expect, 0, sizeof(expect)); \ + TESTS \ + *hvx_output =3D Q6_V##TO##_vcvt_V##FROM##V##FROM(buffers[0], buffe= rs[1]); \ + check_output_##TO(__LINE__, 1); \ + } + +DEF_TEST_CVT_2(ub, hf, { \ + TEST_EXP_2(ub, hf, HF_QNaN, UINT8_MAX); \ + TEST_EXP_2(ub, hf, HF_SNaN, UINT8_MAX); \ + TEST_EXP_2(ub, hf, HF_QNaN_neg, UINT8_MAX); \ + TEST_EXP_2(ub, hf, HF_INF, UINT8_MAX); \ + TEST_EXP_2(ub, hf, HF_INF_neg, 0); \ + TEST_EXP_2(ub, hf, HF_small_neg, 0); \ + TEST_EXP_2(ub, hf, HF_neg_two, 0); \ + TEST_EXP_2(ub, hf, HF_zero_neg, 0); \ + TEST_EXP_2(ub, hf, raw_hf((_Float16)2.1), 2); \ + TEST_EXP_2(ub, hf, HF_one_recip, 1); \ +}) + +DEF_TEST_CVT_2(b, hf, { \ + TEST_EXP_2(b, hf, HF_QNaN, INT8_MAX); \ + TEST_EXP_2(b, hf, HF_SNaN, INT8_MAX); \ + TEST_EXP_2(b, hf, HF_QNaN_neg, INT8_MAX); \ + TEST_EXP_2(b, hf, HF_INF, INT8_MAX); \ + TEST_EXP_2(b, hf, HF_INF_neg, INT8_MIN); \ + TEST_EXP_2(b, hf, HF_small_neg, 0); \ + TEST_EXP_2(b, hf, HF_neg_two, -2); \ + TEST_EXP_2(b, hf, HF_zero_neg, 0); \ + TEST_EXP_2(b, hf, raw_hf((_Float16)2.1), 2); \ + TEST_EXP_2(b, hf, HF_one_recip, 1); \ +}) + +#define DEF_TEST_VCONV(TO, FROM, TESTS) \ + static void test_vconv_##TO##_##FROM(void) \ + { \ + HVX_Vector *hvx_output =3D (HVX_Vector *)&output[0]; \ + HVX_Vector buffer; \ + int index =3D 0; \ + memset(&buffer, 0, sizeof(buffer)); \ + memset(expect, 0, sizeof(expect)); \ + TESTS \ + *hvx_output =3D Q6_V##TO##_equals_V##FROM(buffer); \ + check_output_##TO(__LINE__, 1); \ + } + +DEF_TEST_VCONV(w, sf, { \ + TEST_EXP(w, sf, SF_QNaN, INT32_MAX); \ + TEST_EXP(w, sf, SF_SNaN, INT32_MAX); \ + TEST_EXP(w, sf, SF_QNaN_neg, INT32_MIN); \ + TEST_EXP(w, sf, SF_INF, INT32_MAX); \ + TEST_EXP(w, sf, SF_INF_neg, INT32_MIN); \ + TEST_EXP(w, sf, SF_small_neg, 0); \ + TEST_EXP(w, sf, SF_neg_two, -2); \ + TEST_EXP(w, sf, SF_zero_neg, 0); \ + TEST_EXP(w, sf, raw_sf(2.1f), 2); \ + TEST_EXP(w, sf, raw_sf(2.8f), 2); \ +}) + +DEF_TEST_VCONV(h, hf, { \ + TEST_EXP(h, hf, HF_QNaN, INT16_MAX); \ + TEST_EXP(h, hf, HF_SNaN, INT16_MAX); \ + TEST_EXP(h, hf, HF_QNaN_neg, INT16_MIN); \ + TEST_EXP(h, hf, HF_INF, INT16_MAX); \ + TEST_EXP(h, hf, HF_INF_neg, INT16_MIN); \ + TEST_EXP(h, hf, HF_small_neg, 0); \ + TEST_EXP(h, hf, HF_neg_two, -2); \ + TEST_EXP(h, hf, HF_zero_neg, 0); \ + TEST_EXP(h, hf, raw_hf((_Float16)2.1), 2); \ + TEST_EXP(h, hf, raw_hf((_Float16)2.8), 2); \ +}) + +DEF_TEST_VCONV(hf, h, { \ + TEST_EXP(hf, h, 0, HF_zero); \ + TEST_EXP(hf, h, 2, HF_two); \ + TEST_EXP(hf, h, -2, HF_neg_two); \ + TEST_EXP(hf, h, 2049, raw_hf((_Float16)2048)); /* rounds DOWN */ \ + TEST_EXP(hf, h, 2051, raw_hf((_Float16)2052)); /* rounds UP */ \ +}) + +DEF_TEST_VCONV(sf, w, { \ + TEST_EXP(sf, w, 0, SF_zero); \ + TEST_EXP(sf, w, 2, SF_two); \ + TEST_EXP(sf, w, -2, SF_neg_two); \ + TEST_EXP(sf, w, 16777217, raw_sf((float)16777216)); /* rounds DOWN */ \ + TEST_EXP(sf, w, 16777219, raw_sf((float)16777220)); /* rounds UP */ \ +}) + +int main(void) +{ + test_vcvt_uh_hf(); + test_vcvt_h_hf(); + test_vcvt_ub_hf(); + test_vcvt_b_hf(); + test_vconv_w_sf(); + test_vconv_sf_w(); + test_vconv_h_hf(); + test_vconv_hf_h(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile= .target index afd3dd6d19..1abc5f2124 100644 --- a/tests/tcg/hexagon/Makefile.target +++ b/tests/tcg/hexagon/Makefile.target @@ -51,6 +51,7 @@ HEX_TESTS +=3D scatter_gather HEX_TESTS +=3D hvx_misc HEX_TESTS +=3D hvx_histogram HEX_TESTS +=3D fp_hvx +HEX_TESTS +=3D fp_hvx_cvt HEX_TESTS +=3D fp_hvx_disabled HEX_TESTS +=3D invalid-slots HEX_TESTS +=3D invalid-encoding @@ -132,6 +133,8 @@ fp_hvx: fp_hvx.c hvx_misc.h hex_test.h fp_hvx: CFLAGS +=3D -mhvx -mhvx-ieee-fp fp_hvx_disabled: fp_hvx_disabled.c hvx_misc.h hex_test.h fp_hvx_disabled: CFLAGS +=3D -mhvx -mhvx-ieee-fp +fp_hvx_cvt: fp_hvx_cvt.c hvx_misc.h hex_test.h +fp_hvx_cvt: CFLAGS +=3D -mhvx -mhvx-ieee-fp =20 run-fp_hvx_disabled: QEMU_OPTS +=3D -cpu v73,ieee-fp=3Dfalse =20 --=20 2.37.2 From nobody Sat Apr 11 17:07:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1775843927; cv=none; d=zohomail.com; s=zohoarc; b=ji+R/GIfAs7ANlXC6HzQHgTpNn1AMhI0V0sFmbfu3x83aOpC25aDwEW4nKZR/7KeG1eFEMWnxahRlzDHN/JAVQVpGkM3Y8QwIDKDhbECeg6rEaPB4cvFMibILC5Y20x9ncD0dSHqdx0wRd3qeqEAjjJ+J78EiDjWXnUTMJdJyOA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775843927; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LeO91WsaGzVObVyI9P5c+YuXc4EOnwbcwp3Fwl89AnQ=; b=k45aIrNc6KINS4Uip2m65fy487zuPYDPnegpOk50ZpWG/uVZZJVDY8yKFBaf7SI2e/WOuqmbiuv3AG76TXYEb1UozqTE0gFIq2rEa55SJ2VWzVLhV1eSYB1fNgOloEx6b3VSv5fjrcQ+EqJ5R+JYzt/m4oN+4hCwt+aFgJs+Hj4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177584392793049.79047318848916; Fri, 10 Apr 2026 10:58:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wBG66-0006ug-3n; Fri, 10 Apr 2026 13:56:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wBG5y-0006u1-7U for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:42 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wBG5v-0001gG-UB for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:41 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 63AAp5lg3742884 for ; Fri, 10 Apr 2026 17:56:24 GMT Received: from mail-dl1-f70.google.com (mail-dl1-f70.google.com [74.125.82.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4deytnh8ur-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 10 Apr 2026 17:56:24 +0000 (GMT) Received: by mail-dl1-f70.google.com with SMTP id a92af1059eb24-12bf9974587so2583672c88.0 for ; Fri, 10 Apr 2026 10:56:24 -0700 (PDT) Received: from hu-mathbern-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775843929354154100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino --- tests/tcg/hexagon/hex_test.h | 1 + tests/tcg/hexagon/fp_hvx_cmp.c | 224 ++++++++++++++++++++++++++++++ tests/tcg/hexagon/Makefile.target | 3 + 3 files changed, 228 insertions(+) create mode 100644 tests/tcg/hexagon/fp_hvx_cmp.c diff --git a/tests/tcg/hexagon/hex_test.h b/tests/tcg/hexagon/hex_test.h index d5da8ad240..79d30ec61c 100644 --- a/tests/tcg/hexagon/hex_test.h +++ b/tests/tcg/hexagon/hex_test.h @@ -115,6 +115,7 @@ const uint16_t HF_INF =3D 0x7c00; const uint16_t HF_INF_neg =3D 0xfc00; const uint16_t HF_QNaN =3D 0x7e00; const uint16_t HF_SNaN =3D 0x7d00; +const uint16_t HF_SNaN_neg =3D 0xfd00; const uint16_t HF_QNaN_neg =3D 0xfe00; const uint16_t HF_zero =3D 0x0000; const uint16_t HF_zero_neg =3D 0x8000; diff --git a/tests/tcg/hexagon/fp_hvx_cmp.c b/tests/tcg/hexagon/fp_hvx_cmp.c new file mode 100644 index 0000000000..b1352c786a --- /dev/null +++ b/tests/tcg/hexagon/fp_hvx_cmp.c @@ -0,0 +1,224 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include +#include + +#if __HEXAGON_ARCH__ > 75 +#error "After v75, compiler will replace some FP HVX instructions." +#endif + +int err; +#include "hvx_misc.h" +#include "hex_test.h" + +#define MAX_TESTS_hf (MAX_VEC_SIZE_BYTES / 2) +#define MAX_TESTS_sf (MAX_VEC_SIZE_BYTES / 4) + +#define TRUE_MASK_sf 0xffffffff +#define TRUE_MASK_hf 0xffff + +static const char *comparisons[MAX_TESTS_sf][2]; +static HVX_Vector *hvx_output =3D (HVX_Vector *)&output[0]; +static HVX_Vector buffers[2], true_vec, false_vec; +static int exp_index; + +#define ADD_TEST_CMP(TYPE, VAL1, VAL2, EXP) do { \ + ((MMVector *)&buffers[0])->TYPE[exp_index] =3D VAL1; \ + ((MMVector *)&buffers[1])->TYPE[exp_index] =3D VAL2; \ + expect[0].TYPE[exp_index] =3D EXP ? TRUE_MASK_##TYPE : 0; \ + comparisons[exp_index][0] =3D #VAL1; \ + comparisons[exp_index][1] =3D #VAL2; \ + assert(exp_index < MAX_TESTS_##TYPE); \ + exp_index++; \ +} while (0) + +#define TEST_CMP_GT(TYPE, VAL1, VAL2) do { \ + ADD_TEST_CMP(TYPE, VAL1, VAL2, true); \ + ADD_TEST_CMP(TYPE, VAL2, VAL1, false); \ +} while (0) + +#define PREP_TEST() do { \ + memset(&buffers, 0, sizeof(buffers)); \ + memset(expect, 0, sizeof(expect)); \ + exp_index =3D 0; \ +} while (0) + +#define CHECK(TYPE, TYPESZ) do { \ + HVX_VectorPred pred =3D Q6_Q_vcmp_gt_V##TYPE##V##TYPE(buffers[0], buff= ers[1]); \ + *hvx_output =3D Q6_V_vmux_QVV(pred, true_vec, false_vec); \ + for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / TYPESZ; j++) { \ + if (output[0].TYPE[j] !=3D expect[0].TYPE[j]) { \ + printf("ERROR: expected %s %s %s\n", comparisons[j][0], \ + (expect[0].TYPE[j] !=3D 0 ? ">" : "<=3D"), comparisons[= j][1]); \ + err++; \ + } \ + } \ +} while (0) + +static void test_cmp_sf(void) +{ + /* + * General ordering for sf: + * QNaN > SNaN > +Inf > numbers > -Inf > SNaN_neg > QNaN_neg + */ + + /* Test equality */ + PREP_TEST(); + ADD_TEST_CMP(sf, raw_sf(2.2), raw_sf(2.2), false); + ADD_TEST_CMP(sf, SF_SNaN, SF_SNaN, false); + CHECK(sf, 4); + + /* Common numbers */ + PREP_TEST(); + TEST_CMP_GT(sf, raw_sf(2.2), raw_sf(2.1)); + TEST_CMP_GT(sf, raw_sf(0), raw_sf(-2.2)); + CHECK(sf, 4); + + /* Infinity vs Infinity/NaN */ + PREP_TEST(); + TEST_CMP_GT(sf, SF_QNaN, SF_INF); + TEST_CMP_GT(sf, SF_SNaN, SF_INF); + TEST_CMP_GT(sf, SF_INF, SF_INF_neg); + TEST_CMP_GT(sf, SF_INF, SF_SNaN_neg); + TEST_CMP_GT(sf, SF_INF, SF_QNaN_neg); + TEST_CMP_GT(sf, SF_INF_neg, SF_SNaN_neg); + TEST_CMP_GT(sf, SF_INF_neg, SF_QNaN_neg); + TEST_CMP_GT(sf, SF_SNaN, SF_INF_neg); + TEST_CMP_GT(sf, SF_QNaN, SF_INF_neg); + CHECK(sf, 4); + + /* NaN vs NaN */ + PREP_TEST(); + TEST_CMP_GT(sf, SF_QNaN, SF_SNaN); + TEST_CMP_GT(sf, SF_SNaN, SF_SNaN_neg); + TEST_CMP_GT(sf, SF_SNaN_neg, SF_QNaN_neg); + CHECK(sf, 4); + + /* NaN vs non-NaN */ + PREP_TEST(); + TEST_CMP_GT(sf, SF_QNaN, SF_one); + TEST_CMP_GT(sf, SF_SNaN, SF_one); + TEST_CMP_GT(sf, SF_one, SF_QNaN_neg); + TEST_CMP_GT(sf, SF_one, SF_SNaN_neg); + CHECK(sf, 4); +} + +static void test_cmp_hf(void) +{ + /* + * General ordering for hf: + * QNaN > SNaN > +Inf > numbers > -Inf > QSNaN_neg > QNaN_neg + */ + + /* Test equality */ + PREP_TEST(); + ADD_TEST_CMP(hf, raw_hf((_Float16)2.2), raw_hf((_Float16)2.2), false= ); + ADD_TEST_CMP(hf, HF_SNaN, HF_SNaN, false); + CHECK(hf, 2); + + /* Common numbers */ + PREP_TEST(); + TEST_CMP_GT(hf, raw_hf((_Float16)2.2), raw_hf((_Float16)2.1)); + TEST_CMP_GT(hf, raw_hf((_Float16)0), raw_hf((_Float16)-2.2)); + CHECK(hf, 2); + + /* Infinity vs Infinity/NaN */ + PREP_TEST(); + TEST_CMP_GT(hf, HF_QNaN, HF_INF); + TEST_CMP_GT(hf, HF_SNaN, HF_INF); + TEST_CMP_GT(hf, HF_INF, HF_INF_neg); + TEST_CMP_GT(hf, HF_INF, HF_SNaN_neg); + TEST_CMP_GT(hf, HF_INF, HF_QNaN_neg); + TEST_CMP_GT(hf, HF_INF_neg, HF_SNaN_neg); + TEST_CMP_GT(hf, HF_INF_neg, HF_QNaN_neg); + TEST_CMP_GT(hf, HF_SNaN, HF_INF_neg); + TEST_CMP_GT(hf, HF_QNaN, HF_INF_neg); + CHECK(hf, 2); + + /* NaN vs NaN */ + PREP_TEST(); + TEST_CMP_GT(hf, HF_QNaN, HF_SNaN); + TEST_CMP_GT(hf, HF_SNaN, HF_SNaN_neg); + TEST_CMP_GT(hf, HF_SNaN_neg, HF_QNaN_neg); + CHECK(hf, 2); + + /* NaN vs non-NaN */ + PREP_TEST(); + TEST_CMP_GT(hf, HF_QNaN, HF_one); + TEST_CMP_GT(hf, HF_SNaN, HF_one); + TEST_CMP_GT(hf, HF_one, HF_QNaN_neg); + TEST_CMP_GT(hf, HF_one, HF_SNaN_neg); + CHECK(hf, 2); +} + +static void check_byte_pred(HVX_VectorPred pred, int byte_idx, uint8_t exp= _mask, + int line) +{ + /* + * Note: ((uint8_t *)&pred)[N] returns the expanded value of bit N: + * 0xFF if bit is set, 0x00 if clear. + */ + for (int i =3D 0; i < 8; i++) { + int idx =3D byte_idx * 8 + i; + int val =3D ((uint8_t *)&pred)[idx]; + int exp =3D (exp_mask >> i) & 1 ? 0xff : 0x00; + if (exp !=3D val) { + printf("ERROR line %d: pred bit %d is 0x%x, should be 0x%x\n", + line, idx, val, exp); + err++; + } + } +} + +#define CHECK_BYTE_PRED(PRED, BYTE, EXP) check_byte_pred(PRED, BYTE, EXP, = __LINE__) + +static void test_cmp_variants(void) +{ + HVX_VectorPred pred; + + /* + * Setup: comparison result will have bits 4-7 set (0xF0 in pred byte = 0) + * - sf[0]: SF_zero > SF_one =3D false -> bits 0-3 =3D 0 + * - sf[1]: SF_one > SF_zero =3D true -> bits 4-7 =3D 1 + */ + PREP_TEST(); + ADD_TEST_CMP(sf, SF_zero, SF_one, false); + ADD_TEST_CMP(sf, SF_one, SF_zero, true); + + /* greater and: 0xF0 & 0xF0 =3D 0xF0 */ + memset(&pred, 0xF0, sizeof(pred)); + pred =3D Q6_Q_vcmp_gtand_QVsfVsf(pred, buffers[0], buffers[1]); + CHECK_BYTE_PRED(pred, 0, 0xF0); + + /* greater or: 0x0F | 0xF0 =3D 0xFF */ + memset(&pred, 0x0F, sizeof(pred)); + pred =3D Q6_Q_vcmp_gtor_QVsfVsf(pred, buffers[0], buffers[1]); + CHECK_BYTE_PRED(pred, 0, 0xFF); + + /* greater xor: 0xFF ^ 0xF0 =3D 0x0F */ + memset(&pred, 0xFF, sizeof(pred)); + pred =3D Q6_Q_vcmp_gtxacc_QVsfVsf(pred, buffers[0], buffers[1]); + CHECK_BYTE_PRED(pred, 0, 0x0F); +} + +int main(void) +{ + memset(&true_vec, 0xff, sizeof(true_vec)); + memset(&false_vec, 0, sizeof(false_vec)); + + test_cmp_sf(); + test_cmp_hf(); + test_cmp_variants(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile= .target index 1abc5f2124..92bdedf661 100644 --- a/tests/tcg/hexagon/Makefile.target +++ b/tests/tcg/hexagon/Makefile.target @@ -52,6 +52,7 @@ HEX_TESTS +=3D hvx_misc HEX_TESTS +=3D hvx_histogram HEX_TESTS +=3D fp_hvx HEX_TESTS +=3D fp_hvx_cvt +HEX_TESTS +=3D fp_hvx_cmp HEX_TESTS +=3D fp_hvx_disabled HEX_TESTS +=3D invalid-slots HEX_TESTS +=3D invalid-encoding @@ -135,6 +136,8 @@ fp_hvx_disabled: fp_hvx_disabled.c hvx_misc.h hex_test.h fp_hvx_disabled: CFLAGS +=3D -mhvx -mhvx-ieee-fp fp_hvx_cvt: fp_hvx_cvt.c hvx_misc.h hex_test.h fp_hvx_cvt: CFLAGS +=3D -mhvx -mhvx-ieee-fp +fp_hvx_cmp: fp_hvx_cmp.c hvx_misc.h hex_test.h +fp_hvx_cmp: CFLAGS +=3D -mhvx -mhvx-ieee-fp =20 run-fp_hvx_disabled: QEMU_OPTS +=3D -cpu v73,ieee-fp=3Dfalse =20 --=20 2.37.2 From nobody Sat Apr 11 17:07:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1775844008; cv=none; d=zohomail.com; s=zohoarc; b=Pa3BDlyTmbMhJ6xQrUJXZvLyViLXbd+Ig5aUyzCkFZEEPweOz2yf3XU9ap+fTxsVcrqbfzXuYah3qdcChT6pe8hR4o6/Mhle++lHWCJE1PKoOSwvxptjpfa1EPQnnkPc8bYAvD9WQ+wyV1NxIq+BjP82WmqFq9co4KRpL3xXHDw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775844008; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SKbFbkmU8wzfvxxCTkNuC/9i5QQ14DJJHG483Q4/4f4=; b=NRq69yzzw5EuHdhuLBTDuwlSZGiyjjeSBbzNbM3qcWc4CddYB3oCKfhzShyPOHLOUPEzkdwqXp0pj9TGqW43Rz/O0OdHDC7yAn9wu2/YgEyqlMV6ApL5C3VHTbb1PTiUKyD1up/dimfDe10vtAJUtFpm72WHpt47jEqctpYtZ0M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1775844008619777.3400334743122; Fri, 10 Apr 2026 11:00:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wBG5u-0006sp-8c; Fri, 10 Apr 2026 13:56:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wBG5r-0006ro-Ri for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:35 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wBG5l-0001gM-Th for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:33 -0400 Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 63AH46if1498620 for ; Fri, 10 Apr 2026 17:56:25 GMT Received: from mail-dl1-f71.google.com (mail-dl1-f71.google.com [74.125.82.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dey5b1ctp-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 10 Apr 2026 17:56:25 +0000 (GMT) Received: by mail-dl1-f71.google.com with SMTP id a92af1059eb24-12c21dbc9c1so4625582c88.0 for ; Fri, 10 Apr 2026 10:56:25 -0700 (PDT) Received: from hu-mathbern-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775844010342158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino --- tests/tcg/hexagon/hex_test.h | 13 +++++++++ tests/tcg/hexagon/hvx_misc.h | 30 ++++++++++++++++++++ tests/tcg/hexagon/fp_hvx.c | 41 +++++++++++++++++++++++++++ tests/tcg/hexagon/fp_hvx_cmp.c | 51 ++++++++++++++++++++++++++++++++++ tests/tcg/hexagon/fp_hvx_cvt.c | 31 +++++++++++++++++++++ 5 files changed, 166 insertions(+) diff --git a/tests/tcg/hexagon/hex_test.h b/tests/tcg/hexagon/hex_test.h index 79d30ec61c..f86e6e1a69 100644 --- a/tests/tcg/hexagon/hex_test.h +++ b/tests/tcg/hexagon/hex_test.h @@ -126,6 +126,19 @@ const uint16_t HF_small_neg =3D 0x8010; const uint16_t HF_any =3D 0x3c00; const uint16_t HF_neg_two =3D 0xc000; =20 +const uint16_t BF_INF =3D 0x7f80; +const uint16_t BF_INF_neg =3D 0xff80; +const uint16_t BF_QNaN =3D 0x7fc0; +const uint16_t BF_SNaN =3D 0x7f81; +const uint16_t BF_QNaN_neg =3D 0xffc0; +const uint16_t BF_SNaN_neg =3D 0xff81; +const uint16_t BF_HEX_NaN =3D 0x7fff; +const uint16_t BF_zero =3D 0x0000; +const uint16_t BF_zero_neg =3D 0x8000; +const uint16_t BF_one =3D 0x3f80; +const uint16_t BF_two =3D 0x4000; +const uint16_t BF_four =3D 0x4080; + const uint32_t SF_INF =3D 0x7f800000; const uint32_t SF_INF_neg =3D 0xff800000; const uint32_t SF_QNaN =3D 0x7fc00000; diff --git a/tests/tcg/hexagon/hvx_misc.h b/tests/tcg/hexagon/hvx_misc.h index 43de20da6a..c21ea975c1 100644 --- a/tests/tcg/hexagon/hvx_misc.h +++ b/tests/tcg/hexagon/hvx_misc.h @@ -41,6 +41,7 @@ typedef union { uint16_t uh[MAX_VEC_SIZE_BYTES / 2]; uint16_t hf[MAX_VEC_SIZE_BYTES / 2]; /* convenience alias */ int16_t h[MAX_VEC_SIZE_BYTES / 2]; + uint16_t bf[MAX_VEC_SIZE_BYTES / 2]; uint8_t ub[MAX_VEC_SIZE_BYTES / 1]; int8_t b[MAX_VEC_SIZE_BYTES / 1]; } MMVector; @@ -73,6 +74,7 @@ CHECK_OUTPUT_FUNC(uh, 2) CHECK_OUTPUT_FUNC(hf, 2) CHECK_OUTPUT_FUNC(ub, 1) CHECK_OUTPUT_FUNC(b, 1) +CHECK_OUTPUT_FUNC(bf, 2) =20 static inline void init_buffers(void) { @@ -97,6 +99,12 @@ static const uint32_t FP_VALUES[] =3D { }; #define FP_VALUES_MAX ARRAY_SIZE(FP_VALUES) =20 +static const uint16_t BF_VALUES[] =3D { + BF_INF, BF_INF_neg, BF_QNaN, BF_SNaN, BF_QNaN_neg, BF_SNaN_neg, + BF_HEX_NaN, BF_zero, BF_zero_neg, BF_one, BF_two, BF_four, +}; +#define BF_VALUES_MAX ARRAY_SIZE(BF_VALUES) + static inline void init_buffers_fp(void) { _Static_assert(BUFSIZE * (MAX_VEC_SIZE_BYTES / 4) > @@ -116,6 +124,25 @@ static inline void init_buffers_fp(void) } } =20 +static inline void init_buffers_bf(void) +{ + _Static_assert(BUFSIZE * (MAX_VEC_SIZE_BYTES / 2) > + BF_VALUES_MAX * BF_VALUES_MAX, + "test arrays can't fit all BF_VALUES combinations"); + int counter1 =3D 0, counter2 =3D 0; + for (int i =3D 0; i < BUFSIZE; i++) { + for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / 2; j++) { + buffer0[i].bf[j] =3D BF_VALUES[counter1]; + buffer1[i].bf[j] =3D BF_VALUES[counter2]; + counter2++; + if (counter2 =3D=3D BF_VALUES_MAX) { + counter2 =3D 0; + counter1 =3D (counter1 + 1) % BF_VALUES_MAX; + } + } + } +} + #define VEC_OP1(ASM, EL, IN, OUT) \ asm("v2 =3D vmem(%0 + #0)\n\t" \ "v2" #EL " =3D " #ASM "(v2" #EL ")\n\t" \ @@ -212,10 +239,13 @@ static inline void test_##NAME(bool invert) \ =20 #define float_sf(x) ({ typeof(x) _x =3D (x); *((float *)&(_x)); }) #define float_hf(x) ({ typeof(x) _x =3D (x); *((_Float16 *) &(_x)); }) +#define float_bf(x) ({ uint32_t _u =3D ((uint32_t)(x)) << 16; *((float *)&= (_u)); }) #define raw_sf(x) ({ typeof(x) _x =3D (x); *((uint32_t *)&(_x)); }) #define raw_hf(x) ({ typeof(x) _x =3D (x); *((uint16_t *)&(_x)); }) +#define raw_bf(x) ({ typeof(x) _x =3D (x); (uint16_t)(*((uint32_t *)&(_x))= >> 16); }) #define float_hf_to_sf(x) ((float)x) #define bytes_hf 2 #define bytes_sf 4 +#define bytes_bf 2 =20 #endif diff --git a/tests/tcg/hexagon/fp_hvx.c b/tests/tcg/hexagon/fp_hvx.c index dee0781bd7..4543a0aa8c 100644 --- a/tests/tcg/hexagon/fp_hvx.c +++ b/tests/tcg/hexagon/fp_hvx.c @@ -29,6 +29,7 @@ int err; #define CHECK_NAN(A, DEF_NAN) (isnan(A) ? DEF_NAN : (A)) #define NAN_SF float_sf(0x7FFFFFFF) #define NAN_HF float_hf(0x7FFF) +#define NAN_BF float_hf(0x7FFF) =20 /*************************************************************************= ***** * Binary operations @@ -91,11 +92,43 @@ DEF_TEST_OP_2(vmpy, MULT_HF, hf, hf); #define MAX_HF(X, Y) MAX(X, Y, NAN_HF) #define MIN_SF(X, Y) MIN(X, Y, NAN_SF) #define MAX_SF(X, Y) MAX(X, Y, NAN_SF) +#define MIN_BF(X, Y) MIN(X, Y, NAN_BF) +#define MAX_BF(X, Y) MAX(X, Y, NAN_BF) =20 DEF_TEST_OP_2(vfmin, MIN_SF, sf, sf); DEF_TEST_OP_2(vfmax, MAX_SF, sf, sf); DEF_TEST_OP_2(vfmin, MIN_HF, hf, hf); DEF_TEST_OP_2(vfmax, MAX_HF, hf, hf); +DEF_TEST_OP_2(vmin, MIN_BF, bf, bf); +DEF_TEST_OP_2(vmax, MAX_BF, bf, bf); + +#define DEF_TEST_OP_2_INTERLEAVED(vop, op, type_res, type_arg) \ + static void test_##vop##_##type_res##_##type_arg(void) \ + { \ + memset(expect, 0xff, sizeof(expect)); \ + memset(output, 0xff, sizeof(output)); \ + for (int i =3D 0; i < BUFSIZE / 2; i++) { \ + HVX_VectorPair *hvx_output =3D (HVX_VectorPair *)&output[2 * i= ]; \ + HVX_Vector hvx_buffer0 =3D *(HVX_Vector *)&buffer0[i]; \ + HVX_Vector hvx_buffer1 =3D *(HVX_Vector *)&buffer1[i]; \ + *hvx_output =3D \ + Q6_W##type_res##_##vop##_V##type_arg##V##type_arg(hvx_buff= er0, \ + hvx_buff= er1); \ + for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / bytes_##type_res; j= ++) { \ + expect[2 * i].type_res[j] =3D \ + raw_##type_res(op(float_##type_arg(buffer0[i].type_arg= [2 * j]), \ + float_##type_arg(buffer1[i].type_arg= [2 * j]))); \ + expect[2 * i + 1].type_res[j] =3D \ + raw_##type_res(op(float_##type_arg(buffer0[i].type_arg= [2 * j + 1]), \ + float_##type_arg(buffer1[i].type_arg[2= * j + 1]))); \ + } \ + } \ + check_output_##type_res(__LINE__, BUFSIZE); \ + } + +DEF_TEST_OP_2_INTERLEAVED(vadd, SUM_SF, sf, bf); +DEF_TEST_OP_2_INTERLEAVED(vsub, SUB_SF, sf, bf); +DEF_TEST_OP_2_INTERLEAVED(vmpy, MULT_SF, sf, bf); =20 /*************************************************************************= ***** * Other tests @@ -180,6 +213,14 @@ int main(void) test_vfmax_sf_sf(); test_vfmax_hf_hf(); =20 + /* bfloat */ + init_buffers_bf(); + test_vmin_bf_bf(); + test_vmax_bf_bf(); + test_vadd_sf_bf(); + test_vsub_sf_bf(); + test_vmpy_sf_bf(); + puts(err ? "FAIL" : "PASS"); return err ? 1 : 0; } diff --git a/tests/tcg/hexagon/fp_hvx_cmp.c b/tests/tcg/hexagon/fp_hvx_cmp.c index b1352c786a..22c18bc299 100644 --- a/tests/tcg/hexagon/fp_hvx_cmp.c +++ b/tests/tcg/hexagon/fp_hvx_cmp.c @@ -22,9 +22,11 @@ int err; =20 #define MAX_TESTS_hf (MAX_VEC_SIZE_BYTES / 2) #define MAX_TESTS_sf (MAX_VEC_SIZE_BYTES / 4) +#define MAX_TESTS_bf (MAX_VEC_SIZE_BYTES / 2) =20 #define TRUE_MASK_sf 0xffffffff #define TRUE_MASK_hf 0xffff +#define TRUE_MASK_bf 0xffff =20 static const char *comparisons[MAX_TESTS_sf][2]; static HVX_Vector *hvx_output =3D (HVX_Vector *)&output[0]; @@ -160,6 +162,54 @@ static void test_cmp_hf(void) CHECK(hf, 2); } =20 +static void test_cmp_bf(void) +{ + /* + * General ordering for bf: + * QNaN > SNaN > +Inf > numbers > -Inf > SNaN_neg > QNaN_neg + */ + + /* Test equality */ + PREP_TEST(); + ADD_TEST_CMP(bf, 0, 0, false); + ADD_TEST_CMP(bf, BF_SNaN, BF_SNaN, false); + CHECK(bf, 2); + + /* Common numbers */ + PREP_TEST(); + TEST_CMP_GT(bf, raw_hf((_Float16)2.2), raw_hf((_Float16)2.1)); + TEST_CMP_GT(bf, raw_hf((_Float16)0), raw_hf((_Float16)-2.2)); + CHECK(bf, 2); + + /* Infinity vs Infinity/NaN */ + PREP_TEST(); + TEST_CMP_GT(bf, BF_QNaN, BF_INF); + TEST_CMP_GT(bf, BF_SNaN, BF_INF); + TEST_CMP_GT(bf, BF_INF, BF_INF_neg); + TEST_CMP_GT(bf, BF_INF, BF_SNaN_neg); + TEST_CMP_GT(bf, BF_INF, BF_QNaN_neg); + TEST_CMP_GT(bf, BF_INF_neg, BF_SNaN_neg); + TEST_CMP_GT(bf, BF_INF_neg, BF_QNaN_neg); + TEST_CMP_GT(bf, BF_SNaN, BF_INF_neg); + TEST_CMP_GT(bf, BF_QNaN, BF_INF_neg); + CHECK(bf, 2); + + /* NaN vs NaN */ + PREP_TEST(); + TEST_CMP_GT(bf, BF_QNaN, BF_SNaN); + TEST_CMP_GT(bf, BF_SNaN, BF_SNaN_neg); + TEST_CMP_GT(bf, BF_SNaN_neg, BF_QNaN_neg); + CHECK(bf, 2); + + /* NaN vs non-NaN */ + PREP_TEST(); + TEST_CMP_GT(bf, BF_QNaN, BF_one); + TEST_CMP_GT(bf, BF_SNaN, BF_one); + TEST_CMP_GT(bf, BF_one, BF_QNaN_neg); + TEST_CMP_GT(bf, BF_one, BF_SNaN_neg); + CHECK(bf, 2); +} + static void check_byte_pred(HVX_VectorPred pred, int byte_idx, uint8_t exp= _mask, int line) { @@ -217,6 +267,7 @@ int main(void) =20 test_cmp_sf(); test_cmp_hf(); + test_cmp_bf(); test_cmp_variants(); =20 puts(err ? "FAIL" : "PASS"); diff --git a/tests/tcg/hexagon/fp_hvx_cvt.c b/tests/tcg/hexagon/fp_hvx_cvt.c index 71c3f0fd4f..bd8d39d6b6 100644 --- a/tests/tcg/hexagon/fp_hvx_cvt.c +++ b/tests/tcg/hexagon/fp_hvx_cvt.c @@ -19,6 +19,8 @@ int err; #include "hvx_misc.h" #include "hex_test.h" =20 +#define NAN_BF 0x7FFF + #define TEST_EXP(TO, FROM, VAL, EXP) do { \ ((MMVector *)&buffer)->FROM[index] =3D VAL; \ expect[0].TO[index] =3D EXP; \ @@ -172,6 +174,34 @@ DEF_TEST_VCONV(sf, w, { \ TEST_EXP(sf, w, 16777219, raw_sf((float)16777220)); /* rounds UP */ \ }) =20 +#define TEST_EXP_BF(VAL, EXP) do { \ + ((MMVector *)&buffers[1])->sf[index] =3D VAL; \ + ((MMVector *)&buffers[0])->sf[index] =3D VAL; \ + expect[0].bf[2 * index] =3D EXP; \ + expect[0].bf[2 * index + 1] =3D EXP; \ + index++; \ +} while (0) + +static void test_vconv_bf_sf(void) +{ + HVX_Vector *hvx_output =3D (HVX_Vector *)&output[0]; + HVX_Vector buffers[2]; + int index =3D 0; + memset(&buffers, 0, sizeof(buffers)); + memset(expect, 0, sizeof(expect)); + + TEST_EXP_BF(SF_QNaN, NAN_BF); + TEST_EXP_BF(SF_SNaN, NAN_BF); + TEST_EXP_BF(SF_QNaN_neg, NAN_BF); + TEST_EXP_BF(SF_INF, BF_INF); + TEST_EXP_BF(SF_INF_neg, BF_INF_neg); + TEST_EXP_BF(SF_one, BF_one); + TEST_EXP_BF(SF_zero_neg, BF_zero_neg); + + *hvx_output =3D Q6_Vbf_vcvt_VsfVsf(buffers[0], buffers[1]); + check_output_hf(__LINE__, 1); +} + int main(void) { test_vcvt_uh_hf(); @@ -182,6 +212,7 @@ int main(void) test_vconv_sf_w(); test_vconv_h_hf(); test_vconv_hf_h(); + test_vconv_bf_sf(); =20 puts(err ? "FAIL" : "PASS"); return err ? 1 : 0; --=20 2.37.2