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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.04.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:04:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411052; x=1770015852; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T2xUEoYpnLX+y7kFhG9JXWkUeGWlapfsje21sWW5Bcs=; b=bRzN3zRfCqYHxLRYzZXXwDivnHVZquUwbJqLtqyDhJtZidE2+6byVatS6BX0X8nVHp 6RMLjAXw14g/CqM05/iUABa3xfYwkHxhIlPFYGC/hB5y85hpB1NEkU9OCbG0hzEjIlKZ OacGPsMVi24SX8U3c99FWYeFubyr2XGNqHHPWnPL4Jlh1j9Y6QKmwtSSXahXbx/w1cI6 WGYDl1vAQHJLPhau6i8okQxpKpEqAyjjxS14T9l++UV+ii+lrPy2mZR+nw4QpsC5aK7l u44ZC0DxiAW49pZ+25IV4Z9rVLMfzoeliNxDWQEFiAK/RCUqprh9CX0YzjxhPm9M4Q+P 9adg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411052; x=1770015852; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=T2xUEoYpnLX+y7kFhG9JXWkUeGWlapfsje21sWW5Bcs=; b=ReAQwv1/NKceNdFnXkzUXfT64UdpVEdJmgTGEp0vIiIgAOe/zAPNcicxZmxi/n40p3 QNtlU/TXNfBwOdPKrWsjWbenUQFYMuHIYkY9qE9rKsLTNmzWB7e49zJDfeTQyqAXqjQz Nyudp3eimXK9O/ZSBiDDVoWH3jvxiLgzj5JGiBfETShEe0M8TNbm+MAklmD6D0YKhNL9 r8dqLx3pa+EZH0WXP15fY6Dd0viFZEfuVclTUgj0A0NX4TyNmJRBkRNbNZ6z1mT1IqTD c6Ei1P+YzyoPvnN1hbCwQ6ZACCu8L02M9taRmZJVLGdXUcA6yTD+U7CnV8bGP6p1l1cd G97g== X-Gm-Message-State: AOJu0YzDpvEjEapG4QrsHkO11jiVP/q3mXJ3nQ7IrLS92207vYd/lbeN WJPUVNysGz2quio8DzPYwXAgTDuqxfjCOgqSibywjYclH5wx5c6kTUTpn8ylbfg5 X-Gm-Gg: AZuq6aItxYOOuBUMV1HevPtQGOnKh8we6hNMz20Xb8U7Lm4Uff1jRl5P6oJNUryHecP 3D7HyIbjOuLZ2hj1PVMVeUf/MyNZXjQL0YsZ0WM991nvpdtD0SHQdDE+WaRL1NcACba1fky1hT2 jy0ncMozKpBCr76Xs+FRzckU7bpVlGI9zbNDtcPytOYLeMqm34THOcYF3lQW0vrAV3tBSSZP93e 8GxqwVwB3ZfHzu89AGmYxGqTCWWHufADbxVekHMMSPrOwUL9rIROD92Qaf/GPqb+u7r2zGc/UvM Xk0Pqa5HWa56X6tKyy0BpvfWVjKQ0GogO6f3Ase6gM6t8OKhso5P234xyyMbgwi0qj9OSKtK1St yzHAvjVq0+TeT/1df/BbOPd/SYBKGTiAKqtuSAEF5eY1atjbZrh9kky1UwdgHNc898ZT8qLxhVw /USyxKJSXPWwqw7ulugGYkA8oLG2xuaSAQWAwcOX0F5w== X-Received: by 2002:a05:6a00:12e2:b0:81e:8e66:38d8 with SMTP id d2e1a72fcca58-823411dbc89mr3190318b3a.10.1769411052479; Sun, 25 Jan 2026 23:04:12 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 01/33] tcg/wasm64: Add tcg-target.h Date: Mon, 26 Jan 2026 07:03:14 +0000 Message-ID: <1061c734ff63e09ea0544ebecf09abfd6fc25b11.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412783790158500 Content-Type: text/plain; charset="utf-8" Since WebAssembly instructions vary in size and can include single-byte instructions, TCG_TARGET_INSN_UNIT_SIZE is set to 1. Signed-off-by: Kohei Tokunaga --- MAINTAINERS | 5 ++++ tcg/wasm64/tcg-target.h | 61 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) create mode 100644 tcg/wasm64/tcg-target.h V4: - Removed tcg-target-reg-bits.h as the 32bit support has been removed and TCG_TARGET_REG_BITS is no longer needed. diff --git a/MAINTAINERS b/MAINTAINERS index c1e586c58f..470b15eeb7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4107,6 +4107,11 @@ F: tcg/tci/ F: tcg/tci.c F: disas/tci.c =20 +WebAssembly TCG target +M: Kohei Tokunaga +S: Maintained +F: tcg/wasm64/ + Block drivers ------------- VMDK diff --git a/tcg/wasm64/tcg-target.h b/tcg/wasm64/tcg-target.h new file mode 100644 index 0000000000..f00761d19f --- /dev/null +++ b/tcg/wasm64/tcg-target.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Tiny Code Generator for QEMU + * + * Based on tci/tcg-target.h + * + * Copyright (c) 2009, 2011 Stefan Weil + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef TCG_TARGET_H +#define TCG_TARGET_H + +#define TCG_TARGET_INSN_UNIT_SIZE 1 +#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) + +/* Number of registers available. */ +#define TCG_TARGET_NB_REGS 16 + +/* List of registers which are used by TCG. */ +typedef enum { + TCG_REG_R0 =3D 0, + TCG_REG_R1, + TCG_REG_R2, + TCG_REG_R3, + TCG_REG_R4, + TCG_REG_R5, + TCG_REG_R6, + TCG_REG_R7, + TCG_REG_R8, + TCG_REG_R9, + TCG_REG_R10, + TCG_REG_R11, + TCG_REG_R12, + TCG_REG_R13, + TCG_REG_R14, + TCG_REG_R15, + + TCG_REG_TMP =3D TCG_REG_R13, + TCG_AREG0 =3D TCG_REG_R14, + TCG_REG_CALL_STACK =3D TCG_REG_R15, +} TCGReg; + +#endif /* TCG_TARGET_H */ --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769411600; cv=none; d=zohomail.com; s=zohoarc; b=Gz0EHK9PQf5XWqK/qFeDbqHegB8wk0hDuZK3bUe4WPlj276VynI45EObY8Pp26LqT8SmRNlywQ1dkS3k+8WVryL499wuMMLkTypUDyWxAYBw0onq0Frt8Ua4Yy6XRhVTj33Dsx1+ArS90EwUnVV40FdsZ2iRcU+zFUVIZm30pno= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769411600; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8FW3Xgb6O5qaPdMbHJGW4nylfvciL9bC4hS3dP0yYtQ=; b=Bmhv+uHDG4ERi3O28kNOnZjSWty1ZMn/qJsximTs/fma/Ie434omtPalQM8JclK26rKGha5DSoOAypZfBk8UbSRTE86mjC9gzVQM6EcO6NAa6hGUkWp85QgcNpBTcwxZLIh1ObtxMN05F/e2qwmJJex8XKGcRrHm+SbYyTKusCU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769411600166134.27148809256698; Sun, 25 Jan 2026 23:13:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGmU-0005mB-P7; Mon, 26 Jan 2026 02:13:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGeG-0002k8-9l for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:05:05 -0500 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGeA-00044L-3l for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:04:29 -0500 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-81f5381d168so3936587b3a.2 for ; Sun, 25 Jan 2026 23:04:18 -0800 (PST) Received: from brahms.. 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.04.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:04:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411057; x=1770015857; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8FW3Xgb6O5qaPdMbHJGW4nylfvciL9bC4hS3dP0yYtQ=; b=Z45nBW7SuEg2aHYl8HU56leVOpybdQef32/aB0XpkWqJMNKEL3vU+LoU3oIclhkX2M RanX1Guj75U/absj0FnG9ST0j9hmcQTqYiWsh4fH3bilvSnZRiC7zbpP2YiFQj+i8qdZ BuzHsJejQCXQe0C7kZrp7F7HLjCIL8EXsDW4SzNow9uDiX5BknKXI8HTr4uf5toNjr1S 7bqa+hwxpvTw1odOn3rvPZ7TlXxI54H959SheonBvUWWtPDEF1MuyxpCQbUdoVUl6Ubp vMNrLZVmijOS/xouJXGOv1Op7H7tgI5zq7vXEOCJdhVSVWmSUcXHy/MpQ4G7MrKNmVYt AOqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411057; x=1770015857; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=8FW3Xgb6O5qaPdMbHJGW4nylfvciL9bC4hS3dP0yYtQ=; b=hv2i3UKH/ob10IhG3Of94JgPw1wQuicpwAcmA5K1GUvT+Ig8D2CdIuFgEruUmIyV23 jVvWVUutncbexxuru9TYTubexD4htEF6CB189A4C6qHHXa4iD1l4Oy5zpinAEn/cADgb J1jDVuCgSlSVbWQHC8O3afp+nj2ro6eXYrkOcHoWEba/NYUSpgX89LxjoUdjjvraIIjc Drs7jQfxhik0HXtpBApvBNFlINrrpyMWJ3cS85bblZ1H4gPLxhy83OSp9GQOtrAX0+mo ZWQ5QouzmqjmfYKkWZKZRVkOCASlHj57Dr4G5xVDfIoCDIAGLQyqhF/dIjQICoW6abkL UwGA== X-Gm-Message-State: AOJu0YyKbxxKIn9VWRa+Mb22LgHerLuiQf6FzhdtieETJWtXdezxw70R scv7W8t+t0M/odao25+lHtMDW+2fCYPmDv7gnIM6iyy+Q4EZbFGEqK/mRb90gxtI X-Gm-Gg: AZuq6aIIE/cU9w0oxVZQYfWkHg/u6tkiYp3eJE6ycDpdI0nAlZwc9rWTjwPeIYh5nYc z5ThaAN2FPkl1CgTTAuCvhMoWGHKmOLFri2/ENJZL5xUNgW8nTbi5Kmskn67XntccqrU5bTsRK2 MFZMXIUyqxZ2/EkHEnrGxqdvPkkahVw7Du5i8OucIipMec9E3amw9F/wnaXgdtcHm7QocEicK8k yWzOZxuY2W1GN7UARYOIjVKqGTrPQRqKlcBXBmrT3VFPX2HM/gG//c2tOJtbDKf95sBjMtsmj2C vejVwJLA6E6IRUvUxUOLooLYFNrpYlu4lliMt9craiLete9bEd1lFtYPtSrHiL1X6BRxP7MtcyG uYV6ZS4S+uepCXZDOz6bgYZvMF3gj5UiQ24awtW6gpsHmfwDCS9KK7aWlDr9/gbhgQP0o+ueNYP 9pCj/IcXhPHuMoZOHFkqeGw6GC76G2jSzhMt+bMTJbeycSJJBrg4oI X-Received: by 2002:a05:6a00:3e11:b0:81f:3f88:89ee with SMTP id d2e1a72fcca58-823411b83c6mr3738378b3a.12.1769411056966; Sun, 25 Jan 2026 23:04:16 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 02/33] tcg/wasm64: Add register-related definitions Date: Mon, 26 Jan 2026 07:03:15 +0000 Message-ID: <8cccaa9366173c874e08d909184bd1c1214a83aa.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769411602521158500 Content-Type: text/plain; charset="utf-8" This commit adds the register allocation definitions and register names to the Wasm backend. As in TCI, call arguments are stored on the stack buffer and the return value is placed in the registers R0 and R1 when needed. Signed-off-by: Kohei Tokunaga --- tcg/wasm64/tcg-target.c.inc | 77 +++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 tcg/wasm64/tcg-target.c.inc diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc new file mode 100644 index 0000000000..3affc17232 --- /dev/null +++ b/tcg/wasm64/tcg-target.c.inc @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2009, 2011 Stefan Weil + * + * Based on tci/tcg-target.c.inc + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +static const int tcg_target_reg_alloc_order[] =3D { + TCG_REG_R2, + TCG_REG_R3, + TCG_REG_R4, + TCG_REG_R5, + TCG_REG_R6, + TCG_REG_R7, + TCG_REG_R8, + TCG_REG_R9, + TCG_REG_R10, + TCG_REG_R11, + TCG_REG_R12, + TCG_REG_R13, + TCG_REG_R14, + TCG_REG_R15, + /* 2 of these are call clobbered, so use them last. */ + TCG_REG_R1, + TCG_REG_R0, +}; + +#ifdef CONFIG_DEBUG_TCG +static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { + "r00", + "r01", + "r02", + "r03", + "r04", + "r05", + "r06", + "r07", + "r08", + "r09", + "r10", + "r11", + "r12", + "r13", + "r14", + "r15", +}; +#endif + +/* No call arguments via registers. All will be stored on the "stack". */ +static const int tcg_target_call_iarg_regs[] =3D { }; + +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot < 128 / TCG_TARGET_REG_BITS); + return TCG_REG_R0 + slot; +} --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769411655; cv=none; d=zohomail.com; s=zohoarc; b=f4D9v6oMX30ESL5Ql5hxeVVfAN4KKoKnGlRDFsJYOT6iKYGGkrjAwhuuvoR1gLuvUOOERUqIqgq3kf+hFHYY5WfTbG0C9vMzJxmNvaND/kNBw6Pyqo+ajrWe9pkwCTH5iXoMLw/5eclmeKpxDj48y1n6oE+HFpqfgyyNiB9ZYWw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769411655; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QiBLBmuJrU9Jg04Dyfz191OWwD91URVjxfllKljJsDk=; b=UFIGN7rC0cxHWU4qyagiNt2Dw3lDPEIrNzogsFHGI1SWJhx40hndeFaUaLDDSwg3IlzfHvA/GsYWZo9R4bC2U2qvOSHGJjVCiz0+5YGnYzBNSD3fiDTKmpPJTFUTNP9I5d3JTtp+XG/5Kvt6qrpAdhzHTIuuO1sBvxdXBJrkBNw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769411655978521.0818116417838; Sun, 25 Jan 2026 23:14:15 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGmZ-0005yi-PX; Mon, 26 Jan 2026 02:13:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGeI-0002kU-Ip for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:05:05 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGeF-00044d-LW for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:04:33 -0500 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-823075fed75so2179036b3a.1 for ; Sun, 25 Jan 2026 23:04:22 -0800 (PST) Received: from brahms.. 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.04.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:04:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411061; x=1770015861; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QiBLBmuJrU9Jg04Dyfz191OWwD91URVjxfllKljJsDk=; b=Wdm9ASPCae7FvJSrkCKvAD+xiQnw9mvMphcPKZQAOh9hoiol4ElgsZnhwbQEhQOuAs CIqLi4ZVSvr3ebFwePhjSLnim80v4LpmG0W1oD64/EhJXWVV084DQn13SNdkqK4gd4Yv fT3i7/lRNAPVru6FNYsaK1izIoej86lA+dB8rtDUEG8MdP/kYRKFOQNAI0vKJRNCDXxi QlAyQqBncu6rtvu47XUj7U0vnH/rbrdre6j2x2hApigWIxwfiFvBvbIP150gLUKZhdii xByBxc9C6s+dN/8ZdTu64FkVwclIIDLyBMQoSB+46pC5TPAMGZX9LpUROhQHqMuTvEd6 577w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411061; x=1770015861; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=QiBLBmuJrU9Jg04Dyfz191OWwD91URVjxfllKljJsDk=; b=OpI9gZ87MfOSCwqBzitERC2kGLnh92tKMKS0WDk5TjD5xyG0yZ+EsyI4bOFOkzKjzZ e5ce3QU6CfLBewZ4E3Km/gOjXrcKCRH65j03eSXZhrztXu4d815IptgVoSx7R3EtUi7t 4kb5uWqYDLmAVIIlnDyioZJ0k20+I2xVSbOL4ZldBWc1/rUQzKcm4MwSVRy+XnymMYuu O3FhU48GdS8DWtUeIi4tBr93BYtO1KAYv/3y9ay6fDjeeQvlbDRgEyWUVoUQ/GmxvM1D YlfCqyX2iACxr21OOWVx1GhilyQ/cpyV1C2dq0ThK6rwFgCJ7azhhiHpEFuTejoKRg72 DcGg== X-Gm-Message-State: AOJu0Yysc5F9PGVJLOYiol/EVVprJ34a6SAL48hFjQTMdcP2tjy+NGoV n/4tEwz+Vev5KlvDn5axm8+E6+/oVqHahCOVMI3Permp/siyLyNIKQrNiwq+eSmy X-Gm-Gg: AZuq6aK2XnAQ8pvCOi/nC+fPUrlZ7IiXNdFau+8Ihd94TB3ewdaOpHzCWWg745CYAst UodKfUf0cFO03yQbUGci/eKRZdebchMocnSP4VP8fDi49YmoWdUAy6HI1bUZUXOFq9U5eHxEpsL xDKtJmNr+RYWv5McUgSW9n5wFvP2OFE5nRbrfD7uGFArtEM4OJwlQRNc7iFYTN8REhBdvQRTqMp JeUsi+si04ppWkFpvLb9lHmwi9Hffa8tPoRX+D3vm8gm2233rlpdIEwlrw3eh8V2X2TflpzZ4bz MQXuQFLctyQlu3QuZNE2DHo/1WXnvqpPzzjeC5LqqcyqEGk8sr9ggqCYD6SPjuP5d+hBA+Cx7sh WIBoayiF3LpivD6pkwBUknqQNoH7bZ/ij5eUt7ACRfv/5xxyOx4hcsmS7pN9WGjqhbFDObV+1pM YOKqfDI9lCq5WipJ41i63Zbb0HO0OhDjjBy+wCO0xzfg== X-Received: by 2002:a05:6a00:22cf:b0:822:6834:9abc with SMTP id d2e1a72fcca58-8234129c3c4mr2979648b3a.24.1769411061316; Sun, 25 Jan 2026 23:04:21 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 03/33] tcg/wasm64: Add constraint definitions Date: Mon, 26 Jan 2026 07:03:16 +0000 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769411658313158500 Content-Type: text/plain; charset="utf-8" The Wasm backend integrates a forked TCI so its constraints are defined to remain compatible with TCI. Signed-off-by: Kohei Tokunaga --- tcg/wasm64/tcg-target-con-set.h | 19 +++++++++++++++++++ tcg/wasm64/tcg-target-con-str.h | 14 ++++++++++++++ tcg/wasm64/tcg-target.c.inc | 13 +++++++++++++ 3 files changed, 46 insertions(+) create mode 100644 tcg/wasm64/tcg-target-con-set.h create mode 100644 tcg/wasm64/tcg-target-con-str.h diff --git a/tcg/wasm64/tcg-target-con-set.h b/tcg/wasm64/tcg-target-con-se= t.h new file mode 100644 index 0000000000..0dc41ebe33 --- /dev/null +++ b/tcg/wasm64/tcg-target-con-set.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Wasm target-specific constraint sets. + * + * Based on tci/tcg-target-con-set.h + * + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) +C_O0_I2(r, r) +C_O1_I1(r, r) +C_O1_I2(r, r, r) +C_O1_I4(r, r, r, r, r) diff --git a/tcg/wasm64/tcg-target-con-str.h b/tcg/wasm64/tcg-target-con-st= r.h new file mode 100644 index 0000000000..21ddbcc01a --- /dev/null +++ b/tcg/wasm64/tcg-target-con-str.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define Wasm target-specific operand constraints. + * + * Based on tci/tcg-target-con-str.h + * + * Copyright (c) 2021 Linaro + */ + +/* + * Define constraint letters for register sets: + * REGS(letter, register_mask) + */ +REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS)) diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index 3affc17232..0b12c4ea03 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -75,3 +75,16 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind= kind, int slot) tcg_debug_assert(slot >=3D 0 && slot < 128 / TCG_TARGET_REG_BITS); return TCG_REG_R0 + slot; } + +static TCGConstraintSetIndex +tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) +{ + return C_NotImplemented; +} + +/* Test if a constant matches the constraint. */ +static bool tcg_target_const_match(int64_t val, int ct, + TCGType type, TCGCond cond, int vece) +{ + return ct & TCG_CT_CONST; +} --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769411543; cv=none; d=zohomail.com; s=zohoarc; b=fdgKHMPCeFtPoF1s15ZipgeHCMJXkEmT2mvowaF+LwZGH7ku+JRAMUGLmWwjR3VrZnEokST21PEHIUAvagDwQ15IA30Gzf6OigEtYxlpte2rpbUnEyPqpNHgGQ/aF0WRWAcTsxSs31fZM/mTZQ9JcFB8aBzWTMUwtxHzy430OIk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769411543; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TXBe1C9rFr756wJ0chsOZMSPb6pQczF5N8rNcYW9UcE=; b=YPvslhhYM7P5t3+15TfaERxIDKuwRrUDNlCfF0vMSo9raG4lk2itM3qCMtbBBBD9eVCJFrjikEA28ymCguxWwBIT7vb1NlKA2/H3bs4FeSr85SluH+UlsXle9etiPZpM3WCCF+WJUx+Wson5FFcQGrdRnGFYzesQ+KmwcYwAEJM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769411543600728.4732382714052; Sun, 25 Jan 2026 23:12:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGl2-0004xE-H8; Mon, 26 Jan 2026 02:11:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGeH-0002kL-Oz for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:05:05 -0500 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGeD-000455-Bb for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:04:32 -0500 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-8230d228372so1748636b3a.1 for ; Sun, 25 Jan 2026 23:04:26 -0800 (PST) Received: from brahms.. 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.04.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:04:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411066; x=1770015866; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TXBe1C9rFr756wJ0chsOZMSPb6pQczF5N8rNcYW9UcE=; b=ACr9kHGodA8V2izDC5ZduCGynnnEsnfpGsFM9g/zYNSMfqnbw+ENsKhuJShI3nBdQt oGpcfYmDJQjP0+Z29JhfjmybUsc2HxhdrKGw0ndymNa+UzRgu81boGj05qbjzisDOUSI G76pp/35bSyelTmR8rG4AVH/iV+iTNKs1bOeMaW+A+vbOJgS1W7JbZ7zKyoCYIc2FluD ffz/+k8OxQa7sIgEld3iCqP+sxgq6Yon3CIZ5wmC6XcATlavQRutS579mT9NgNQbnpsd 9FyzE1+IG2X7YtiUNXd3l3Gfa7a+LRa1OA1Tae+UQoPUO9FbwjXzdZwPOOaRqP8MmfLi c2Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411066; x=1770015866; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=TXBe1C9rFr756wJ0chsOZMSPb6pQczF5N8rNcYW9UcE=; b=T1WIRAeynI2FOsUsGuPUpFouyvj6/mOTC/5bZJnQnCEic+TrXtHcAEEyrsK9DFPXfa s94XEwgMdGtTTLPz1EKwchT+DxmTjhpJXMyeOZqiJyGGZp3CjCE67gW7vMQdNgpkXK2p b57WTGGSfgpe+6Dzoiz6/43sJ6z0w8RFgcMuiZc3tb3mDaTEx/6RdTQwquyNO94gJXdS +wikvd4A2owsQvC9UYnm9r1DzxQHkBbqn3Y8TegK3PXoI6czoVo4Y7jSs2EylMdit7/7 AOnj3vUUEoetV8yEPudHS2KdSeP2NLwty7S2CnW7nctj5O6v0Zk9MPeMQYkftBDy6RCy nw+w== X-Gm-Message-State: AOJu0YwtvjDPXweOrZpDNBPhDr3Vow6OlXjPwsW2OR78q7DyOpoKX976 jkmFrNXBXsvw/+ahZCHhdS2/eqAtSMt/b2vqrzZo/fvLxwSTfYCbn4W8xrkxgEun X-Gm-Gg: AZuq6aIuit/waEZgJZPwmoO7TpuIERPJFykp9e85w6Jr6RrKj/svkjnoujTffLQOQMy szJqSSFzYF3sIExoCMKr03msZABbChdpEyZmwsYIm4Yt9Z4dyoDizlBxi16Cj1WTmK7Uf2yKV7A 4hTG7jmCkboC/udDio1/XrZY5r/k7lw+Vj7l1x5oUqib1+HLeJTNlUKLJFjNOTIPvPXp5+iXyYN t1mAS0G53rWgTH5gKkTGaVv8+mxtwaezm8EMBOr2/wOBgj3T4dKlDEyuOIJzeE0GHwWvNr2Gj6S u6ZRkYqSilomwmS/FJnnKJPBwzxdCHr4tOpDoIabu7KfKMitG9exZrgs9x5uELlnkt/zArJo7yi 28u1jxpKJ7AAUKSWJk8/p6wLzilCcJDQW/EztY3mj1iZCtA6FcGWiC9vezYxmpjzDrSf4TAKbZf Kafy0u4ROtXSRTGoKal3XGQ2qzGtVxyWu5sGtZIU3Iyw== X-Received: by 2002:a05:6a00:1494:b0:821:7ee2:b692 with SMTP id d2e1a72fcca58-8234120a841mr3317785b3a.2.1769411065767; Sun, 25 Jan 2026 23:04:25 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 04/33] tcg/wasm64: Add relocation callbacks Date: Mon, 26 Jan 2026 07:03:17 +0000 Message-ID: <777003050525eac85580bd75bb5473777c278c87.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769411547568154100 Content-Type: text/plain; charset="utf-8" Relocation callbacks are used for the TCI instructions to preserve the original logic of the TCI backend. Signed-off-by: Kohei Tokunaga --- tcg/wasm64/tcg-target.c.inc | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index 0b12c4ea03..4bcb594360 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -88,3 +88,24 @@ static bool tcg_target_const_match(int64_t val, int ct, { return ct & TCG_CT_CONST; } + +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + memset(p, 0, sizeof(*p) * count); +} + +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + intptr_t diff =3D value - (intptr_t)(code_ptr + 4); + + tcg_debug_assert(addend =3D=3D 0); + tcg_debug_assert(type =3D=3D 20); + + if (diff =3D=3D sextract32(diff, 0, type)) { + tcg_patch32(code_ptr, + deposit32(*(uint32_t *)code_ptr, 32 - type, type, diff= )); + return true; + } + return false; +} --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769411582; cv=none; d=zohomail.com; s=zohoarc; b=mlC0oK76mzQETo56jAePQxzHC/O012EzyLybGrHoK9E2MlEv3xMwnpeXMBqE/oo742k0wQ8680eUYorPRcMZ0LfRsLcCW8Th+t4Z97Uf6K6AU73aJjzCrUUC2Nl1usJr0ZOz74vcEsAMJeAeSzadzppgGTYHtc3AFRLiIR4Qy2s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769411582; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6Q81oLzyNhe0nfh2SJ9vu+lqMg2lFcteDby5lmMtWCY=; b=Pvp6OJ3y/aeOwPSN//RleBez9MYqaQWoevnpT5fIIRMs1rmJl56INv877WC3Sz9RaUlNwPUAXmUrF+k3q6f5gWNQAt8HI6ZQPzT+9czj+kiHG7atBLgCBo/dhPHWmE1EFNXv8hhJ2vrbDnXZFK9Lv2yysLDB6LH4BQjVWS5hDso= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176941158293864.45736430447619; Sun, 25 Jan 2026 23:13:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGm5-0005Em-Qb; Mon, 26 Jan 2026 02:12:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGeL-0002kc-HH for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:05:05 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGeG-00045g-2I for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:04:35 -0500 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-81ed3e6b8e3so1963684b3a.2 for ; Sun, 25 Jan 2026 23:04:31 -0800 (PST) Received: from brahms.. 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.04.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:04:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411070; x=1770015870; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6Q81oLzyNhe0nfh2SJ9vu+lqMg2lFcteDby5lmMtWCY=; b=ECYVc8u2YcTdJ2/BzbnD20zS+w2+hMEgmxfPp46He1oDyq69TFw3uchxj2KfSn41cc 6YORlGO1ln7Xen6PTMu0f2TNHKo1u8XDyCCox6vdE3dcAhN2W/BTSPAEetRZhDZL62pT IGfIoY4ZstT2BeboSe541yGmQ3aa9v9Xppxi4ox2sVyppjbzk13irLWXvdolXqmPeqdd AWt4RtJLtFuSYAt69DR7iIjB2eec09CwmF9/LySLbJDZgXXRsld3B+hoId3p8GhqOQkI WmrEVwNO+zUKayGXSVNimoWFl4Yr+8CKgamfZsxv8S4m9wDIngVbbgHnLMEgxNj+E6Za lIVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411070; x=1770015870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=6Q81oLzyNhe0nfh2SJ9vu+lqMg2lFcteDby5lmMtWCY=; b=JpDSnpInXFlEU+E7VWljOGiaMiZUsJCxnGAVcMCnLVP12BlT6A6onKdp9OTpvKpnhV 5PqeFaWp5ULayltmi+ju2LMeNURRqtcXBV8V5sdm+joWhDFNy9lbvjHXCzutievwBhai VOP1L2Fw4FLXvse1L7PBgj0L64sifLtWXjn1/mqfa33LI9HlihWNgzj4ZfsI+z1ktmdI 4TpCe5GZre1tpcAkMh8O5AF2qvdUWniL5vlfI486HE66rG/yBuhQoBULn7Vi1K5KxMY+ CsR/RVo5MZnciiov/sQa5Z4Z3PfY2vw3VltYUu73qOerJ6SI4Qkp1Sa38GZ3AAQLEmgM RLLQ== X-Gm-Message-State: AOJu0Yzm9GEm5ySpEh6Xd9BytIF7zhzvw9VFYIFMyDxSluLBMt7wYGJX mILkIjoyBrUXat4GQrRKQOhoMvi87xe8oGhC7Jn69LK1erNqbCuJikZB3NINmiPP X-Gm-Gg: AZuq6aLKzoR6JuF2xttnT0iDrW4JfX4IWkpoYp3esaneHiVe/HW6jWb/jUUtYAxrtcM af3mV2Pckg616NAxoDRcZCUJtkl1N+iMCIvXo2N0ZaNmrIsQt7GmcGirbCglyeKsarigv89/w1Z R/QV3Fq1BD9RpTGH/tj1uoqWGU/aDImfJc17qYStrh1g8STm6zBoAYS2VJXVILcBP7kvWgCmieM bMQS8yx518KITc4ny90K0TAn1e4rzfHNpO/At1FF7dreXlvWzcxA+a47bUpaLvj6CndS3C10dfR H6MS22omWq7DsYsE6+7uM77ky5nK7CMsFLWqCc0XiKQ4/sC034As8mmulbkaZxGTlhjY6wY1ifY ZJYQUTgoRSPc5AYpsq3wM4LwC2PDMczULQenuN8aKd5P0othNuwHLPzUewVe/aSnsrOBGaIr5sa 0BpPLF0R8Hpyjr8//ZbJsWk817mUWaN/utmOk7swXfkfcsqTVhkwRF X-Received: by 2002:a05:6a00:bd85:b0:81f:8387:53a8 with SMTP id d2e1a72fcca58-82341286955mr3639624b3a.34.1769411070157; Sun, 25 Jan 2026 23:04:30 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 05/33] tcg/wasm64: Add and/or/xor instructions Date: Mon, 26 Jan 2026 07:03:18 +0000 Message-ID: <98489736a6ad338cda86ed9fe31af5cba239fa0c.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769411584945158500 Content-Type: text/plain; charset="utf-8" This commit adds support for generateing the and, or and xor operations. The generated Wasm codes will be instantiated and executed in the browser. Browsers tipycally limit the number of active Wasm instances and the instantiating Wasm modules introduces overhead. As a result, instantiating TBs that are rarely called is undesirable. To address this, the Wasm backend relies on the a forked subset of the TCI interpreter (tcg_qemu_tb_exec_tci function in tcg/wasm64.c) for executing such TBs. The Wasm backend emits both Wasm and TCI instructions. TCI instructions are emitted to s->code_ptr, while the corresponding Wasm instructions are generated into a separate buffer allocated via tcg_malloc(). This buffer intends to be merged into the TB before tcg_gen_code returns. In the Wasm code, each TCG variable is mapped to a 64bit Wasm variable. Execution works by first pushing the operands into the Wasm's stack using get instructions. The result is left on the stack and this can be assigned to a variable by popping it using a set instruction. The Wasm binary format is documented at [1]. Additionally, since the Wasm instuction's index operand must be LEB128-encoded, this commit introduces an encoder function implemented following [2]. [1] https://webassembly.github.io/spec/core/binary/index.html [2] https://en.wikipedia.org/wiki/LEB128 Signed-off-by: Kohei Tokunaga --- MAINTAINERS | 1 + tcg/wasm64.c | 66 +++++++++++++++ tcg/wasm64/tcg-target.c.inc | 160 ++++++++++++++++++++++++++++++++++++ 3 files changed, 227 insertions(+) create mode 100644 tcg/wasm64.c diff --git a/MAINTAINERS b/MAINTAINERS index 470b15eeb7..30e468f290 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4111,6 +4111,7 @@ WebAssembly TCG target M: Kohei Tokunaga S: Maintained F: tcg/wasm64/ +F: tcg/wasm64.c =20 Block drivers ------------- diff --git a/tcg/wasm64.c b/tcg/wasm64.c new file mode 100644 index 0000000000..9f3b1344d6 --- /dev/null +++ b/tcg/wasm64.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * WebAssembly backend with forked TCI, based on tci.c + * + * Copyright (c) 2009, 2011, 2016 Stefan Weil + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "tcg/tcg.h" + +static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) +{ + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); +} + +static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *env, const void *v_tb_= ptr) +{ + const uint32_t *tb_ptr =3D v_tb_ptr; + tcg_target_ulong regs[TCG_TARGET_NB_REGS]; + uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) + / sizeof(uint64_t)]; + + regs[TCG_AREG0] =3D (tcg_target_ulong)env; + regs[TCG_REG_CALL_STACK] =3D (uintptr_t)stack; + + for (;;) { + uint32_t insn; + TCGOpcode opc; + TCGReg r0, r1, r2; + + insn =3D *tb_ptr++; + opc =3D extract32(insn, 0, 8); + + switch (opc) { + case INDEX_op_and: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] & regs[r2]; + break; + case INDEX_op_or: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] | regs[r2]; + break; + case INDEX_op_xor: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] ^ regs[r2]; + break; + default: + g_assert_not_reached(); + } + } +} diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index 4bcb594360..a1757b4db7 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -25,6 +25,10 @@ * THE SOFTWARE. */ =20 +#include "qemu/queue.h" + +typedef uint32_t tcg_insn_unit_tci; + static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_R2, TCG_REG_R3, @@ -109,3 +113,159 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, } return false; } + +/* converts a TCG register to a wasm variable index */ +static const uint8_t tcg_target_reg_index[TCG_TARGET_NB_REGS] =3D { + 0, /* TCG_REG_R0 */ + 1, /* TCG_REG_R1 */ + 2, /* TCG_REG_R2 */ + 3, /* TCG_REG_R3 */ + 4, /* TCG_REG_R4 */ + 5, /* TCG_REG_R5 */ + 6, /* TCG_REG_R6 */ + 7, /* TCG_REG_R7 */ + 8, /* TCG_REG_R8 */ + 9, /* TCG_REG_R9 */ + 10, /* TCG_REG_R10 */ + 11, /* TCG_REG_R11 */ + 12, /* TCG_REG_R12 */ + 13, /* TCG_REG_R13 */ + 14, /* TCG_REG_R14 */ + 15, /* TCG_REG_R15 */ +}; + +#define REG_IDX(r) tcg_target_reg_index[r] + +typedef enum { + OPC_GLOBAL_GET =3D 0x23, + OPC_GLOBAL_SET =3D 0x24, + + OPC_I64_AND =3D 0x83, + OPC_I64_OR =3D 0x84, + OPC_I64_XOR =3D 0x85, +} WasmInsn; + +#define BUF_SIZE 1024 +typedef struct LinkedBufEntry { + uint8_t data[BUF_SIZE]; + uint32_t size; + QSIMPLEQ_ENTRY(LinkedBufEntry) entry; +} LinkedBufEntry; + +typedef QSIMPLEQ_HEAD(, LinkedBufEntry) LinkedBuf; + +static void linked_buf_out8(LinkedBuf *linked_buf, uint8_t v) +{ + LinkedBufEntry *buf =3D QSIMPLEQ_LAST(linked_buf, LinkedBufEntry, entr= y); + if (!buf || (buf->size =3D=3D BUF_SIZE)) { + LinkedBufEntry *e =3D tcg_malloc(sizeof(LinkedBufEntry)); + e->size =3D 0; + QSIMPLEQ_INSERT_TAIL(linked_buf, e, entry); + buf =3D e; + } + buf->data[buf->size++] =3D v; +} + +static void linked_buf_out_leb128(LinkedBuf *p, uint64_t v) +{ + uint8_t b; + do { + b =3D v & 0x7f; + v >>=3D 7; + if (v !=3D 0) { + b |=3D 0x80; + } + linked_buf_out8(p, b); + } while (v !=3D 0); +} + +/* + * wasm code is generataed in the dynamically allocated buffer which + * are managed as a linked list. + */ +static __thread LinkedBuf sub_buf; + +static void init_sub_buf(void) +{ + QSIMPLEQ_INIT(&sub_buf); +} +static void tcg_wasm_out8(TCGContext *s, uint8_t v) +{ + linked_buf_out8(&sub_buf, v); +} +static void tcg_wasm_out_leb128(TCGContext *s, uint64_t v) +{ + linked_buf_out_leb128(&sub_buf, v); +} + +static void tcg_wasm_out_op(TCGContext *s, WasmInsn opc) +{ + tcg_wasm_out8(s, opc); +} +static void tcg_wasm_out_op_idx(TCGContext *s, WasmInsn opc, uint32_t idx) +{ + tcg_wasm_out8(s, opc); + tcg_wasm_out_leb128(s, idx); +} + +static void tcg_wasm_out_o1_i2( + TCGContext *s, WasmInsn opc, TCGReg ret, TCGReg arg1, TCGReg arg2) +{ + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg1)); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg2)); + tcg_wasm_out_op(s, opc); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret)); +} + +static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2) +{ + tcg_insn_unit_tci insn =3D 0; + + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + tcg_out32(s, insn); +} + +static void tgen_and(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tcg_out_op_rrr(s, INDEX_op_and, a0, a1, a2); + tcg_wasm_out_o1_i2(s, OPC_I64_AND, a0, a1, a2); +} + +static const TCGOutOpBinary outop_and =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_and, +}; + +static void tgen_or(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tcg_out_op_rrr(s, INDEX_op_or, a0, a1, a2); + tcg_wasm_out_o1_i2(s, OPC_I64_OR, a0, a1, a2); +} + +static const TCGOutOpBinary outop_or =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_or, +}; + +static void tgen_xor(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tcg_out_op_rrr(s, INDEX_op_xor, a0, a1, a2); + tcg_wasm_out_o1_i2(s, OPC_I64_XOR, a0, a1, a2); +} + +static const TCGOutOpBinary outop_xor =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_xor, +}; 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.04.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:04:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411075; x=1770015875; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V2iLebfIJhQmyKZPxD/7vvE0TY7hMO11zANvgz7Zbqg=; b=JmemzOPjEZKlW/JDaC+SjnSpSwwma4vfo0PrAuStAPCAO6trB2l8Gh3NzZuvqnp7MK aBCtEHSLQaUSUQ4lCYn52pnv9GWRKrKKOJL2I1uZYgUAGpIzaONppek7ukUn7jvWEz+4 ao5O1jZYxlRDD7Vw78qRmmlkmbW4qF8blwpPZlhogI+gGJswfKFqYsn/H3JvLKPFD8E6 mO44JKWSpEpDIYTSG7d0IPZQhKtsUxWx/IKuftr/VuID/cjOVK72hCKoJ5WDinn1LcNt bZrS/KqIKmNXrjTKniJ42m0kgHsZM6xwwd7Kzaq0rUDn6QnLb9LDx8Awij5J4NuMSRRk gPgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411075; x=1770015875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=V2iLebfIJhQmyKZPxD/7vvE0TY7hMO11zANvgz7Zbqg=; b=wGAJ5h+5PdxHw1cCP9XJHZXzy+9WWn8+N6C+dBHfUbHHhjbnyOENvtSdpjjHhldx/Z mFSE7+rQ2KBwZQZjaC2ypv50+l6zWNMVEHOTUWd+YbW9Qoeu68hdUvgVyPjzq2Y52WW6 DIQRME0F3V4JNksCi8GaXu8l9pxtMcRmVCg6JXD22krASFYDaq1mG7k+pFt62xnYy6SC XppHaicmvrw1/gdkeEUMbZVSNA61IlTfxTopDmdswoGHtclwtULGth0TxDuBNL2iNX9J Ad9V/mSs7XeIIgLWULQnDNZgZ019BKYvsRN7tsYcmO7R7JvoAoElo47+/EtFWU9LG5Ge X07Q== X-Gm-Message-State: AOJu0YytoE77bqUCHah2CDneai650zrIOXe0qB2XrFgOwd/0UiQi4ge5 sZlAkKlPoI/SD5eGqLogsEJWZ1oFBiQxXHfSAnCdIPuScXtC/LG4OwXOpVIGctKx X-Gm-Gg: AZuq6aIPISap0J44ic3wLywm1Wd8YyBo16bAOYsUo80yA9IjVMrQwWrAdi0iRWcIW+W qhlLNq4m2zVYgkJsOCBVD3QuPl3BtcGlrXPve7yg/Qp3j7SStDaTXEaLRXXh0SgFcPH+tNz6M/Y YAtytT9uGJwKOeIwKN9YvBQSo3AMisc1XN/4KyswH6z7hvgIZb+2yGzvd3MQY3ONlZTcC5t8UcT sWXg/0ZvnVSahIeac98loblniMWQTsM/6vPIxcfKSEVzagch226ol8M0m0XHopqWPbQbt49vN1k xWAYo678OXBo2ZC0gWxE6J9HTl4HIC6c+/Khxm6J1bHGnYtpsPM68k6+QZ87SdO3GxaLVCg28mA lhpfPR9q2xwiYrBUDYIc2znOvaJsSCSWGHDQuLkaDnGJHcogNBeph6rmbTXhOoLXITy7G4hosEt QcNJYELkM3T+Wc8JO3sv8T7/XoIZgp9fIQZjQ4j6I/1g== X-Received: by 2002:a05:6a00:1813:b0:81f:3cd5:2069 with SMTP id d2e1a72fcca58-8234119f8edmr3207365b3a.4.1769411074579; Sun, 25 Jan 2026 23:04:34 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 06/33] tcg/wasm64: Add add/sub/mul instructions Date: Mon, 26 Jan 2026 07:03:19 +0000 Message-ID: <96df2d2b5ca095dfbc280ee73bf8f82f5ae4c770.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769411658308158500 Content-Type: text/plain; charset="utf-8" The add, sub and mul operations are implemented using the corresponding instructions in Wasm. TCI instructions are also generated in the same way as the original TCI backend. Signed-off-by: Kohei Tokunaga --- tcg/wasm64.c | 12 ++++++++++++ tcg/wasm64/tcg-target.c.inc | 39 +++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/tcg/wasm64.c b/tcg/wasm64.c index 9f3b1344d6..ba8a89d920 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -59,6 +59,18 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *env,= const void *v_tb_ptr) tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] ^ regs[r2]; break; + case INDEX_op_add: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] + regs[r2]; + break; + case INDEX_op_sub: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] - regs[r2]; + break; + case INDEX_op_mul: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] * regs[r2]; + break; default: g_assert_not_reached(); } diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index a1757b4db7..d5cf324e7b 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -140,6 +140,9 @@ typedef enum { OPC_GLOBAL_GET =3D 0x23, OPC_GLOBAL_SET =3D 0x24, =20 + OPC_I64_ADD =3D 0x7c, + OPC_I64_SUB =3D 0x7d, + OPC_I64_MUL =3D 0x7e, OPC_I64_AND =3D 0x83, OPC_I64_OR =3D 0x84, OPC_I64_XOR =3D 0x85, @@ -265,6 +268,42 @@ static const TCGOutOpBinary outop_xor =3D { .out_rrr =3D tgen_xor, }; =20 +static void tgen_add(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tcg_out_op_rrr(s, INDEX_op_add, a0, a1, a2); + tcg_wasm_out_o1_i2(s, OPC_I64_ADD, a0, a1, a2); +} + +static const TCGOutOpBinary outop_add =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_add, +}; + +static void tgen_sub(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tcg_out_op_rrr(s, INDEX_op_sub, a0, a1, a2); + tcg_wasm_out_o1_i2(s, OPC_I64_SUB, a0, a1, a2); +} + +static const TCGOutOpSubtract outop_sub =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_sub, +}; + +static void tgen_mul(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tcg_out_op_rrr(s, INDEX_op_mul, a0, a1, a2); + tcg_wasm_out_o1_i2(s, OPC_I64_MUL, a0, a1, a2); +} + +static const TCGOutOpBinary outop_mul =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_mul, +}; + static void tcg_out_tb_start(TCGContext *s) { init_sub_buf(); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769411997; cv=none; d=zohomail.com; s=zohoarc; b=BqkyLXn/0aB0TfpIi+N4D+RX13c56oZqO/bL76neNSfQsOhNLWimEBeOLHu/4D3bG0a3WoJG7nnDEi77IxZYxGITHniZ5RrB9KJ43MQipGCn/Wsaycrd1xx/Do/43gfG+2eprLXtd8q4/zokAlykHZ6b1wJ4A6uPn7fNiGEFZuU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769411997; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TdihhC1LP2ZtiZICPjP+OqK+hRFdFoU/q+if4s9CxEk=; b=LbHCYU6xQyAYDxerV3rM2LiQS1HynEkDGLards2BGZU3YMoaskK1s9AVEk5CcZ+Ih+2cYkZ8BPer2HDgMLx5f/eVyBR9h2my9e40cJ2A4W/ZpoQN9P+5lEkQpr466DYozm3Nk6FnC9vqYoaqpXJroV10NTRpZ88+hjv23rIkuSs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769411997988679.6355014204598; Sun, 25 Jan 2026 23:19:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGt4-0004mB-HT; Mon, 26 Jan 2026 02:19:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGeT-0002lh-B6 for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:05:05 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGeO-00047K-QW for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:04:44 -0500 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-81e9d0cd082so3369335b3a.0 for ; Sun, 25 Jan 2026 23:04:40 -0800 (PST) Received: from brahms.. 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.04.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:04:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411079; x=1770015879; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TdihhC1LP2ZtiZICPjP+OqK+hRFdFoU/q+if4s9CxEk=; b=BSjsUWW2PjPwkJHFRywhnMW0FAbF9bBLjgagLkTRv8qPOTgdw33l6wjHyN0IQ83VRi 356zl0I2Pdyx4m5wcSPkCscMZ+Mi4L6RL9ROMzkig4ApeSJLMOScOQgVm7IEBgiFdT4p Tgg/6RuvSuQsbSBlgeCHSYDlemXV+JHPq6Tgu7d6MGvs9TQ7ryKiDULkL4goxGXcDUOj ag7ReU6cuAMXFcAXsmBPD9UkJHlcagVXADmuOdwi3EgzlF3s9rotLPHPGOoT6mPJzkUU m9wQUNuoH+h4wxdvtN4CKkEdgsB0z8z0+8hCEMh7NcYtBAsU5kUEk7gY25jNBSS3C4hw J64w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411079; x=1770015879; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=TdihhC1LP2ZtiZICPjP+OqK+hRFdFoU/q+if4s9CxEk=; b=sEkMZjUafYPw5fgjgSbzWorByRPgSoGRK9tOPeW7DM3mUUnG4ZdpEwFICZbr5jbiFn c5KjEu9DquPSNhsqPN9YQG9qxEJYn2KIdSAK4rZzX24Kgr7AbZljmYJZwGDkqWiLKnsW FHGsWmBOgjMgyR+F5HkgFJc0DZCGRpRR+U8aR/H9fjKiwrAbgMF5okn65HDu1PvSkG+f 0GoSNm23wkvSvL1QqYNqo/E06NG7f7+2hxJX+c6Lv78zLVdRrkwnJTPkpRfW3svMWQ6W FUYVoXNUoEOvPOjHaCMQIASekLm1Bc+dWTqHsNjmNIpFMjzOEyQzsc04+QBKcAlVY9r6 csfQ== X-Gm-Message-State: AOJu0YxufrHHcREZblnipF6e8wSsIPsdxDEuyVBZZ8PzBlEfTPfZlqyw BxIQMB47GKthQcgMq6MKDeAyNOiRLqV+rAJDg96tB7JJb5PJw50wGZqeEee35g6/ X-Gm-Gg: AZuq6aI+rNQBZbb0WhA60J/iLFAQIGfrfUSUKaCUYhdxKQ9QxKdui3HrC/W93N8JBvD n9GlAN2HmHI+MiIRDjyphEhYeWI5zrfsGaCuKnfjEfmy6DtVsmG2D+dj7I0KDCEGlTuWdOcBx85 5f/gfADj9KUUmeas8513U/qtTCtZhBWWtpFBzNj9jW+KQ1lRivXhcr/HrJC2b5DPGO45D0yb7jk S0fOhzZJJM1xzz/3fGgc3Tp7l8UGlRy/lPz5B7x1YEzkc3cf7axjANTCIqHc8DlB4YqKzfczSb6 1J1VL+5+ypNgAUmstbkw3dcCH5nfuET4PWZb3W0UpSppuBugGkcRKvVYPRDjr4yfvgqZrghz0q2 KSrD7G5vJdMnQ+cG9nQyVIJ1JhtoK5CYAoz4vYatZil2lKKHE+rlnmEUHe9aC6mdqp+x6VgARFh pH+iGYWqcWO5n/JyEzV3JEnOo8kf774WuhevKHKR4xAw== X-Received: by 2002:a05:6a00:bd83:b0:81e:b2ba:5b36 with SMTP id d2e1a72fcca58-823412d84b3mr3225922b3a.63.1769411079018; Sun, 25 Jan 2026 23:04:39 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 07/33] tcg/wasm64: Add shl/shr/sar instructions Date: Mon, 26 Jan 2026 07:03:20 +0000 Message-ID: <5d4b7281f9d786559357c267946a00a5b3ef87f0.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769411999376158500 Content-Type: text/plain; charset="utf-8" This commit implements the shl, shr and sar operations using Wasm instructions. Since the Wasm backend uses 64bit variables, right shifts on 32bit values extract the lower 32bit of the operand before shifting. TCI instructions are also generated in the same way as the original TCI backend. Signed-off-by: Kohei Tokunaga --- tcg/wasm64.c | 31 +++++++++++++ tcg/wasm64/tcg-target.c.inc | 93 +++++++++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+) diff --git a/tcg/wasm64.c b/tcg/wasm64.c index ba8a89d920..b63b88e011 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -28,6 +28,15 @@ static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGR= eg *r1, TCGReg *r2) *r2 =3D extract32(insn, 16, 4); } =20 +static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, + uint8_t *i2, uint8_t *i3) +{ + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *i2 =3D extract32(insn, 16, 6); + *i3 =3D extract32(insn, 22, 6); +} + static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *env, const void *v_tb_= ptr) { const uint32_t *tb_ptr =3D v_tb_ptr; @@ -42,6 +51,7 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *env, = const void *v_tb_ptr) uint32_t insn; TCGOpcode opc; TCGReg r0, r1, r2; + uint8_t pos, len; =20 insn =3D *tb_ptr++; opc =3D extract32(insn, 0, 8); @@ -71,6 +81,27 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *env,= const void *v_tb_ptr) tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] * regs[r2]; break; + case INDEX_op_extract: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] =3D extract64(regs[r1], pos, len); + break; + case INDEX_op_sextract: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] =3D sextract64(regs[r1], pos, len); + break; + case INDEX_op_shl: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] << (regs[r2] % TCG_TARGET_REG_BITS); + break; + case INDEX_op_shr: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] >> (regs[r2] % TCG_TARGET_REG_BITS); + break; + case INDEX_op_sar: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D ((tcg_target_long)regs[r1] + >> (regs[r2] % TCG_TARGET_REG_BITS)); + break; default: g_assert_not_reached(); } diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index d5cf324e7b..3a2a707619 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -140,12 +140,21 @@ typedef enum { OPC_GLOBAL_GET =3D 0x23, OPC_GLOBAL_SET =3D 0x24, =20 + OPC_I32_SHR_S =3D 0x75, + OPC_I32_SHR_U =3D 0x76, + OPC_I64_ADD =3D 0x7c, OPC_I64_SUB =3D 0x7d, OPC_I64_MUL =3D 0x7e, OPC_I64_AND =3D 0x83, OPC_I64_OR =3D 0x84, OPC_I64_XOR =3D 0x85, + OPC_I64_SHL =3D 0x86, + OPC_I64_SHR_S =3D 0x87, + OPC_I64_SHR_U =3D 0x88, + + OPC_I32_WRAP_I64 =3D 0xa7, + OPC_I64_EXTEND_I32_U =3D 0xad, } WasmInsn; =20 #define BUF_SIZE 1024 @@ -219,6 +228,27 @@ static void tcg_wasm_out_o1_i2( tcg_wasm_out_op(s, opc); tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret)); } +static void tcg_wasm_out_o1_i2_type( + TCGContext *s, TCGType type, WasmInsn opc32, WasmInsn opc64, + TCGReg ret, TCGReg arg1, TCGReg arg2) +{ + switch (type) { + case TCG_TYPE_I32: + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg1)); + tcg_wasm_out_op(s, OPC_I32_WRAP_I64); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg2)); + tcg_wasm_out_op(s, OPC_I32_WRAP_I64); + tcg_wasm_out_op(s, opc32); + tcg_wasm_out_op(s, OPC_I64_EXTEND_I32_U); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret)); + break; + case TCG_TYPE_I64: + tcg_wasm_out_o1_i2(s, opc64, ret, arg1, arg2); + break; + default: + g_assert_not_reached(); + } +} =20 static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2) @@ -232,6 +262,21 @@ static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, tcg_out32(s, insn); } =20 +static void tcg_out_op_rrbb(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, uint8_t b2, uint8_t b3) +{ + tcg_insn_unit_tci insn =3D 0; + + tcg_debug_assert(b2 =3D=3D extract32(b2, 0, 6)); + tcg_debug_assert(b3 =3D=3D extract32(b3, 0, 6)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 6, b2); + insn =3D deposit32(insn, 22, 6, b3); + tcg_out32(s, insn); +} + static void tgen_and(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { @@ -304,6 +349,54 @@ static const TCGOutOpBinary outop_mul =3D { .out_rrr =3D tgen_mul, }; =20 +static void tgen_shl(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + tcg_out_op_rrr(s, INDEX_op_shl, a0, a1, a2); + tcg_wasm_out_o1_i2(s, OPC_I64_SHL, a0, a1, a2); +} + +static const TCGOutOpBinary outop_shl =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_shl, +}; + +static void tgen_shr(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + TCGReg orig_a1 =3D a1; + if (type < TCG_TYPE_REG) { + tcg_out_op_rrbb(s, INDEX_op_extract, TCG_REG_TMP, a1, 0, 32); + a1 =3D TCG_REG_TMP; + } + tcg_out_op_rrr(s, INDEX_op_shr, a0, a1, a2); + tcg_wasm_out_o1_i2_type(s, type, OPC_I32_SHR_U, OPC_I64_SHR_U, + a0, orig_a1, a2); +} + +static const TCGOutOpBinary outop_shr =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_shr, +}; + +static void tgen_sar(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + TCGReg orig_a1 =3D a1; + if (type < TCG_TYPE_REG) { + tcg_out_op_rrbb(s, INDEX_op_sextract, TCG_REG_TMP, a1, 0, 32); + a1 =3D TCG_REG_TMP; + } + tcg_out_op_rrr(s, INDEX_op_sar, a0, a1, a2); + tcg_wasm_out_o1_i2_type(s, type, OPC_I32_SHR_S, OPC_I64_SHR_S, + a0, orig_a1, a2); +} + +static const TCGOutOpBinary outop_sar =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_sar, +}; + static void tcg_out_tb_start(TCGContext *s) { init_sub_buf(); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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TCI instructions are also generated in the same way as the original TCI backend. Since support for TCG_COND_TSTEQ and TCG_COND_TSTNE is not yet implemented, TCG_TARGET_HAS_tst is set to 0. Signed-off-by: Kohei Tokunaga --- tcg/wasm64.c | 136 ++++++++++++++++++- tcg/wasm64/tcg-target-has.h | 7 + tcg/wasm64/tcg-target-opc.h.inc | 8 ++ tcg/wasm64/tcg-target.c.inc | 230 ++++++++++++++++++++++++++++++++ 4 files changed, 380 insertions(+), 1 deletion(-) create mode 100644 tcg/wasm64/tcg-target-has.h create mode 100644 tcg/wasm64/tcg-target-opc.h.inc diff --git a/tcg/wasm64.c b/tcg/wasm64.c index b63b88e011..183dad10a2 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -21,6 +21,12 @@ #include "qemu/osdep.h" #include "tcg/tcg.h" =20 +static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1) +{ + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); +} + static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) { *r0 =3D extract32(insn, 8, 4); @@ -37,6 +43,110 @@ static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TC= GReg *r1, *i3 =3D extract32(insn, 22, 6); } =20 +static void tci_args_rrrc(uint32_t insn, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) +{ + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *c3 =3D extract32(insn, 20, 4); +} + +static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c= 5) +{ + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *r2 =3D extract32(insn, 16, 4); + *r3 =3D extract32(insn, 20, 4); + *r4 =3D extract32(insn, 24, 4); + *c5 =3D extract32(insn, 28, 4); +} + +static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) +{ + bool result =3D false; + int32_t i0 =3D u0; + int32_t i1 =3D u1; + switch (condition) { + case TCG_COND_EQ: + result =3D (u0 =3D=3D u1); + break; + case TCG_COND_NE: + result =3D (u0 !=3D u1); + break; + case TCG_COND_LT: + result =3D (i0 < i1); + break; + case TCG_COND_GE: + result =3D (i0 >=3D i1); + break; + case TCG_COND_LE: + result =3D (i0 <=3D i1); + break; + case TCG_COND_GT: + result =3D (i0 > i1); + break; + case TCG_COND_LTU: + result =3D (u0 < u1); + break; + case TCG_COND_GEU: + result =3D (u0 >=3D u1); + break; + case TCG_COND_LEU: + result =3D (u0 <=3D u1); + break; + case TCG_COND_GTU: + result =3D (u0 > u1); + break; + default: + g_assert_not_reached(); + } + return result; +} + +static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) +{ + bool result =3D false; + int64_t i0 =3D u0; + int64_t i1 =3D u1; + switch (condition) { + case TCG_COND_EQ: + result =3D (u0 =3D=3D u1); + break; + case TCG_COND_NE: + result =3D (u0 !=3D u1); + break; + case TCG_COND_LT: + result =3D (i0 < i1); + break; + case TCG_COND_GE: + result =3D (i0 >=3D i1); + break; + case TCG_COND_LE: + result =3D (i0 <=3D i1); + break; + case TCG_COND_GT: + result =3D (i0 > i1); + break; + case TCG_COND_LTU: + result =3D (u0 < u1); + break; + case TCG_COND_GEU: + result =3D (u0 >=3D u1); + break; + case TCG_COND_LEU: + result =3D (u0 <=3D u1); + break; + case TCG_COND_GTU: + result =3D (u0 > u1); + break; + default: + g_assert_not_reached(); + } + return result; +} + static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *env, const void *v_tb_= ptr) { const uint32_t *tb_ptr =3D v_tb_ptr; @@ -50,8 +160,10 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *env= , const void *v_tb_ptr) for (;;) { uint32_t insn; TCGOpcode opc; - TCGReg r0, r1, r2; + TCGReg r0, r1, r2, r3, r4; uint8_t pos, len; + TCGCond condition; + uint32_t tmp32; =20 insn =3D *tb_ptr++; opc =3D extract32(insn, 0, 8); @@ -102,6 +214,28 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *en= v, const void *v_tb_ptr) regs[r0] =3D ((tcg_target_long)regs[r1] >> (regs[r2] % TCG_TARGET_REG_BITS)); break; + case INDEX_op_neg: + tci_args_rr(insn, &r0, &r1); + regs[r0] =3D -regs[r1]; + break; + case INDEX_op_setcond: + tci_args_rrrc(insn, &r0, &r1, &r2, &condition); + regs[r0] =3D tci_compare64(regs[r1], regs[r2], condition); + break; + case INDEX_op_movcond: + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); + tmp32 =3D tci_compare64(regs[r1], regs[r2], condition); + regs[r0] =3D regs[tmp32 ? r3 : r4]; + break; + case INDEX_op_tci_setcond32: + tci_args_rrrc(insn, &r0, &r1, &r2, &condition); + regs[r0] =3D tci_compare32(regs[r1], regs[r2], condition); + break; + case INDEX_op_tci_movcond32: + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); + tmp32 =3D tci_compare32(regs[r1], regs[r2], condition); + regs[r0] =3D regs[tmp32 ? r3 : r4]; + break; default: g_assert_not_reached(); } diff --git a/tcg/wasm64/tcg-target-has.h b/tcg/wasm64/tcg-target-has.h new file mode 100644 index 0000000000..7e3caf8790 --- /dev/null +++ b/tcg/wasm64/tcg-target-has.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef TCG_TARGET_HAS_H +#define TCG_TARGET_HAS_H + +#define TCG_TARGET_HAS_tst 0 + +#endif diff --git a/tcg/wasm64/tcg-target-opc.h.inc b/tcg/wasm64/tcg-target-opc.h.= inc new file mode 100644 index 0000000000..57274d4569 --- /dev/null +++ b/tcg/wasm64/tcg-target-opc.h.inc @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Based on tci/tcg-target-opc.h.inc + * + * These opcodes for use between the tci generator and interpreter. + */ +DEF(tci_setcond32, 1, 2, 1, TCG_OPF_NOT_PRESENT) +DEF(tci_movcond32, 1, 2, 1, TCG_OPF_NOT_PRESENT) diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index 3a2a707619..70de3bbf83 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -137,9 +137,37 @@ static const uint8_t tcg_target_reg_index[TCG_TARGET_N= B_REGS] =3D { #define REG_IDX(r) tcg_target_reg_index[r] =20 typedef enum { + OPC_IF =3D 0x04, + OPC_ELSE =3D 0x05, + OPC_END =3D 0x0b, OPC_GLOBAL_GET =3D 0x23, OPC_GLOBAL_SET =3D 0x24, =20 + OPC_I32_CONST =3D 0x41, + OPC_I64_CONST =3D 0x42, + + OPC_I32_EQ =3D 0x46, + OPC_I32_NE =3D 0x47, + OPC_I32_LT_S =3D 0x48, + OPC_I32_LT_U =3D 0x49, + OPC_I32_GT_S =3D 0x4a, + OPC_I32_GT_U =3D 0x4b, + OPC_I32_LE_S =3D 0x4c, + OPC_I32_LE_U =3D 0x4d, + OPC_I32_GE_S =3D 0x4e, + OPC_I32_GE_U =3D 0x4f, + + OPC_I64_EQ =3D 0x51, + OPC_I64_NE =3D 0x52, + OPC_I64_LT_S =3D 0x53, + OPC_I64_LT_U =3D 0x54, + OPC_I64_GT_S =3D 0x55, + OPC_I64_GT_U =3D 0x56, + OPC_I64_LE_S =3D 0x57, + OPC_I64_LE_U =3D 0x58, + OPC_I64_GE_S =3D 0x59, + OPC_I64_GE_U =3D 0x5a, + OPC_I32_SHR_S =3D 0x75, OPC_I32_SHR_U =3D 0x76, =20 @@ -157,6 +185,10 @@ typedef enum { OPC_I64_EXTEND_I32_U =3D 0xad, } WasmInsn; =20 +typedef enum { + BLOCK_I64 =3D 0x7e, +} WasmBlockType; + #define BUF_SIZE 1024 typedef struct LinkedBufEntry { uint8_t data[BUF_SIZE]; @@ -191,6 +223,23 @@ static void linked_buf_out_leb128(LinkedBuf *p, uint64= _t v) } while (v !=3D 0); } =20 +static void linked_buf_out_sleb128(LinkedBuf *p, int64_t v) +{ + bool more =3D true; + uint8_t b; + while (more) { + b =3D v & 0x7f; + v >>=3D 7; + if (((v =3D=3D 0) && ((b & 0x40) =3D=3D 0)) || + ((v =3D=3D -1) && ((b & 0x40) !=3D 0))) { + more =3D false; + } else { + b |=3D 0x80; + } + linked_buf_out8(p, b); + } +} + /* * wasm code is generataed in the dynamically allocated buffer which * are managed as a linked list. @@ -209,6 +258,10 @@ static void tcg_wasm_out_leb128(TCGContext *s, uint64_= t v) { linked_buf_out_leb128(&sub_buf, v); } +static void tcg_wasm_out_sleb128(TCGContext *s, int64_t v) +{ + linked_buf_out_sleb128(&sub_buf, v); +} =20 static void tcg_wasm_out_op(TCGContext *s, WasmInsn opc) { @@ -219,6 +272,25 @@ static void tcg_wasm_out_op_idx(TCGContext *s, WasmIns= n opc, uint32_t idx) tcg_wasm_out8(s, opc); tcg_wasm_out_leb128(s, idx); } +static void tcg_wasm_out_op_block(TCGContext *s, WasmInsn opc, WasmBlockTy= pe t) +{ + tcg_wasm_out8(s, opc); + tcg_wasm_out8(s, t); +} +static void tcg_wasm_out_op_const(TCGContext *s, WasmInsn opc, int64_t v) +{ + tcg_wasm_out8(s, opc); + switch (opc) { + case OPC_I32_CONST: + tcg_wasm_out_sleb128(s, (int32_t)v); + break; + case OPC_I64_CONST: + tcg_wasm_out_sleb128(s, v); + break; + default: + g_assert_not_reached(); + } +} =20 static void tcg_wasm_out_o1_i2( TCGContext *s, WasmInsn opc, TCGReg ret, TCGReg arg1, TCGReg arg2) @@ -250,6 +322,85 @@ static void tcg_wasm_out_o1_i2_type( } } =20 +static const struct { + WasmInsn i32; + WasmInsn i64; +} tcg_cond_to_inst[] =3D { + [TCG_COND_EQ] =3D { OPC_I32_EQ, OPC_I64_EQ }, + [TCG_COND_NE] =3D { OPC_I32_NE, OPC_I64_NE }, + [TCG_COND_LT] =3D { OPC_I32_LT_S, OPC_I64_LT_S }, + [TCG_COND_GE] =3D { OPC_I32_GE_S, OPC_I64_GE_S }, + [TCG_COND_LE] =3D { OPC_I32_LE_S, OPC_I64_LE_S }, + [TCG_COND_GT] =3D { OPC_I32_GT_S, OPC_I64_GT_S }, + [TCG_COND_LTU] =3D { OPC_I32_LT_U, OPC_I64_LT_U }, + [TCG_COND_GEU] =3D { OPC_I32_GE_U, OPC_I64_GE_U }, + [TCG_COND_LEU] =3D { OPC_I32_LE_U, OPC_I64_LE_U }, + [TCG_COND_GTU] =3D { OPC_I32_GT_U, OPC_I64_GT_U } +}; + +static void tcg_wasm_out_cond( + TCGContext *s, TCGType type, TCGCond cond, TCGReg arg1, TCGReg arg2) +{ + switch (type) { + case TCG_TYPE_I32: + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg1)); + tcg_wasm_out_op(s, OPC_I32_WRAP_I64); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg2)); + tcg_wasm_out_op(s, OPC_I32_WRAP_I64); + tcg_wasm_out_op(s, tcg_cond_to_inst[cond].i32); + break; + case TCG_TYPE_I64: + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg1)); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg2)); + tcg_wasm_out_op(s, tcg_cond_to_inst[cond].i64); + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_wasm_out_setcond(TCGContext *s, TCGType type, TCGReg ret, + TCGReg arg1, TCGReg arg2, TCGCond cond) +{ + tcg_wasm_out_cond(s, type, cond, arg1, arg2); + tcg_wasm_out_op(s, OPC_I64_EXTEND_I32_U); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret)); +} + +static void tcg_wasm_out_negsetcond(TCGContext *s, TCGType type, TCGReg re= t, + TCGReg arg1, TCGReg arg2, TCGCond cond) +{ + tcg_wasm_out_op_const(s, OPC_I64_CONST, 0); + tcg_wasm_out_cond(s, type, cond, arg1, arg2); + tcg_wasm_out_op(s, OPC_I64_EXTEND_I32_U); + tcg_wasm_out_op(s, OPC_I64_SUB); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret)); +} + +static void tcg_wasm_out_movcond(TCGContext *s, TCGType type, TCGReg ret, + TCGReg c1, TCGReg c2, + TCGReg v1, TCGReg v2, + TCGCond cond) +{ + tcg_wasm_out_cond(s, type, cond, c1, c2); + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_I64); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(v1)); + tcg_wasm_out_op(s, OPC_ELSE); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(v2)); + tcg_wasm_out_op(s, OPC_END); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret)); +} + +static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) +{ + tcg_insn_unit_tci insn =3D 0; + + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + tcg_out32(s, insn); +} + static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2) { @@ -277,6 +428,35 @@ static void tcg_out_op_rrbb(TCGContext *s, TCGOpcode o= p, TCGReg r0, tcg_out32(s, insn); } =20 +static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) +{ + tcg_insn_unit_tci insn =3D 0; + + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, c3); + tcg_out32(s, insn); +} + +static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, + TCGReg r3, TCGReg r4, TCGCond c5) +{ + tcg_insn_unit_tci insn =3D 0; + + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 4, r2); + insn =3D deposit32(insn, 20, 4, r3); + insn =3D deposit32(insn, 24, 4, r4); + insn =3D deposit32(insn, 28, 4, c5); + tcg_out32(s, insn); +} + static void tgen_and(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { @@ -397,6 +577,56 @@ static const TCGOutOpBinary outop_sar =3D { .out_rrr =3D tgen_sar, }; =20 +static void tgen_setcond_tci(TCGContext *s, TCGType type, TCGCond cond, + TCGReg dest, TCGReg arg1, TCGReg arg2) +{ + TCGOpcode opc =3D (type =3D=3D TCG_TYPE_I32 + ? INDEX_op_tci_setcond32 + : INDEX_op_setcond); + tcg_out_op_rrrc(s, opc, dest, arg1, arg2, cond); +} + +static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, + TCGReg dest, TCGReg arg1, TCGReg arg2) +{ + tgen_setcond_tci(s, type, cond, dest, arg1, arg2); + tcg_wasm_out_setcond(s, type, dest, arg1, arg2, cond); +} + +static const TCGOutOpSetcond outop_setcond =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_setcond, +}; + +static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, + TCGReg dest, TCGReg arg1, TCGReg arg2) +{ + tgen_setcond_tci(s, type, cond, dest, arg1, arg2); + tcg_out_op_rr(s, INDEX_op_neg, dest, dest); + tcg_wasm_out_negsetcond(s, type, dest, arg1, arg2, cond); +} + +static const TCGOutOpSetcond outop_negsetcond =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_negsetcond, +}; + +static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, + TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, + TCGArg vt, bool const_vt, TCGArg vf, bool consf_v= f) +{ + TCGOpcode opc =3D (type =3D=3D TCG_TYPE_I32 + ? INDEX_op_tci_movcond32 + : INDEX_op_movcond); + tcg_out_op_rrrrrc(s, opc, ret, c1, c2, vt, vf, cond); + tcg_wasm_out_movcond(s, type, ret, c1, c2, vt, vf, cond); +} + +static const TCGOutOpMovcond outop_movcond =3D { + .base.static_constraint =3D C_O1_I4(r, r, r, r, r), + .out =3D tgen_movcond, +}; + static void tcg_out_tb_start(TCGContext *s) { init_sub_buf(); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769411849; cv=none; d=zohomail.com; s=zohoarc; b=jf/pZ6dZGt3j1TnZsGn4OpMQR8BgtS3DgoiZGTiN+e2Adijc+uUaW3+KOAh9nRqmi/+AphKou+jPGJrGvRcgn6ITHh//oSS7/O1SFuZiq/Y5bgr2xM6DGtlcefAelzv8nKWgYzNSrGY2YcUyegKaSQbRqjaevgD1oPxh2eiLmoM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769411849; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gmEhCMQFwYXprx7A0TkE7yYmCb0tF8cpp+0XtJ4tnk8=; b=KCKSroRqidanpRovALXg90ffKZp202di+cLU/43ht2S1B+FFmtgsKYb2L4bTjXzxwSm8KNpGwWpp9Wdo+tp3M0rBEdskndRZ9q19Mci/3Iu9+lKCpN1bswzkIfM3f2xzKtAqjYULrWdg2PzTazSswfns1RMxZmV5Gz9Gpa6t/38= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176941184943680.31170437509422; Sun, 25 Jan 2026 23:17:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGna-0007OJ-Qm; Mon, 26 Jan 2026 02:14:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGf3-0002tL-Lz for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:05:42 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGeu-00048B-Ax for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:05:15 -0500 Received: by mail-pf1-x441.google.com with SMTP id d2e1a72fcca58-81f4e36512aso4129078b3a.3 for ; Sun, 25 Jan 2026 23:04:49 -0800 (PST) Received: from brahms.. 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.04.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:04:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411088; x=1770015888; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gmEhCMQFwYXprx7A0TkE7yYmCb0tF8cpp+0XtJ4tnk8=; b=RBI+F8Zhs0ppSEBrIUiGQeUyGoN6KrgjhAXaruo7e3YERfrrOK59/ydfAslf3M/szL Yk14XehU8IhFNj2BAqaTleFtWOPMUIkdx0XDQ+C62MbxsXzRxr85nOEDFMkIL4cbLJfK ryEl5BzgoOzm8o4tGSpz046IHVJHtGRCyIAs+cOImlORSliq3Ukihvyi004EouwbR6w+ MpL6lj8m/ktgLWZTGfdARRzG7fFYtpql8tZ08HhTx6nt9eB+MqJootiAhSsub5SeGPX8 hv0lpSMnOHkRfcfY9/symuIwpSdzmtyNGQMx/+p2B2koRwA5hMDSn0V8qYW8PL3H8S0K zJuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411088; x=1770015888; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=gmEhCMQFwYXprx7A0TkE7yYmCb0tF8cpp+0XtJ4tnk8=; b=jybzVcI0JE30U9Pe0CEWosJd4ke6Rwb3IA1p1qBLlJWKWfcl3qx8JBtlFxU6A217hd d28HqHjCyLTAkUP9iSza72AZvYhizjLMHOyjNsfxPu3GPe3YMS85SJ3Ab7vLsf/0DSyB g7IPVeWdeyhJyP9GleYzp5ee9t4eq6BW5VxWM1UbU66ra6xx+fuKybFe8AUgdRwP/ZTX Yts5gY7J217C97Z/tacbRiWoGNZZG6eNxiumCHu3W62clqALabGtwHYsxhsneBQSvyfY LjZEODtVqvXv6HoZmaL2vMPPRsd4xqneLNfNwMUWmIUHIoJINoxr22rz2aVO6jyKjwfS pGsg== X-Gm-Message-State: AOJu0Yy6DUecIRys8xUBcrRxQYJs0zhr7JRFSh8DFNgJpcgphb6xpsd+ nKeNZDyvKwZU9GAVGOGtly/PbTSXdB2DEBFaWELdzQWpkM5AuoNpKVEXzr67lCWAwDs= X-Gm-Gg: AZuq6aKktceXVmVjP7Wfape/oSdpnzi4Dbc1VDMB2u0BXDtP05ktFGY7TW7lH1IR3nS /crh5k8rzEozYigMAdPqttua2h/THKNfD033zLsYA7JMynscnPcWMA5UJYZfZJ1l8o3jI4Hyk63 1wQqJ8beI2jLzDDqopTMOr1VTsa5SZAjvtY84ROsw5XOUsVH0jNst6OjkdQyUdxKe4/MHPcdQQk ebezIt/AzgVh1RHK0yxG6HjuLNZ6GIfepcQE8HXW7SQ4GsveYFC3dKZYRbXRkPTZYOYslAeznc1 7eIxOGUIz3FvG669S0EXhODQR5r27jaAk2L4IC6AYnnl8FdqsEk3ZhRUJwh2NRlf0IRfBzGshe2 X2OYMwSLkb51RqQAXTesBNjhkzSwHxScrXD8JCbcMpX1acBauq574ooUG8zAioM6LHaqedo4ZDP C30jDaSgNB9jH3yVdIlONTD+0eYndQYLlV3HWtmeWrIYcyUbTvRWjX X-Received: by 2002:a05:6a00:2408:b0:81f:3e3e:c1fd with SMTP id d2e1a72fcca58-823411b854fmr3394964b3a.5.1769411087920; Sun, 25 Jan 2026 23:04:47 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 09/33] tcg/wasm64: Add sextract instruction Date: Mon, 26 Jan 2026 07:03:22 +0000 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x441.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769411850887158500 Content-Type: text/plain; charset="utf-8" The sextract operation is genereted only when the corresponding Wasm instructions are available, as specified by TCG_TARGET_sextract_valid. Signed-off-by: Kohei Tokunaga --- tcg/wasm64/tcg-target-has.h | 5 +++++ tcg/wasm64/tcg-target.c.inc | 42 +++++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/tcg/wasm64/tcg-target-has.h b/tcg/wasm64/tcg-target-has.h index 7e3caf8790..cfb85388de 100644 --- a/tcg/wasm64/tcg-target-has.h +++ b/tcg/wasm64/tcg-target-has.h @@ -4,4 +4,9 @@ =20 #define TCG_TARGET_HAS_tst 0 =20 +#define TCG_TARGET_extract_valid(type, ofs, len) 0 +#define TCG_TARGET_sextract_valid(type, ofs, len) \ + ((ofs =3D=3D 0) && ((len =3D=3D 8) || (len =3D=3D 16) || (len =3D=3D 3= 2))) +#define TCG_TARGET_deposit_valid(type, ofs, len) 0 + #endif diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index 70de3bbf83..dd75deecd3 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -182,7 +182,10 @@ typedef enum { OPC_I64_SHR_U =3D 0x88, =20 OPC_I32_WRAP_I64 =3D 0xa7, + OPC_I64_EXTEND_I32_S =3D 0xac, OPC_I64_EXTEND_I32_U =3D 0xad, + OPC_I64_EXTEND8_S =3D 0xc2, + OPC_I64_EXTEND16_S =3D 0xc3, } WasmInsn; =20 typedef enum { @@ -391,6 +394,33 @@ static void tcg_wasm_out_movcond(TCGContext *s, TCGTyp= e type, TCGReg ret, tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret)); } =20 +static void tcg_wasm_out_sextract(TCGContext *s, TCGReg dest, TCGReg arg1, + int pos, int len) +{ + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg1)); + + if (pos =3D=3D 0) { + switch (len) { + case 8: + tcg_wasm_out_op(s, OPC_I64_EXTEND8_S); + break; + case 16: + tcg_wasm_out_op(s, OPC_I64_EXTEND16_S); + break; + case 32: + tcg_wasm_out_op(s, OPC_I32_WRAP_I64); + tcg_wasm_out_op(s, OPC_I64_EXTEND_I32_S); + break; + default: + g_assert_not_reached(); + } + } else { + g_assert_not_reached(); + } + + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(dest)); +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { tcg_insn_unit_tci insn =3D 0; @@ -529,6 +559,18 @@ static const TCGOutOpBinary outop_mul =3D { .out_rrr =3D tgen_mul, }; =20 +static void tcg_out_sextract(TCGContext *s, TCGType type, TCGReg rd, + TCGReg rs, unsigned pos, unsigned len) +{ + tcg_out_op_rrbb(s, INDEX_op_sextract, rd, rs, pos, len); + tcg_wasm_out_sextract(s, rd, rs, pos, len); +} + +static const TCGOutOpExtract outop_sextract =3D { + .base.static_constraint =3D C_O1_I1(r, r), + .out_rr =3D tcg_out_sextract, +}; + static void tgen_shl(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412782; cv=none; d=zohomail.com; s=zohoarc; b=D2kWnvEa+jx0DKWvNeyvDz6PFdiw386FPrONOjtAhdHoX0GAaHhL43NyA3BvwrBViXuKefEPZBOwPovRVvfEUkgEMqHcyqTcKrVYXcnINT0/si2ZprzY3LuC5oZDGIXG5lll4z0SyJ/pgJv/1WGJ0QvPpF3Gq9YJYek9bG/O+vQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769412782; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=eKGZrzBEZomEKs9twQKesDOc8wmIyiWzTpm7XRfkzkI=; b=T5OciIQkaoHiOqBWY+G99cWcaKmmg3EG54mYRNpKSKGMFGDeHmazUZU6gfujwJbyOaT+NRpuUwfQqraLMvU8xR1qf7Nvpz14n2qT5ovtpJYWO3AbjA2BDAfRnLoarRa7aLYTHz0eqt6oZOGI3jJtP+XGIc+FyCXH8+6MdQvjQAE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769412782740102.54242698741325; Sun, 25 Jan 2026 23:33:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGt7-0004uA-ND; Mon, 26 Jan 2026 02:19:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGf3-0002rH-2m for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:05:42 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGes-00048e-9F for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:05:15 -0500 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-34c718c5481so2278678a91.3 for ; Sun, 25 Jan 2026 23:04:53 -0800 (PST) Received: from brahms.. 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.04.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:04:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411092; x=1770015892; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eKGZrzBEZomEKs9twQKesDOc8wmIyiWzTpm7XRfkzkI=; b=hUL0/QkRdtoMkM4N5lwtq68ZLzkrcAv9mobP3ptsoQ+vfQlMRav5SihI4Gb20zVGVj brDMnbeRFnSiYfdFLB48DWqh30lID6D02TeYOGwZR2cXnBvb8nysvRJSshXlq8Y9IR/d Ux764yTTCs3qCI/LJu7mvsxo4IfZW4awJ9VQpHF0kXm5Q+aFVc1VV5xhMqz6yrvJBfEK XISMCThuSiUXN06Fsl9elcqbk+BVox0kIk+KdKzQ6H6FinOhkbWdbQqOZM1EQ/tof5HB z1/ZUFVTe5aegIPgzNjdxLUjmo2rCCSL4lNmWegLd214kDEVipXtbz6bBlC1hE+s/Xz7 wbzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411092; x=1770015892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=eKGZrzBEZomEKs9twQKesDOc8wmIyiWzTpm7XRfkzkI=; b=fED2wuPE7K/1nteOwyM8FUAj6Dl3xGJs16ZWj+2q/HzudPkMzN4uFmY2NdVVakAxZd icq61Kk29l6qLqY3h8na5+Z5WixRI/IixeAs7PeXieswaEXB0RO8CZRYo9YbhBARCedd 1JUZ2lIasTvMnpZmqb+ggKhfG+IIAsc6q6v7qlmAT2jbRcb7BU+v9JrU/77izD/S0rnK eR/IOSZTNsph+02SnojxeAch5Yt2xaME5e4B/QO251h6FSp9GTJ/jTAyLz0Zxrdh2vCV 576YLeSeWOouj8fOQ9CTfQ/RXFUeIYJHJ6EPllWu2xgp4qhRNRwL8jPP5AAljDQgCZ8C Fe3g== X-Gm-Message-State: AOJu0Yy78EqnqnVcUvZGwxkZYy463k/j4W//JZw+vN/awPOhqkV+t98i vkyeGzRTkxgMGpfg3UssOeY3LB2oh79fOVBobODM9f1AO0XnVyJNyBcNmWvpad9r X-Gm-Gg: AZuq6aJn/nTTodHky3JtsWneV3vvOlyJdKdcjg5bUpMReP4lH5mQKoKYEr/uaSBYrCh kCzIbGoydaoLEWIRpNqFM4zTXIYHYuddedTFn4ccXb3bFIqPvKZ/N5XE0TZ1Ghxb3qBQnJ9BkkO 5KlWLxRrxkDVdkvndNYqKEt4MsofnivTUEhhhWonfoXvugTsJE2GnmFWrtlLU9uI1ckyDIKbFKa zwv+ZA9/tAdrMbtp8UHHp9KP5+cumiCTmrJItybI4x9SfcB00MDPhwCYyMHElN0L07cHHN683GH rgLGXaSE9UzmNe5XduRrahHiiaqmlyfpDc3DNBIokqMOr3TJZos5M2qeiDMM+1auFx/HfhUsiI9 CJuK4p9/x35SEiaALfI9xrj4XL7JhHfM49X+WWjwyazs+fsLsHfCTrZmJ5mShjszT7A5of9bbWY LzIeg4Tk4NYKR2ZwrbaTMgtFF39oB68r7WrzLosRBR4Q== X-Received: by 2002:a17:90b:1b10:b0:34c:75d1:6f90 with SMTP id 98e67ed59e1d1-353c41789c1mr3781364a91.17.1769411092379; Sun, 25 Jan 2026 23:04:52 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 10/33] tcg/wasm64: Add load and store instructions Date: Mon, 26 Jan 2026 07:03:23 +0000 Message-ID: <6573ef95bf4d2bd6d454b5cb3fe80026b19350b2.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412785426154100 Content-Type: text/plain; charset="utf-8" Since Wasm load and store instructions don't support negative offsets, address calculations are performed separately before the memory access. When Emscripten's -sMEMORY64=3D2 is enabled, the address size must be 32bits. So this commit updates the build tools to propagate this flag to the C code via the WASM64_MEMORY64_2 macro. In this case, the emitted code casts pointers to 32bit before memory oprations. Additionally, the declaration of "--wasm64-32bit-address-limit" flag has been moved from the configure script to meson.build. So the flag name is updated to "--enable-wasm64-32bit-address-limit" to follow Meson's naming conventions. TCI instructions are also generated in the same way as the original TCI backend. Signed-off-by: Kohei Tokunaga --- .gitlab-ci.d/buildtest.yml | 2 +- configure | 8 +- meson.build | 4 + meson_options.txt | 3 + scripts/meson-buildoptions.sh | 5 + tcg/wasm64.c | 87 ++++++++++ tcg/wasm64/tcg-target-mo.h | 20 +++ tcg/wasm64/tcg-target-opc.h.inc | 2 + tcg/wasm64/tcg-target.c.inc | 286 ++++++++++++++++++++++++++++++++ 9 files changed, 411 insertions(+), 6 deletions(-) create mode 100644 tcg/wasm64/tcg-target-mo.h diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index e9b5b05e6e..f9a2d4de74 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buildtest.yml @@ -801,4 +801,4 @@ build-wasm64-32bit: - job: wasm64-emsdk-cross-container variables: IMAGE: emsdk-wasm64-cross - CONFIGURE_ARGS: --static --cpu=3Dwasm64 --wasm64-32bit-address-limit -= -disable-tools --enable-debug --enable-tcg-interpreter + CONFIGURE_ARGS: --static --cpu=3Dwasm64 --enable-wasm64-32bit-address-= limit --disable-tools --enable-debug --enable-tcg-interpreter diff --git a/configure b/configure index e69b3e474e..e3e8e8387e 100755 --- a/configure +++ b/configure @@ -243,7 +243,9 @@ for opt do ;; --without-default-features) default_feature=3D"no" ;; - --wasm64-32bit-address-limit) wasm64_memory64=3D"2" + --enable-wasm64-32bit-address-limit) wasm64_memory64=3D"2" + ;; + --disable-wasm64-32bit-address-limit) wasm64_memory64=3D"1" ;; esac done @@ -760,8 +762,6 @@ for opt do ;; --disable-rust) rust=3Ddisabled ;; - --wasm64-32bit-address-limit) - ;; # everything else has the same name in configure and meson --*) meson_option_parse "$opt" "$optarg" ;; @@ -887,8 +887,6 @@ Advanced options (experts only): --disable-containers don't use containers for cross-building --container-engine=3DTYPE which container engine to use [$container_eng= ine] --gdb=3DGDB-path gdb to use for gdbstub tests [$gdb_bin] - --wasm64-32bit-address-limit Restrict wasm64 address space to 32-bit (de= fault - is to use the whole 64-bit range). EOF meson_options_help cat << EOF diff --git a/meson.build b/meson.build index 3108f01e88..7a81ff58be 100644 --- a/meson.build +++ b/meson.build @@ -371,6 +371,10 @@ elif host_os =3D=3D 'windows' if compiler.get_id() =3D=3D 'clang' and compiler.get_linker_id() !=3D 'l= d.lld' error('On windows, you need to use lld with clang - use msys2 clang64/= clangarm64 env') endif +elif host_os =3D=3D 'emscripten' + if cpu =3D=3D 'wasm64' and get_option('wasm64_32bit_address_limit') + qemu_common_flags +=3D '-DWASM64_MEMORY64_2' + endif endif =20 # Choose instruction set (currently x86-only) diff --git a/meson_options.txt b/meson_options.txt index 2836156257..8b36159a45 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -390,3 +390,6 @@ option('rust', type: 'feature', value: 'disabled', description: 'Rust support') option('strict_rust_lints', type: 'boolean', value: false, description: 'Enable stricter set of Rust warnings') + +option('wasm64_32bit_address_limit', type: 'boolean', value: false, + description: 'Restrict wasm64 address space to 32-bit (default is t= o use the whole 64-bit range).') diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh index 3d0d132344..04311765be 100644 --- a/scripts/meson-buildoptions.sh +++ b/scripts/meson-buildoptions.sh @@ -56,6 +56,9 @@ meson_options_help() { printf "%s\n" ' dtrace/ftrace/log/nop/simple/s= yslog/ust)' printf "%s\n" ' --enable-tsan enable thread sanitizer' printf "%s\n" ' --enable-ubsan enable undefined behaviour san= itizer' + printf "%s\n" ' --enable-wasm64-32bit-address-limit' + printf "%s\n" ' Restrict wasm64 address space = to 32-bit (default' + printf "%s\n" ' is to use the whole 64-bit ran= ge).' printf "%s\n" ' --firmwarepath=3DVALUES search PATH for firmware fil= es [share/qemu-' printf "%s\n" ' firmware]' printf "%s\n" ' --gdb=3DVALUE Path to GDB' @@ -576,6 +579,8 @@ _meson_option_parse() { --disable-vte) printf "%s" -Dvte=3Ddisabled ;; --enable-vvfat) printf "%s" -Dvvfat=3Denabled ;; --disable-vvfat) printf "%s" -Dvvfat=3Ddisabled ;; + --enable-wasm64-32bit-address-limit) printf "%s" -Dwasm64_32bit_addres= s_limit=3Dtrue ;; + --disable-wasm64-32bit-address-limit) printf "%s" -Dwasm64_32bit_addre= ss_limit=3Dfalse ;; --enable-werror) printf "%s" -Dwerror=3Dtrue ;; --disable-werror) printf "%s" -Dwerror=3Dfalse ;; --enable-whpx) printf "%s" -Dwhpx=3Denabled ;; diff --git a/tcg/wasm64.c b/tcg/wasm64.c index 183dad10a2..fa7413fc1d 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -20,6 +20,14 @@ =20 #include "qemu/osdep.h" #include "tcg/tcg.h" +#include "tcg/tcg-ldst.h" + +static void tci_args_rl(uint32_t insn, const void *tb_ptr, + TCGReg *r0, void **l1) +{ + *r0 =3D extract32(insn, 8, 4); + *l1 =3D sextract32(insn, 12, 20) + (void *)tb_ptr; +} =20 static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1) { @@ -27,6 +35,12 @@ static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGRe= g *r1) *r1 =3D extract32(insn, 12, 4); } =20 +static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1) +{ + *r0 =3D extract32(insn, 8, 4); + *i1 =3D sextract32(insn, 12, 20); +} + static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) { *r0 =3D extract32(insn, 8, 4); @@ -34,6 +48,13 @@ static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGR= eg *r1, TCGReg *r2) *r2 =3D extract32(insn, 16, 4); } =20 +static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i= 2) +{ + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *i2 =3D sextract32(insn, 16, 16); +} + static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, uint8_t *i2, uint8_t *i3) { @@ -161,9 +182,12 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *en= v, const void *v_tb_ptr) uint32_t insn; TCGOpcode opc; TCGReg r0, r1, r2, r3, r4; + tcg_target_ulong t1; uint8_t pos, len; TCGCond condition; uint32_t tmp32; + int32_t ofs; + void *ptr; =20 insn =3D *tb_ptr++; opc =3D extract32(insn, 0, 8); @@ -236,6 +260,69 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *en= v, const void *v_tb_ptr) tmp32 =3D tci_compare32(regs[r1], regs[r2], condition); regs[r0] =3D regs[tmp32 ? r3 : r4]; break; + case INDEX_op_tci_movi: + tci_args_ri(insn, &r0, &t1); + regs[r0] =3D t1; + break; + case INDEX_op_tci_movl: + tci_args_rl(insn, tb_ptr, &r0, &ptr); + regs[r0] =3D *(tcg_target_ulong *)ptr; + break; + case INDEX_op_ld: + tci_args_rrs(insn, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(tcg_target_ulong *)ptr; + break; + case INDEX_op_ld8u: + tci_args_rrs(insn, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint8_t *)ptr; + break; + case INDEX_op_ld8s: + tci_args_rrs(insn, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(int8_t *)ptr; + break; + case INDEX_op_ld16u: + tci_args_rrs(insn, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint16_t *)ptr; + break; + case INDEX_op_ld16s: + tci_args_rrs(insn, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(int16_t *)ptr; + break; + case INDEX_op_st: + tci_args_rrs(insn, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(tcg_target_ulong *)ptr =3D regs[r0]; + break; + case INDEX_op_st8: + tci_args_rrs(insn, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint8_t *)ptr =3D regs[r0]; + break; + case INDEX_op_st16: + tci_args_rrs(insn, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint16_t *)ptr =3D regs[r0]; + break; + case INDEX_op_ld32u: + tci_args_rrs(insn, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(uint32_t *)ptr; + break; + case INDEX_op_ld32s: + tci_args_rrs(insn, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + regs[r0] =3D *(int32_t *)ptr; + break; + case INDEX_op_st32: + tci_args_rrs(insn, &r0, &r1, &ofs); + ptr =3D (void *)(regs[r1] + ofs); + *(uint32_t *)ptr =3D regs[r0]; + break; default: g_assert_not_reached(); } diff --git a/tcg/wasm64/tcg-target-mo.h b/tcg/wasm64/tcg-target-mo.h new file mode 100644 index 0000000000..3ccc56e899 --- /dev/null +++ b/tcg/wasm64/tcg-target-mo.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific memory model + * + * Based on tci/tcg-target-mo.h + * + * Copyright (c) 2009, 2011 Stefan Weil + */ + +#ifndef TCG_TARGET_MO_H +#define TCG_TARGET_MO_H + +/* + * We could notice __x86_64__ or __s390x__ and reduce the barriers dependi= ng + * on the host. But if you want performance, you use the normal backend. + * We prefer consistency across hosts on this. + */ +#define TCG_TARGET_DEFAULT_MO 0 + +#endif diff --git a/tcg/wasm64/tcg-target-opc.h.inc b/tcg/wasm64/tcg-target-opc.h.= inc index 57274d4569..122b45749a 100644 --- a/tcg/wasm64/tcg-target-opc.h.inc +++ b/tcg/wasm64/tcg-target-opc.h.inc @@ -4,5 +4,7 @@ * * These opcodes for use between the tci generator and interpreter. */ +DEF(tci_movi, 1, 0, 1, TCG_OPF_NOT_PRESENT) +DEF(tci_movl, 1, 0, 1, TCG_OPF_NOT_PRESENT) DEF(tci_setcond32, 1, 2, 1, TCG_OPF_NOT_PRESENT) DEF(tci_movcond32, 1, 2, 1, TCG_OPF_NOT_PRESENT) diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index dd75deecd3..6b6d6402f4 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -143,6 +143,18 @@ typedef enum { OPC_GLOBAL_GET =3D 0x23, OPC_GLOBAL_SET =3D 0x24, =20 + OPC_I64_LOAD =3D 0x29, + OPC_I64_LOAD8_S =3D 0x30, + OPC_I64_LOAD8_U =3D 0x31, + OPC_I64_LOAD16_S =3D 0x32, + OPC_I64_LOAD16_U =3D 0x33, + OPC_I64_LOAD32_S =3D 0x34, + OPC_I64_LOAD32_U =3D 0x35, + OPC_I64_STORE =3D 0x37, + OPC_I64_STORE8 =3D 0x3c, + OPC_I64_STORE16 =3D 0x3d, + OPC_I64_STORE32 =3D 0x3e, + OPC_I32_CONST =3D 0x41, OPC_I64_CONST =3D 0x42, =20 @@ -168,6 +180,7 @@ typedef enum { OPC_I64_GE_S =3D 0x59, OPC_I64_GE_U =3D 0x5a, =20 + OPC_I32_ADD =3D 0x6a, OPC_I32_SHR_S =3D 0x75, OPC_I32_SHR_U =3D 0x76, =20 @@ -421,6 +434,84 @@ static void tcg_wasm_out_sextract(TCGContext *s, TCGRe= g dest, TCGReg arg1, tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(dest)); } =20 +/* + * The size of the offset field of Wasm's load/store instruction differs + * depending on the "-sMEMORY64" flag value: 64bit when "-sMEMORY64=3D1" + * and 32bit when "-sMEMORY64=3D2". + */ +#if defined(WASM64_MEMORY64_2) +typedef uint32_t wasm_ldst_offset_t; +#else +typedef uint64_t wasm_ldst_offset_t; +#endif +static void tcg_wasm_out_op_ldst( + TCGContext *s, WasmInsn instr, uint32_t a, wasm_ldst_offset_t o) +{ + tcg_wasm_out_op(s, instr); + tcg_wasm_out_leb128(s, a); + tcg_wasm_out_leb128(s, (wasm_ldst_offset_t)o); +} + +/* + * tcg_wasm_out_norm_ptr emits instructions to adjust the 64bit pointer va= lue + * at the top of the stack to satisfy Wasm's memory addressing requirement= s. + */ +static intptr_t tcg_wasm_out_norm_ptr(TCGContext *s, intptr_t offset) +{ +#if defined(WASM64_MEMORY64_2) + /* + * If Emscripten's "-sMEMORY64=3D2" is enabled, + * the address size is limited to 32bit. + */ + tcg_wasm_out_op(s, OPC_I32_WRAP_I64); +#endif + /* + * Wasm's load/store instructions don't support negative value in + * the offset field. So this function calculates the target address + * using the base and the offset and makes the offset field 0. + */ + if (offset < 0) { +#if defined(WASM64_MEMORY64_2) + tcg_wasm_out_op_const(s, OPC_I32_CONST, offset); + tcg_wasm_out_op(s, OPC_I32_ADD); +#else + tcg_wasm_out_op_const(s, OPC_I64_CONST, offset); + tcg_wasm_out_op(s, OPC_I64_ADD); +#endif + offset =3D 0; + } + return offset; +} + +static void tcg_wasm_out_ld( + TCGContext *s, WasmInsn opc, TCGReg val, TCGReg base, intptr_t offset) +{ + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(base)); + offset =3D tcg_wasm_out_norm_ptr(s, offset); + tcg_wasm_out_op_ldst(s, opc, 0, offset); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(val)); +} + +static void tcg_wasm_out_st( + TCGContext *s, WasmInsn opc, TCGReg val, TCGReg base, intptr_t offset) +{ + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(base)); + offset =3D tcg_wasm_out_norm_ptr(s, offset); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(val)); + tcg_wasm_out_op_ldst(s, opc, 0, offset); +} + +static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t = i1) +{ + tcg_insn_unit_tci insn =3D 0; + + tcg_debug_assert(i1 =3D=3D sextract32(i1, 0, 20)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 20, i1); + tcg_out32(s, insn); +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { tcg_insn_unit_tci insn =3D 0; @@ -443,6 +534,19 @@ static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, tcg_out32(s, insn); } =20 +static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, intptr_t i2) +{ + tcg_insn_unit_tci insn =3D 0; + + tcg_debug_assert(i2 =3D=3D sextract32(i2, 0, 16)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 16, i2); + tcg_out32(s, insn); +} + static void tcg_out_op_rrbb(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, uint8_t b2, uint8_t b3) { @@ -669,6 +773,188 @@ static const TCGOutOpMovcond outop_movcond =3D { .out =3D tgen_movcond, }; =20 +static void tcg_tci_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + switch (type) { + case TCG_TYPE_I32: + arg =3D (int32_t)arg; + /* fall through */ + case TCG_TYPE_I64: + break; + default: + g_assert_not_reached(); + } + + if (arg =3D=3D sextract32(arg, 0, 20)) { + tcg_out_op_ri(s, INDEX_op_tci_movi, ret, arg); + } else { + tcg_insn_unit_tci insn =3D 0; + + new_pool_label(s, arg, 20, s->code_ptr, 0); + insn =3D deposit32(insn, 0, 8, INDEX_op_tci_movl); + insn =3D deposit32(insn, 8, 4, ret); + tcg_out32(s, insn); + } +} + +static void stack_bounds_check(TCGReg base, intptr_t offset) +{ + if (base =3D=3D TCG_REG_CALL_STACK) { + tcg_debug_assert(offset >=3D 0); + tcg_debug_assert(offset < (TCG_STATIC_CALL_ARGS_SIZE + + TCG_STATIC_FRAME_SIZE)); + } +} + +static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val, + TCGReg base, intptr_t offset) +{ + stack_bounds_check(base, offset); + if (offset !=3D sextract32(offset, 0, 16)) { + tcg_tci_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); + tcg_out_op_rrr(s, INDEX_op_add, TCG_REG_TMP, TCG_REG_TMP, base); + base =3D TCG_REG_TMP; + offset =3D 0; + } + tcg_out_op_rrs(s, op, val, base, offset); +} + +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, + intptr_t offset) +{ + TCGOpcode op =3D INDEX_op_ld; + WasmInsn wasm_opc =3D OPC_I64_LOAD; + + if (type =3D=3D TCG_TYPE_I32) { + op =3D INDEX_op_ld32u; + wasm_opc =3D OPC_I64_LOAD32_U; + } + tcg_out_ldst(s, op, val, base, offset); + tcg_wasm_out_ld(s, wasm_opc, val, base, offset); +} + +static void tgen_ld8u(TCGContext *s, TCGType type, TCGReg dest, + TCGReg base, ptrdiff_t offset) +{ + tcg_out_ldst(s, INDEX_op_ld8u, dest, base, offset); + tcg_wasm_out_ld(s, OPC_I64_LOAD8_U, dest, base, offset); +} + +static const TCGOutOpLoad outop_ld8u =3D { + .base.static_constraint =3D C_O1_I1(r, r), + .out =3D tgen_ld8u, +}; + +static void tgen_ld8s(TCGContext *s, TCGType type, TCGReg dest, + TCGReg base, ptrdiff_t offset) +{ + tcg_out_ldst(s, INDEX_op_ld8s, dest, base, offset); + tcg_wasm_out_ld(s, OPC_I64_LOAD8_S, dest, base, offset); +} + +static const TCGOutOpLoad outop_ld8s =3D { + .base.static_constraint =3D C_O1_I1(r, r), + .out =3D tgen_ld8s, +}; + +static void tgen_ld16u(TCGContext *s, TCGType type, TCGReg dest, + TCGReg base, ptrdiff_t offset) +{ + tcg_out_ldst(s, INDEX_op_ld16u, dest, base, offset); + tcg_wasm_out_ld(s, OPC_I64_LOAD16_U, dest, base, offset); +} + +static const TCGOutOpLoad outop_ld16u =3D { + .base.static_constraint =3D C_O1_I1(r, r), + .out =3D tgen_ld16u, +}; + +static void tgen_ld16s(TCGContext *s, TCGType type, TCGReg dest, + TCGReg base, ptrdiff_t offset) +{ + tcg_out_ldst(s, INDEX_op_ld16s, dest, base, offset); + tcg_wasm_out_ld(s, OPC_I64_LOAD16_S, dest, base, offset); +} + +static const TCGOutOpLoad outop_ld16s =3D { + .base.static_constraint =3D C_O1_I1(r, r), + .out =3D tgen_ld16s, +}; + +static void tgen_ld32u(TCGContext *s, TCGType type, TCGReg dest, + TCGReg base, ptrdiff_t offset) +{ + tcg_out_ldst(s, INDEX_op_ld32u, dest, base, offset); + tcg_wasm_out_ld(s, OPC_I64_LOAD32_U, dest, base, offset); +} + +static const TCGOutOpLoad outop_ld32u =3D { + .base.static_constraint =3D C_O1_I1(r, r), + .out =3D tgen_ld32u, +}; + +static void tgen_ld32s(TCGContext *s, TCGType type, TCGReg dest, + TCGReg base, ptrdiff_t offset) +{ + tcg_out_ldst(s, INDEX_op_ld32s, dest, base, offset); + tcg_wasm_out_ld(s, OPC_I64_LOAD32_S, dest, base, offset); +} + +static const TCGOutOpLoad outop_ld32s =3D { + .base.static_constraint =3D C_O1_I1(r, r), + .out =3D tgen_ld32s, +}; + +static void tgen_st8(TCGContext *s, TCGType type, TCGReg data, + TCGReg base, ptrdiff_t offset) +{ + tcg_out_ldst(s, INDEX_op_st8, data, base, offset); + tcg_wasm_out_st(s, OPC_I64_STORE8, data, base, offset); +} + +static const TCGOutOpStore outop_st8 =3D { + .base.static_constraint =3D C_O0_I2(r, r), + .out_r =3D tgen_st8, +}; + +static void tgen_st16(TCGContext *s, TCGType type, TCGReg data, + TCGReg base, ptrdiff_t offset) +{ + tcg_out_ldst(s, INDEX_op_st16, data, base, offset); + tcg_wasm_out_st(s, OPC_I64_STORE16, data, base, offset); +} + +static const TCGOutOpStore outop_st16 =3D { + .base.static_constraint =3D C_O0_I2(r, r), + .out_r =3D tgen_st16, +}; + +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg bas= e, + intptr_t offset) +{ + TCGOpcode op =3D INDEX_op_st; + WasmInsn wasm_opc =3D OPC_I64_STORE; + + if (type =3D=3D TCG_TYPE_I32) { + op =3D INDEX_op_st32; + wasm_opc =3D OPC_I64_STORE32; + } + tcg_out_ldst(s, op, val, base, offset); + tcg_wasm_out_st(s, wasm_opc, val, base, offset); +} + +static const TCGOutOpStore outop_st =3D { + .base.static_constraint =3D C_O0_I2(r, r), + .out_r =3D tcg_out_st, +}; + +static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) +{ + return false; +} + static void tcg_out_tb_start(TCGContext *s) { init_sub_buf(); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.04.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:04:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411097; x=1770015897; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xLnjwS0H8xJ5zGA0L6/eddBTubde3eAT1NVQlZwuDi8=; b=II1bCHKCZQrsTr9T76FujldLyteVnlwmblxLXEDc811WOsysnbX43kYGr8+15fswxG /2I0czXOkdO+dY4C/DFGVnAQw2AIbLsIXFp9/HEGOlctWko4EUaXXhK86Fq6TKBE7set K12P7n+Y0JCEmTOBubV4TNzDMDU/6IWv6wZPfbO3gIUGMfhIy1pZYkJBt44YxtQ3Wuvb +qhzPvf5+hvtUAJ330NVL2XQf5GmbC9wKCy6UQKzGd4bNvI11Q1wYrUcr5bLSwjzjB+9 7iw8RrbX7yTwUn8TRrE/LdLt/FDXdLNCAJP3lTvHhr5/cVK+K4N2ZJ5IyPIZX3sPR9iD tOiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411097; x=1770015897; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=xLnjwS0H8xJ5zGA0L6/eddBTubde3eAT1NVQlZwuDi8=; b=JzCud14VvlW2PMO+Co6AfVjtg2KHhXBaw21Z9srFpDXoqXxfTtuD44oZH2fOWlhTDD 3I7KYtIfbK3Gz3lafSILageirMc2noQXIAkzZ0ofvuHlv/Y75BO1eN5LrbZXAe3HFxz3 1Rvdx6yYO7Jr9qyjeY8BDw/FfxD1L5E6GcZ1cpTySvcmDFgZ1NMju7H8n197Gxjf+TBL U7pAAC0Ebvy+1O4WWoZPk6+OZ7GR50HjqJ0c5Z9H/2gWtrsAzZ46VwB9Bu583G72eqf9 grHP9AnX+sciy9Z9kKzhBVJ3XnVBBDOHag04u0dSs6e/+MD8khZMm22wwXFBMF+rJpcI e/DA== X-Gm-Message-State: AOJu0Yxx5DDrfivDYEeEOFDfCOKxo17SBPHYDReNlUoTbAM4m/W0pxQ0 k7DI47D1NcMBrS/EMmtQ5ltaOFpQo2pXx3AesjLas9ogGZX5n9TFJEW15wBp5+Xt X-Gm-Gg: AZuq6aK5C3ev3GQOfU+6SPXN1nwf2bPgMWtCQtoo2mqSY+J4vQif4dnd9FRsty50g8T C2V4eEtQhKBfPjpbsBydsk0Wsnu7ueagBz7N1quc0hVV6aGzs5JIWhJn5ZLtLuys3zE8p0IvUhT a8tpHlDJdaHdk9HIzSotQjdjZSikup//lCdKF/Rp4javLkuSWzunqI/Jc9Wm2VTI4A1JOwIJOCk DEAowgpc5wfZKYeKfgy9SlHO3im2IJejtP0bNuWtioUYtvUc/g5ulVf1XnguUUxXA6VQdCz0OWr FgknN/aWZChZKSiDcOidP3BHVQKqznmlkHMqHvyvNZH+f/iQ/a/MvMH1fJO7iDOYwgb6y8HMZZi Hqs+fkkHabqY6RWBO3tSs2mNll+We51cpAJcoNtKhYPW+x8Rwkv5XnOZfhkYDHoZaZiosPUkDEh qGaTq/U1pLW7Cuc6wrwnKHeg5h72bf3NRyMMsJ/wwPzA== X-Received: by 2002:a05:6a00:188f:b0:821:8ebc:2899 with SMTP id d2e1a72fcca58-823411dc3d6mr3174807b3a.7.1769411096762; Sun, 25 Jan 2026 23:04:56 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 11/33] tcg/wasm64: Add mov/movi instructions Date: Mon, 26 Jan 2026 07:03:24 +0000 Message-ID: <8c72aab90a9c5839e91914ff545face4aa37f2d0.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412014944154100 Content-Type: text/plain; charset="utf-8" Theese operations are implemented using the corresponding instructions in Wasm. TCI instructions are also generated in the same way as the original TCI backend. Signed-off-by: Kohei Tokunaga --- tcg/wasm64.c | 4 ++++ tcg/wasm64/tcg-target.c.inc | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/tcg/wasm64.c b/tcg/wasm64.c index fa7413fc1d..2c8a7b814e 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -260,6 +260,10 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *en= v, const void *v_tb_ptr) tmp32 =3D tci_compare32(regs[r1], regs[r2], condition); regs[r0] =3D regs[tmp32 ? r3 : r4]; break; + case INDEX_op_mov: + tci_args_rr(insn, &r0, &r1); + regs[r0] =3D regs[r1]; + break; case INDEX_op_tci_movi: tci_args_ri(insn, &r0, &t1); regs[r0] =3D t1; diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index 6b6d6402f4..f308cc68f2 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -501,6 +501,28 @@ static void tcg_wasm_out_st( tcg_wasm_out_op_ldst(s, opc, 0, offset); } =20 +static void tcg_wasm_out_mov(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg)); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret)); +} + +static void tcg_wasm_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + switch (type) { + case TCG_TYPE_I32: + tcg_wasm_out_op_const(s, OPC_I64_CONST, (int32_t)arg); + break; + case TCG_TYPE_I64: + tcg_wasm_out_op_const(s, OPC_I64_CONST, arg); + break; + default: + g_assert_not_reached(); + } + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret)); +} + static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t = i1) { tcg_insn_unit_tci insn =3D 0; @@ -798,6 +820,20 @@ static void tcg_tci_out_movi(TCGContext *s, TCGType ty= pe, } } =20 +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +{ + tcg_out_op_rr(s, INDEX_op_mov, ret, arg); + tcg_wasm_out_mov(s, ret, arg); + return true; +} + +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + tcg_tci_out_movi(s, type, ret, arg); + tcg_wasm_out_movi(s, type, ret, arg); +} + static void stack_bounds_check(TCGReg base, intptr_t offset) { if (base =3D=3D TCG_REG_CALL_STACK) { --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769411731; cv=none; d=zohomail.com; s=zohoarc; b=BzJZq0NWC2/4lhzt45R5vRCyPuQadY0RSyWKGXw9kq6rw9tBkusRCshckjZctkszi78HLpknz43+B5KYYGvEqdrOszbXSEULjdDqF4xR4G/H0FY1w1s1+/IOq4DBuCtyEqmP7Ms7jhv5hEjb4nptYW5i0OtpGc77REBbAvm3trg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769411731; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4YcIv62PuJ+rNK7vCkPRmKZd5P+oXUEOIgAG8NgaOBE=; b=TK28D+GsccGEXYnEr07mmXDKuOE8xFLyQ87tmRgIiTZM3/qLgILpQBItt7mtK/OCzd+PKrgkSBSdunJdcG388gyhsoRbl2DDoii0iZPtoeC/TfsEHHT7lkwetlb5oGbUrn8kaF5V9Nt7FBJL2mtKMuq3Kb4xfFJ59Q3tLt8/qLM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769411731295260.1639472890246; Sun, 25 Jan 2026 23:15:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGoQ-000896-Tf; Mon, 26 Jan 2026 02:15:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGf3-0002tM-Lw for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:05:42 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGeu-000496-Ph for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:05:15 -0500 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-81f4e36512aso4129231b3a.3 for ; Sun, 25 Jan 2026 23:05:02 -0800 (PST) Received: from brahms.. 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TCI instructions are also generated in the same way as the original TCI backend. Signed-off-by: Kohei Tokunaga --- tcg/wasm64/tcg-target-has.h | 1 + tcg/wasm64/tcg-target.c.inc | 79 +++++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/tcg/wasm64/tcg-target-has.h b/tcg/wasm64/tcg-target-has.h index cfb85388de..a29ceb2ea5 100644 --- a/tcg/wasm64/tcg-target-has.h +++ b/tcg/wasm64/tcg-target-has.h @@ -3,6 +3,7 @@ #define TCG_TARGET_HAS_H =20 #define TCG_TARGET_HAS_tst 0 +#define TCG_TARGET_HAS_extr_i64_i32 0 =20 #define TCG_TARGET_extract_valid(type, ofs, len) 0 #define TCG_TARGET_sextract_valid(type, ofs, len) \ diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index f308cc68f2..4131595fce 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -434,6 +434,22 @@ static void tcg_wasm_out_sextract(TCGContext *s, TCGRe= g dest, TCGReg arg1, tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(dest)); } =20 +static void tcg_wasm_out_extract(TCGContext *s, TCGReg dest, TCGReg arg1, + int pos, int len) +{ + int64_t mask =3D ~0ULL >> (64 - len); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg1)); + if (pos > 0) { + tcg_wasm_out_op_const(s, OPC_I64_CONST, pos); + tcg_wasm_out_op(s, OPC_I64_SHR_U); + } + if ((pos + len) < 64) { + tcg_wasm_out_op_const(s, OPC_I64_CONST, mask); + tcg_wasm_out_op(s, OPC_I64_AND); + } + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(dest)); +} + /* * The size of the offset field of Wasm's load/store instruction differs * depending on the "-sMEMORY64" flag value: 64bit when "-sMEMORY64=3D1" @@ -991,6 +1007,69 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType= type, TCGArg val, return false; } =20 +static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg r= s) +{ + tcg_out_sextract(s, type, rd, rs, 0, 8); + tcg_wasm_out_sextract(s, rd, rs, 0, 8); +} + +static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_op_rrbb(s, INDEX_op_extract, rd, rs, 0, 8); + tcg_wasm_out_extract(s, rd, rs, 0, 8); +} + +static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg = rs) +{ + tcg_out_sextract(s, type, rd, rs, 0, 16); + tcg_wasm_out_sextract(s, rd, rs, 0, 16); +} + +static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_op_rrbb(s, INDEX_op_extract, rd, rs, 0, 16); + tcg_wasm_out_extract(s, rd, rs, 0, 16); +} + +static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_sextract(s, TCG_TYPE_I64, rd, rs, 0, 32); + tcg_wasm_out_sextract(s, rd, rs, 0, 32); +} + +static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_op_rrbb(s, INDEX_op_extract, rd, rs, 0, 32); + tcg_wasm_out_extract(s, rd, rs, 0, 32); +} + +static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_ext32s(s, rd, rs); +} + +static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_ext32u(s, rd, rs); +} + +static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_op_rr(s, INDEX_op_mov, rd, rs); + tcg_wasm_out_extract(s, rd, rs, 0, 32); +} + +static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg= a1) +{ + tcg_out_op_rrbb(s, INDEX_op_extract, a0, a1, 32, 32); + tcg_wasm_out_extract(s, a0, a1, 32, 32); +} + +static const TCGOutOpUnary outop_extrh_i64_i32 =3D { + .base.static_constraint =3D C_O1_I1(r, r), + .out_rr =3D tgen_extrh_i64_i32, +}; + static void tcg_out_tb_start(TCGContext *s) { init_sub_buf(); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412523; cv=none; d=zohomail.com; s=zohoarc; b=VFQnWEQCtZvu3C8157jKBBjdWj65tnxR8OfZIA3hnb7Oh/MWJ1jxMEEDpGNjnK2PyVbaZJWXZd8Tax3vp7/w4hmcWaHblnTzg2LUXvzF8nntazeRxhNAGyD2YrJ8/OnBffRiUuikyLUqcCoGBBTZhyh6na9r81PfpcC8z4+qLWM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769412523; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:05:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411106; x=1770015906; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g3Pe0nbPZv/rihffMMsnlYdWZcSw9d/3vgrrjLHECqs=; b=ljhcINzbtiDwm7u39KEJlMx7qkAefOAy724yUz5z8x7LGHVa1n8CVCvmIKeQYaeiaS d2H/CeGRTQtTFu109VTAKRjwshBmC9duuz2/KApYBv04ZMOMmsPtLey1G5UC54q/LVuT YN/0L9jplpSOxa8e5IUxQn3WG+JUdZOCqYzn0fMEHsMlkgcFGis9co6SA4tI1kCRG0Zq OwyLMDQiEjlFg2gqDjoVcKZB2bvuLQz74qQ4Gdl141NNmoFQf/Z3lpS7zoEcSlNJAUyd bRwGApdHXofnwapeoTb2KzZhsPPrbvPhyxsUjHYPofCyjgTvY1gbHQNK+8XbEwaFz/kR SYVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411106; x=1770015906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=g3Pe0nbPZv/rihffMMsnlYdWZcSw9d/3vgrrjLHECqs=; b=iosGyF0+Ogk6tYGKh7S6Wr9zaQjc+ojM65n20DaKKV9e79lnPxGOZhKiarmIiKnNu2 nuoZMlYJIuBto1k5VXqLTgDwMdNwb7Fse1c/jhtBwrrrQARXEf4dtPBNc0nqJxFNgj1W o/hhB3mNtm++Uy0F50vbDddGNN8lqGbfYZjtj99Tbl8EibHdTYazeVOXL69Gd4p/SFg6 iUdSP/f4J7xqu0YMNapMdCrWy3tKt+KV/YPUMqgudtdRDivx9DZNCnxJarEqxTR5PVPb MPuPzU5lkP5OiUP0MnQrKU4W/XNI8TN9YB8i/G7VkU7WI0b/nMPF50FwoXLKPXPduDCH 5+YA== X-Gm-Message-State: AOJu0YxiyomS/4+/2bwUvWqwjLIMLR8pDl53BonRlFYKrDMXRKTqgutI i2/Oy/a+vRxLNzyTs5/eTCse8A+38b4MhI6S6NFf0kX8Ce8yDgYil2WmfXi72Ba1 X-Gm-Gg: AZuq6aLpLYrV1Es3SYzYJ/vOPvUymN/ThIfsZBD5sCOyd6BvdFMH5knDdGkBsd3/9Bg 1DGBfNiS69TzDqFSsFVU7NhxMeh3K679Kwk9MRTiLGLLGU1LERDvG+HeM2727f9U0h7F+5X0pwl 85MQVLALt8OGwOhhgQjuxYgvuurtiCZ417qXQ36VcPEWw/cKRiDuAbTDxlsOLwNNsITYBfWZHf3 RRFfKhzTBTI1WIOVlnx7TlZ5GHRm3xR4bmfbn5ahlpM1OAXZ+Kam4rCZfpqrWQZXEJ/CRdgIcSA xhJ5DPyM9nDYmBaisBiVhCigXM5Oj5Xjs2UVGRzpafVhjacII2UrDd5IYy9Z9vrvDnAqG0ETPT/ aVmkhvWpwRREldydSm1NYxf6JtPoQNiRiXTJ7SutIdF5MiJsroL8FwN/UdARoSulvukefxBKRLx j7vsRxtyEadlLYlpWydTcs5DYRUTt4dC6JbjsTOGkoTb6Xno9qGXdo X-Received: by 2002:a05:6a00:94f5:b0:81c:5bca:8104 with SMTP id d2e1a72fcca58-8234122e4f1mr2902683b3a.24.1769411105684; Sun, 25 Jan 2026 23:05:05 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 13/33] tcg/wasm64: Add div/rem instructions Date: Mon, 26 Jan 2026 07:03:26 +0000 Message-ID: <6d41128fb32942c6f6ee526b078c611cf147960b.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412525684154100 Content-Type: text/plain; charset="utf-8" The div and rem operations are implemented using the corresponding instructions in Wasm. TCI instructions are also generated in the same way as the original TCI backend. Signed-off-by: Kohei Tokunaga --- tcg/wasm64.c | 32 ++++++++++++++++ tcg/wasm64/tcg-target-opc.h.inc | 4 ++ tcg/wasm64/tcg-target.c.inc | 68 +++++++++++++++++++++++++++++++++ 3 files changed, 104 insertions(+) diff --git a/tcg/wasm64.c b/tcg/wasm64.c index 2c8a7b814e..8c8dcb81c7 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -327,6 +327,38 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *en= v, const void *v_tb_ptr) ptr =3D (void *)(regs[r1] + ofs); *(uint32_t *)ptr =3D regs[r0]; break; + case INDEX_op_divs: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D (int64_t)regs[r1] / (int64_t)regs[r2]; + break; + case INDEX_op_divu: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D (uint64_t)regs[r1] / (uint64_t)regs[r2]; + break; + case INDEX_op_rems: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D (int64_t)regs[r1] % (int64_t)regs[r2]; + break; + case INDEX_op_remu: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D (uint64_t)regs[r1] % (uint64_t)regs[r2]; + break; + case INDEX_op_tci_divs32: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D (int32_t)regs[r1] / (int32_t)regs[r2]; + break; + case INDEX_op_tci_divu32: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] / (uint32_t)regs[r2]; + break; + case INDEX_op_tci_rems32: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D (int32_t)regs[r1] % (int32_t)regs[r2]; + break; + case INDEX_op_tci_remu32: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D (uint32_t)regs[r1] % (uint32_t)regs[r2]; + break; default: g_assert_not_reached(); } diff --git a/tcg/wasm64/tcg-target-opc.h.inc b/tcg/wasm64/tcg-target-opc.h.= inc index 122b45749a..5ed8c67535 100644 --- a/tcg/wasm64/tcg-target-opc.h.inc +++ b/tcg/wasm64/tcg-target-opc.h.inc @@ -8,3 +8,7 @@ DEF(tci_movi, 1, 0, 1, TCG_OPF_NOT_PRESENT) DEF(tci_movl, 1, 0, 1, TCG_OPF_NOT_PRESENT) DEF(tci_setcond32, 1, 2, 1, TCG_OPF_NOT_PRESENT) DEF(tci_movcond32, 1, 2, 1, TCG_OPF_NOT_PRESENT) +DEF(tci_divs32, 1, 2, 0, TCG_OPF_NOT_PRESENT) +DEF(tci_divu32, 1, 2, 0, TCG_OPF_NOT_PRESENT) +DEF(tci_rems32, 1, 2, 0, TCG_OPF_NOT_PRESENT) +DEF(tci_remu32, 1, 2, 0, TCG_OPF_NOT_PRESENT) diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index 4131595fce..d4db2528f8 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -181,12 +181,20 @@ typedef enum { OPC_I64_GE_U =3D 0x5a, =20 OPC_I32_ADD =3D 0x6a, + OPC_I32_DIV_S =3D 0x6d, + OPC_I32_DIV_U =3D 0x6e, + OPC_I32_REM_S =3D 0x6f, + OPC_I32_REM_U =3D 0x70, OPC_I32_SHR_S =3D 0x75, OPC_I32_SHR_U =3D 0x76, =20 OPC_I64_ADD =3D 0x7c, OPC_I64_SUB =3D 0x7d, OPC_I64_MUL =3D 0x7e, + OPC_I64_DIV_S =3D 0x7f, + OPC_I64_DIV_U =3D 0x80, + OPC_I64_REM_S =3D 0x81, + OPC_I64_REM_U =3D 0x82, OPC_I64_AND =3D 0x83, OPC_I64_OR =3D 0x84, OPC_I64_XOR =3D 0x85, @@ -1070,6 +1078,66 @@ static const TCGOutOpUnary outop_extrh_i64_i32 =3D { .out_rr =3D tgen_extrh_i64_i32, }; =20 +static void tgen_divs(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + TCGOpcode opc =3D (type =3D=3D TCG_TYPE_I32 + ? INDEX_op_tci_divs32 + : INDEX_op_divs); + tcg_out_op_rrr(s, opc, a0, a1, a2); + tcg_wasm_out_o1_i2_type(s, type, OPC_I32_DIV_S, OPC_I64_DIV_S, a0, a1,= a2); +} + +static const TCGOutOpBinary outop_divs =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_divs, +}; + +static void tgen_divu(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + TCGOpcode opc =3D (type =3D=3D TCG_TYPE_I32 + ? INDEX_op_tci_divu32 + : INDEX_op_divu); + tcg_out_op_rrr(s, opc, a0, a1, a2); + tcg_wasm_out_o1_i2_type(s, type, OPC_I32_DIV_U, OPC_I64_DIV_U, a0, a1,= a2); +} + +static const TCGOutOpBinary outop_divu =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_divu, +}; + +static void tgen_rems(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + TCGOpcode opc =3D (type =3D=3D TCG_TYPE_I32 + ? INDEX_op_tci_rems32 + : INDEX_op_rems); + tcg_out_op_rrr(s, opc, a0, a1, a2); + tcg_wasm_out_o1_i2_type(s, type, OPC_I32_REM_S, OPC_I64_REM_S, a0, a1,= a2); +} + +static const TCGOutOpBinary outop_rems =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_rems, +}; + +static void tgen_remu(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + TCGOpcode opc =3D (type =3D=3D TCG_TYPE_I32 + ? INDEX_op_tci_remu32 + : INDEX_op_remu); + tcg_out_op_rrr(s, opc, a0, a1, a2); + tcg_wasm_out_o1_i2_type(s, type, OPC_I32_REM_U, OPC_I64_REM_U, a0, a1,= a2); +} + +static const TCGOutOpBinary outop_remu =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_remu, +}; + static void tcg_out_tb_start(TCGContext *s) { init_sub_buf(); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412093; cv=none; d=zohomail.com; s=zohoarc; b=hq3yxPCt0nRjkzB+6X0fSmDd69N35HUB0x7SDqbp/A85khdG/CwzY+R6ToF188IVCg689x12SzvOXGG9K/N3vZ2ZPjKp93E4wNLtNnob5R40nTVtTjA8HIcbxACFOh9I4XCZbD8jQrQD+3YBElYi/CWZTiS9H26vaovK49l1Ou0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769412093; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4wyAR69Bcdaoiwt/QbVg4P4PwKbHvN8hOTaOTvBaaj0=; b=calL2vLkNl075X0qGO0Tch9o4LXGA436YiGj4UNjiEhHxrBVaOvpukhNPA17NbeSmcXVfSO7pLKLSUjnd5+Q3ilXl51VvybNtOgyg769TtFaVcu2i1rvb8VN966LCesfu3+QPG5GLnyR1p/Pe+PQBEfZnniCmGPn9+6ZLNRMe4o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769412093564947.4322917100754; Sun, 25 Jan 2026 23:21:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGtF-0005BE-ML; Mon, 26 Jan 2026 02:20:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGg2-00038P-9s for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:06:30 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGfr-0004Kq-Hc for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:06:16 -0500 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-823210d1d8eso1136940b3a.1 for ; Sun, 25 Jan 2026 23:05:11 -0800 (PST) Received: from brahms.. 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.05.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:05:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411110; x=1770015910; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4wyAR69Bcdaoiwt/QbVg4P4PwKbHvN8hOTaOTvBaaj0=; b=m/rktlBuYrMjqwiZ2xdutqSryeLsY2RCQVBWSfO9UtsZCu+CHl6+z+yrfKiO2RN6HN /2s9GXp+IzFzSe7pQhmnRPoj1Wb8SYnKRv6EOQ58kSiFG8Q1S/rfQqAAeMLkwfflrKS2 aN4QCJB5BHUs+WkXyAOnzwIx5E7kj9r8zaqxjXO88pnG2pPWMWVIvgR3xi0qPyMGvTnP 9+EnBnT3CSR4L4BQZO/eBcbSAzFMegGafHvD2ek0QRVKObGPQq3BHWd8bG+ddoBFkC05 aMgsx6lNcAwVaHVtRjr1q6xpKB09DdboRr8i4WoABRdKa91mCujg7Rv5AkhpTKfo3SFq bnAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411110; x=1770015910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=4wyAR69Bcdaoiwt/QbVg4P4PwKbHvN8hOTaOTvBaaj0=; b=Iqm9pXI3owafuGyMrBhEFutgOioSfBzLs4JbJTAPv+YfH4YICPkz2VFL9tgQ2TVZWR 05AvBbvW93S8QZScnsx39C/JCXXJkNEzHvSn6lFkZNWbBoRE9dpkib/yFeQOFmGwZ88Q a/2vghExOyPqmG5gfWyK8IahZjhqdDlGY0elPiQS0CQQ6nSq/euMLGyqtyKkJcI2owA+ BawUoKpL+mA1QW706Ff0SdM2b1PvmW6i5vBmrudIk8I7d9enUncEupoGxGHyL+mRyrgw nTat4d9zf/IDwVLosix1PPJUKQaLhfNg5/FmLOth2tHy52d1QW14E569qev+g/pfxKXp wEtQ== X-Gm-Message-State: AOJu0YxDgm3J/wqt3NmQr0GEQF3xP5nD1aCt57tyg3ZUYTSnsvrGrBTC uibyMsP6JlVSXeYreOWonl7xzxrAajgmXyfirUYwWGwMBh+igP8f+k02ONItcwfS X-Gm-Gg: AZuq6aIfHs4oY5euOKLccqhYmHncwQAVXzfH7Fig7Ax/xXB/8wSvV3xbXaG88+Smu3T vlfwHFI4GAytB87IqrTVk+NimE7afV9EC3wf6oyxJ+SMYfPdeVAzoSjKJ0pf2fkquyCGkpyRv+W eqiv7k+00OH9+uWnG8bYfgABjzH+r9ylCQsr24OGTfj00CyndgHob2BWeJu1Ekso0hlaCE6YNcx B4jMaBdc2KjhTszVXnNY2Y0QAOBVgMYD3YZq0i1ecOzxQdtaXoguAGJC47B58Q2n823Ce72bi7x 9jfrmQQHDBil4AHylVoo0xK/1JT8qpLrrQrTK6ZWb4PhUHj1eYHT/0ly2Ta06DyAOJ5JiTQYqvz DRa/GZlLu4xDPP/imOH5p3bVW7RBcceL7rzy8UDqzS5zV7+rdz7JlLzqHm06tRC3G162Hv4NKLY yjtXSpU9Q1JL5tszusjjl3jl1/FhfnK0EXMDQuC6GquwBwQ2Mp6sDP X-Received: by 2002:a05:6a00:3cce:b0:823:1406:8797 with SMTP id d2e1a72fcca58-8234121c8cemr2920028b3a.31.1769411110265; Sun, 25 Jan 2026 23:05:10 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 14/33] tcg/wasm64: Add neg/ctpop instructions Date: Mon, 26 Jan 2026 07:03:27 +0000 Message-ID: <5011a6543e5e20630673e27b681e6de31e9d28eb.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412095499158500 Content-Type: text/plain; charset="utf-8" The neg/ctpop operations are implemented using the corresponding instructions in Wasm. TCI instructions are also generated in the same way as the original TCI backend. The Wasm backend implements only TCG_TARGET_REG_BITS=3D64 so the ctpop instruction is generated only for 64bit operations, as declared in cset_ctpop. Therefore, this commit adds only the 64bit version of ctpop implementation. Signed-off-by: Kohei Tokunaga --- tcg/wasm64.c | 4 ++++ tcg/wasm64/tcg-target.c.inc | 44 +++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/tcg/wasm64.c b/tcg/wasm64.c index 8c8dcb81c7..a5e72d8fe5 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -359,6 +359,10 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *en= v, const void *v_tb_ptr) tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; + case INDEX_op_ctpop: + tci_args_rr(insn, &r0, &r1); + regs[r0] =3D ctpop64(regs[r1]); + break; default: g_assert_not_reached(); } diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index d4db2528f8..8932330e3a 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -188,6 +188,7 @@ typedef enum { OPC_I32_SHR_S =3D 0x75, OPC_I32_SHR_U =3D 0x76, =20 + OPC_I64_POPCNT =3D 0x7b, OPC_I64_ADD =3D 0x7c, OPC_I64_SUB =3D 0x7d, OPC_I64_MUL =3D 0x7e, @@ -547,6 +548,21 @@ static void tcg_wasm_out_movi(TCGContext *s, TCGType t= ype, tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret)); } =20 +static void tcg_wasm_out_neg(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_wasm_out_op_const(s, OPC_I64_CONST, 0); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg)); + tcg_wasm_out_op(s, OPC_I64_SUB); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret)); +} + +static void tcg_wasm_out_ctpop64(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg)); + tcg_wasm_out_op(s, OPC_I64_POPCNT); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret)); +} + static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t = i1) { tcg_insn_unit_tci insn =3D 0; @@ -1138,6 +1154,34 @@ static const TCGOutOpBinary outop_remu =3D { .out_rrr =3D tgen_remu, }; =20 +static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) +{ + tcg_out_op_rr(s, INDEX_op_neg, a0, a1); + tcg_wasm_out_neg(s, a0, a1); +} + +static const TCGOutOpUnary outop_neg =3D { + .base.static_constraint =3D C_O1_I1(r, r), + .out_rr =3D tgen_neg, +}; + +static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) +{ + tcg_out_op_rr(s, INDEX_op_ctpop, a0, a1); + tcg_wasm_out_ctpop64(s, a0, a1); +} + +static TCGConstraintSetIndex cset_ctpop(TCGType type, unsigned flags) +{ + return type =3D=3D TCG_TYPE_REG ? C_O1_I1(r, r) : C_NotImplemented; +} + +static const TCGOutOpUnary outop_ctpop =3D { + .base.static_constraint =3D C_Dynamic, + .base.dynamic_constraint =3D cset_ctpop, + .out_rr =3D tgen_ctpop, +}; + static void tcg_out_tb_start(TCGContext *s) { init_sub_buf(); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412995; cv=none; d=zohomail.com; s=zohoarc; b=AAdLz35fd/WKbJCbDL3VWvM1EriWbS9gh1JskeAT1W3M4MMlBJVPL5T7U3DgigfcociPICAs4pfFMrELrozYW4XTWB9x1mwyGIv77SKc93M/a+EV0K0l4oHLcF2yVm3vIfTh5BUbYDU191GR17/ENyq1PohrW1dxlU5riOQmmXg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769412995; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=r6xRwxR8Gqwk8zRsC9Xk72G+qx04EZA2MfdW30gzxV0=; b=hSFy+iInE0APce3pu/wizcjIpyZbqG7d9fFN8MwdStdaibblxS+k0WoNVp3li7ZzTmSS6j7QNn80hySzz8drG+S+z/DjB+x3AaMEIn4WtwdfNTXmHMm+tzryBOAurSJLEhOLAPo3YSDQRsZJzpQxS20FMIv/jtzafH4xUvj5j4E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769412995534770.6747462936838; Sun, 25 Jan 2026 23:36:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGtA-00050X-9A; Mon, 26 Jan 2026 02:19:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGfW-0002yQ-9r for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:05:58 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGf3-0004LX-Fo for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:05:36 -0500 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-81f4ba336b4so4125007b3a.1 for ; Sun, 25 Jan 2026 23:05:15 -0800 (PST) Received: from brahms.. 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TCI instructions are also generated in the same way as the original TCI backend. Signed-off-by: Kohei Tokunaga --- tcg/wasm64.c | 34 ++++++++++ tcg/wasm64/tcg-target-opc.h.inc | 4 ++ tcg/wasm64/tcg-target.c.inc | 107 ++++++++++++++++++++++++++++++++ 3 files changed, 145 insertions(+) diff --git a/tcg/wasm64.c b/tcg/wasm64.c index a5e72d8fe5..2688ded58a 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -363,6 +363,40 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *en= v, const void *v_tb_ptr) tci_args_rr(insn, &r0, &r1); regs[r0] =3D ctpop64(regs[r1]); break; + case INDEX_op_clz: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] ? clz64(regs[r1]) : regs[r2]; + break; + case INDEX_op_ctz: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D regs[r1] ? ctz64(regs[r1]) : regs[r2]; + break; + case INDEX_op_tci_clz32: + tci_args_rrr(insn, &r0, &r1, &r2); + tmp32 =3D regs[r1]; + regs[r0] =3D tmp32 ? clz32(tmp32) : regs[r2]; + break; + case INDEX_op_tci_ctz32: + tci_args_rrr(insn, &r0, &r1, &r2); + tmp32 =3D regs[r1]; + regs[r0] =3D tmp32 ? ctz32(tmp32) : regs[r2]; + break; + case INDEX_op_rotl: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D rol64(regs[r1], regs[r2] & 63); + break; + case INDEX_op_rotr: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D ror64(regs[r1], regs[r2] & 63); + break; + case INDEX_op_tci_rotl32: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D rol32(regs[r1], regs[r2] & 31); + break; + case INDEX_op_tci_rotr32: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] =3D ror32(regs[r1], regs[r2] & 31); + break; default: g_assert_not_reached(); } diff --git a/tcg/wasm64/tcg-target-opc.h.inc b/tcg/wasm64/tcg-target-opc.h.= inc index 5ed8c67535..092a5086ec 100644 --- a/tcg/wasm64/tcg-target-opc.h.inc +++ b/tcg/wasm64/tcg-target-opc.h.inc @@ -12,3 +12,7 @@ DEF(tci_divs32, 1, 2, 0, TCG_OPF_NOT_PRESENT) DEF(tci_divu32, 1, 2, 0, TCG_OPF_NOT_PRESENT) DEF(tci_rems32, 1, 2, 0, TCG_OPF_NOT_PRESENT) DEF(tci_remu32, 1, 2, 0, TCG_OPF_NOT_PRESENT) +DEF(tci_clz32, 1, 2, 0, TCG_OPF_NOT_PRESENT) +DEF(tci_ctz32, 1, 2, 0, TCG_OPF_NOT_PRESENT) +DEF(tci_rotl32, 1, 2, 0, TCG_OPF_NOT_PRESENT) +DEF(tci_rotr32, 1, 2, 0, TCG_OPF_NOT_PRESENT) diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index 8932330e3a..1d980fb99f 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -158,6 +158,7 @@ typedef enum { OPC_I32_CONST =3D 0x41, OPC_I64_CONST =3D 0x42, =20 + OPC_I32_EQZ =3D 0x45, OPC_I32_EQ =3D 0x46, OPC_I32_NE =3D 0x47, OPC_I32_LT_S =3D 0x48, @@ -169,6 +170,7 @@ typedef enum { OPC_I32_GE_S =3D 0x4e, OPC_I32_GE_U =3D 0x4f, =20 + OPC_I64_EQZ =3D 0x50, OPC_I64_EQ =3D 0x51, OPC_I64_NE =3D 0x52, OPC_I64_LT_S =3D 0x53, @@ -180,6 +182,8 @@ typedef enum { OPC_I64_GE_S =3D 0x59, OPC_I64_GE_U =3D 0x5a, =20 + OPC_I32_CLZ =3D 0x67, + OPC_I32_CTZ =3D 0x68, OPC_I32_ADD =3D 0x6a, OPC_I32_DIV_S =3D 0x6d, OPC_I32_DIV_U =3D 0x6e, @@ -187,7 +191,11 @@ typedef enum { OPC_I32_REM_U =3D 0x70, OPC_I32_SHR_S =3D 0x75, OPC_I32_SHR_U =3D 0x76, + OPC_I32_ROTL =3D 0x77, + OPC_I32_ROTR =3D 0x78, =20 + OPC_I64_CLZ =3D 0x79, + OPC_I64_CTZ =3D 0x7a, OPC_I64_POPCNT =3D 0x7b, OPC_I64_ADD =3D 0x7c, OPC_I64_SUB =3D 0x7d, @@ -202,6 +210,8 @@ typedef enum { OPC_I64_SHL =3D 0x86, OPC_I64_SHR_S =3D 0x87, OPC_I64_SHR_U =3D 0x88, + OPC_I64_ROTL =3D 0x89, + OPC_I64_ROTR =3D 0x8a, =20 OPC_I32_WRAP_I64 =3D 0xa7, OPC_I64_EXTEND_I32_S =3D 0xac, @@ -212,6 +222,7 @@ typedef enum { =20 typedef enum { BLOCK_I64 =3D 0x7e, + BLOCK_I32 =3D 0x7f, } WasmBlockType; =20 #define BUF_SIZE 1024 @@ -563,6 +574,42 @@ static void tcg_wasm_out_ctpop64(TCGContext *s, TCGReg= ret, TCGReg arg) tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret)); } =20 +static void tcg_wasm_out_cz( + TCGContext *s, TCGType type, WasmInsn opc32, WasmInsn opc64, + TCGReg ret, TCGReg arg1, TCGReg arg2) +{ + switch (type) { + case TCG_TYPE_I32: + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg1)); + tcg_wasm_out_op(s, OPC_I32_WRAP_I64); + tcg_wasm_out_op(s, OPC_I32_EQZ); + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_I32); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg2)); + tcg_wasm_out_op(s, OPC_I32_WRAP_I64); + tcg_wasm_out_op(s, OPC_ELSE); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg1)); + tcg_wasm_out_op(s, OPC_I32_WRAP_I64); + tcg_wasm_out_op(s, opc32); + tcg_wasm_out_op(s, OPC_END); + tcg_wasm_out_op(s, OPC_I64_EXTEND_I32_U); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret)); + break; + case TCG_TYPE_I64: + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg1)); + tcg_wasm_out_op(s, OPC_I64_EQZ); + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_I64); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg2)); + tcg_wasm_out_op(s, OPC_ELSE); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg1)); + tcg_wasm_out_op(s, opc64); + tcg_wasm_out_op(s, OPC_END); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret)); + break; + default: + g_assert_not_reached(); + } +} + static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t = i1) { tcg_insn_unit_tci insn =3D 0; @@ -1182,6 +1229,66 @@ static const TCGOutOpUnary outop_ctpop =3D { .out_rr =3D tgen_ctpop, }; =20 +static void tgen_rotl(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + TCGOpcode opc =3D (type =3D=3D TCG_TYPE_I32 + ? INDEX_op_tci_rotl32 + : INDEX_op_rotl); + tcg_out_op_rrr(s, opc, a0, a1, a2); + tcg_wasm_out_o1_i2_type(s, type, OPC_I32_ROTL, OPC_I64_ROTL, a0, a1, a= 2); +} + +static const TCGOutOpBinary outop_rotl =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_rotl, +}; + +static void tgen_rotr(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + TCGOpcode opc =3D (type =3D=3D TCG_TYPE_I32 + ? INDEX_op_tci_rotr32 + : INDEX_op_rotr); + tcg_out_op_rrr(s, opc, a0, a1, a2); + tcg_wasm_out_o1_i2_type(s, type, OPC_I32_ROTR, OPC_I64_ROTR, a0, a1, a= 2); +} + +static const TCGOutOpBinary outop_rotr =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_rotr, +}; + +static void tgen_clz(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + TCGOpcode opc =3D (type =3D=3D TCG_TYPE_I32 + ? INDEX_op_tci_clz32 + : INDEX_op_clz); + tcg_out_op_rrr(s, opc, a0, a1, a2); + tcg_wasm_out_cz(s, type, OPC_I32_CLZ, OPC_I64_CLZ, a0, a1, a2); +} + +static const TCGOutOpBinary outop_clz =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_clz, +}; + +static void tgen_ctz(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + TCGOpcode opc =3D (type =3D=3D TCG_TYPE_I32 + ? INDEX_op_tci_ctz32 + : INDEX_op_ctz); + tcg_out_op_rrr(s, opc, a0, a1, a2); + tcg_wasm_out_cz(s, type, OPC_I32_CTZ, OPC_I64_CTZ, a0, a1, a2); +} + +static const TCGOutOpBinary outop_ctz =3D { + .base.static_constraint =3D C_O1_I2(r, r, r), + .out_rrr =3D tgen_ctz, +}; + static void tcg_out_tb_start(TCGContext *s) { init_sub_buf(); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412037; cv=none; d=zohomail.com; s=zohoarc; b=LwEzSi2dbJawmFOV1b9I0T/s7xR9vxQ756MbwZESWb51+gOPIhQj8Mj6hxowKr9auWWhXqYzaclVlW/KNORHivvkC7DntyAHvT2NAs2Q1nceUKY9E+b/GUbQ2S1GJqwkdJji8ACpBeFhLTNu5rEWtwxVQk1xl21/14A53tRyExA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769412037; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LPrO3MqYxjuyosp2uxkP4V042VRYRHbBi3On28UyzFo=; b=R/f4EHHJCgg6NrV5SglOJiAng4XNXz35UL7up4n1lJpZpgCjwbEdrz0LFB0qmmpotBap/pSyFTdjpanadM37hum5KFLvJITHZy3Ysynrn7n3B9fMXtik4enI4ZAITvTb3YJxbb4YmBbwXO+Vpwq8QBFL/B6g/HCJncMDfNyu9Oc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769412037638965.2790787208025; Sun, 25 Jan 2026 23:20:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGt9-0004zb-OJ; Mon, 26 Jan 2026 02:19:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGfZ-0002zM-6M for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:05:58 -0500 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGf3-0004MK-HF for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:05:37 -0500 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-8220bd582ddso2075785b3a.2 for ; Sun, 25 Jan 2026 23:05:20 -0800 (PST) Received: from brahms.. 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.05.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:05:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411119; x=1770015919; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LPrO3MqYxjuyosp2uxkP4V042VRYRHbBi3On28UyzFo=; b=JWdOKDjA/FgCy/DW/Z/eqDhouTUD7YldzCD9YPodRMh3S9ArYRnsV7hkhtn+bT4o1i BxvNpHyAIjDcU6HLYyfjLweg+Fp3P0rsTZ7REN572usq+cEar4zfqOK5KRoc/Etf0IVI B9ALwQDsTk/zuyv5dxS37ZRkHAmcMxV+5B5mjfQXpgt1N6vV6yzDhqh1exMqUg+cc581 MNkCLVxEum0RR80Kz3kqEdPiDb6b9goHO8ubUeUQvfwsCLzN+uH0TQMHEsyc9ewib/vU S3mCbzUnhjM10U2S8Nl5I/3KnpZEeqief45wUduU2U31bXijyVv+68Ucf1kJuc5kI7DJ 3tPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411119; x=1770015919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=LPrO3MqYxjuyosp2uxkP4V042VRYRHbBi3On28UyzFo=; b=PDkv980QcSPUNVrmVE6VbWcWk9GZCzeAGI9/44zKsddwBBkKmPnpYSHd2mbhnJpaQF /JbEGYeVjEvJ68t2qY7HpwzC78VFtCN+Ad7BjAT1cTueIhUPatDVM+n9T9g4yUebABqQ 94ujx/Oc/xTHEWLfsidiSEmdymBYLk3gPCCQU/jOHp4Q4pAtkIO5UykkyPyQHT31FeXP zBZTkb4CSVDuTeLM7/KvZFZ984I7nnc1QVmlOVxib3GDCmxamwPBRvfgVfhdCy7dQPrQ BGScPdV7gesBzk9MFkto8HgUWPJCoSR7NLdjJjQ54KfqU02lKNzaDrRL3DYlwVz2SFM2 VMsg== X-Gm-Message-State: AOJu0YwGt3s/RifmwEeD9Srpai9WNr/oErDMZCmrpyTpaXUPxaT485el Qp8TotPBKTYmcdv3hxJrtqxHf047yrsZCfJWlcKo3Kv1Z3SoRk5u1amQ08twZ0bG X-Gm-Gg: AZuq6aKlvi/NGySARRuq+PPZ8MUHlI+iWz6K4hmphxAeb/qJZwAIcIfOxEkTJ14B95G gzFML1iBCce6hkSMzjSnSs825bHyrLiXZJ+ueVMCM7voB+/yXm8E09BVpvh1ZjWx+sSwv5v9/Q6 N9fM4zG4xqIAGOcnMRw5WfYXqqsw2H2h3tlJ7fyfRtqcRrNqSXj9A5dCWsb8te2isnzr8J6/WWq zTQWG/hqIeeoe6xkLy7CZ4s7YsUccv5ehwb5rRydEFzCzyooSBfQDxBV5zDKaORJxKD3xMtEkgp B4BW/9LphAzDUaCYqHVgvSXtr2YJ5La2PGZWZyvRyxC+ikTdnns3C/9iR3JkDkCfGwJRki76HoW GQmG9uMx9x8bxItK6l7uj+ZoLq9KKXa5vyFL3O5433CjE9+h4TqylasiTaQ48XE016WNpp+0GOd isspcoeBKDxCKk27LDI0k7k/d3C1Hz5ZhjyqTnYDbJxg== X-Received: by 2002:a05:6a00:1ca2:b0:823:f96:63bb with SMTP id d2e1a72fcca58-823412a30c2mr3250724b3a.52.1769411119374; Sun, 25 Jan 2026 23:05:19 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 16/33] tcg/wasm64: Add br/brcond instructions Date: Mon, 26 Jan 2026 07:03:29 +0000 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412039046154101 Content-Type: text/plain; charset="utf-8" Wasm does not support direct jumps to arbitrary code addresses, so br and brcond are implemented using Wasm's control flow instructions. As illustrated in the pseudo-code below, each TB wraps Wasm instructions inside a large loop. Each set of codes separated by TCG labels is placed inside an "if" block. Br is implemented by breaking out of the current block and entering the target block: loop if ... code after the first label end if ... code after the second label end ... end Each block is assigned an unique integer ID. The br implementation sets the destination block's ID in BLOCK_IDX Wasm variable and breaks from the current if block. As control flow continues, each if block checks whether the BLOCK_IDX matches its own ID. If so, execution resumes within that block. The tcg_out_tb_start function generates the start of the global loop and the first if block. To properly close these blocks, this commit also introduces a new callback tcg_out_tb_end which emits the "end" instructions for the final if block and the loop. Another new callback tcg_out_label_cb is used to emit block boundaries, specifically the end of the previous block and the if of the next block, at label positions. It also records the mapping between label IDs and block IDs in a LabelInfo list. Since the block ID for a label might not be known when a br instruction is generated, a placeholder is emitted instead. These placeholders are tracked in a BlockPlaceholder list and resolved later using LabelInfo. TCI instructions are also generated in the same way as the original TCI backend. Signed-off-by: Kohei Tokunaga --- tcg/aarch64/tcg-target.c.inc | 11 ++ tcg/loongarch64/tcg-target.c.inc | 11 ++ tcg/mips64/tcg-target.c.inc | 11 ++ tcg/ppc64/tcg-target.c.inc | 11 ++ tcg/riscv64/tcg-target.c.inc | 11 ++ tcg/s390x/tcg-target.c.inc | 11 ++ tcg/sparc64/tcg-target.c.inc | 11 ++ tcg/tcg.c | 7 ++ tcg/tci/tcg-target.c.inc | 11 ++ tcg/wasm64.c | 16 +++ tcg/wasm64/tcg-target.c.inc | 196 +++++++++++++++++++++++++++++++ tcg/x86_64/tcg-target.c.inc | 11 ++ 12 files changed, 318 insertions(+) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index caf79c742d..112659e7b6 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -3514,6 +3514,17 @@ static void tcg_out_tb_start(TCGContext *s) tcg_out_bti(s, BTI_J); } =20 +static int tcg_out_tb_end(TCGContext *s) +{ + /* nothing to do */ + return 0; +} + +static void tcg_out_label_cb(TCGContext *s, TCGLabel *l) +{ + /* nothing to do */ +} + static void tcg_out_nop_fill(tcg_insn_unit *p, int count) { int i; diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index c3350c90fc..2532395f44 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -2658,6 +2658,17 @@ static void tcg_out_tb_start(TCGContext *s) /* nothing to do */ } =20 +static int tcg_out_tb_end(TCGContext *s) +{ + /* nothing to do */ + return 0; +} + +static void tcg_out_label_cb(TCGContext *s, TCGLabel *l) +{ + /* nothing to do */ +} + static void tcg_out_nop_fill(tcg_insn_unit *p, int count) { for (int i =3D 0; i < count; ++i) { diff --git a/tcg/mips64/tcg-target.c.inc b/tcg/mips64/tcg-target.c.inc index 60c703a093..4b8dd9393f 100644 --- a/tcg/mips64/tcg-target.c.inc +++ b/tcg/mips64/tcg-target.c.inc @@ -2522,6 +2522,17 @@ static void tcg_out_tb_start(TCGContext *s) /* nothing to do */ } =20 +static int tcg_out_tb_end(TCGContext *s) +{ + /* nothing to do */ + return 0; +} + +static void tcg_out_label_cb(TCGContext *s, TCGLabel *l) +{ + /* nothing to do */ +} + static void tcg_target_init(TCGContext *s) { tcg_target_detect_isa(); diff --git a/tcg/ppc64/tcg-target.c.inc b/tcg/ppc64/tcg-target.c.inc index b54afa0b6d..340a2829f6 100644 --- a/tcg/ppc64/tcg-target.c.inc +++ b/tcg/ppc64/tcg-target.c.inc @@ -2643,6 +2643,17 @@ static void tcg_out_tb_start(TCGContext *s) } } =20 +static int tcg_out_tb_end(TCGContext *s) +{ + /* nothing to do */ + return 0; +} + +static void tcg_out_label_cb(TCGContext *s, TCGLabel *l) +{ + /* nothing to do */ +} + static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, arg); diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc index 76dd4fca97..a6f7fbeee2 100644 --- a/tcg/riscv64/tcg-target.c.inc +++ b/tcg/riscv64/tcg-target.c.inc @@ -2988,6 +2988,17 @@ static void tcg_out_tb_start(TCGContext *s) init_setting_vtype(s); } =20 +static int tcg_out_tb_end(TCGContext *s) +{ + /* nothing to do */ + return 0; +} + +static void tcg_out_label_cb(TCGContext *s, TCGLabel *l) +{ + /* nothing to do */ +} + static bool vtype_check(unsigned vtype) { unsigned long tmp; diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 84a9e73a46..457e568d30 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -3830,6 +3830,17 @@ static void tcg_out_tb_start(TCGContext *s) /* nothing to do */ } =20 +static int tcg_out_tb_end(TCGContext *s) +{ + /* nothing to do */ + return 0; +} + +static void tcg_out_label_cb(TCGContext *s, TCGLabel *l) +{ + /* nothing to do */ +} + static void tcg_out_nop_fill(tcg_insn_unit *p, int count) { memset(p, 0x07, count * sizeof(tcg_insn_unit)); diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 5e5c3f1cda..ae695b115b 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1017,6 +1017,17 @@ static void tcg_out_tb_start(TCGContext *s) /* nothing to do */ } =20 +static int tcg_out_tb_end(TCGContext *s) +{ + /* nothing to do */ + return 0; +} + +static void tcg_out_label_cb(TCGContext *s, TCGLabel *l) +{ + /* nothing to do */ +} + static void tcg_out_nop_fill(tcg_insn_unit *p, int count) { int i; diff --git a/tcg/tcg.c b/tcg/tcg.c index e7bf4dad4e..3c68699138 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -116,6 +116,7 @@ static void tcg_register_jit_int(const void *buf, size_= t size, =20 /* Forward declarations for functions declared and used in tcg-target.c.in= c. */ static void tcg_out_tb_start(TCGContext *s); +static int tcg_out_tb_end(TCGContext *s); static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg= 1, intptr_t arg2); static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); @@ -187,6 +188,7 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_= unit *target, static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot); static bool tcg_target_const_match(int64_t val, int ct, TCGType type, TCGCond cond, int vece); +static void tcg_out_label_cb(TCGContext *s, TCGLabel *l); =20 #ifndef CONFIG_USER_ONLY #define guest_base ({ qemu_build_not_reached(); (uintptr_t)0; }) @@ -357,6 +359,7 @@ static void tcg_out_label(TCGContext *s, TCGLabel *l) tcg_debug_assert(!l->has_value); l->has_value =3D 1; l->u.value_ptr =3D tcg_splitwx_to_rx(s->code_ptr); + tcg_out_label_cb(s, l); } =20 TCGLabel *gen_new_label(void) @@ -6746,6 +6749,10 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb= , uint64_t pc_start) if (!tcg_resolve_relocs(s)) { return -2; } + i =3D tcg_out_tb_end(s); + if (i < 0) { + return i; + } =20 #ifndef CONFIG_TCG_INTERPRETER /* flush instruction cache */ diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 1b22c70616..940f9f93bb 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -1241,6 +1241,17 @@ static void tcg_out_tb_start(TCGContext *s) /* nothing to do */ } =20 +static int tcg_out_tb_end(TCGContext *s) +{ + /* nothing to do */ + return 0; +} + +static void tcg_out_label_cb(TCGContext *s, TCGLabel *l) +{ + /* nothing to do */ +} + bool tcg_target_has_memory_bswap(MemOp memop) { return true; diff --git a/tcg/wasm64.c b/tcg/wasm64.c index 2688ded58a..ca67436192 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -22,6 +22,12 @@ #include "tcg/tcg.h" #include "tcg/tcg-ldst.h" =20 +static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0) +{ + int diff =3D sextract32(insn, 12, 20); + *l0 =3D diff ? (void *)tb_ptr + diff : NULL; +} + static void tci_args_rl(uint32_t insn, const void *tb_ptr, TCGReg *r0, void **l1) { @@ -397,6 +403,16 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *en= v, const void *v_tb_ptr) tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D ror32(regs[r1], regs[r2] & 31); break; + case INDEX_op_br: + tci_args_l(insn, tb_ptr, &ptr); + tb_ptr =3D ptr; + continue; + case INDEX_op_brcond: + tci_args_rl(insn, tb_ptr, &r0, &ptr); + if (regs[r0]) { + tb_ptr =3D ptr; + } + break; default: g_assert_not_reached(); } diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index 1d980fb99f..3fe0ae2381 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -136,10 +136,16 @@ static const uint8_t tcg_target_reg_index[TCG_TARGET_= NB_REGS] =3D { =20 #define REG_IDX(r) tcg_target_reg_index[r] =20 +/* Global variable used for storing the current block index */ +#define BLOCK_IDX 16 + typedef enum { + OPC_UNREACHABLE =3D 0x00, + OPC_LOOP =3D 0x03, OPC_IF =3D 0x04, OPC_ELSE =3D 0x05, OPC_END =3D 0x0b, + OPC_BR =3D 0x0c, OPC_GLOBAL_GET =3D 0x23, OPC_GLOBAL_SET =3D 0x24, =20 @@ -221,6 +227,7 @@ typedef enum { } WasmInsn; =20 typedef enum { + BLOCK_NORET =3D 0x40, BLOCK_I64 =3D 0x7e, BLOCK_I32 =3D 0x7f, } WasmBlockType; @@ -276,6 +283,17 @@ static void linked_buf_out_sleb128(LinkedBuf *p, int64= _t v) } } =20 +static int linked_buf_len(LinkedBuf *p) +{ + int total =3D 0; + LinkedBufEntry *e; + + QSIMPLEQ_FOREACH(e, p, entry) { + total +=3D e->size; + } + return total; +} + /* * wasm code is generataed in the dynamically allocated buffer which * are managed as a linked list. @@ -286,6 +304,10 @@ static void init_sub_buf(void) { QSIMPLEQ_INIT(&sub_buf); } +static int sub_buf_len(void) +{ + return linked_buf_len(&sub_buf); +} static void tcg_wasm_out8(TCGContext *s, uint8_t v) { linked_buf_out8(&sub_buf, v); @@ -610,6 +632,134 @@ static void tcg_wasm_out_cz( } } =20 +typedef struct LabelInfo { + int label; + int block; + QSIMPLEQ_ENTRY(LabelInfo) entry; +} LabelInfo; + +static __thread QSIMPLEQ_HEAD(, LabelInfo) label_info; + +static void init_label_info(void) +{ + QSIMPLEQ_INIT(&label_info); +} + +static void add_label(int label, int block) +{ + LabelInfo *e =3D tcg_malloc(sizeof(LabelInfo)); + e->label =3D label; + e->block =3D block; + QSIMPLEQ_INSERT_TAIL(&label_info, e, entry); +} + +typedef struct BlockPlaceholder { + int label; + int pos; + QSIMPLEQ_ENTRY(BlockPlaceholder) entry; +} BlockPlaceholder; + +static __thread QSIMPLEQ_HEAD(, BlockPlaceholder) block_placeholder; +static __thread int64_t cur_block_idx; + +static void init_blocks(void) +{ + QSIMPLEQ_INIT(&block_placeholder); + cur_block_idx =3D 0; +} + +static void add_block_placeholder(int label, int pos) +{ + BlockPlaceholder *e =3D tcg_malloc(sizeof(BlockPlaceholder)); + e->label =3D label; + e->pos =3D pos; + QSIMPLEQ_INSERT_TAIL(&block_placeholder, e, entry); +} + +static int get_block_of_label(int label) +{ + LabelInfo *e; + QSIMPLEQ_FOREACH(e, &label_info, entry) { + if (e->label =3D=3D label) { + return e->block; + } + } + return -1; +} + +static void tcg_wasm_out_new_block(TCGContext *s) +{ + tcg_wasm_out_op(s, OPC_END); /* close this block */ + + /* next block */ + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, BLOCK_IDX); + tcg_wasm_out_op_const(s, OPC_I64_CONST, ++cur_block_idx); + tcg_wasm_out_op(s, OPC_I64_LE_U); + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_NORET); +} + +static void tcg_out_label_cb(TCGContext *s, TCGLabel *l) +{ + add_label(l->id, cur_block_idx + 1); + tcg_wasm_out_new_block(s); +} + +static void tcg_wasm_out_br_to_label(TCGContext *s, TCGLabel *l, bool br_i= f) +{ + int toploop_depth =3D 1; + if (br_if) { + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_NORET); + toploop_depth++; + } + tcg_wasm_out8(s, OPC_I64_CONST); + + add_block_placeholder(l->id, sub_buf_len()); + + tcg_wasm_out8(s, 0x80); /* placeholder for the target block idx */ + tcg_wasm_out8(s, 0x80); + tcg_wasm_out8(s, 0x80); + tcg_wasm_out8(s, 0x80); + tcg_wasm_out8(s, 0x00); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, BLOCK_IDX); + if (get_block_of_label(l->id) !=3D -1) { + /* + * The label is placed before this br, branch to the top of loop + */ + tcg_wasm_out_op_idx(s, OPC_BR, toploop_depth); + } else { + /* + * The label will be generated after this br, + * branch to the end of the current block + */ + tcg_wasm_out_op_idx(s, OPC_BR, toploop_depth - 1); + } + if (br_if) { + tcg_wasm_out_op(s, OPC_END); + } +} + +static void tcg_wasm_out_br(TCGContext *s, TCGLabel *l) +{ + tcg_wasm_out_br_to_label(s, l, false); +} + +static void tcg_wasm_out_brcond(TCGContext *s, TCGType type, + TCGReg arg1, TCGReg arg2, + TCGCond cond, TCGLabel *l) +{ + tcg_wasm_out_cond(s, type, cond, arg1, arg2); + tcg_wasm_out_br_to_label(s, l, true); +} + +static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) +{ + tcg_insn_unit_tci insn =3D 0; + + tcg_out_reloc(s, s->code_ptr, 20, l0, 0); + insn =3D deposit32(insn, 0, 8, op); + tcg_out32(s, insn); +} + static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t = i1) { tcg_insn_unit_tci insn =3D 0; @@ -621,6 +771,16 @@ static void tcg_out_op_ri(TCGContext *s, TCGOpcode op,= TCGReg r0, int32_t i1) tcg_out32(s, insn); } =20 +static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel= *l1) +{ + tcg_insn_unit_tci insn =3D 0; + + tcg_out_reloc(s, s->code_ptr, 20, l1, 0); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + tcg_out32(s, insn); +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r= 1) { tcg_insn_unit_tci insn =3D 0; @@ -1289,7 +1449,43 @@ static const TCGOutOpBinary outop_ctz =3D { .out_rrr =3D tgen_ctz, }; =20 +static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, + TCGReg arg0, TCGReg arg1, TCGLabel *l) +{ + tgen_setcond_tci(s, type, cond, TCG_REG_TMP, arg0, arg1); + tcg_out_op_rl(s, INDEX_op_brcond, TCG_REG_TMP, l); + tcg_wasm_out_brcond(s, type, arg0, arg1, cond, l); +} + +static const TCGOutOpBrcond outop_brcond =3D { + .base.static_constraint =3D C_O0_I2(r, r), + .out_rr =3D tgen_brcond, +}; + +static void tcg_out_br(TCGContext *s, TCGLabel *l) +{ + tcg_out_op_l(s, INDEX_op_br, l); + tcg_wasm_out_br(s, l); +} + static void tcg_out_tb_start(TCGContext *s) { init_sub_buf(); + init_blocks(); + init_label_info(); + + tcg_wasm_out_op_block(s, OPC_LOOP, BLOCK_NORET); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, BLOCK_IDX); + tcg_wasm_out_op(s, OPC_I64_EQZ); + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_NORET); +} + +static int tcg_out_tb_end(TCGContext *s) +{ + tcg_wasm_out_op(s, OPC_END); /* end if */ + tcg_wasm_out_op(s, OPC_END); /* end loop */ + tcg_wasm_out_op(s, OPC_UNREACHABLE); + tcg_wasm_out_op(s, OPC_END); /* end func */ + + return 0; } diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc index 92251f8327..61e70b337b 100644 --- a/tcg/x86_64/tcg-target.c.inc +++ b/tcg/x86_64/tcg-target.c.inc @@ -4504,6 +4504,17 @@ static void tcg_out_tb_start(TCGContext *s) /* nothing to do */ } =20 +static int tcg_out_tb_end(TCGContext *s) +{ + /* nothing to do */ + return 0; +} + +static void tcg_out_label_cb(TCGContext *s, TCGLabel *l) +{ + /* nothing to do */ +} + static void tcg_out_nop_fill(tcg_insn_unit *p, int count) { memset(p, 0x90, count); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Control transfer between TBs (i.e. from one Wasm module to another) is handled by the caller of the module. The goto_tb and goto_ptr operations are implemented by returning control to the caller using the return instruction. The destination TB's pointer is passed to the caller via a shared WasmContext structure which is accessible from both the Wasm module and the caller. This WasmContext must be provided to the module as an argument. If the destination TB is the current TB itself, there is no need to return control to the caller. Instead, execution can jump directly to the top of the loop within the TB. The exit_tb operation sets the pointer in WasmContext to 0, indicating that there is no destination TB. TCI instructions are also generated in the same way as the original TCI backend. Signed-off-by: Kohei Tokunaga --- MAINTAINERS | 1 + tcg/wasm64.c | 20 ++++++ tcg/wasm64.h | 15 ++++ tcg/wasm64/tcg-target.c.inc | 136 ++++++++++++++++++++++++++++++++++++ 4 files changed, 172 insertions(+) create mode 100644 tcg/wasm64.h diff --git a/MAINTAINERS b/MAINTAINERS index 30e468f290..40aae1fc8e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4112,6 +4112,7 @@ M: Kohei Tokunaga S: Maintained F: tcg/wasm64/ F: tcg/wasm64.c +F: tcg/wasm64.h =20 Block drivers ------------- diff --git a/tcg/wasm64.c b/tcg/wasm64.c index ca67436192..c54c5c5b2c 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -28,6 +28,11 @@ static void tci_args_l(uint32_t insn, const void *tb_ptr= , void **l0) *l0 =3D diff ? (void *)tb_ptr + diff : NULL; } =20 +static void tci_args_r(uint32_t insn, TCGReg *r0) +{ + *r0 =3D extract32(insn, 8, 4); +} + static void tci_args_rl(uint32_t insn, const void *tb_ptr, TCGReg *r0, void **l1) { @@ -413,6 +418,21 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *en= v, const void *v_tb_ptr) tb_ptr =3D ptr; } break; + case INDEX_op_exit_tb: + tci_args_l(insn, tb_ptr, &ptr); + return (uintptr_t)ptr; + case INDEX_op_goto_tb: + tci_args_l(insn, tb_ptr, &ptr); + tb_ptr =3D *(void **)ptr; + break; + case INDEX_op_goto_ptr: + tci_args_r(insn, &r0); + ptr =3D (void *)regs[r0]; + if (!ptr) { + return 0; + } + tb_ptr =3D ptr; + break; default: g_assert_not_reached(); } diff --git a/tcg/wasm64.h b/tcg/wasm64.h new file mode 100644 index 0000000000..9da38e4d0e --- /dev/null +++ b/tcg/wasm64.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef TCG_WASM_H +#define TCG_WASM_H + +/* + * WasmContext is a data shared among QEMU and wasm modules. + */ +struct WasmContext { + /* + * Pointer to the TB to be executed. + */ + void *tb_ptr; +}; + +#endif diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index 3fe0ae2381..ff1151390b 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -26,6 +26,7 @@ */ =20 #include "qemu/queue.h" +#include "../wasm64.h" =20 typedef uint32_t tcg_insn_unit_tci; =20 @@ -139,6 +140,9 @@ static const uint8_t tcg_target_reg_index[TCG_TARGET_NB= _REGS] =3D { /* Global variable used for storing the current block index */ #define BLOCK_IDX 16 =20 +/* Local variable pointing to WasmContext */ +#define CTX_IDX 0 + typedef enum { OPC_UNREACHABLE =3D 0x00, OPC_LOOP =3D 0x03, @@ -146,6 +150,8 @@ typedef enum { OPC_ELSE =3D 0x05, OPC_END =3D 0x0b, OPC_BR =3D 0x0c, + OPC_RETURN =3D 0x0f, + OPC_LOCAL_GET =3D 0x20, OPC_GLOBAL_GET =3D 0x23, OPC_GLOBAL_SET =3D 0x24, =20 @@ -751,6 +757,81 @@ static void tcg_wasm_out_brcond(TCGContext *s, TCGType= type, tcg_wasm_out_br_to_label(s, l, true); } =20 +#define CTX_OFFSET(f) offsetof(struct WasmContext, f) + +static intptr_t tcg_wasm_out_get_ctx(TCGContext *s, intptr_t off) +{ + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, CTX_IDX); + return tcg_wasm_out_norm_ptr(s, off); +} + +static void tcg_wasm_out_exit_tb(TCGContext *s, uintptr_t arg) +{ + intptr_t ofs; + + /* Store ctx.tb_ptr =3D 0 which indicates there is no next TB */ + ofs =3D tcg_wasm_out_get_ctx(s, CTX_OFFSET(tb_ptr)); + tcg_wasm_out_op_const(s, OPC_I64_CONST, 0); + tcg_wasm_out_op_ldst(s, OPC_I64_STORE, 0, ofs); + + /* Return the control to the caller */ + tcg_wasm_out_op_const(s, OPC_I64_CONST, arg); + tcg_wasm_out_op(s, OPC_RETURN); +} + +static void tcg_wasm_out_goto(TCGContext *s, TCGReg target, int block_dept= h) +{ + intptr_t ofs; + + /* Check if the target TB is the same as the current TB */ + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(target)); + ofs =3D tcg_wasm_out_get_ctx(s, CTX_OFFSET(tb_ptr)); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, ofs); + tcg_wasm_out_op(s, OPC_I64_EQ); + + /* + * If the target TB is the same as the current TB, no need to return t= o the + * caller. Just branch to the top of the current TB. + */ + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_NORET); + tcg_wasm_out_op_const(s, OPC_I64_CONST, 0); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, BLOCK_IDX); + tcg_wasm_out_op_idx(s, OPC_BR, block_depth); /* br to the top of loop = */ + tcg_wasm_out_op(s, OPC_END); + + /* Store the target TB to ctx.tb_ptr and return */ + ofs =3D tcg_wasm_out_get_ctx(s, CTX_OFFSET(tb_ptr)); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(target)); + tcg_wasm_out_op_ldst(s, OPC_I64_STORE, 0, ofs); + tcg_wasm_out_op_const(s, OPC_I64_CONST, 0); + tcg_wasm_out_op(s, OPC_RETURN); +} + +static void tcg_wasm_out_goto_ptr(TCGContext *s, TCGReg arg) +{ + tcg_wasm_out_goto(s, arg, 2); +} + +static void tcg_wasm_out_goto_tb( + TCGContext *s, int which, uintptr_t cur_reset_ptr) +{ + intptr_t ofs; + + /* Set the target TB in the tmp variable. */ + tcg_wasm_out_op_const(s, OPC_I64_CONST, get_jmp_target_addr(s, which)); + ofs =3D tcg_wasm_out_norm_ptr(s, 0); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, ofs); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(TCG_REG_TMP)); + + /* Goto the target TB if it's registered. */ + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(TCG_REG_TMP)); + tcg_wasm_out_op_const(s, OPC_I64_CONST, cur_reset_ptr); + tcg_wasm_out_op(s, OPC_I64_NE); + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_NORET); + tcg_wasm_out_goto(s, TCG_REG_TMP, 3); + tcg_wasm_out_op(s, OPC_END); +} + static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) { tcg_insn_unit_tci insn =3D 0; @@ -760,6 +841,35 @@ static void tcg_out_op_l(TCGContext *s, TCGOpcode op, = TCGLabel *l0) tcg_out32(s, insn); } =20 +static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) +{ + tcg_insn_unit_tci insn =3D 0; + intptr_t diff; + + /* Special case for exit_tb: map null -> 0. */ + if (p0 =3D=3D NULL) { + diff =3D 0; + } else { + diff =3D p0 - (void *)(s->code_ptr + 4); + tcg_debug_assert(diff !=3D 0); + if (diff !=3D sextract32(diff, 0, 20)) { + tcg_raise_tb_overflow(s); + } + } + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 12, 20, diff); + tcg_out32(s, insn); +} + +static void tcg_out_op_r(TCGContext *s, TCGOpcode op, TCGReg r0) +{ + tcg_insn_unit_tci insn =3D 0; + + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + tcg_out32(s, insn); +} + static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t = i1) { tcg_insn_unit_tci insn =3D 0; @@ -1468,6 +1578,32 @@ static void tcg_out_br(TCGContext *s, TCGLabel *l) tcg_wasm_out_br(s, l); } =20 +static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) +{ + tcg_out_op_p(s, INDEX_op_exit_tb, (void *)arg); + tcg_wasm_out_exit_tb(s, arg); +} + +static void tcg_out_goto_tb(TCGContext *s, int which) +{ + /* indirect jump method. */ + tcg_out_op_p(s, INDEX_op_goto_tb, (void *)get_jmp_target_addr(s, which= )); + set_jmp_reset_offset(s, which); + tcg_wasm_out_goto_tb(s, which, (intptr_t)s->code_ptr); +} + +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) +{ + tcg_out_op_r(s, INDEX_op_goto_ptr, a0); + tcg_wasm_out_goto_ptr(s, a0); +} + +void tb_target_set_jmp_target(const TranslationBlock *tb, int n, + uintptr_t jmp_rx, uintptr_t jmp_rw) +{ + /* Always indirect, nothing to do */ +} + static void tcg_out_tb_start(TCGContext *s) { init_sub_buf(); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412213; cv=none; d=zohomail.com; s=zohoarc; b=QR+8yR4KpyeuB8/va4zy0uTpvEjsI3oJTXcZrhxAaT3pSAGfXXoMStLkpY6rFbweXHxMH50RyW5Pi5TluwwSyolCw+Er5JNf2tVT8kql2N1Q4Dh+EXE6dr/nNJ5orkauBlAmsB0D0pXJv0YJRVThqrjTvazanZ4rUSX9bOZhmSg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769412213; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wasm's call instruction can invoke an imported function using a locally assigned function index. When a call TCG operation is generated, the Wasm backend assigns the ID (starting from 0) to the target function. The mapping between the function pointer and its assigned ID is recorded in a list of HelperInfo. Since Wasm's call instruction requires arguments to be pushed onto the Wasm stack, the backend retrieves the function arguments from TCG's stack array and pushes them to the Wasm stack before the call. After the function returns, the result is retrieved from the Wasm stack and set in the corresponding TCG variable. In the Emscripten build configured with !has_int128_type, a 128bit value is represented by the Int128 struct. Such values are passed to the function via pointer parameters and returned via a prepended pointer argument, as described in [1]. For this prepended buffer area, the module expects a pre-allocated Int128 buffer from the caller via ctx.buf128. Helper functions expect the target of the return instruction via the GETPC macro (the tci_tb_ptr variable in TCI). However, unlike other architectures, Wasm doesn't have a register pointing to the return target. To emulate this behaviour, the Wasm module sets the instruction pointer to the corresponding TCI instruction (s->code_ptr) in tci_tb_ptr passed via the WasmContext. TCI instructions are also generated in the same way as the original TCI backend. [1] https://github.com/WebAssembly/tool-conventions/blob/060cf4073e46931160= c2e9ecd43177ee1fe93866/BasicCABI.md#function-arguments-and-return-values Signed-off-by: Kohei Tokunaga --- tcg/wasm64.c | 59 ++++++++++++ tcg/wasm64.h | 10 ++ tcg/wasm64/tcg-target.c.inc | 183 ++++++++++++++++++++++++++++++++++++ 3 files changed, 252 insertions(+) diff --git a/tcg/wasm64.c b/tcg/wasm64.c index c54c5c5b2c..9fb29131cb 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -21,6 +21,10 @@ #include "qemu/osdep.h" #include "tcg/tcg.h" #include "tcg/tcg-ldst.h" +#include "tcg/helper-info.h" +#include + +__thread uintptr_t tci_tb_ptr; =20 static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0) { @@ -33,6 +37,13 @@ static void tci_args_r(uint32_t insn, TCGReg *r0) *r0 =3D extract32(insn, 8, 4); } =20 +static void tci_args_nl(uint32_t insn, const void *tb_ptr, + uint8_t *n0, void **l1) +{ + *n0 =3D extract32(insn, 8, 4); + *l1 =3D sextract32(insn, 12, 20) + (void *)tb_ptr; +} + static void tci_args_rl(uint32_t insn, const void *tb_ptr, TCGReg *r0, void **l1) { @@ -204,6 +215,54 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *en= v, const void *v_tb_ptr) opc =3D extract32(insn, 0, 8); =20 switch (opc) { + case INDEX_op_call: + { + void *call_slots[MAX_CALL_IARGS]; + ffi_cif *cif; + void *func; + unsigned i, s, n; + + tci_args_nl(insn, tb_ptr, &len, &ptr); + func =3D ((void **)ptr)[0]; + cif =3D ((void **)ptr)[1]; + + n =3D cif->nargs; + for (i =3D s =3D 0; i < n; ++i) { + ffi_type *t =3D cif->arg_types[i]; + call_slots[i] =3D &stack[s]; + s +=3D DIV_ROUND_UP(t->size, 8); + } + + /* Helper functions may need to access the "return address= " */ + tci_tb_ptr =3D (uintptr_t)tb_ptr; + ffi_call(cif, func, stack, call_slots); + } + + switch (len) { + case 0: /* void */ + break; + case 1: /* uint32_t */ + /* + * The result winds up "left-aligned" in the stack[0] slot. + * Note that libffi has an odd special case in that it will + * always widen an integral result to ffi_arg. + */ + if (sizeof(ffi_arg) =3D=3D 8) { + regs[TCG_REG_R0] =3D (uint32_t)stack[0]; + } else { + regs[TCG_REG_R0] =3D *(uint32_t *)stack; + } + break; + case 2: /* uint64_t */ + memcpy(®s[TCG_REG_R0], stack, 8); + break; + case 3: /* Int128 */ + memcpy(®s[TCG_REG_R0], stack, 16); + break; + default: + g_assert_not_reached(); + } + break; case INDEX_op_and: tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] =3D regs[r1] & regs[r2]; diff --git a/tcg/wasm64.h b/tcg/wasm64.h index 9da38e4d0e..a3631b34a8 100644 --- a/tcg/wasm64.h +++ b/tcg/wasm64.h @@ -10,6 +10,16 @@ struct WasmContext { * Pointer to the TB to be executed. */ void *tb_ptr; + + /* + * Pointer to the tci_tb_ptr variable. + */ + void *tci_tb_ptr; + + /* + * Buffer to store 128bit return value on call. + */ + void *buf128; }; =20 #endif diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index ff1151390b..765ab72941 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -28,6 +28,14 @@ #include "qemu/queue.h" #include "../wasm64.h" =20 +/* Used for function call generation. */ +#define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_STACK_ALIGN 8 +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL + typedef uint32_t tcg_insn_unit_tci; =20 static const int tcg_target_reg_alloc_order[] =3D { @@ -143,6 +151,9 @@ static const uint8_t tcg_target_reg_index[TCG_TARGET_NB= _REGS] =3D { /* Local variable pointing to WasmContext */ #define CTX_IDX 0 =20 +/* Function index */ +#define HELPER_IDX_START 0 /* The first index of helper functions */ + typedef enum { OPC_UNREACHABLE =3D 0x00, OPC_LOOP =3D 0x03, @@ -151,6 +162,7 @@ typedef enum { OPC_END =3D 0x0b, OPC_BR =3D 0x0c, OPC_RETURN =3D 0x0f, + OPC_CALL =3D 0x10, OPC_LOCAL_GET =3D 0x20, OPC_GLOBAL_GET =3D 0x23, OPC_GLOBAL_SET =3D 0x24, @@ -832,6 +844,147 @@ static void tcg_wasm_out_goto_tb( tcg_wasm_out_op(s, OPC_END); } =20 +static void push_arg_i64(TCGContext *s, int *stack_offset) +{ + intptr_t ofs; + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(TCG_REG_CALL_STACK)); + ofs =3D tcg_wasm_out_norm_ptr(s, *stack_offset); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, ofs); + *stack_offset =3D *stack_offset + 8; +} + +static void gen_call(TCGContext *s, + const TCGHelperInfo *info, uint32_t func_idx) +{ + unsigned typemask =3D info->typemask; + int rettype =3D typemask & 7; + int stack_offset =3D 0; + intptr_t ofs; + + if (rettype =3D=3D dh_typecode_i128) { + /* receive 128bit return value via the buffer */ + ofs =3D tcg_wasm_out_get_ctx(s, CTX_OFFSET(buf128)); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, ofs); + } + + for (typemask >>=3D 3; typemask; typemask >>=3D 3) { + switch (typemask & 7) { + case dh_typecode_void: + break; + case dh_typecode_i32: + case dh_typecode_s32: + push_arg_i64(s, &stack_offset); + tcg_wasm_out_op(s, OPC_I32_WRAP_I64); + break; + case dh_typecode_i64: + case dh_typecode_s64: + push_arg_i64(s, &stack_offset); + break; + case dh_typecode_i128: + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(TCG_REG_CALL_ST= ACK)); + tcg_wasm_out_op_const(s, OPC_I64_CONST, stack_offset); + tcg_wasm_out_op(s, OPC_I64_ADD); + stack_offset +=3D 16; + break; + case dh_typecode_ptr: + push_arg_i64(s, &stack_offset); + break; + default: + g_assert_not_reached(); + } + } + + tcg_wasm_out_op_idx(s, OPC_CALL, func_idx); + + switch (rettype) { + case dh_typecode_void: + break; + case dh_typecode_i32: + case dh_typecode_s32: + tcg_wasm_out_op(s, OPC_I64_EXTEND_I32_S); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(TCG_REG_R0)); + break; + case dh_typecode_i64: + case dh_typecode_s64: + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(TCG_REG_R0)); + break; + case dh_typecode_i128: + ofs =3D tcg_wasm_out_get_ctx(s, CTX_OFFSET(buf128)); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, ofs); + ofs =3D tcg_wasm_out_norm_ptr(s, 0); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, ofs); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(TCG_REG_R0)); + ofs =3D tcg_wasm_out_get_ctx(s, CTX_OFFSET(buf128)); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, ofs); + ofs =3D tcg_wasm_out_norm_ptr(s, 8); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, ofs); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(TCG_REG_R1)); + break; + case dh_typecode_ptr: + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(TCG_REG_R0)); + break; + default: + g_assert_not_reached(); + } +} + +typedef struct HelperInfo { + intptr_t idx_on_qemu; + QSIMPLEQ_ENTRY(HelperInfo) entry; +} HelperInfo; + +static __thread QSIMPLEQ_HEAD(, HelperInfo) helpers; +__thread uint32_t helper_idx; + +static void init_helpers(void) +{ + QSIMPLEQ_INIT(&helpers); + helper_idx =3D HELPER_IDX_START; +} + +static uint32_t register_helper(TCGContext *s, intptr_t helper_idx_on_qemu) +{ + tcg_debug_assert(helper_idx_on_qemu >=3D 0); + + HelperInfo *e =3D tcg_malloc(sizeof(HelperInfo)); + e->idx_on_qemu =3D helper_idx_on_qemu; + QSIMPLEQ_INSERT_TAIL(&helpers, e, entry); + + return helper_idx++; +} + +static int64_t get_helper_idx(TCGContext *s, intptr_t helper_idx_on_qemu) +{ + uint32_t idx =3D HELPER_IDX_START; + HelperInfo *e; + + QSIMPLEQ_FOREACH(e, &helpers, entry) { + if (e->idx_on_qemu =3D=3D helper_idx_on_qemu) { + return idx; + } + idx++; + } + return -1; +} + +static void tcg_wasm_out_call(TCGContext *s, intptr_t func, + const TCGHelperInfo *info) +{ + intptr_t ofs; + int64_t func_idx =3D get_helper_idx(s, func); + if (func_idx < 0) { + func_idx =3D register_helper(s, func); + } + + ofs =3D tcg_wasm_out_get_ctx(s, CTX_OFFSET(tci_tb_ptr)); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, ofs); + ofs =3D tcg_wasm_out_norm_ptr(s, 0); + tcg_wasm_out_op_const(s, OPC_I64_CONST, (uint64_t)s->code_ptr); + tcg_wasm_out_op_ldst(s, OPC_I64_STORE, 0, ofs); + + gen_call(s, info, func_idx); +} + static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) { tcg_insn_unit_tci insn =3D 0; @@ -1604,11 +1757,41 @@ void tb_target_set_jmp_target(const TranslationBloc= k *tb, int n, /* Always indirect, nothing to do */ } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *func, + const TCGHelperInfo *info) +{ + ffi_cif *cif =3D info->cif; + tcg_insn_unit_tci insn =3D 0; + uint8_t which; + + if (cif->rtype =3D=3D &ffi_type_void) { + which =3D 0; + } else { + tcg_debug_assert(cif->rtype->size =3D=3D 4 || + cif->rtype->size =3D=3D 8 || + cif->rtype->size =3D=3D 16); + which =3D ctz32(cif->rtype->size) - 1; + } + new_pool_l2(s, 20, s->code_ptr, 0, (uintptr_t)func, (uintptr_t)cif); + insn =3D deposit32(insn, 0, 8, INDEX_op_call); + insn =3D deposit32(insn, 8, 4, which); + tcg_out32(s, insn); + tcg_wasm_out_call(s, (intptr_t)func, info); +} + static void tcg_out_tb_start(TCGContext *s) { init_sub_buf(); init_blocks(); init_label_info(); + init_helpers(); =20 tcg_wasm_out_op_block(s, OPC_LOOP, BLOCK_NORET); tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, BLOCK_IDX); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412236; cv=none; d=zohomail.com; s=zohoarc; b=DCCNqgtxXQHvk/qFQaxsZBeGCv55BY00qJ3aYBducGu8gWWqHwRll9vc25zmGK2OdbhZBaaTuaSCfUCdOidG7e4C3UQptsu3xfF5EjqW+1lTA5lBRippc02GPvJ+i96X5KDueVTrHIVQXKyM+rQMRATDSEKlqL7ekW7z2JMUOpo= ARC-Message-Signature: i=1; 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Signed-off-by: Kohei Tokunaga --- tcg/tcg-op-ldst.c | 2 +- tcg/wasm64.c | 82 +++++++++++++++++ tcg/wasm64/tcg-target-has.h | 1 + tcg/wasm64/tcg-target-opc.h.inc | 2 + tcg/wasm64/tcg-target.c.inc | 155 ++++++++++++++++++++++++++++++++ 5 files changed, 241 insertions(+), 1 deletion(-) diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 354d9968f9..05c145f353 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -125,7 +125,7 @@ static void tcg_gen_req_mo(TCGBar type) =20 static TCGTemp *tci_extend_addr(TCGTemp *addr) { -#ifdef CONFIG_TCG_INTERPRETER +#if defined(CONFIG_TCG_INTERPRETER) || defined(EMSCRIPTEN) /* * 64-bit interpreter requires 64-bit addresses. * Compare to the extension performed by tcg_out_{ld,st}_helper_args diff --git a/tcg/wasm64.c b/tcg/wasm64.c index 9fb29131cb..bb2651c4dc 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -63,6 +63,14 @@ static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_t= arget_ulong *i1) *i1 =3D sextract32(insn, 12, 20); } =20 +static void tci_args_rrm(uint32_t insn, TCGReg *r0, + TCGReg *r1, MemOpIdx *m2) +{ + *r0 =3D extract32(insn, 8, 4); + *r1 =3D extract32(insn, 12, 4); + *m2 =3D extract32(insn, 16, 16); +} + static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) { *r0 =3D extract32(insn, 8, 4); @@ -190,6 +198,56 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TC= GCond condition) return result; } =20 +static uint64_t tci_qemu_ld(CPUArchState *env, uint64_t taddr, + MemOpIdx oi, const void *tb_ptr) +{ + MemOp mop =3D get_memop(oi); + uintptr_t ra =3D (uintptr_t)tb_ptr; + + switch (mop & MO_SSIZE) { + case MO_UB: + return helper_ldub_mmu(env, taddr, oi, ra); + case MO_SB: + return helper_ldsb_mmu(env, taddr, oi, ra); + case MO_UW: + return helper_lduw_mmu(env, taddr, oi, ra); + case MO_SW: + return helper_ldsw_mmu(env, taddr, oi, ra); + case MO_UL: + return helper_ldul_mmu(env, taddr, oi, ra); + case MO_SL: + return helper_ldsl_mmu(env, taddr, oi, ra); + case MO_UQ: + return helper_ldq_mmu(env, taddr, oi, ra); + default: + g_assert_not_reached(); + } +} + +static void tci_qemu_st(CPUArchState *env, uint64_t taddr, uint64_t val, + MemOpIdx oi, const void *tb_ptr) +{ + MemOp mop =3D get_memop(oi); + uintptr_t ra =3D (uintptr_t)tb_ptr; + + switch (mop & MO_SIZE) { + case MO_UB: + helper_stb_mmu(env, taddr, val, oi, ra); + break; + case MO_UW: + helper_stw_mmu(env, taddr, val, oi, ra); + break; + case MO_UL: + helper_stl_mmu(env, taddr, val, oi, ra); + break; + case MO_UQ: + helper_stq_mmu(env, taddr, val, oi, ra); + break; + default: + g_assert_not_reached(); + } +} + static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *env, const void *v_tb_= ptr) { const uint32_t *tb_ptr =3D v_tb_ptr; @@ -208,6 +266,8 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *env= , const void *v_tb_ptr) uint8_t pos, len; TCGCond condition; uint32_t tmp32; + uint64_t taddr; + MemOpIdx oi; int32_t ofs; void *ptr; =20 @@ -492,6 +552,28 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *en= v, const void *v_tb_ptr) } tb_ptr =3D ptr; break; + case INDEX_op_qemu_ld: + tci_args_rrm(insn, &r0, &r1, &oi); + taddr =3D regs[r1]; + regs[r0] =3D tci_qemu_ld(env, taddr, oi, tb_ptr); + break; + case INDEX_op_tci_qemu_ld_rrr: + tci_args_rrr(insn, &r0, &r1, &r2); + taddr =3D regs[r1]; + oi =3D regs[r2]; + regs[r0] =3D tci_qemu_ld(env, taddr, oi, tb_ptr); + break; + case INDEX_op_qemu_st: + tci_args_rrm(insn, &r0, &r1, &oi); + taddr =3D regs[r1]; + tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr); + break; + case INDEX_op_tci_qemu_st_rrr: + tci_args_rrr(insn, &r0, &r1, &r2); + taddr =3D regs[r1]; + oi =3D regs[r2]; + tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr); + break; default: g_assert_not_reached(); } diff --git a/tcg/wasm64/tcg-target-has.h b/tcg/wasm64/tcg-target-has.h index a29ceb2ea5..8fe9b45403 100644 --- a/tcg/wasm64/tcg-target-has.h +++ b/tcg/wasm64/tcg-target-has.h @@ -4,6 +4,7 @@ =20 #define TCG_TARGET_HAS_tst 0 #define TCG_TARGET_HAS_extr_i64_i32 0 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 =20 #define TCG_TARGET_extract_valid(type, ofs, len) 0 #define TCG_TARGET_sextract_valid(type, ofs, len) \ diff --git a/tcg/wasm64/tcg-target-opc.h.inc b/tcg/wasm64/tcg-target-opc.h.= inc index 092a5086ec..dcafaad93f 100644 --- a/tcg/wasm64/tcg-target-opc.h.inc +++ b/tcg/wasm64/tcg-target-opc.h.inc @@ -16,3 +16,5 @@ DEF(tci_clz32, 1, 2, 0, TCG_OPF_NOT_PRESENT) DEF(tci_ctz32, 1, 2, 0, TCG_OPF_NOT_PRESENT) DEF(tci_rotl32, 1, 2, 0, TCG_OPF_NOT_PRESENT) DEF(tci_rotr32, 1, 2, 0, TCG_OPF_NOT_PRESENT) +DEF(tci_qemu_ld_rrr, 1, 2, 0, TCG_OPF_NOT_PRESENT) +DEF(tci_qemu_st_rrr, 0, 3, 0, TCG_OPF_NOT_PRESENT) diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index 765ab72941..0f51310700 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -985,6 +985,99 @@ static void tcg_wasm_out_call(TCGContext *s, intptr_t = func, gen_call(s, info, func_idx); } =20 +static void *qemu_ld_helper_ptr(uint32_t oi) +{ + MemOp mop =3D get_memop(oi); + switch (mop & MO_SSIZE) { + case MO_UB: + return helper_ldub_mmu; + case MO_SB: + return helper_ldsb_mmu; + case MO_UW: + return helper_lduw_mmu; + case MO_SW: + return helper_ldsw_mmu; + case MO_UL: + return helper_ldul_mmu; + case MO_SL: + return helper_ldsl_mmu; + case MO_UQ: + return helper_ldq_mmu; + default: + g_assert_not_reached(); + } +} + +static void tcg_wasm_out_qemu_ld(TCGContext *s, TCGReg data_reg, + TCGReg addr_reg, MemOpIdx oi) +{ + intptr_t helper_idx; + int64_t func_idx; + + helper_idx =3D (intptr_t)qemu_ld_helper_ptr(oi); + func_idx =3D get_helper_idx(s, helper_idx); + if (func_idx < 0) { + func_idx =3D register_helper(s, helper_idx); + } + + /* call the target helper */ + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(TCG_AREG0)); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(addr_reg)); + tcg_wasm_out_op_const(s, OPC_I32_CONST, oi); + tcg_wasm_out_op_const(s, OPC_I64_CONST, (intptr_t)s->code_ptr); + + tcg_wasm_out_op_idx(s, OPC_CALL, func_idx); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(data_reg)); +} + +static void *qemu_st_helper_ptr(uint32_t oi) +{ + MemOp mop =3D get_memop(oi); + switch (mop & MO_SIZE) { + case MO_8: + return helper_stb_mmu; + case MO_16: + return helper_stw_mmu; + case MO_32: + return helper_stl_mmu; + case MO_64: + return helper_stq_mmu; + default: + g_assert_not_reached(); + } +} + +static void tcg_wasm_out_qemu_st(TCGContext *s, TCGReg data_reg, + TCGReg addr_reg, MemOpIdx oi) +{ + intptr_t helper_idx; + int64_t func_idx; + MemOp mop =3D get_memop(oi); + + helper_idx =3D (intptr_t)qemu_st_helper_ptr(oi); + func_idx =3D get_helper_idx(s, helper_idx); + if (func_idx < 0) { + func_idx =3D register_helper(s, helper_idx); + } + + /* call the target helper */ + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(TCG_AREG0)); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(addr_reg)); + switch (mop & MO_SSIZE) { + case MO_UQ: + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(data_reg)); + break; + default: + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(data_reg)); + tcg_wasm_out_op(s, OPC_I32_WRAP_I64); + break; + } + tcg_wasm_out_op_const(s, OPC_I32_CONST, oi); + tcg_wasm_out_op_const(s, OPC_I64_CONST, (intptr_t)s->code_ptr); + + tcg_wasm_out_op_idx(s, OPC_CALL, func_idx); +} + static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) { tcg_insn_unit_tci insn =3D 0; @@ -1054,6 +1147,19 @@ static void tcg_out_op_rr(TCGContext *s, TCGOpcode o= p, TCGReg r0, TCGReg r1) tcg_out32(s, insn); } =20 +static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGArg m2) +{ + tcg_insn_unit_tci insn =3D 0; + + tcg_debug_assert(m2 =3D=3D extract32(m2, 0, 16)); + insn =3D deposit32(insn, 0, 8, op); + insn =3D deposit32(insn, 8, 4, r0); + insn =3D deposit32(insn, 12, 4, r1); + insn =3D deposit32(insn, 16, 16, m2); + tcg_out32(s, insn); +} + static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2) { @@ -1786,6 +1892,55 @@ static void tcg_out_call(TCGContext *s, const tcg_in= sn_unit *func, tcg_wasm_out_call(s, (intptr_t)func, info); } =20 +static void tgen_qemu_ld(TCGContext *s, TCGType type, TCGReg data, + TCGReg addr, MemOpIdx oi) +{ + if (oi & ~0xffff) { + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, oi); + tcg_out_op_rrr(s, INDEX_op_tci_qemu_ld_rrr, data, addr, TCG_REG_TM= P); + } else { + tcg_out_op_rrm(s, INDEX_op_qemu_ld, data, addr, oi); + } + tcg_wasm_out_qemu_ld(s, data, addr, oi); +} + +static const TCGOutOpQemuLdSt outop_qemu_ld =3D { + .base.static_constraint =3D C_O1_I1(r, r), + .out =3D tgen_qemu_ld, +}; + +static void tgen_qemu_st(TCGContext *s, TCGType type, TCGReg data, + TCGReg addr, MemOpIdx oi) +{ + if (oi & ~0xffff) { + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, oi); + tcg_out_op_rrr(s, INDEX_op_tci_qemu_st_rrr, data, addr, TCG_REG_TM= P); + } else { + tcg_out_op_rrm(s, INDEX_op_qemu_st, data, addr, oi); + } + tcg_wasm_out_qemu_st(s, data, addr, oi); +} + +static const TCGOutOpQemuLdSt outop_qemu_st =3D { + .base.static_constraint =3D C_O0_I2(r, r), + .out =3D tgen_qemu_st, +}; + +bool tcg_target_has_memory_bswap(MemOp memop) +{ + return true; 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.05.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:05:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411137; x=1770015937; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5xCSzQWwTJF2/7eDxsKs1AgITtRoia5ffM8pnhI5abA=; b=naxPWNJPr54nlrTeMkWFOYXTayh/QLY2ozsf8XjLJkShgieXzm2At46tUHzZE6vgVL W8XI7qhkY4ONSGidMeu44OqSh76/eY9k0d0qLQOPtm5oJ20ZEW6ZurLzKwyoaB27PA0H 1dvNTzjyWBEJAHL7FFmS8iE/PRHpzTqqpzFYc8rkwDJ/WSGalTQIVrM3tqikyd4SlDpV 3UdFbJ8f7w1aw64/wuDZWrLsSzZONkk/mBH1kIRh3RUnhztWZeolPJFOKSLzGcHSMVqq 3lE+BqjFNQ4QD46TMVmCY1g8a+T4Hh7Vb9aigJST5p+mD5nGh/ZbodbYrgeMx4HY5kwZ 8hNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411137; x=1770015937; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=5xCSzQWwTJF2/7eDxsKs1AgITtRoia5ffM8pnhI5abA=; b=eMZCAmVrfRxnjDzHTvu9CEa9P+oQ4sOa/X5FBprTryQKY0YapsX8ht/OhDuyqbN1VT 8+UQvPLPD2PqCRdu1s58heKq7+9lm2VBSw4ezpDk46uzeH1tRB92N/T3YxpPyyFoTeCh 1vueyHbhQ42hC+6Jc6TxWyvBE62oeuS2VV/mT53TJGd5E5oQuS8yhpmbRL5q98OIRYB3 vgs4q2XCtGaGSfoer0I+ISMLkEC9/9lp4AU1AuftwEJ5XxtBy8/OOSOEFLiVYG1X7fGC sXbg7kUPseAljWR8r6FeGeH+5oIEKHuaCbFIDGLCJqyY6LkdcS3AVBGI1Lqz2cAf/Cca Hjnw== X-Gm-Message-State: AOJu0YwfJB70ELSaZlv9oMwYjOCDObjjh31VfYc27Vzjp38ZmBjeHGI8 toQyrBN4YauusVxfq4zyJfPVKe4WW3xWgg/BNTFpMb94GZhLbBq2XPfubCo1RQ9h X-Gm-Gg: AZuq6aJlXUN5M6rtzOJdlZoeNMOOqLnsNXd0ADb0psV2GwV+HFKQRajnJk0uT2r0yQP sTt0ECJnK16DrjsAM1LKH9HUgd9k4xKQtVGZogt+H5PO81PlaPQws4N1qP/u9qEa9TyIwe9isHt p/V0sm9OeiIpCqmuOhMQFc6OOVSyuuTpVIced4wNTDrpBkRxY+hJqUCic7PZxjou4uhJc6deDK0 QsQaFpKUX0jo10rQjUbp6Ei+Ohr8bjtbTXZKUzBk9ayOQRNh7FHc+R6wh1LyemFR3LkTPAU5fFm vOxXYiK5Y3/lTF5knbF5lM0kJ2ndthRzsOdlzzmCinZJYSYR+rOgcncZmjJIRIqMbsHxPFnM09/ 6eQQFwK7TvIV5QK6DcCQbolumQgAF+MlL0jUa3+6aI5LLvikUTrk4FP0hGB2HGnJbpt4D2gsGni Ez+CI6u45LC+tvZSBkDhZlj9/YIgX4mWXr1yUR67RxNg== X-Received: by 2002:a17:902:f54b:b0:2a0:906b:db3e with SMTP id d9443c01a7336-2a8455b76e9mr29605695ad.27.1769411137276; Sun, 25 Jan 2026 23:05:37 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 20/33] tcg/wasm64: Add mb instruction Date: Mon, 26 Jan 2026 07:03:33 +0000 Message-ID: <27f082f262e67da490da8c00f35df78d13e62767.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412199443154100 Content-Type: text/plain; charset="utf-8" This commit generates the mb operation. In Wasm, it uses the atomic.fence instruction as the fence operator [1]. TCI instruction is also generated in the same way as the original TCI backend using smp_mb(). [1] https://webassembly.github.io/threads/core/syntax/instructions.html#ato= mic-memory-instructions Signed-off-by: Kohei Tokunaga --- tcg/wasm64.c | 3 +++ tcg/wasm64/tcg-target.c.inc | 19 +++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/tcg/wasm64.c b/tcg/wasm64.c index bb2651c4dc..895ae062ee 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -573,6 +573,9 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *env= , const void *v_tb_ptr) taddr =3D regs[r1]; oi =3D regs[r2]; tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr); + case INDEX_op_mb: + /* Ensure ordering for all kinds */ + smp_mb(); break; default: g_assert_not_reached(); diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index 0f51310700..d187dca970 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -1116,6 +1116,11 @@ static void tcg_out_op_r(TCGContext *s, TCGOpcode op= , TCGReg r0) tcg_out32(s, insn); } =20 +static void tcg_out_op_v(TCGContext *s, TCGOpcode op) +{ + tcg_out32(s, (uint8_t)op); +} + static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t = i1) { tcg_insn_unit_tci insn =3D 0; @@ -1941,6 +1946,20 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) g_assert_not_reached(); } =20 +static void tcg_out_mb(TCGContext *s, unsigned a0) +{ + tcg_out_op_v(s, INDEX_op_mb); + + /* + * Wasm's threading proposal provides atomic.fence instruction as the = fence + * operator. + * https://webassembly.github.io/threads/core/syntax/instructions.html= #atomic-memory-instructions + */ + tcg_wasm_out8(s, 0xfe); + tcg_wasm_out8(s, 0x03); + tcg_wasm_out8(s, 0x00); +} + static void tcg_out_tb_start(TCGContext *s) { init_sub_buf(); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412095; cv=none; d=zohomail.com; s=zohoarc; b=Px8wxRVqVAIQMTwF7I6GwtEM55GQsRYllGHzKjSNoQ0qoE4fYtJdBE7VXEw3hEKMSwEPcWVVqGFGwYO2ShOYQA3ss3xYzCxwQFpFa2iABfcKVYqm/LEkMX9EYg04GAhYQEYzItkd2O09yaecs0R0ufNT1rCwtzI6nkkmrKUAi48= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769412095; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=90E4mxgxD+julKzw6BxH6qVTPgf7G7qUtJs5JfsrDkI=; b=M3lkkrICNwR9xSlLfatGkvUCF0UfBvD54QjrjDxPtRfmcWaYptBLZHHB2z+iX4NvG0nA760U68BMhX/YVwNBEdIM/BfmWMfNwv82/ae+vDx6LNC5zSIC88eGfGj9syR7GeEBqRiUXrxhS77tQVaOYE4c5aFAnhlnBn8st8ZhuNs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769412095727961.3721057753996; Sun, 25 Jan 2026 23:21:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGtE-00058I-GN; Mon, 26 Jan 2026 02:20:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGft-00034z-5J for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:06:21 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGfm-0004Pf-RY for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:06:10 -0500 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-29f2676bb21so42989245ad.0 for ; Sun, 25 Jan 2026 23:05:42 -0800 (PST) Received: from brahms.. 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Signed-off-by: Kohei Tokunaga --- tcg/wasm64/tcg-target.c.inc | 119 ++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index d187dca970..bab69b00ca 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -1960,6 +1960,125 @@ static void tcg_out_mb(TCGContext *s, unsigned a0) tcg_wasm_out8(s, 0x00); } =20 +static const TCGOutOpDeposit outop_deposit =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpExtract outop_extract =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpExtract2 outop_extract2 =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpBinary outop_addco =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpAddSubCarry outop_addci =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpBinary outop_addcio =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpAddSubCarry outop_subbo =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpAddSubCarry outop_subbi =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpAddSubCarry outop_subbio =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpUnary outop_not =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpBinary outop_andc =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpBinary outop_eqv =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpBinary outop_nand =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpBinary outop_nor =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpBinary outop_orc =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpDivRem outop_divs2 =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpDivRem outop_divu2 =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpMul2 outop_muls2 =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpBinary outop_mulsh =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpMul2 outop_mulu2 =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpBinary outop_muluh =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpBswap outop_bswap16 =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpBswap outop_bswap32 =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpUnary outop_bswap64 =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpQemuLdSt2 outop_qemu_ld2 =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static const TCGOutOpQemuLdSt2 outop_qemu_st2 =3D { + .base.static_constraint =3D C_NotImplemented, +}; + +static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) +{ + return false; +} + +static void tcg_out_set_borrow(TCGContext *s) +{ + g_assert_not_reached(); +} + +static void tcg_out_set_carry(TCGContext *s) +{ + g_assert_not_reached(); +} + static void tcg_out_tb_start(TCGContext *s) { init_sub_buf(); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412228; cv=none; d=zohomail.com; s=zohoarc; b=bP/Zbb8t6MLT5Vrh0EZ+FPm8liqr8BHlytS6CAa9FkHKvp/iKCFmJXuXE0MwhWwlomcd4ZR11EPogkASLz5ZlZ9LOEqz6lW6TbuFjVExIsIldj82Bkes6lbVNO6zkSnvmTSCDWWQzN5V0WQwc+kxLA3NvoZF1kzDmbINY2GdNpQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.05.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:05:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411146; x=1770015946; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XETmM2o4EihK8AYeDPsdnFJxfC4XHKe6S6lQlmdsixE=; b=eYHahDfWFF4r920hK66ZPecCEIXyRcDI5s1whq8qu54ogaLduvag3CjyQVEjBipGoE vv8ZmNSh8AA6Bo1HYvjg67r+eAKrp3YxS9TavRgA+myrVwo7tL8lY5F7mBBOojD8Z6zM kSJUZREkqquwEvbcGm4PwShfuCzLfCW1nGO8aNuFSn8NCO2jz5EtyuMVbW8gl+4SxPYy ZcuGQ/vHhQrm6zsbEdd21riRKwqMIIFtQFRA6yk/cSG4tmYUYVsUCLBkQ1fD/b6B1R4F ub8E0RkjS2+PhTrnsEtsHBHyu/4IIQlL36MF8ZlHTIqtbSmpNS/qFZVfW/Cqt67ej5RJ imGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411146; x=1770015946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=XETmM2o4EihK8AYeDPsdnFJxfC4XHKe6S6lQlmdsixE=; b=HRphmgJqot/xpEr2rrhsQMFWlmiF07eIASuh2/y2CE1kFOi+GB/zVf4V1D1mCklh3j +IFhIGeBGiY7LQ9CDuZcWPxorngttvvkYw0al8jmYHFjJZG106K7WqGGtbKyVCCgH+s9 WUBMbgV598ZnuRG7yyB0GjhjCNxb+kITzl9onu5xLf4829szPeyzYT/pJy8OZjLCh5PO Y/lLEJ1zkZMicuXgSON29bkJn+IVWyGSYbcD2UXTnVAo7LIU8MaoVALVmmxbDyOWOBUw ewXUtI3KztecAFCU2K0h3mwrckaJbkp1wGxcd2EaK03+HN7V5s6nnOol7J+S3ZFp+F0U Se5w== X-Gm-Message-State: AOJu0YxTwerd+CrgV2NrbEQCW3p8cGOrsFUOZmsUHLE/28h3ux8qvyVz BmI30dDpQh7dtswO5wYLZSYu/3oJHpuL6+3CThx/5gwx7yzL65Hk8KNlbh7IVCCz X-Gm-Gg: AZuq6aJ/y7e60FeOWdsiYo8R5Q1SbnL2N/nV5Kk1Qfe5Np1b94zRhkPJa74Bi8oD8oY CNmvoGMHHYQakhCzrGsfPvSIQPYQHw3eZBItYPf/305KZtvi85rVPViRDOncw0BCDJzHscJjgpX GGJdHn1ov8P8i/eEVyuG4HTEcUxuLQBj6ZABjeXJ+mDoZ11xhJx9hTuhI8H6t0XiW9gu/z72l/w 7nww2kaKolCI+xIk3yb6WAyrnQkhEfjSb3kk2OPPJKnYUCP7oI5Iils3oBkIR0mz7UoXPj6Shy7 LqxK2oXDDZ44qFqwdZy68k84p6Sp3jglohOg6o371VK04Vc4pHN+H49qtTBW7GCw91OayZzSxSg V15sTTyDf5l8vVwL/CoTsHoJwu71H1uMGLZT2o9qOua7AN/xvj1R8Je1MiDo3m3VHK7KUE6LNR6 OCREeTOGRxVfbu8r+/GkJcalTXWITVkzUfBqXeFN1LFA== X-Received: by 2002:aa7:9067:0:b0:823:d04:dee1 with SMTP id d2e1a72fcca58-823412a2f70mr3586480b3a.32.1769411146200; Sun, 25 Jan 2026 23:05:46 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 22/33] tcg/wasm64: Add initialization of fundamental registers Date: Mon, 26 Jan 2026 07:03:35 +0000 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_GMAIL_RCVD=1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412229594154100 Content-Type: text/plain; charset="utf-8" This commit adds initialization of TCG_AREG0 and TCG_REG_CALL_STACK at the beginning of each TB. The CPUArchState struct and the stack array are passed from the caller via the WasmContext structure. The BLOCK_IDX variable is initialized to 0 as TB execution begins at the first block. Signed-off-by: Kohei Tokunaga --- tcg/wasm64.h | 10 ++++++++++ tcg/wasm64/tcg-target.c.inc | 19 +++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/tcg/wasm64.h b/tcg/wasm64.h index a3631b34a8..f2b67c1099 100644 --- a/tcg/wasm64.h +++ b/tcg/wasm64.h @@ -20,6 +20,16 @@ struct WasmContext { * Buffer to store 128bit return value on call. */ void *buf128; + + /* + * Pointer to the CPUArchState struct. + */ + CPUArchState *env; + + /* + * Pointer to a stack array. + */ + uint64_t *stack; }; =20 #endif diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index bab69b00ca..f5d4cb4139 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -2081,11 +2081,30 @@ static void tcg_out_set_carry(TCGContext *s) =20 static void tcg_out_tb_start(TCGContext *s) { + intptr_t ofs; + init_sub_buf(); init_blocks(); init_label_info(); init_helpers(); =20 + /* Initialize fundamental registers */ + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(TCG_AREG0)); + tcg_wasm_out_op(s, OPC_I64_EQZ); + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_NORET); + + ofs =3D tcg_wasm_out_get_ctx(s, CTX_OFFSET(env)); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, ofs); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(TCG_AREG0)); + + ofs =3D tcg_wasm_out_get_ctx(s, CTX_OFFSET(stack)); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, ofs); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(TCG_REG_CALL_STACK)); + tcg_wasm_out_op(s, OPC_END); + + tcg_wasm_out_op_const(s, OPC_I64_CONST, 0); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, BLOCK_IDX); + tcg_wasm_out_op_block(s, OPC_LOOP, BLOCK_NORET); tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, BLOCK_IDX); tcg_wasm_out_op(s, OPC_I64_EQZ); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412093; cv=none; d=zohomail.com; s=zohoarc; b=I/Pc7WtuZdeu67j83vn0qLGsbhuYR2ztYb0jgkC9sHsloAxu1sqjtI1wOB+SfqbZV+hvKFGDuHdPhaie+xOiq0YLcnI+5lrQtm80SQWH307717D/hozVy8kfKG6jNu5dc10deqkjIZxD7zFrc4R9LwPu/iwxM/5GfWqa7HMFehA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769412093; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1DUM9H9Xhv4bjjQ4nTppfOZBFCe9No2iFqGRcQo1YjY=; b=eatxnntt7iJfjNrv545AVMAUysUGuCtWxeiWnlSXpSxMQYPI4PI9aLJQ57m/yfJnfpu3LXdjYi18qAgVj+M2N8kjsyxBu2JdUqU9hog2/eJax4MV17wbNgDFAmn1UdLN3lse8HBIOrne94QpRBtAi7o7Iy1UCyGvnrBCYbW7e68= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769412093214299.2524911980139; Sun, 25 Jan 2026 23:21:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGtB-000535-0n; Mon, 26 Jan 2026 02:19:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGfl-00034A-MJ for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:06:17 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGff-0004Qa-EU for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:06:04 -0500 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-8230c2d3128so1646661b3a.0 for ; Sun, 25 Jan 2026 23:05:51 -0800 (PST) Received: from brahms.. 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.05.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:05:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411151; x=1770015951; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1DUM9H9Xhv4bjjQ4nTppfOZBFCe9No2iFqGRcQo1YjY=; b=Unb4FAEU2VbgXMPeRIkvK1LTeOWAeulY1yAlWJQTydet6I4vzyuZbnBDrQlq9POA2o 6CbsHTAtjOPoygnZZFPAqQbz8wUM/UFb7BFE5NgOISCB1Rsaly1FsFbC3pnkol2rzCnK v3usP239gJQxiveiYjG3jfYGCFFvMH2oJ5tG7NLy3MCUm3I6Lq8vqQdBXGH5xLHVJZVk /QQT44iF9mtCIIJtI5xSUes5hN5+nFpVaxZqoV28BKjkHyLzpvxYiu5bzaV13Sql5Zvq uxq3J2MpSa+wv/OwhEeNus0+eqD5+ZzSDGjwBkxW/TdcgMbqss/3jJIxUjiG741EyLEs Iy/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411151; x=1770015951; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=1DUM9H9Xhv4bjjQ4nTppfOZBFCe9No2iFqGRcQo1YjY=; b=sNHjOMYYg/Tt6ahtL3dGeZOI0RJdpThztI0rGHujO63/QtG5ei0XSuQGgaq8wZPtJo xJLDAb03bieLKpOEG5c3SGYfx2b2b1aTMy5ofi14JS9YA9WEouaWdhsZUvLfJW/VdRzU UxhMUgGFgFDN6rj2gxnGLFYdt1k4es5nCwMcybTVKaXV05sENsobP7nKjsIQgtKWrUsI vYIcM6ffSOYvkZNpX4l7K7HMgH2vlzcbJUZ5+9VRqzl9Uas8ggZV+CeZXKvHptXbUWb9 qm5HZzY3wp0xfb3DK7il41F2PBdmgbJ8GwaE8MDGgCps85ur4FoVbSHxxFF23d0lKFeC E/uw== X-Gm-Message-State: AOJu0Yz/eiKwev9kfqtYU2zQhPmC6grp8BTpYVCOCKzQWN0ziRRe+rCg yb//lvYMaSrPL12mor+fPfLitM2p174X5JR8AfZWEA8NbiFRyFTR/iyp0UQnnTzQ X-Gm-Gg: AZuq6aIl9bgfevp7rGOn053m0yAqDNwQdIZnmIrZ7CgsR85GOwiR0jX0fr1Yqb8sxpH 5iD12XR5qtBWmxPmOAA7sNpH3m2q7y9o+PUDpsnYz1npkKFIhzp8RQWimSYH5GhE91P3MgM84dj Xw8JVQAQu7Drt/XmdLdLJeVY0ukxtHWh83xTHFK0H+APb0VtI27k1ZoB/tv9Ao+VDFsb7wWomBE Ssn2usMbjB7Qpw+aQMUvf8cyIDIr7J3aogtGA5DRgZqe/J8WCXSgYvf+eALbGYLI58YwGrCEftK w4h/jq8POED/pWm4113IZl3eHptGS2A//MVfxDetqKw/3vH5rbcykwLeTAKLBxXPxuAtct/k8f1 JwAYLS0Xv+IgJzNOgQ47CY4h+G0jMoes/3WrARk2zK9vebPdfD07YdZtDGUMby1XGAX4NVZW7PE tHUuf4Ixrw4rsA/fcIO4t38R0lkOpe9tXKVeYjg2ylMA== X-Received: by 2002:a05:6a00:b904:b0:823:148c:d785 with SMTP id d2e1a72fcca58-823411dd242mr2978008b3a.27.1769411150705; Sun, 25 Jan 2026 23:05:50 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 23/33] tcg/wasm64: Write wasm binary to TB Date: Mon, 26 Jan 2026 07:03:36 +0000 Message-ID: <6f6e5a4d136f0e736b732f30481446d360271978.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412095564158500 Content-Type: text/plain; charset="utf-8" This commit updates tcg_out_tb_start and tcg_out_tb_end to emit Wasm binaries into the TB code buffer. The generated Wasm binary defines a function of type wasm_tb_func which takes a WasmContext, executes the TB, and returns a result. In the Wasm backend, each TB starts with a WasmTBHeader which contains pointers to the following data: - TCI code - Wasm code - Array of helper function pointers imported into the Wasm instance tcg_out_tb_start writes the WasmTBHeader to the code buffer. tcg_out_tb_end generates the full Wasm executable binary by creating the Wasm module header following the spec[1][2][3] and copying the Wasm code body from sub_buf to the TB. This Wasm binary is placed after the TCI code which was emitted earlier. Additionally, an array of imported function pointers is appended to the TB. They are used during Wasm module instantiation. Function are imported to Wasm with names like "helper.0", "helper.1", etc., where the number corresponds to the array index. Each function's type signature must also be encoded in the Wasm module header. To support this, every emission of "call", "qemu_ld" and "qemu_st" operations also records the target function's type information in a buffer which will be copied to the code buffer during tcg_out_tb_end. Memory is shared between QEMU and the TBs and is imported to the Wasm module with the name "env.memory". [1] https://webassembly.github.io/spec/core/binary/modules.html [2] https://github.com/WebAssembly/threads/blob/b2567bff61ee6fbe731934f0ed1= 7a5d48dc9ab01/proposals/threads/Overview.md [3] https://github.com/WebAssembly/memory64/blob/9003cd5e24e53b84cd9027ea3d= d7ae57159a6db1/proposals/memory64/Overview.md Signed-off-by: Kohei Tokunaga --- tcg/wasm64.h | 26 +++ tcg/wasm64/tcg-target.c.inc | 406 ++++++++++++++++++++++++++++++++++++ 2 files changed, 432 insertions(+) diff --git a/tcg/wasm64.h b/tcg/wasm64.h index f2b67c1099..b5d9ce75da 100644 --- a/tcg/wasm64.h +++ b/tcg/wasm64.h @@ -32,4 +32,30 @@ struct WasmContext { uint64_t *stack; }; =20 +/* Instantiated Wasm function of a TB */ +typedef uintptr_t (*wasm_tb_func)(struct WasmContext *); + +/* + * A TB of the Wasm backend starts from a header which contains pointers f= or + * each data stored in the following region in the TB. + */ +struct WasmTBHeader { + /* + * Pointer to the region containing TCI instructions. + */ + void *tci_ptr; + + /* + * Pointer to the region containing Wasm instructions. + */ + void *wasm_ptr; + int wasm_size; + + /* + * Pointer to the array containing imported function pointers. + */ + void *import_ptr; + int import_size; +}; + #endif diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index f5d4cb4139..9854f5538c 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -154,6 +154,8 @@ static const uint8_t tcg_target_reg_index[TCG_TARGET_NB= _REGS] =3D { /* Function index */ #define HELPER_IDX_START 0 /* The first index of helper functions */ =20 +#define PTR_TYPE 0x7e + typedef enum { OPC_UNREACHABLE =3D 0x00, OPC_LOOP =3D 0x03, @@ -312,6 +314,19 @@ static int linked_buf_len(LinkedBuf *p) return total; } =20 +static int linked_buf_write(LinkedBuf *p, void *dst) +{ + int total =3D 0; + LinkedBufEntry *e; + + QSIMPLEQ_FOREACH(e, p, entry) { + memcpy(dst, e->data, e->size); + dst +=3D e->size; + total +=3D e->size; + } + return total; +} + /* * wasm code is generataed in the dynamically allocated buffer which * are managed as a linked list. @@ -928,6 +943,99 @@ static void gen_call(TCGContext *s, } } =20 +static __thread LinkedBuf types_buf; + +static void init_types_buf(void) +{ + QSIMPLEQ_INIT(&types_buf); +} + +static void types_buf_out8(uint8_t v) +{ + linked_buf_out8(&types_buf, v); +} + +static void gen_func_type_call(TCGContext *s, const TCGHelperInfo *info) +{ + unsigned typemask =3D info->typemask; + int rettype =3D typemask & 7; + uint32_t vec_size =3D 0; + + if (rettype =3D=3D dh_typecode_i128) { + vec_size++; + } + for (int m =3D typemask >> 3; m; m >>=3D 3) { + if ((m & 7) !=3D dh_typecode_void) { + vec_size++; + } + } + + types_buf_out8(0x60); + linked_buf_out_leb128(&types_buf, vec_size); + + if (rettype =3D=3D dh_typecode_i128) { + types_buf_out8(PTR_TYPE); + } + + for (int m =3D typemask >> 3; m; m >>=3D 3) { + switch (m & 7) { + case dh_typecode_void: + break; + case dh_typecode_i32: + case dh_typecode_s32: + types_buf_out8(0x7f); + break; + case dh_typecode_i64: + case dh_typecode_s64: + types_buf_out8(0x7e); + break; + case dh_typecode_i128: + types_buf_out8(PTR_TYPE); + break; + case dh_typecode_ptr: + types_buf_out8(PTR_TYPE); + break; + default: + g_assert_not_reached(); + } + } + + switch (rettype) { + case dh_typecode_void: + case dh_typecode_i128: + types_buf_out8(0x0); + break; + case dh_typecode_i32: + case dh_typecode_s32: + types_buf_out8(0x1); + types_buf_out8(0x7f); + break; + case dh_typecode_i64: + case dh_typecode_s64: + types_buf_out8(0x1); + types_buf_out8(0x7e); + break; + case dh_typecode_ptr: + types_buf_out8(0x1); + types_buf_out8(PTR_TYPE); + break; + default: + g_assert_not_reached(); + } +} + +static __thread LinkedBuf imports_buf; + +static void init_imports_buf(void) +{ + QSIMPLEQ_INIT(&imports_buf); +} + +static void imports_buf_out8(uint8_t v) +{ + linked_buf_out8(&imports_buf, v); +} + typedef struct HelperInfo { intptr_t idx_on_qemu; QSIMPLEQ_ENTRY(HelperInfo) entry; @@ -944,15 +1052,56 @@ static void init_helpers(void) =20 static uint32_t register_helper(TCGContext *s, intptr_t helper_idx_on_qemu) { + uint32_t typeidx =3D helper_idx + 1; + char buf[11]; /* enough for decimal int max + NULL*/ + int n =3D snprintf(buf, sizeof(buf), "%d", helper_idx - HELPER_IDX_STA= RT); + tcg_debug_assert(helper_idx_on_qemu >=3D 0); =20 HelperInfo *e =3D tcg_malloc(sizeof(HelperInfo)); e->idx_on_qemu =3D helper_idx_on_qemu; QSIMPLEQ_INSERT_TAIL(&helpers, e, entry); =20 + tcg_debug_assert(n < sizeof(buf)); + imports_buf_out8(6); /* helper */ + imports_buf_out8(0x68); + imports_buf_out8(0x65); + imports_buf_out8(0x6c); + imports_buf_out8(0x70); + imports_buf_out8(0x65); + imports_buf_out8(0x72); + linked_buf_out_leb128(&imports_buf, (uint32_t)n); + for (int i =3D 0; i < n; i++) { + imports_buf_out8(buf[i]); + } + imports_buf_out8(0); /* type(0) */ + linked_buf_out_leb128(&imports_buf, typeidx); + return helper_idx++; } =20 +static int helpers_len(void) +{ + int n =3D 0; + HelperInfo *e; + + QSIMPLEQ_FOREACH(e, &helpers, entry) { + n++; + } + return n; +} + +static int helpers_write_to_array(intptr_t *dst) +{ + intptr_t *start =3D dst; + HelperInfo *e; + + QSIMPLEQ_FOREACH(e, &helpers, entry) { + *dst++ =3D e->idx_on_qemu; + } + return (intptr_t)dst - (intptr_t)start; +} + static int64_t get_helper_idx(TCGContext *s, intptr_t helper_idx_on_qemu) { uint32_t idx =3D HELPER_IDX_START; @@ -974,6 +1123,7 @@ static void tcg_wasm_out_call(TCGContext *s, intptr_t = func, int64_t func_idx =3D get_helper_idx(s, func); if (func_idx < 0) { func_idx =3D register_helper(s, func); + gen_func_type_call(s, info); } =20 ofs =3D tcg_wasm_out_get_ctx(s, CTX_OFFSET(tci_tb_ptr)); @@ -985,6 +1135,39 @@ static void tcg_wasm_out_call(TCGContext *s, intptr_t= func, gen_call(s, info, func_idx); } =20 +static void gen_func_type_qemu_ld(TCGContext *s, uint32_t oi) +{ + types_buf_out8(0x60); + types_buf_out8(0x4); + types_buf_out8(PTR_TYPE); + types_buf_out8(0x7e); + types_buf_out8(0x7f); + types_buf_out8(PTR_TYPE); + types_buf_out8(0x1); + types_buf_out8(0x7e); +} + +static void gen_func_type_qemu_st(TCGContext *s, uint32_t oi) +{ + MemOp mop =3D get_memop(oi); + + types_buf_out8(0x60); + types_buf_out8(0x5); + types_buf_out8(PTR_TYPE); + types_buf_out8(0x7e); + switch (mop & MO_SSIZE) { + case MO_UQ: + types_buf_out8(0x7e); + break; + default: + types_buf_out8(0x7f); + break; + } + types_buf_out8(0x7f); + types_buf_out8(PTR_TYPE); + types_buf_out8(0x0); +} + static void *qemu_ld_helper_ptr(uint32_t oi) { MemOp mop =3D get_memop(oi); @@ -1018,6 +1201,7 @@ static void tcg_wasm_out_qemu_ld(TCGContext *s, TCGRe= g data_reg, func_idx =3D get_helper_idx(s, helper_idx); if (func_idx < 0) { func_idx =3D register_helper(s, helper_idx); + gen_func_type_qemu_ld(s, oi); } =20 /* call the target helper */ @@ -1058,6 +1242,7 @@ static void tcg_wasm_out_qemu_st(TCGContext *s, TCGRe= g data_reg, func_idx =3D get_helper_idx(s, helper_idx); if (func_idx < 0) { func_idx =3D register_helper(s, helper_idx); + gen_func_type_qemu_st(s, oi); } =20 /* call the target helper */ @@ -2079,14 +2264,164 @@ static void tcg_out_set_carry(TCGContext *s) g_assert_not_reached(); } =20 +static const uint8_t mod_1[] =3D { + 0x0, 0x61, 0x73, 0x6d, /* magic */ + 0x01, 0x0, 0x0, 0x0, /* version */ + + 0x01, /* type section */ + 0x80, 0x80, 0x80, 0x80, 0x00, /* placehodler for size */ + 0x80, 0x80, 0x80, 0x80, 0x00, /* placehodler for num of types vec */ + 0x60, /* 0: Type of "start" function */ + 0x01, PTR_TYPE, /* arg: ctx pointer */ + 0x01, PTR_TYPE, /* return: res */ +}; + +#define MOD_1_PH_TYPE_SECTION_SIZE_OFF 9 +#define MOD_1_PH_TYPE_VEC_NUM_OFF 14 + +static const uint8_t mod_2[] =3D { + 0x02, /* import section */ + 0x80, 0x80, 0x80, 0x80, 0x00, /* placehodler for size */ + 0x80, 0x80, 0x80, 0x80, 0x00, /* placehodler for imports n= um */ + 0x03, 0x65, 0x6e, 0x76, /* module: "env" */ + 0x06, 0x6d, 0x65, 0x6d, 0x6f, 0x72, 0x79, /* name: "memory" */ +#if defined(WASM64_MEMORY64_2) + /* 32bit memory is used for Emscripten's "-sMEMORY64=3D2" configuratio= n. */ + 0x02, 0x03, /* shared mem */ + 0x00, 0x80, 0x80, 0x04, /* min: 0, max: 65536 pages = */ +#else + /* + * 64bit memory is used for Emscripten's "-sMEMORY64=3D1" configuratio= n. + * Note: the maximum 64bit memory size of the engine implementations is + * limited to 262144 pages(16GiB) + * https://webassembly.github.io/memory64/js-api/#limits + */ + 0x02, 0x07, /* shared mem(64bit) */ + 0x00, 0x80, 0x80, 0x10, /* min: 0, max: 262144 pages= */ +#endif +}; + +#define MOD_2_PH_IMPORT_SECTION_SIZE_OFF 1 +#define MOD_2_PH_IMPORT_VEC_NUM_OFF 6 + +static const uint8_t mod_3[] =3D { + 0x03, /* function section */ + 2, 1, 0x00, /* function type 0 */ + + 0x06, /* global section */ + 86, /* section size */ + 17, /* num of global vars */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + 0x7e, 0x01, 0x42, 0x00, 0x0b, /* 0-cleared 64bit var */ + + 0x07, /* export section */ + 13, /* size of section */ + 1, /* num of funcs */ + 0x05, 0x73, 0x74, 0x61, 0x72, 0x74, /* "start" function */ + 0x00, 0x80, 0x80, 0x80, 0x80, 0x00, /* placeholder for func index*/ + + 0x0a, /* code section */ + 0x80, 0x80, 0x80, 0x80, 0x00, /* placeholder for section size*/ + 1, /* num of codes */ + 0x80, 0x80, 0x80, 0x80, 0x00, /* placeholder for code size */ + 0x0, /* local variables (none) */ +}; + +#define MOD_3_PH_EXPORT_START_FUNC_IDX 102 +#define MOD_3_PH_CODE_SECTION_SIZE_OFF 108 +#define MOD_3_PH_CODE_SIZE_OFF 114 +#define MOD_3_VARIABLES_SIZE 5 +#define MOD_3_CODE_SECTION_SIZE_ADD 11 + +static void fill_uint32_leb128(uint8_t *b, uint32_t v) +{ + do { + *b |=3D v & 0x7f; + v >>=3D 7; + b++; + } while (v !=3D 0); +} + +typedef struct FillValueU32 { + int64_t offset; + uint32_t value; +} FillValueU32; + +static int write_mod(TCGContext *s, const uint8_t mod[], int len, + FillValueU32 values[], int values_len) +{ + void *base =3D s->code_ptr; + + if (unlikely(((void *)s->code_ptr + len) + > s->code_gen_highwater)) { + return -1; + } + + memcpy(s->code_ptr, mod, len); + s->code_ptr +=3D len; + + for (int i =3D 0; i < values_len; i++) { + fill_uint32_leb128(base + values[i].offset, values[i].value); + } + + return 0; +} + +static int write_mod_code(TCGContext *s) +{ + void *base =3D s->code_ptr; + int code_size =3D sub_buf_len(); + BlockPlaceholder *e; + + if (unlikely(((void *)s->code_ptr + code_size) > s->code_gen_highwater= )) { + return -1; + } + linked_buf_write(&sub_buf, s->code_ptr); + s->code_ptr +=3D code_size; + + QSIMPLEQ_FOREACH(e, &block_placeholder, entry) { + uint8_t *ph =3D e->pos + base; + int blk =3D get_block_of_label(e->label); + tcg_debug_assert(blk >=3D 0); + fill_uint32_leb128(ph, blk); + } + + return 0; +} + static void tcg_out_tb_start(TCGContext *s) { intptr_t ofs; + struct WasmTBHeader *h; =20 init_sub_buf(); init_blocks(); init_label_info(); init_helpers(); + init_types_buf(); + init_imports_buf(); + + /* TB starts from a header */ + h =3D (struct WasmTBHeader *)(s->code_ptr); + s->code_ptr +=3D sizeof(struct WasmTBHeader); + + /* Followed by TCI code */ + h->tci_ptr =3D s->code_ptr; =20 /* Initialize fundamental registers */ tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(TCG_AREG0)); @@ -2113,10 +2448,81 @@ static void tcg_out_tb_start(TCGContext *s) =20 static int tcg_out_tb_end(TCGContext *s) { + int res; + struct WasmTBHeader *h =3D (struct WasmTBHeader *)(s->code_buf); + tcg_wasm_out_op(s, OPC_END); /* end if */ tcg_wasm_out_op(s, OPC_END); /* end loop */ tcg_wasm_out_op(s, OPC_UNREACHABLE); tcg_wasm_out_op(s, OPC_END); /* end func */ =20 + /* write wasm blob */ + h->wasm_ptr =3D s->code_ptr; + + res =3D write_mod(s, mod_1, sizeof(mod_1), (FillValueU32[]) { + { + MOD_1_PH_TYPE_SECTION_SIZE_OFF, + linked_buf_len(&types_buf) + + sizeof(mod_1) - MOD_1_PH_TYPE_VEC_NUM_OFF + }, + { + MOD_1_PH_TYPE_VEC_NUM_OFF, + HELPER_IDX_START + helpers_len() + 1/* start */ + }, + }, 2); + if (res < 0) { + return res; + } + s->code_ptr +=3D linked_buf_write(&types_buf, s->code_ptr); + + res =3D write_mod(s, mod_2, sizeof(mod_2), (FillValueU32[]) { + { + MOD_2_PH_IMPORT_SECTION_SIZE_OFF, + linked_buf_len(&imports_buf) + + sizeof(mod_2) - MOD_2_PH_IMPORT_VEC_NUM_OFF + }, + { + MOD_2_PH_IMPORT_VEC_NUM_OFF, + HELPER_IDX_START + helpers_len() + 1/* memory */ + }, + }, 2); + if (res < 0) { + return res; + } + s->code_ptr +=3D linked_buf_write(&imports_buf, s->code_ptr); + + res =3D write_mod(s, mod_3, sizeof(mod_3), (FillValueU32[]) { + { + MOD_3_PH_EXPORT_START_FUNC_IDX, + HELPER_IDX_START + helpers_len() + }, + { + MOD_3_PH_CODE_SECTION_SIZE_OFF, + sub_buf_len() + MOD_3_CODE_SECTION_SIZE_ADD + }, + { + MOD_3_PH_CODE_SIZE_OFF, + sub_buf_len() + MOD_3_VARIABLES_SIZE + }, + }, 3); + if (res < 0) { + return res; + } + + res =3D write_mod_code(s); + if (res < 0) { + return res; + } + h->wasm_size =3D (intptr_t)s->code_ptr - (intptr_t)h->wasm_ptr; + + /* record imported helper functions */ + if (unlikely(((void *)s->code_ptr + helpers_len() * 4) + > s->code_gen_highwater)) { + return -1; + } + h->import_ptr =3D s->code_ptr; + s->code_ptr +=3D helpers_write_to_array((intptr_t *)s->code_ptr); + h->import_size =3D (intptr_t)s->code_ptr - (intptr_t)h->import_ptr; + return 0; } --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412094; cv=none; d=zohomail.com; s=zohoarc; b=ZlRj9KJUHruAjyVl8uJAa4AZa8zYtvna2JYFRnIr97FmR8vovxDpFiJ0S12esOc7b1Y6oUa3cLTLcOGwwMfUZaWr7Wlq1A0d8a+N3zuN8L7ahVorZflR3hPvM3B10oIQEapkIjejJpX/3VaVb1865sdzgldpl61xihsnSVMWk+8= ARC-Message-Signature: i=1; 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.05.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:05:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411155; x=1770015955; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QBiuZHC2ujyOFipmh/6NFwPTzHzb15N2Yq98z1rMyKY=; b=GiIJEj9B7HMoskYSCrhOFVzSDCmqGrUD1s0hQJ4QxJ5CkldaUFG0Qsky5LP7o0giya Lwv9jsX/nC72hdN8EmFI7FC9t5E4lb/YTPNf5eD9GmPHS60/FtPFLlS/uV9OuMxkFlQ/ xzvu5THNfd2ukZt5Bz+GzWJEUZTHJWdvwE4mLgIjFF/iEgW0g1pCY7wsEf4fQrBUNlWa nnzu289V9aQoCnjaNypv+zu4SZr9XeH4oh8EyAPEdEeJa2YtV4O6B2PLEQTaZ+UqBqMH /7EDYIfK1ub7V/WK9nD33th8zl4mZXtS0+dogvp9kqu7eaQsZnxsboUIlyIcZBDo59Wx wo0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411155; x=1770015955; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=QBiuZHC2ujyOFipmh/6NFwPTzHzb15N2Yq98z1rMyKY=; b=mWsx0q2hCqb684Ej4no2v3XYnfNK1v1Y/KbZ7dLtDd6+WAcKesX7opk5O4gKt1UVmZ Ih4IIzYIW56LfUXOy9h7EyvoHiVmM8CgToBWNxC5f2Fhn1g9ZQGC0ynMAmlqzBXNN634 Ik84USTcbuKc38ecQqtg2oZ2pBbQZ0FOs7PFZ7RTFL+Xp4DI5NaRv0ZEGya3YYdibgTt n14XS1tEZrELXFxjEGiOa2bw75NLSOQR0geXnuK7C1e2tAcGEXsvwPGQdFAUqAykkdj/ POkeAYoXoOi2kRm06FvU1OQSvfsNruEA9OndSXbZTLvuxrdjgEcbm7EuSyJOmb0WYnEV oLYA== X-Gm-Message-State: AOJu0YwG18Lk+06J1fWuYgiCCHV1bxytehIYZbwY4ustxqaHkuiKwK+x Z9/ra1utp6tXsLXZfD3XptTlA46bzfyiCo+cdOZIE+ZQlqFb6Z6+SBV9NNor0eUo X-Gm-Gg: AZuq6aITd7Vl3nCPt/4KaTxqMNaNtenAzfwfLWZkrDl5+i9ZI8kdntSkGKuqPuhQ2/x cjo87FY/NizTkaDZ76BQXTCpOP56zNea7vV3ixzq9xyL3WoPMQT10rtHZhp+qlrsldZfaX0Zo+a mScZb4MvSFrf4eavKqeDo80teS08HXTL/JEKYLHnQLXC9KLAtIG9ppEQoITiGSAM4W1JeMNVV9O XJYDP9xB5IJpLTUOSwj5quRIafqMDrzU/pAT4p16cFOHkrP9pPLlNwt8kflfN4URSqzMlkKB8/h 4rAzN8b+NZobDk8Y+ABPn8F3Fm5cJFtWuymtETge0H0q+V1962SAq+XTXsd/AF6BeAahgSx3SCF F3LZJIpTZgt2t1TBmznsiSLrhDeFjsdgXHZARYc0PSDTG8m3TnPAAo0We7b41Z2X6EhJf6V/ugD eSopeRnYBCz0JaTG59ohYgq9Gm5vrUmx0QMZo2+3zpEA== X-Received: by 2002:a17:90b:6c3:b0:34a:9d9a:3f67 with SMTP id 98e67ed59e1d1-353c41a69e3mr3084073a91.33.1769411155173; Sun, 25 Jan 2026 23:05:55 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 24/33] tcg/wasm64: Implement instantiation of Wasm binary Date: Mon, 26 Jan 2026 07:03:37 +0000 Message-ID: <00b8d87b3e0acf00b140a3f60f91c84eeae95b3b.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412110230158500 Content-Type: text/plain; charset="utf-8" instantiate_wasm is a function that instantiates a TB's Wasm binary, importing the functions as specified by its arguments. Following the header definition in wasm64/tcg-target.c.inc, QEMU's memory is imported into the module as "env.memory", and helper functions are imported as "helper.". The instantiated Wasm module is imported to QEMU using Emscripten's "addFunction" feature[1] which returns a function pointer. This allows QEMU to call this module directly from C code via that pointer. Since the subarray() method doesn't accept a BigInt value which is used for the 64bit pointer value, it is converted to a Number (i53) using bigintToI53Checked method of Emscripten. Although this conversion (64bit to 53bit) drops higher bits, the maximum memory size of the engine implementations is currently limited to 16GiB[2] so we can assume that the pointers are within the Number's range. Note that since FireFox 138, WebAssembly.Module no longer accepts a SharedArrayBuffer as input [3] as reported by Nicolas Vandeginste in my fork[4]. This commit ensures that WebAssembly.Module() is passed a Uint8Array created from the binary data on a SharedArrayBuffer. [1] https://emscripten.org/docs/porting/connecting_cpp_and_javascript/Inter= acting-with-code.html#calling-javascript-functions-as-function-pointers-fro= m-c [2] https://webassembly.github.io/memory64/js-api/#limits [3] https://bugzilla.mozilla.org/show_bug.cgi?id=3D1965217 [4] https://github.com/ktock/qemu-wasm/pull/25 Signed-off-by: Kohei Tokunaga --- tcg/wasm64.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/tcg/wasm64.c b/tcg/wasm64.c index 895ae062ee..41898ff867 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -23,6 +23,42 @@ #include "tcg/tcg-ldst.h" #include "tcg/helper-info.h" #include +#include + +#define EM_JS_PRE(ret, name, args, body...) EM_JS(ret, name, args, body) + +#define DEC_PTR(p) bigintToI53Checked(p) +#define ENC_PTR(p) BigInt(p) +#if defined(WASM64_MEMORY64_2) +#define ENC_WASM_TABLE_IDX(i) Number(i) +#else +#define ENC_WASM_TABLE_IDX(i) i +#endif + +EM_JS_PRE(void*, instantiate_wasm, (void *wasm_begin, + int wasm_size, + void *import_vec_begin, + int import_vec_size), +{ + const memory_v =3D new DataView(HEAP8.buffer); + const wasm =3D HEAP8.subarray(DEC_PTR(wasm_begin), + DEC_PTR(wasm_begin) + wasm_size); + var helper =3D {}; + for (var i =3D 0; i < import_vec_size / 8; i++) { + const idx =3D memory_v.getBigInt64( + DEC_PTR(import_vec_begin) + i * 8, true); + helper[i] =3D wasmTable.get(ENC_WASM_TABLE_IDX(idx)); + } + const mod =3D new WebAssembly.Module(new Uint8Array(wasm)); + const inst =3D new WebAssembly.Instance(mod, { + "env" : { + "memory" : wasmMemory, + }, + "helper" : helper, + }); + + return ENC_PTR(addFunction(inst.exports.start, 'ii')); +}); =20 __thread uintptr_t tci_tb_ptr; =20 --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412359; cv=none; d=zohomail.com; s=zohoarc; b=ACJtGZh6ShDWO1eNZNh6buOy+vHax7s2B/RyPVKRh5RONKLlKP2SA+oc3mRdMW5nbGSA5HuXAIv99/zh/pIZcfGs2zfHWiAmfE9CfKOpqkk4Sa0UAj1almGcskSzHlPBD72RaSuA01fZOhnFNc1gtie2xLgm5u+3QCieaMGtKtM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769412359; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=31758oVt+UsNtiVkJ/ZaHor2xPA47heR/D/TsozA2Cg=; b=d5kysFlOkN0tvfQDAFmjQGTa3kEHmkF2YKZqWh8pTQf1MToQbpeHnGfPcq5INNGzmVVQskP1pRY94U+dXoOtS+cFVp7Ay6ssiVCYOWTMON9ReGtKxBddxS5XqOAliz62yvhAcPeodG/slnCIUCRim64nZxdWd75HiNJva9Q8d4k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769412359787568.3334040761534; Sun, 25 Jan 2026 23:25:59 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGtH-0005Ep-BO; Mon, 26 Jan 2026 02:20:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGg2-00038O-9o for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:06:30 -0500 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGfs-0004S4-QY for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:06:16 -0500 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-81f4f4d4822so2135027b3a.3 for ; Sun, 25 Jan 2026 23:06:00 -0800 (PST) Received: from brahms.. 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.05.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:05:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411160; x=1770015960; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=31758oVt+UsNtiVkJ/ZaHor2xPA47heR/D/TsozA2Cg=; b=HMh42XkbbPUzHMLDSA3SvEhjNoHQ1ydpFYRJ8nOOX4sxsSNq4iHcO/9ojCAfaNcCWp ZmxadJVEjxBQXy0Vc4XAxi8Fga+wBk3yIta+yCbUogCSGojbskM6vUjppS6VJXshe4w/ e42+W/xwbdNyNqe7JUKfmA2X0O3eX5tif1czW/2GaXRi+xdJHtD3Z+Y99+QZbBA3VqWn XjOkPqVkim3YDgz/I4S2Gb5EIXYV0QSsGYtEqWJdHC5QKTbv8DwqZ1v3uQ3UoW9/bKny rqu6POuutvGaAmSV1pyFDkIdoRtcI91vU+Z4NmEiHVwLFs/S9PgCW0YMTJ8+2bP7yig+ 1PVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411160; x=1770015960; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=31758oVt+UsNtiVkJ/ZaHor2xPA47heR/D/TsozA2Cg=; b=kP13+pBXO/Q5L1oBLMx2SIkcn5nH927EJmRp16O60GosIb/1dMv7nbvN9hxIsumo48 /FGnbWTMlEKeZd3uf31YF9MBNwVrrV4lP88zrmJeJCqnxM7xHnLr5O5zUA8Q94T/S/pJ bYjWebkG9q41RfAl+mOfRS/91imiX5Xjl5poOa2AJyvsvnnGCT2MyameqjINYyjowjN4 0yMXOCiXyEtpbRT1+Syh0hzWchbzMTFFPuvaJeLkQ6jAsr8Ni7xToy1DRexjwIEl2xdR uibdUaWjaHhqPlsmn8DqNq0KzQyenj0qUsUp8fH8CskY5kvVg4TyMbSoI/PTN2HetPpJ 2IMw== X-Gm-Message-State: AOJu0YwpYdSrbTVD9ma3w095uX+rZe0vnLnvmZU27zc/0tXuv65QkV60 ozhJJqL/XWo/d+sZC9ln+uJ0nq1HNQjE1+5/4mcam1PMZzlGkSdNolR9797PTY41 X-Gm-Gg: AZuq6aI6gX7bDr4ZbWP+RBNnmm6zJ2++myXhZ8o/N4MuxZWfUu0cRxBK633hRkY6DLA VTY32kxYAZ1prByg7Ht9lzYma3i+mzBJumpaBFFJCC7FYaJKzAAPTbzUdMMK9/sCGvVmY7de60I Iu7yX/VmBQAtNqjkQXZISlO0JvopuAO+VKd/n1N0LA9ZQx1gxvnAEqDx4vtWQO9JIvR2xKadcHv MG/1Ui1IqrqR5S74mW29ynw8fLbMFFmaUUL6iEG93eNZ01zN36h10Cqp7RNjGIQ7ut42SJiWBZY St7Sm3fLfRQ7nruyf71+34UzQqv0Ct89ORKmQu3hsf8NyKHOmm3Y489MWpw5DcipsNYFjAwIZ9U p4CjHScnYMxtWRk/qS1gDgDX6vm7ThIi2MTj7V3XLwVffuMm05qgGpxEvFkV69Usf2InXEoMjRg xwcH2En6qEP5Hl3jg7bLDhjweZzP9rdvpD6XAmzi5g6g== X-Received: by 2002:a05:6a00:94c8:b0:81f:4dfe:dddf with SMTP id d2e1a72fcca58-823411a0098mr3193586b3a.3.1769411159634; Sun, 25 Jan 2026 23:05:59 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 25/33] tcg/wasm64: Allow switching coroutine from a helper Date: Mon, 26 Jan 2026 07:03:38 +0000 Message-ID: <8917febfda7824f56867d7f227311eeb568d3d0d.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412361468154100 Content-Type: text/plain; charset="utf-8" Emscripten's Fiber coroutine implements coroutine switching using Asyncify's stack unwinding and rewinding features [1]. When a coroutine yields (i.e. switches out), Asyncify unwinds the stack, returning control to Emscripten's JS code (Fiber.trampoline()). Then execution resumes in the target coroutine by rewinding the stack. Stack unwinding is implemented by a sequence of immediate function returns, while rewinding re-enters the functions in the call stack, skipping any code between the function's entry point and the original call position [2]. This commit updates the TB's Wasm module to allow helper functions to trigger coroutine switching. Particaully, the TB handles the unwinding and rewinding flows as follows: - The TB check the Asyncify.state JS object after each helper call. If unwinding is in progress, the TB immediately returns to the caller so that the unwinding can continue. - Each function call is preceded by a block boundary and an update of the BLOCK_IDX variable. This enables rewinding to skip any code between the function's entry point and the original call position. Additionally, this commit introduces WasmContext.do_init which is a flag indicating whether the TB should reset the BLOCK_IDX variable to 0 (i.e. start from the beginning). call_wasm_tb is a newly introduced wrapper function for the Wasm module's entrypoint and this sets "do_init =3D 1" to ensure normal TB execution begins at the first block. During a rewinding, the C code does not set do_init to 1, allowing the TB to preserve the BLOCK_IDX value from the previous unwinding and correctly resume execution from the last unwound block. [1] https://emscripten.org/docs/api_reference/fiber.h.html [2] https://kripken.github.io/blog/wasm/2019/07/16/asyncify.html#new-asynci= fy Signed-off-by: Kohei Tokunaga --- tcg/wasm64.c | 3 ++ tcg/wasm64.h | 11 +++++++ tcg/wasm64/tcg-target.c.inc | 58 ++++++++++++++++++++++++++++++++++++- 3 files changed, 71 insertions(+), 1 deletion(-) diff --git a/tcg/wasm64.c b/tcg/wasm64.c index 41898ff867..7ae976d9eb 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -44,6 +44,9 @@ EM_JS_PRE(void*, instantiate_wasm, (void *wasm_begin, const wasm =3D HEAP8.subarray(DEC_PTR(wasm_begin), DEC_PTR(wasm_begin) + wasm_size); var helper =3D {}; + helper.u =3D () =3D> { + return (Asyncify.state !=3D Asyncify.State.Unwinding) ? 1 : 0; + }; for (var i =3D 0; i < import_vec_size / 8; i++) { const idx =3D memory_v.getBigInt64( DEC_PTR(import_vec_begin) + i * 8, true); diff --git a/tcg/wasm64.h b/tcg/wasm64.h index b5d9ce75da..fdde908557 100644 --- a/tcg/wasm64.h +++ b/tcg/wasm64.h @@ -30,11 +30,22 @@ struct WasmContext { * Pointer to a stack array. */ uint64_t *stack; + + /* + * Flag indicating whether to initialize the block index(1) or not(0). + */ + uint32_t do_init; }; =20 /* Instantiated Wasm function of a TB */ typedef uintptr_t (*wasm_tb_func)(struct WasmContext *); =20 +static inline uintptr_t call_wasm_tb(wasm_tb_func f, struct WasmContext *c= tx) +{ + ctx->do_init =3D 1; /* reset the block index (rewinding will skip this= ) */ + return f(ctx); +} + /* * A TB of the Wasm backend starts from a header which contains pointers f= or * each data stored in the following region in the TB. diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index 9854f5538c..ad9e5a43b5 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -152,7 +152,8 @@ static const uint8_t tcg_target_reg_index[TCG_TARGET_NB= _REGS] =3D { #define CTX_IDX 0 =20 /* Function index */ -#define HELPER_IDX_START 0 /* The first index of helper functions */ +#define CHECK_UNWINDING_IDX 0 /* A function to check the Asyncify status */ +#define HELPER_IDX_START 1 /* The first index of helper functions */ =20 #define PTR_TYPE 0x7e =20 @@ -169,6 +170,7 @@ typedef enum { OPC_GLOBAL_GET =3D 0x23, OPC_GLOBAL_SET =3D 0x24, =20 + OPC_I32_LOAD =3D 0x28, OPC_I64_LOAD =3D 0x29, OPC_I64_LOAD8_S =3D 0x30, OPC_I64_LOAD8_U =3D 0x31, @@ -176,6 +178,7 @@ typedef enum { OPC_I64_LOAD16_U =3D 0x33, OPC_I64_LOAD32_S =3D 0x34, OPC_I64_LOAD32_U =3D 0x35, + OPC_I32_STORE =3D 0x36, OPC_I64_STORE =3D 0x37, OPC_I64_STORE8 =3D 0x3c, OPC_I64_STORE16 =3D 0x3d, @@ -1116,6 +1119,17 @@ static int64_t get_helper_idx(TCGContext *s, intptr_= t helper_idx_on_qemu) return -1; } =20 +static void tcg_wasm_out_handle_unwinding(TCGContext *s) +{ + tcg_wasm_out_op_idx(s, OPC_CALL, CHECK_UNWINDING_IDX); + tcg_wasm_out_op(s, OPC_I32_EQZ); + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_NORET); + tcg_wasm_out_op_const(s, OPC_I64_CONST, 0); + /* returns if unwinding */ + tcg_wasm_out_op(s, OPC_RETURN); + tcg_wasm_out_op(s, OPC_END); +} + static void tcg_wasm_out_call(TCGContext *s, intptr_t func, const TCGHelperInfo *info) { @@ -1132,7 +1146,16 @@ static void tcg_wasm_out_call(TCGContext *s, intptr_= t func, tcg_wasm_out_op_const(s, OPC_I64_CONST, (uint64_t)s->code_ptr); tcg_wasm_out_op_ldst(s, OPC_I64_STORE, 0, ofs); =20 + /* + * update the block index so that the possible rewinding will + * skip this block + */ + tcg_wasm_out_op_const(s, OPC_I64_CONST, cur_block_idx + 1); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, BLOCK_IDX); + tcg_wasm_out_new_block(s); + gen_call(s, info, func_idx); + tcg_wasm_out_handle_unwinding(s); } =20 static void gen_func_type_qemu_ld(TCGContext *s, uint32_t oi) @@ -1204,6 +1227,14 @@ static void tcg_wasm_out_qemu_ld(TCGContext *s, TCGR= eg data_reg, gen_func_type_qemu_ld(s, oi); } =20 + /* + * update the block index so that the possible rewinding will + * skip this block + */ + tcg_wasm_out_op_const(s, OPC_I64_CONST, cur_block_idx + 1); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, BLOCK_IDX); + tcg_wasm_out_new_block(s); + /* call the target helper */ tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(TCG_AREG0)); tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(addr_reg)); @@ -1212,6 +1243,7 @@ static void tcg_wasm_out_qemu_ld(TCGContext *s, TCGRe= g data_reg, =20 tcg_wasm_out_op_idx(s, OPC_CALL, func_idx); tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(data_reg)); + tcg_wasm_out_handle_unwinding(s); } =20 static void *qemu_st_helper_ptr(uint32_t oi) @@ -1245,6 +1277,14 @@ static void tcg_wasm_out_qemu_st(TCGContext *s, TCGR= eg data_reg, gen_func_type_qemu_st(s, oi); } =20 + /* + * update the block index so that the possible rewinding will + * skip this block + */ + tcg_wasm_out_op_const(s, OPC_I64_CONST, cur_block_idx + 1); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, BLOCK_IDX); + tcg_wasm_out_new_block(s); + /* call the target helper */ tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(TCG_AREG0)); tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(addr_reg)); @@ -1261,6 +1301,7 @@ static void tcg_wasm_out_qemu_st(TCGContext *s, TCGRe= g data_reg, tcg_wasm_out_op_const(s, OPC_I64_CONST, (intptr_t)s->code_ptr); =20 tcg_wasm_out_op_idx(s, OPC_CALL, func_idx); + tcg_wasm_out_handle_unwinding(s); } =20 static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) @@ -2274,6 +2315,9 @@ static const uint8_t mod_1[] =3D { 0x60, /* 0: Type of "start" function */ 0x01, PTR_TYPE, /* arg: ctx pointer */ 0x01, PTR_TYPE, /* return: res */ + 0x60, /* 1: Type of the asyncify helper */ + 0x0, /* no argument */ + 0x01, 0x7f, /* return: res (i32) */ }; =20 #define MOD_1_PH_TYPE_SECTION_SIZE_OFF 9 @@ -2299,6 +2343,9 @@ static const uint8_t mod_2[] =3D { 0x02, 0x07, /* shared mem(64bit) */ 0x00, 0x80, 0x80, 0x10, /* min: 0, max: 262144 pages= */ #endif + 0x06, 0x68, 0x65, 0x6c, 0x70, 0x65, 0x72, /* module: "helper" */ + 0x01, 0x75, /* name: "u" */ + 0x00, 0x01, /* func type 1 */ }; =20 #define MOD_2_PH_IMPORT_SECTION_SIZE_OFF 1 @@ -2437,8 +2484,17 @@ static void tcg_out_tb_start(TCGContext *s) tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(TCG_REG_CALL_STACK)); tcg_wasm_out_op(s, OPC_END); =20 + ofs =3D tcg_wasm_out_get_ctx(s, CTX_OFFSET(do_init)); + tcg_wasm_out_op_ldst(s, OPC_I32_LOAD, 0, ofs); + tcg_wasm_out_op_const(s, OPC_I32_CONST, 0); + tcg_wasm_out_op(s, OPC_I32_NE); + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_NORET); tcg_wasm_out_op_const(s, OPC_I64_CONST, 0); tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, BLOCK_IDX); + ofs =3D tcg_wasm_out_get_ctx(s, CTX_OFFSET(do_init)); + tcg_wasm_out_op_const(s, OPC_I32_CONST, 0); + tcg_wasm_out_op_ldst(s, OPC_I32_STORE, 0, ofs); + tcg_wasm_out_op(s, OPC_END); =20 tcg_wasm_out_op_block(s, OPC_LOOP, BLOCK_NORET); tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, BLOCK_IDX); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.05.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:06:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411164; x=1770015964; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kRijlfK2AhaCQITdyGLgCjetEZy1TZO2LBKInu/R++E=; b=hEpFiElAcXQFDBLTk5FdNTplszmgD/mqQysy3M45wJFgAz+acYGRrZHq4Bh4+BS+5m 3wsaH1dPLScgCnUme7Y5cwCbBmmIm0HyYunb+4493L1iS76G4zvvySWc1QKPXHIyCbxh fU9/KdjAfA4gr0LM21mKHCYrn/23FUr5nCDjMfpU5/eYKOmiqgwjAFgEJznaoWz1CZsJ Z0x3HLth0C5VBo4sACBdT0c/JXpdl7kVLz8xaK1ek786tDT1dZvjiwr0brpx9ygtrSss Y2iiWjto4QDrQHfRWAjjVssMGjk+H8yUaN5gQ0X4rZxyiDzqgj6yDb5lIQ36bl/JAavA LmDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411164; x=1770015964; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=kRijlfK2AhaCQITdyGLgCjetEZy1TZO2LBKInu/R++E=; b=FGaW0whcPOT6zLz/r+ylpZ6t4oHQpB7SzupRhFL4+DXD2J2ObFiY8Ne/Bgq+l9PriX A3ig4P2w1WB/xQzvoWtGNmBUGc5YYyPeOC6cHpskElSFPkrFw9L5OkbAKWm9vOsdqwMh yCSlEuiBq0ZdTJa45mAR1NsQEhN0H5o5kEHKkPEXWB0FOHm+Ta2GpTaUc15OAstMaTR9 LztD8UCXj+Di+3w41DmVtrxvP4MwxUCf78sJo6ZlDBdIt/j7EaVajyBOzyulfBlSXZw4 dXvgPwBkTerxRMkeT4dJieA8PMjsTvC7TJc5TyOfWkETAEkjpIzkGlhTUWbR+/26yHGh EODA== X-Gm-Message-State: AOJu0YzMZ4G33N2TcmTTpYOT2yfRIb1wNcnQAqJwhL7hZ+ShATDDADmo Yt1hy2zM7ytoO7vA+3ysnzpsA/14pmN4BEU5gBIvP0Mu4KbglyeoV7Epec85iedqfHI= X-Gm-Gg: AZuq6aKvelkNHecAXMy0JhER8FpEewy7/BgFsacKBDmBRwrYonoMHzS4wpDHKgczVlr LDqQZpX8NtQGa6jFS2R7iO3bTAATxU1OI8ioSOxZSbLJOXcafAtJhM85jYqBEOoO6SutVMGB8Rb ZL7vmPKonFjOTO49uQG7hASn7qWGt6dcuhqmblEhVKxo3rswMuj0N5a8iUTL1jX+0BE3CpTeVtY +FO+MOhhLP1NrFZaJG0V/2mY5MEQWi4aoxsbklKKBcOkh0GFZqFqYlggzWJ23h0hYqFE1MWBh+I JnlqAglYJWVH/E/sB8evGoYZgzpSne7YJKCiEMjDlYVWDsdr09fGpVXaP+33qoDZrT3k3irh9QC gne1+lKulG1mMwBX4QZ7o8vInAoJFXhu3QdKio2TFcQ+jYIpN1yecw0PZBpzDLqLjrd6GaB6qIF Y7y4heuyEOtNqugpZJDoVm4Vb7fVL4VnOwg7yY8/QVLw== X-Received: by 2002:a05:6a00:808d:b0:81f:9f14:ecc8 with SMTP id d2e1a72fcca58-823412491b8mr2793425b3a.27.1769411164172; Sun, 25 Jan 2026 23:06:04 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 26/33] tcg/wasm64: Enable instantiation of TBs executed many times Date: Mon, 26 Jan 2026 07:03:39 +0000 Message-ID: <69e8725f30a790dd000be9deaf97e222f392a157.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x441.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412361484154100 Content-Type: text/plain; charset="utf-8" This commit enables the instantiation and execution of TBs in wasm64.c. As in TCI, the tcg_qemu_tb_exec function serves as the entrypoint for the TB execution, handling both instantiation and invocation of the Wasm module. Since browsers cause out of memory error if too many Wasm instances are created, this commit restricts instantiation to TBs that are called many times. This commit adds a counter (or its array if there are multiple threads) to the TB. Each time a TB is executed on TCI, the counter on TB is incremented. If it reaches to a threshold, that TB is instantiated as Wasm via instantiate_wasm. The total number of instances are tracked by the instances_global variable and its maximum number is limited by MAX_INSTANCES. When a Wasm module is instantiated, instances_global is incremented and the instance's function pointer is recorded to an array of WasmInstanceInfo. Each TB refers to the WasmInstanceInfo entry via WasmTBHeader's info_ptr (or its array if there are multiple threads). This allows tcg_qemu_tb_exec to resolve the instance's function pointer from the TB. When a new instantiation would exceed the limit, the Wasm backend doesn't perform instantiation (i.e. TB continues execution on TCI). Instead, it triggers the removal of older Wasm instances using Emscripten's removeFunction function. Once the removal is completed and detected via FinalizationRegistry API[1], instances_global is decremented, allowing new modules to be instantiated. [1] https://developer.mozilla.org/en-US/docs/Web/JavaScript/Reference/Globa= l_Objects/FinalizationRegistry Signed-off-by: Kohei Tokunaga --- tcg/wasm64.c | 244 +++++++++++++++++++++++++++++++++++- tcg/wasm64.h | 45 +++++++ tcg/wasm64/tcg-target.c.inc | 21 ++++ 3 files changed, 307 insertions(+), 3 deletions(-) diff --git a/tcg/wasm64.c b/tcg/wasm64.c index 7ae976d9eb..b947be3aa9 100644 --- a/tcg/wasm64.c +++ b/tcg/wasm64.c @@ -24,6 +24,10 @@ #include "tcg/helper-info.h" #include #include +#include "wasm64.h" + +/* TBs executed more than this value will be compiled to wasm */ +#define INSTANTIATE_NUM 1500 =20 #define EM_JS_PRE(ret, name, args, body...) EM_JS(ret, name, args, body) =20 @@ -60,6 +64,8 @@ EM_JS_PRE(void*, instantiate_wasm, (void *wasm_begin, "helper" : helper, }); =20 + Module.__wasm_tb.inst_gc_registry.register(inst, "tbinstance"); + return ENC_PTR(addFunction(inst.exports.start, 'ii')); }); =20 @@ -287,9 +293,53 @@ static void tci_qemu_st(CPUArchState *env, uint64_t ta= ddr, uint64_t val, } } =20 -static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *env, const void *v_tb_= ptr) +static __thread int thread_idx; + +static inline int32_t get_counter_local(void *tb_ptr) +{ + return get_counter(tb_ptr, thread_idx); +} + +static inline void set_counter_local(void *tb_ptr, int v) +{ + set_counter(tb_ptr, thread_idx, v); +} + +static inline struct WasmInstanceInfo *get_info_local(void *tb_ptr) +{ + return get_info(tb_ptr, thread_idx); +} + +static inline void set_info_local(void *tb_ptr, struct WasmInstanceInfo *i= nfo) +{ + set_info(tb_ptr, thread_idx, info); +} + +/* + * inc_counter increments the execution counter in the specified TB. + * If the counter reaches the limit, it returns true otherwise returns fal= se. + */ +static inline bool inc_counter(void *tb_ptr) { - const uint32_t *tb_ptr =3D v_tb_ptr; + int32_t counter =3D get_counter_local(tb_ptr); + if ((counter >=3D 0) && (counter < INSTANTIATE_NUM)) { + set_counter_local(tb_ptr, counter + 1); + } else { + return true; /* enter to wasm TB */ + } + return false; +} + +static __thread struct WasmContext ctx =3D { + .tb_ptr =3D 0, + .stack =3D NULL, + .do_init =3D 1, + .buf128 =3D NULL, +}; + +static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *env) +{ + uint32_t *tb_ptr =3D get_tci_ptr(ctx.tb_ptr); tcg_target_ulong regs[TCG_TARGET_NB_REGS]; uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) / sizeof(uint64_t)]; @@ -578,18 +628,32 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *e= nv, const void *v_tb_ptr) break; case INDEX_op_exit_tb: tci_args_l(insn, tb_ptr, &ptr); + ctx.tb_ptr =3D 0; return (uintptr_t)ptr; case INDEX_op_goto_tb: tci_args_l(insn, tb_ptr, &ptr); - tb_ptr =3D *(void **)ptr; + if (tb_ptr !=3D *(void **)ptr) { + tb_ptr =3D *(void **)ptr; + ctx.tb_ptr =3D tb_ptr; + if (inc_counter(tb_ptr)) { + return 0; /* enter to wasm TB */ + } + tb_ptr =3D get_tci_ptr(tb_ptr); + } break; case INDEX_op_goto_ptr: tci_args_r(insn, &r0); ptr =3D (void *)regs[r0]; if (!ptr) { + ctx.tb_ptr =3D 0; return 0; } tb_ptr =3D ptr; + ctx.tb_ptr =3D tb_ptr; + if (inc_counter(tb_ptr)) { + return 0; /* enter to wasm TB */ + } + tb_ptr =3D get_tci_ptr(tb_ptr); break; case INDEX_op_qemu_ld: tci_args_rrm(insn, &r0, &r1, &oi); @@ -621,3 +685,177 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *e= nv, const void *v_tb_ptr) } } } + +/* + * The maximum number of instances that can exist simultaneously + * + * If this limit is reached and a new instance is required, older instance= s are + * removed to allow creation of new ones without exceeding the browser's l= imit. + */ +#define MAX_INSTANCES 12000 + +static int instances_global; + +/* Avoid overwrapping of begin/end pointers */ +#define INSTANCES_BUF_MAX (MAX_INSTANCES + 1) + +static __thread struct WasmInstanceInfo instances[INSTANCES_BUF_MAX]; +static __thread int instances_begin; +static __thread int instances_end; + +static void add_instance(wasm_tb_func tb_func, void *tb_ptr) +{ + instances[instances_end].tb_func =3D tb_func; + instances[instances_end].tb_ptr =3D tb_ptr; + set_info_local(tb_ptr, &(instances[instances_end])); + instances_end =3D (instances_end + 1) % INSTANCES_BUF_MAX; + + qatomic_inc(&instances_global); +} + +static __thread int instance_pending_gc; +static __thread int instance_done_gc; + +static void remove_old_instances(void) +{ + int num; + if (instance_pending_gc > 0) { + return; + } + if (instances_begin <=3D instances_end) { + num =3D instances_end - instances_begin; + } else { + num =3D instances_end + (INSTANCES_BUF_MAX - instances_begin); + } + /* removes the half of the oldest instances in the buffer */ + num /=3D 2; + for (int i =3D 0; i < num; i++) { + EM_ASM({ removeFunction($0); }, instances[instances_begin].tb_func= ); + instances[instances_begin].tb_ptr =3D NULL; + instances_begin =3D (instances_begin + 1) % INSTANCES_BUF_MAX; + } + instance_pending_gc +=3D num; +} + +static bool can_add_instance(void) +{ + return qatomic_read(&instances_global) < MAX_INSTANCES; +} + +static wasm_tb_func get_instance_from_tb(void *tb_ptr) +{ + struct WasmInstanceInfo *elm =3D get_info_local(tb_ptr); + if (elm =3D=3D NULL) { + return NULL; + } + if (elm->tb_ptr !=3D tb_ptr) { + /* + * This TB was instantiated before, but has been removed. Set coun= ter to + * the max value so that this will be instantiated. + */ + set_counter_local(tb_ptr, INSTANTIATE_NUM); + set_info_local(tb_ptr, NULL); + return NULL; + } + return elm->tb_func; +} + +static void check_gc_completion(void) +{ + if (instance_done_gc > 0) { + qatomic_sub(&instances_global, instance_done_gc); + instance_pending_gc -=3D instance_done_gc; + instance_done_gc =3D 0; + } +} + +EM_JS_PRE(void, init_wasm_js, (void *instance_done_gc), +{ + Module.__wasm_tb =3D { + inst_gc_registry: new FinalizationRegistry((i) =3D> { + if (i =3D=3D "tbinstance") { + const memory_v =3D new DataView(HEAP8.buffer); + let v =3D memory_v.getInt32(DEC_PTR(instance_done_gc), tru= e); + memory_v.setInt32(DEC_PTR(instance_done_gc), v + 1, true); + } + }) + }; +}); + +#define MAX_EXEC_NUM 50000 +static __thread int exec_cnt =3D MAX_EXEC_NUM; +static inline void trysleep(void) +{ + /* + * Even during running TBs continuously, try to return the control + * to the browser periodically and allow browsers doing tasks. + */ + if (--exec_cnt =3D=3D 0) { + if (!can_add_instance()) { + emscripten_sleep(0); + check_gc_completion(); + } + exec_cnt =3D MAX_EXEC_NUM; + } +} + +static int thread_idx_max; + +static void init_wasm(void) +{ + thread_idx =3D qatomic_fetch_inc(&thread_idx_max); + ctx.stack =3D g_malloc(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SI= ZE); + ctx.buf128 =3D g_malloc(16); + ctx.tci_tb_ptr =3D (uint32_t *)&tci_tb_ptr; + init_wasm_js(&instance_done_gc); +} + +static __thread bool initdone; + +uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *v_tb_ptr) +{ + if (!initdone) { + init_wasm(); + initdone =3D true; + } + ctx.env =3D env; + ctx.tb_ptr =3D (void *)v_tb_ptr; + while (true) { + trysleep(); + uintptr_t res; + wasm_tb_func tb_func =3D get_instance_from_tb(ctx.tb_ptr); + if (tb_func) { + /* + * Call the Wasm instance + */ + res =3D call_wasm_tb(tb_func, &ctx); + } else if (!inc_counter(ctx.tb_ptr)) { + /* + * Run it on TCI because the counter value is small + */ + res =3D tcg_qemu_tb_exec_tci(env); + } else if (!can_add_instance()) { + /* + * Too many instances has been created, try removing older + * instances and keep running this TB on TCI + */ + remove_old_instances(); + check_gc_completion(); + res =3D tcg_qemu_tb_exec_tci(env); + } else { + /* + * Instantiate and run the Wasm module + */ + struct WasmTBHeader *header =3D (struct WasmTBHeader *)ctx.tb_= ptr; + tb_func =3D (wasm_tb_func)instantiate_wasm(header->wasm_ptr, + header->wasm_size, + header->import_ptr, + header->import_size); + add_instance(tb_func, ctx.tb_ptr); + res =3D call_wasm_tb(tb_func, &ctx); + } + if (!ctx.tb_ptr) { + return res; + } + } +} diff --git a/tcg/wasm64.h b/tcg/wasm64.h index fdde908557..88163c28df 100644 --- a/tcg/wasm64.h +++ b/tcg/wasm64.h @@ -46,6 +46,14 @@ static inline uintptr_t call_wasm_tb(wasm_tb_func f, str= uct WasmContext *ctx) return f(ctx); } =20 +/* + * WasmInstanceInfo holds the relationship between TB and Wasm instance. + */ +struct WasmInstanceInfo { + void *tb_ptr; + wasm_tb_func tb_func; +}; + /* * A TB of the Wasm backend starts from a header which contains pointers f= or * each data stored in the following region in the TB. @@ -67,6 +75,43 @@ struct WasmTBHeader { */ void *import_ptr; int import_size; + + /* + * Counter holds how many times the TB is executed before the instanti= ation + * for each thread. + */ + int32_t *counter_ptr; + + /* + * Pointer to the instance information on each thread. + */ + struct WasmInstanceInfo **info_ptr; }; =20 +static inline void *get_tci_ptr(void *tb_ptr) +{ + return ((struct WasmTBHeader *)tb_ptr)->tci_ptr; +} + +static inline int32_t get_counter(void *tb_ptr, int idx) +{ + return ((struct WasmTBHeader *)tb_ptr)->counter_ptr[idx]; +} + +static inline void set_counter(void *tb_ptr, int idx, int v) +{ + ((struct WasmTBHeader *)tb_ptr)->counter_ptr[idx] =3D v; +} + +static inline struct WasmInstanceInfo *get_info(void *tb_ptr, int idx) +{ + return ((struct WasmTBHeader *)tb_ptr)->info_ptr[idx]; +} + +static inline void set_info(void *tb_ptr, int idx, + struct WasmInstanceInfo *info) +{ + ((struct WasmTBHeader *)tb_ptr)->info_ptr[idx] =3D info; +} + #endif diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index ad9e5a43b5..8e62f6a237 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -28,6 +28,9 @@ #include "qemu/queue.h" #include "../wasm64.h" =20 +/* This is included to get the number of threads via tcg_max_ctxs. */ +#include "../tcg-internal.h" + /* Used for function call generation. */ #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_STACK_ALIGN 8 @@ -2305,6 +2308,11 @@ static void tcg_out_set_carry(TCGContext *s) g_assert_not_reached(); } =20 +/* Generate global QEMU prologue and epilogue code. */ +static inline void tcg_target_qemu_prologue(TCGContext *s) +{ +} + static const uint8_t mod_1[] =3D { 0x0, 0x61, 0x73, 0x6d, /* magic */ 0x01, 0x0, 0x0, 0x0, /* version */ @@ -2453,6 +2461,7 @@ static int write_mod_code(TCGContext *s) =20 static void tcg_out_tb_start(TCGContext *s) { + int size; intptr_t ofs; struct WasmTBHeader *h; =20 @@ -2467,6 +2476,18 @@ static void tcg_out_tb_start(TCGContext *s) h =3D (struct WasmTBHeader *)(s->code_ptr); s->code_ptr +=3D sizeof(struct WasmTBHeader); =20 + /* locate counters */ + h->counter_ptr =3D (int32_t *)s->code_ptr; + size =3D tcg_max_ctxs * sizeof(int32_t); + memset(s->code_ptr, 0, size); + s->code_ptr +=3D size; + + /* locate the instance information */ + h->info_ptr =3D (struct WasmInstanceInfo **)s->code_ptr; + size =3D tcg_max_ctxs * sizeof(void *); + memset(s->code_ptr, 0, size); + s->code_ptr +=3D size; + /* Followed by TCI code */ h->tci_ptr =3D s->code_ptr; =20 --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Unlike other backends, the Wasm backend cannot use ldst labels, as jumping to specific code addresses (e.g. raddr) is not possible in Wasm. Instead, each TLB lookup is followed by a if branch: if the lookup succeeds, the memory is accessed directly; otherwise, a fallback helper function is invoked. Support for MO_BSWAP is not yet implemented, so has_memory_bswap is set to false. Signed-off-by: Kohei Tokunaga --- tcg/wasm64/tcg-target.c.inc | 225 +++++++++++++++++++++++++++++++++++- 1 file changed, 222 insertions(+), 3 deletions(-) diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index 8e62f6a237..7c414a8a36 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -3,8 +3,12 @@ * Tiny Code Generator for QEMU * * Copyright (c) 2009, 2011 Stefan Weil + * Copyright (c) 2018 SiFive, Inc + * Copyright (c) 2008-2009 Arnaud Patard + * Copyright (c) 2009 Aurelien Jarno + * Copyright (c) 2008 Fabrice Bellard * - * Based on tci/tcg-target.c.inc + * Based on tci/tcg-target.c.inc and riscv/tcg-target.c.inc * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -154,6 +158,11 @@ static const uint8_t tcg_target_reg_index[TCG_TARGET_N= B_REGS] =3D { /* Local variable pointing to WasmContext */ #define CTX_IDX 0 =20 +/* Temporary local variables */ +#define TMP32_LOCAL_0_IDX 1 +#define TMP64_LOCAL_0_IDX 2 +#define TMP64_LOCAL_1_IDX 3 + /* Function index */ #define CHECK_UNWINDING_IDX 0 /* A function to check the Asyncify status */ #define HELPER_IDX_START 1 /* The first index of helper functions */ @@ -170,6 +179,8 @@ typedef enum { OPC_RETURN =3D 0x0f, OPC_CALL =3D 0x10, OPC_LOCAL_GET =3D 0x20, + OPC_LOCAL_SET =3D 0x21, + OPC_LOCAL_TEE =3D 0x22, OPC_GLOBAL_GET =3D 0x23, OPC_GLOBAL_SET =3D 0x24, =20 @@ -1217,11 +1228,156 @@ static void *qemu_ld_helper_ptr(uint32_t oi) } } =20 +#define MIN_TLB_MASK_TABLE_OFS INT_MIN + +static uint8_t prepare_host_addr_wasm(TCGContext *s, uint8_t *hit_var, + TCGReg addr_reg, MemOpIdx oi, + bool is_ld) +{ + MemOp opc =3D get_memop(oi); + TCGAtomAlign aa; + unsigned a_mask; + unsigned s_bits =3D opc & MO_SIZE; + unsigned s_mask =3D (1u << s_bits) - 1; + int mem_index =3D get_mmuidx(oi); + int fast_ofs =3D tlb_mask_table_ofs(s, mem_index); + int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); + int add_off =3D offsetof(CPUTLBEntry, addend); + tcg_target_long compare_mask; + int offset; + + uint8_t tmp1 =3D TMP64_LOCAL_0_IDX; + uint8_t tmp2 =3D TMP64_LOCAL_1_IDX; + + if (!tcg_use_softmmu) { + g_assert_not_reached(); + } + + *hit_var =3D TMP32_LOCAL_0_IDX; + tcg_wasm_out_op_const(s, OPC_I32_CONST, 0); + tcg_wasm_out_op_idx(s, OPC_LOCAL_SET, *hit_var); + + aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); + a_mask =3D (1u << aa.align) - 1; + + /* Get the CPUTLBEntry offset */ + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(addr_reg)); + tcg_wasm_out_op_const(s, OPC_I64_CONST, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_wasm_out_op(s, OPC_I64_SHR_U); + + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(TCG_AREG0)); + offset =3D tcg_wasm_out_norm_ptr(s, mask_ofs); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, offset); + tcg_wasm_out_op(s, OPC_I64_AND); + + /* Get the pointer to the target CPUTLBEntry */ + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(TCG_AREG0)); + offset =3D tcg_wasm_out_norm_ptr(s, table_ofs); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, offset); + tcg_wasm_out_op(s, OPC_I64_ADD); + tcg_wasm_out_op_idx(s, OPC_LOCAL_TEE, tmp1); + + /* Load the tlb copmarator */ + offset =3D tcg_wasm_out_norm_ptr(s, is_ld ? offsetof(CPUTLBEntry, addr= _read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, offset); + + /* + * For aligned accesses, we check the first byte and include the + * alignment bits within the address. For unaligned access, we + * check that we don't cross pages using the address of the last + * byte of the access. + */ + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(addr_reg)); + if (a_mask < s_mask) { + tcg_wasm_out_op_const(s, OPC_I64_CONST, s_mask - a_mask); + tcg_wasm_out_op(s, OPC_I64_ADD); + } + compare_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; + tcg_wasm_out_op_const(s, OPC_I64_CONST, compare_mask); + tcg_wasm_out_op(s, OPC_I64_AND); + + /* Compare masked address with the TLB entry. */ + tcg_wasm_out_op(s, OPC_I64_EQ); + + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_NORET); + + /* TLB Hit - translate address using addend. */ + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, tmp1); + offset =3D tcg_wasm_out_norm_ptr(s, add_off); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, offset); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(addr_reg)); + tcg_wasm_out_op(s, OPC_I64_ADD); + tcg_wasm_out_op_idx(s, OPC_LOCAL_SET, tmp2); + tcg_wasm_out_op_const(s, OPC_I32_CONST, 1); + tcg_wasm_out_op_idx(s, OPC_LOCAL_SET, *hit_var); + + tcg_wasm_out_op(s, OPC_END); + + return tmp2; +} + +static void tcg_wasm_out_qemu_ld_direct( + TCGContext *s, TCGReg r, uint8_t base, MemOp opc) +{ + intptr_t ofs; + switch (opc & (MO_SSIZE)) { + case MO_UB: + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, base); + ofs =3D tcg_wasm_out_norm_ptr(s, 0); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD8_U, 0, ofs); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(r)); + break; + case MO_SB: + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, base); + ofs =3D tcg_wasm_out_norm_ptr(s, 0); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD8_S, 0, ofs); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(r)); + break; + case MO_UW: + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, base); + ofs =3D tcg_wasm_out_norm_ptr(s, 0); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD16_U, 0, ofs); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(r)); + break; + case MO_SW: + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, base); + ofs =3D tcg_wasm_out_norm_ptr(s, 0); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD16_S, 0, ofs); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(r)); + break; + case MO_UL: + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, base); + ofs =3D tcg_wasm_out_norm_ptr(s, 0); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD32_U, 0, ofs); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(r)); + break; + case MO_SL: + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, base); + ofs =3D tcg_wasm_out_norm_ptr(s, 0); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD32_S, 0, ofs); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(r)); + break; + case MO_UQ: + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, base); + ofs =3D tcg_wasm_out_norm_ptr(s, 0); + tcg_wasm_out_op_ldst(s, OPC_I64_LOAD, 0, ofs); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(r)); + break; + default: + g_assert_not_reached(); + } +} + static void tcg_wasm_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, MemOpIdx oi) { intptr_t helper_idx; int64_t func_idx; + MemOp mop =3D get_memop(oi); + uint8_t base_var, hit_var; =20 helper_idx =3D (intptr_t)qemu_ld_helper_ptr(oi); func_idx =3D get_helper_idx(s, helper_idx); @@ -1230,6 +1386,14 @@ static void tcg_wasm_out_qemu_ld(TCGContext *s, TCGR= eg data_reg, gen_func_type_qemu_ld(s, oi); } =20 + base_var =3D prepare_host_addr_wasm(s, &hit_var, addr_reg, oi, true); + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, hit_var); + tcg_wasm_out_op_const(s, OPC_I32_CONST, 1); + tcg_wasm_out_op(s, OPC_I32_EQ); + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_NORET); + tcg_wasm_out_qemu_ld_direct(s, data_reg, base_var, mop); /* fast path = */ + tcg_wasm_out_op(s, OPC_END); + /* * update the block index so that the possible rewinding will * skip this block @@ -1238,6 +1402,10 @@ static void tcg_wasm_out_qemu_ld(TCGContext *s, TCGR= eg data_reg, tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, BLOCK_IDX); tcg_wasm_out_new_block(s); =20 + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, hit_var); + tcg_wasm_out_op(s, OPC_I32_EQZ); + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_NORET); + /* call the target helper */ tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(TCG_AREG0)); tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(addr_reg)); @@ -1247,6 +1415,8 @@ static void tcg_wasm_out_qemu_ld(TCGContext *s, TCGRe= g data_reg, tcg_wasm_out_op_idx(s, OPC_CALL, func_idx); tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(data_reg)); tcg_wasm_out_handle_unwinding(s); + + tcg_wasm_out_op(s, OPC_END); } =20 static void *qemu_st_helper_ptr(uint32_t oi) @@ -1266,12 +1436,47 @@ static void *qemu_st_helper_ptr(uint32_t oi) } } =20 +static void tcg_wasm_out_qemu_st_direct( + TCGContext *s, TCGReg lo, uint8_t base, MemOp opc) +{ + intptr_t ofs; + switch (opc & (MO_SSIZE)) { + case MO_8: + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, base); + ofs =3D tcg_wasm_out_norm_ptr(s, 0); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(lo)); + tcg_wasm_out_op_ldst(s, OPC_I64_STORE8, 0, ofs); + break; + case MO_16: + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, base); + ofs =3D tcg_wasm_out_norm_ptr(s, 0); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(lo)); + tcg_wasm_out_op_ldst(s, OPC_I64_STORE16, 0, ofs); + break; + case MO_32: + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, base); + ofs =3D tcg_wasm_out_norm_ptr(s, 0); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(lo)); + tcg_wasm_out_op_ldst(s, OPC_I64_STORE32, 0, ofs); + break; + case MO_64: + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, base); + ofs =3D tcg_wasm_out_norm_ptr(s, 0); + tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(lo)); + tcg_wasm_out_op_ldst(s, OPC_I64_STORE, 0, ofs); + break; + default: + g_assert_not_reached(); + } +} + static void tcg_wasm_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, MemOpIdx oi) { intptr_t helper_idx; int64_t func_idx; MemOp mop =3D get_memop(oi); + uint8_t base_var, hit_var; =20 helper_idx =3D (intptr_t)qemu_st_helper_ptr(oi); func_idx =3D get_helper_idx(s, helper_idx); @@ -1280,6 +1485,14 @@ static void tcg_wasm_out_qemu_st(TCGContext *s, TCGR= eg data_reg, gen_func_type_qemu_st(s, oi); } =20 + base_var =3D prepare_host_addr_wasm(s, &hit_var, addr_reg, oi, false); + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, hit_var); + tcg_wasm_out_op_const(s, OPC_I32_CONST, 1); + tcg_wasm_out_op(s, OPC_I32_EQ); + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_NORET); + tcg_wasm_out_qemu_st_direct(s, data_reg, base_var, mop); /* fast path = */ + tcg_wasm_out_op(s, OPC_END); + /* * update the block index so that the possible rewinding will * skip this block @@ -1288,6 +1501,10 @@ static void tcg_wasm_out_qemu_st(TCGContext *s, TCGR= eg data_reg, tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, BLOCK_IDX); tcg_wasm_out_new_block(s); =20 + tcg_wasm_out_op_idx(s, OPC_LOCAL_GET, hit_var); + tcg_wasm_out_op(s, OPC_I32_EQZ); + tcg_wasm_out_op_block(s, OPC_IF, BLOCK_NORET); + /* call the target helper */ tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(TCG_AREG0)); tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(addr_reg)); @@ -1305,6 +1522,8 @@ static void tcg_wasm_out_qemu_st(TCGContext *s, TCGRe= g data_reg, =20 tcg_wasm_out_op_idx(s, OPC_CALL, func_idx); tcg_wasm_out_handle_unwinding(s); + + tcg_wasm_out_op(s, OPC_END); } =20 static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) @@ -2162,7 +2381,7 @@ static const TCGOutOpQemuLdSt outop_qemu_st =3D { =20 bool tcg_target_has_memory_bswap(MemOp memop) { - return true; + return false; } =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) @@ -2394,7 +2613,7 @@ static const uint8_t mod_3[] =3D { 0x80, 0x80, 0x80, 0x80, 0x00, /* placeholder for section size*/ 1, /* num of codes */ 0x80, 0x80, 0x80, 0x80, 0x00, /* placeholder for code size */ - 0x0, /* local variables (none) */ + 0x2, 0x1, 0x7f, 0x2, 0x7e, /* local variables (32bit*1, 64bit*2) */ }; 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Signed-off-by: Kohei Tokunaga --- tcg/wasm64/tcg-target.c.inc | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc index 7c414a8a36..797ebf3f88 100644 --- a/tcg/wasm64/tcg-target.c.inc +++ b/tcg/wasm64/tcg-target.c.inc @@ -2822,3 +2822,32 @@ static int tcg_out_tb_end(TCGContext *s) =20 return 0; } + +static void tcg_target_init(TCGContext *s) +{ + /* The current code uses uint8_t for tcg operations. */ + tcg_debug_assert(tcg_op_defs_max <=3D UINT8_MAX); + + /* Registers available for 32 bit operations. */ + tcg_target_available_regs[TCG_TYPE_I32] =3D BIT(TCG_TARGET_NB_REGS) - = 1; + /* Registers available for 64 bit operations. */ + tcg_target_available_regs[TCG_TYPE_I64] =3D BIT(TCG_TARGET_NB_REGS) - = 1; + /* + * The TCI "registers" are in the local stack frame and + * cannot be clobbered by the called helper functions. Additionally, W= asm + * modules for a TB and QEMU itself (i.e. helpers) are separated so al= so + * those variables aren't clobbered by the called helper functions. + * However, the TB assumes a 128-bit return value and assigns to + * the return value registers. + */ + tcg_target_call_clobber_regs =3D + MAKE_64BIT_MASK(TCG_REG_R0, 128 / TCG_TARGET_REG_BITS); + + s->reserved_regs =3D 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); + + /* The call arguments come first, followed by the temp storage. */ + tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, + TCG_STATIC_FRAME_SIZE); +} --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412052; cv=none; d=zohomail.com; s=zohoarc; b=DtRuqD10Hgt385BWp9ED6ZwEfLexvuBnDIZbaxoOE5G6ew3BxGNsB79TZunMVTflPRQwFbzsC3wdto0KUu9yLOwcVcFoPVff+x8THrMX9Xqf3WTAw1DT5nKtan23JyvRnlYCgkTDO4R8qUOi2MC7a2FfiCYlmP0awqeX8QVf7QM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769412052; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RU7WmALXZc85DAN4jRhE1kjsBrYxH2shv0NiJQVureY=; b=eAacp8GQ5HTSwvnbtlDwYX+/GzbX09lCCocalLgkbMoN9sxM1JkdStz9iaY4qzB2JJ5T/vmqyPpMg0sCxAphA0bVtOl/aflDQFYRMqTHxhPNVxQSc9Rk/QioIf6wnMf+QJnSFne9rjL1o2IV8F6GtIgXNR1ej7qO/GDTVQ5zvs0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176941205206252.88539202204947; Sun, 25 Jan 2026 23:20:52 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGtr-00063s-5p; Mon, 26 Jan 2026 02:20:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGgL-0003Ox-Dm for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:06:53 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGgA-0004hA-Tp for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:06:35 -0500 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-81f47610542so2101099b3a.0 for ; Sun, 25 Jan 2026 23:06:18 -0800 (PST) Received: from brahms.. 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.06.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:06:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411178; x=1770015978; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RU7WmALXZc85DAN4jRhE1kjsBrYxH2shv0NiJQVureY=; b=JJpOPm2tFff0KpKjv3r2nB0Cuq9JCohD1Y1Q7ufT7ZH+zQyrwkrb2ElBwroA+6afYb Qn3dqpRKjUrWxsxkL4sDQXKhFqGOIl7FLj/cqYUDcHsKnphvUJcB85lHjHDZPH8btXsH qnSImOZZCTKvTDoA6yHnr9sG7ky7wohBhpJ5q9G5HOeUXgpwulgjTrQhfZYCze8Ql5zp topc1OuU7TEH5gJ2MF7jt228HJQsKl1AHr22wuBH6gTRFOsUOl3EJJUEjaDlkbvYlbHk GULj1KZdiY5r0DCXQIcU5LgIwhdRxH3jKOc2zrUZ9Wnx3WT9rcXvOYyoDs21tcZqW7Qc BIhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411178; x=1770015978; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=RU7WmALXZc85DAN4jRhE1kjsBrYxH2shv0NiJQVureY=; b=cDy3RWIadqt6/ooWXDKHyoo46W3uKHBtoHxjPOkoxFwNqNLIy25GU0cnjYU0CP29Ry hzGZHAcZUBtZbZbljNvE0TGK1MVCjOt1v/7O6eDyR2T1UfMtfVgvHoXTK+m7qo3CR19+ IL4mjUJKLu6sUnhSjIZVIvPzGBeusDq5F6PNSPbJQxrhM+plDADwX62epR//BUtSZJPZ O/l6AWBFMYlEX2BpDZFL7PkNSIoEaHDgZMH6QmEdMzzQH78uxmSvq1Cpr410MgNTcshz PZzjRKwiz5yeTw/fI2tccftbMXJzbbxWp/W7ipv0yqDgMpMckhc1JxoUHGdcqm60Px9V E4tQ== X-Gm-Message-State: AOJu0YxQrZGWsOoV5CGOXSzTE+1sImctyYvF1uiCoLbnuVszvc2CqUjy PJL3WkEVbOofRI8bdGMfhpo/x837ONE7k+IxB/6WY2Nu6wx5iNbsg8ZPmXYTjJ1x X-Gm-Gg: AZuq6aL3j43wt5WSUh2yDzMmTrFNZVm1ttdX1GpUI8qmfsv5So5VFhDa4iVD+gruU/3 wUsEvztml+vTz7ZOlNfyKZr3LIIxNDwukkFVZ4fE+4AubXQupStGHlAhdDLgcD3bUNa5ehMq90Z Ep/7iaZ2jcrK4yMYRRNKErmvu3TKMITR7CmKez4qYk8B5tSOEmtI4s7HauCIrDPEB14//yORMJL Ai6MAVZfW4wY1nUJA5xPWlv3jvxqb9RZVOxgW2aCPu8SHKGrO9Vd4E/AZ9He9AmAkE5VECHJ/vs J+6pB8r8ivZekyFRWBZbn0XvleDupsPXJKVmWTuwPAOn7bgmZhz3zGDHjDd8r+EXF/QYsyJs9sQ iJK0mRkVCjviZrHlFOCiX95MdAl8IlDBUt3Mx1OfU5ksrKT+Dm/0LZXCGjYDMieXQfVQzz9Keoy QpHvZN5+PT83+pgxHuaMARBpvLC8slosGEP0Z1crDAeg== X-Received: by 2002:a05:6a00:2316:b0:81f:9aa4:1e70 with SMTP id d2e1a72fcca58-8234131dce2mr2974527b3a.70.1769411177763; Sun, 25 Jan 2026 23:06:17 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 29/33] meson.build: enable to build Wasm backend Date: Mon, 26 Jan 2026 07:03:42 +0000 Message-ID: <9b4d7d51d8a255277937142e2b731538e0371e19.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412053680158500 Content-Type: text/plain; charset="utf-8" Enable to use tcg/wasm64 as the TCG backend for the WebAssembly (wasm64) build. Signed-off-by: Kohei Tokunaga --- include/accel/tcg/getpc.h | 2 +- include/tcg/helper-info.h | 4 ++-- include/tcg/tcg.h | 2 +- meson.build | 4 ---- tcg/meson.build | 5 +++++ tcg/region.c | 10 +++++----- tcg/tcg.c | 14 +++++++------- 7 files changed, 21 insertions(+), 20 deletions(-) diff --git a/include/accel/tcg/getpc.h b/include/accel/tcg/getpc.h index 0fc08addcf..3901655715 100644 --- a/include/accel/tcg/getpc.h +++ b/include/accel/tcg/getpc.h @@ -9,7 +9,7 @@ #define ACCEL_TCG_GETPC_H =20 /* GETPC is the true target of the return instruction that we'll execute. = */ -#ifdef CONFIG_TCG_INTERPRETER +#if defined(CONFIG_TCG_INTERPRETER) || defined(EMSCRIPTEN) extern __thread uintptr_t tci_tb_ptr; # define GETPC() tci_tb_ptr #else diff --git a/include/tcg/helper-info.h b/include/tcg/helper-info.h index d5bda83a2e..a586b90470 100644 --- a/include/tcg/helper-info.h +++ b/include/tcg/helper-info.h @@ -9,7 +9,7 @@ #ifndef TCG_HELPER_INFO_H #define TCG_HELPER_INFO_H =20 -#ifdef CONFIG_TCG_INTERPRETER +#if defined(CONFIG_TCG_INTERPRETER) || defined(EMSCRIPTEN) /* * MacOSX 15 uses an old version of libffi which contains * #if FFI_GO_CLOSURES @@ -60,7 +60,7 @@ struct TCGHelperInfo { const char *name; =20 /* Used with g_once_init_enter. */ -#ifdef CONFIG_TCG_INTERPRETER +#if defined(CONFIG_TCG_INTERPRETER) || defined(EMSCRIPTEN) ffi_cif *cif; #else uintptr_t init; diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 60942ce05c..9937b997ac 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -940,7 +940,7 @@ static inline size_t tcg_current_code_size(TCGContext *= s) #define TB_EXIT_IDXMAX 1 #define TB_EXIT_REQUESTED 3 =20 -#ifdef CONFIG_TCG_INTERPRETER +#if defined(CONFIG_TCG_INTERPRETER) || defined(EMSCRIPTEN) uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); #else typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); diff --git a/meson.build b/meson.build index 7a81ff58be..82d9c94f4a 100644 --- a/meson.build +++ b/meson.build @@ -891,10 +891,6 @@ if have_tcg if not get_option('tcg_interpreter') error('Unsupported CPU @0@, try --enable-tcg-interpreter'.format(cpu= )) endif - elif host_arch =3D=3D 'wasm64' - if not get_option('tcg_interpreter') - error('WebAssembly host requires --enable-tcg-interpreter') - endif elif get_option('tcg_interpreter') warning('Use of the TCG interpreter is not recommended on this host') warning('architecture. There is a native TCG execution backend availab= le') diff --git a/tcg/meson.build b/tcg/meson.build index 706a6eb260..b67d857957 100644 --- a/tcg/meson.build +++ b/tcg/meson.build @@ -20,6 +20,11 @@ if get_option('tcg_interpreter') method: 'pkg-config') tcg_ss.add(libffi) tcg_ss.add(files('tci.c')) +elif host_os =3D=3D 'emscripten' + libffi =3D dependency('libffi', version: '>=3D3.0', required: true, + method: 'pkg-config') + specific_ss.add(libffi) + specific_ss.add(files('wasm64.c')) endif =20 tcg_ss.add(when: libdw, if_true: files('debuginfo.c')) diff --git a/tcg/region.c b/tcg/region.c index 5d4be1453b..6adf876d87 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -94,7 +94,7 @@ bool in_code_gen_buffer(const void *p) return (size_t)(p - region.start_aligned) <=3D region.total_size; } =20 -#ifndef CONFIG_TCG_INTERPRETER +#if !defined(CONFIG_TCG_INTERPRETER) && !defined(EMSCRIPTEN) static int host_prot_read_exec(void) { #if defined(CONFIG_LINUX) && defined(HOST_AARCH64) && defined(PROT_BTI) @@ -557,7 +557,7 @@ static int alloc_code_gen_buffer_anon(size_t size, int = prot, return prot; } =20 -#ifndef CONFIG_TCG_INTERPRETER +#if !defined(CONFIG_TCG_INTERPRETER) && !defined(EMSCRIPTEN) #ifdef CONFIG_POSIX #include "qemu/memfd.h" =20 @@ -655,11 +655,11 @@ static int alloc_code_gen_buffer_splitwx_vmremap(size= _t size, Error **errp) return PROT_READ | PROT_WRITE; } #endif /* CONFIG_DARWIN */ -#endif /* CONFIG_TCG_INTERPRETER */ +#endif /* !CONFIG_TCG_INTERPRETER && !EMSCRIPTEN */ =20 static int alloc_code_gen_buffer_splitwx(size_t size, Error **errp) { -#ifndef CONFIG_TCG_INTERPRETER +#if !defined(CONFIG_TCG_INTERPRETER) && !defined(EMSCRIPTEN) # ifdef CONFIG_DARWIN return alloc_code_gen_buffer_splitwx_vmremap(size, errp); # endif @@ -801,7 +801,7 @@ void tcg_region_init(size_t tb_size, int splitwx, unsig= ned max_threads) * Work with the page protections set up with the initial mapping. */ need_prot =3D PROT_READ | PROT_WRITE; -#ifndef CONFIG_TCG_INTERPRETER +#if !defined(CONFIG_TCG_INTERPRETER) && !defined(EMSCRIPTEN) if (tcg_splitwx_diff =3D=3D 0) { need_prot |=3D host_prot_read_exec(); } diff --git a/tcg/tcg.c b/tcg/tcg.c index 3c68699138..b5690c7c5b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -252,7 +252,7 @@ TCGv_env tcg_env; const void *tcg_code_gen_epilogue; uintptr_t tcg_splitwx_diff; =20 -#ifndef CONFIG_TCG_INTERPRETER +#if !defined(CONFIG_TCG_INTERPRETER) && !defined(EMSCRIPTEN) tcg_prologue_fn *tcg_qemu_tb_exec; #endif =20 @@ -1415,7 +1415,7 @@ static TCGHelperInfo info_helper_st128_mmu =3D { | dh_typemask(ptr, 5) /* uintptr_t ra */ }; =20 -#ifdef CONFIG_TCG_INTERPRETER +#if defined(CONFIG_TCG_INTERPRETER) || defined(EMSCRIPTEN) static ffi_type *typecode_to_ffi(int argmask) { /* @@ -1492,7 +1492,7 @@ static ffi_cif *init_ffi_layout(TCGHelperInfo *info) #else #define HELPER_INFO_INIT(I) (&(I)->init) #define HELPER_INFO_INIT_VAL(I) 1 -#endif /* CONFIG_TCG_INTERPRETER */ +#endif /* CONFIG_TCG_INTERPRETER || EMSCRIPTEN */ =20 static inline bool arg_slot_reg_p(unsigned arg_slot) { @@ -1860,7 +1860,7 @@ void tcg_prologue_init(void) s->code_buf =3D s->code_gen_ptr; s->data_gen_ptr =3D NULL; =20 -#ifndef CONFIG_TCG_INTERPRETER +#if !defined(CONFIG_TCG_INTERPRETER) && !defined(EMSCRIPTEN) tcg_qemu_tb_exec =3D (tcg_prologue_fn *)tcg_splitwx_to_rx(s->code_ptr); #endif =20 @@ -1879,7 +1879,7 @@ void tcg_prologue_init(void) prologue_size =3D tcg_current_code_size(s); perf_report_prologue(s->code_gen_ptr, prologue_size); =20 -#ifndef CONFIG_TCG_INTERPRETER +#if !defined(CONFIG_TCG_INTERPRETER) && !defined(EMSCRIPTEN) flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf), (uintptr_t)s->code_buf, prologue_size); #endif @@ -1916,7 +1916,7 @@ void tcg_prologue_init(void) } } =20 -#ifndef CONFIG_TCG_INTERPRETER +#if !defined(CONFIG_TCG_INTERPRETER) && !defined(EMSCRIPTEN) /* * Assert that goto_ptr is implemented completely, setting an epilogue. * For tci, we use NULL as the signal to return from the interpreter, @@ -6754,7 +6754,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) return i; } =20 -#ifndef CONFIG_TCG_INTERPRETER +#if !defined(CONFIG_TCG_INTERPRETER) && !defined(EMSCRIPTEN) /* flush instruction cache */ flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf), (uintptr_t)s->code_buf, --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:06:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411182; x=1770015982; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A2m1YYGNyq/Rz1FBTgbyAMMQAXZAUd22fOojccDF0Y8=; b=XYgj41gN2ZOhPFh/8Qs2BKn7z1Uwjg686Nf+pdM65cbtzKfG7Yoth2DfFUiR6WJOpF 9NPeUau+ggna95ae1E4aQY/hAxLMUMNFiLbPjJfNIz62JdG5NJSGczrgHDWKNegHd8w7 RiFJ1QM6SsFJA7tR5MHXlOXrcCN0G5yNntPaDDds8li/w/Qz+l2fR4GdRypeYCsIClVv ZRSxMkRFK1cnyAGRiFEQHRkxorRyx7vGrgh5LYK05xJJqtPx4mMHHTMM4hjCEFhSvOqL 5NixUfBbGY6l0UUfTdaOMc29aN9P4VtBjpMQ5jgZzkhpqWIcl8AuWIF9ykme5vL6dm6N OG0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411182; x=1770015982; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=A2m1YYGNyq/Rz1FBTgbyAMMQAXZAUd22fOojccDF0Y8=; b=btBsXhdfJ2hRgfVWKx1V7G4uJaZNaQYhR18OKWjOaFB/XEH5QkyQbwJUVDhClYNW4f 1Bpdx5bhlEymheLcNm9+gPE4QYDnajlPtJi0zSXpfy8Xc2tkhpfM65JsPYvGjii7JSw5 t2Bq5/Zp6Qv3iR/LP7Ht05yuiq3NsR8JfCR9+7Ig/j6uhGBYEiY5wbZiEeCAOnaN+q1g SQ0raTCagppHIhWBpiY1FJpzf28jFMVZjX7Nn/MQxoWrTv0Olq4iaPIuvQihXqrY+826 rnycqFf5sDRaqTO4fJsIa24nkY0W48CQunwIeV30PeJlUhkOf3oDVeS5D+wh9Monp1j9 Aohg== X-Gm-Message-State: AOJu0YzaXZJNmp/NcdQAh41ffl7qFYJOJ245WhLwUeqjOQ4h+ZFxnca5 stHg8ovQwSjjSxTQqMWQs0osPWlq5q8HCkCkpUxIA444JmO422iv6qQjB1fT1mw9 X-Gm-Gg: AZuq6aKN0kM3jWpnegcX+A+uBMRk4hanjvyY9KcDbfpp03RIXJ1bdLLnCIYr2XvtsTn Vk9KncuLAa7ykcdv2VpjuMicT79qDuPhUoTk/9II373jCWktWt/TbKQ41iHTHD24oeHiwtVFyHk BW5OlsWEsAJFZy7p9qnz7PcWZPG4wQIb7J/dEmKAvnW4l0jEJ8C8+jFtPQKYYW4WBpdDBjRWSFP vVIvcfnaWJ1ei32ww/U0oX3+VHIiMuVNgzYZkoHj7y93dXkl/d/mgTPbt8KeGR924YVSXWRLrzL 0LyBRhHwjL6ck1RBppZO7jAptm2DlpRzC/bYao63aimitqY14uHcdQDfIfximw30NQjKNtvElX+ Z8AgNOS33qrJtdm9vL/V9HaWAmLRqaG1cXUrdMe1Sg/C2oF3qKGI2GAFVfFtmTMUqd1U12iJ9B/ c/pHdy6WDviOuSXgOpqJBYTqrhilElG/Rs2hLuJEBy3g== X-Received: by 2002:a05:6a00:4b07:b0:822:30e:d15f with SMTP id d2e1a72fcca58-823411d7ee9mr3616085b3a.6.1769411182178; Sun, 25 Jan 2026 23:06:22 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 30/33] meson.build: Propagate optimization flag for linking on Emscripten Date: Mon, 26 Jan 2026 07:03:43 +0000 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412619241158500 Content-Type: text/plain; charset="utf-8" Emscripten uses the optimization flag at the link time to enable optimizations via Binaryen [1]. While meson.build currently recognizes the -Doptimization option, it does not propagate it to the linking. This commit updates meson.build to propagate the optimization flag to the linking when targeting WebAssembly. [1] https://emscripten.org/docs/optimizing/Optimizing-Code.html#how-emscrip= ten-optimizes Signed-off-by: Kohei Tokunaga --- meson.build | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/meson.build b/meson.build index 82d9c94f4a..0bdc350f16 100644 --- a/meson.build +++ b/meson.build @@ -841,6 +841,12 @@ elif host_os =3D=3D 'openbsd' # Disable OpenBSD W^X if available emulator_link_args =3D cc.get_supported_link_arguments('-Wl,-z,wxneede= d') endif +elif host_os =3D=3D 'emscripten' + # Emscripten uses the optimization flag also during the link time. + # https://emscripten.org/docs/optimizing/Optimizing-Code.html#how-emscri= pten-optimizes + if get_option('optimization') !=3D 'plain' + emulator_link_args +=3D ['-O' + get_option('optimization')] + endif endif =20 ############################################### --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412973; cv=none; d=zohomail.com; s=zohoarc; b=OPWEaoWP1PJJRY3mBvG0JVKyofhGltYozAqDEEj8nRCA77bdHPjRdQBAexTjOtS+RE2d7zhLK6SEJ/iEIgHDESHmkr56eJtDHDMaaAqYPjDnuHB9QvY7o3t6UWk7DpmFbc77dVOHsQ+FJV3IIGYrA4n8xQIcDdUByjF3IpOq+MA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769412973; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=j2wRRRhpw2QeH+ly9lZWVccsQ4eVHSDC2ik4WsoAFuw=; b=IDhsNM7yIiG0mnoTMrE+HOe1S1kcxIi8Z4Vitbq+/a8HPEBiei7qIUsNeimXfQu2tPwNCHDLXTDkAlXEOmyPb3lQLu9NJZ+WCvF6uT23YLWB+ofuJigALiSC3CmyVbqHnLCq6+X6o5aOB1feuZFg8arGqbDSortCuVisVSB2KY0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769412973294649.5304852669574; Sun, 25 Jan 2026 23:36:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkH3A-0007Mk-Rz; Mon, 26 Jan 2026 02:30:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGgV-0003Rn-V7 for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:07:03 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGgT-0004l8-Ei for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:06:51 -0500 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-81c72659e6bso3920532b3a.0 for ; Sun, 25 Jan 2026 23:06:27 -0800 (PST) Received: from brahms.. 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Signed-off-by: Kohei Tokunaga --- .gitlab-ci.d/buildtest.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index f9a2d4de74..f7843e6e5a 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buildtest.yml @@ -792,7 +792,7 @@ build-wasm64-64bit: - job: wasm64-emsdk-cross-container variables: IMAGE: emsdk-wasm64-cross - CONFIGURE_ARGS: --static --cpu=3Dwasm64 --disable-tools --enable-debug= --enable-tcg-interpreter + CONFIGURE_ARGS: --static --cpu=3Dwasm64 --disable-tools --enable-debug =20 build-wasm64-32bit: extends: .wasm_build_job_template @@ -801,4 +801,4 @@ build-wasm64-32bit: - job: wasm64-emsdk-cross-container variables: IMAGE: emsdk-wasm64-cross - CONFIGURE_ARGS: --static --cpu=3Dwasm64 --enable-wasm64-32bit-address-= limit --disable-tools --enable-debug --enable-tcg-interpreter + CONFIGURE_ARGS: --static --cpu=3Dwasm64 --enable-wasm64-32bit-address-= limit --disable-tools --enable-debug --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412163; cv=none; d=zohomail.com; s=zohoarc; b=HF9q5yoFminW/dzHqQMl0IcJm8r5X8f2MEIs+EnlDceiyavenSL8Z4QU639VSVqStWW2Ta9dWBAIC9SeQM6ziGzStbOAwOMLyO4OS34tGCdlIb/yzI36e69R4FFUhKLKnJ1E5dZ+5Xy3fUqd0nmLsTgNc87MfvQ1hjh48lZOlRc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769412163; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Oj8vRqVMDeN0JON25L/5cGpcqDkG3XOVfGvUsHWl4zU=; b=OlAmwgSsmVAHncBcZbaIkYxsBkG0p+SP25/PvDy6QVVOuh64GJo36ktp8YP0QrQbbmmJ1ts7VuOOP1l3YoD71gpwHBtmUZDD+KgVTeCZS5zY8jIfZ0LU3Q9cBb3h2Y2vT3z2O0R0E2Ibf/Y3CjsW/69hV0bxYh56xdAy0YG9G3o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769412163581742.3288848924659; Sun, 25 Jan 2026 23:22:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGug-00073i-VA; Mon, 26 Jan 2026 02:21:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGgR-0003Qc-MF for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:06:59 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGgL-0004le-5P for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:06:44 -0500 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-81e8b1bdf0cso2223815b3a.3 for ; Sun, 25 Jan 2026 23:06:31 -0800 (PST) Received: from brahms.. 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:06:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411191; x=1770015991; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Oj8vRqVMDeN0JON25L/5cGpcqDkG3XOVfGvUsHWl4zU=; b=CaxY4BqOdyyH2UYsMdjAIDJ8U/9VZ7tAIvtbOSIBM1uNDCgHZxig9AHy1jwtf7jUwc HbBz7MQDFe9+bYMxd2pZ69wmPU9vCTJUx1uRO6Xkv3L7F5qAUfvHFto7vWIyEqz8/Cal KAcagYEaC0jcyxQDRac3o7yIVMCL2G7AoFQoXj8eN54Ii1N5DCA17gQx00VFqVK16BTw rM8gqQu7GNcCWuVfGsX71Tre4K9K0OveehxkMh7XTyf3JigVA7ZLrk7TN2jWEqaG/6pW /1zYknLhBessgi2+7xovFI+bXPeQVOTTQm22ZKRva4TPYtHfghW4TDVPh8XiPPF0BT7Q LCeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411191; x=1770015991; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Oj8vRqVMDeN0JON25L/5cGpcqDkG3XOVfGvUsHWl4zU=; b=bFg6LyGHIPblwncyJ+nBmLXwJe1xYw5dAD4U7vs3hMCN/CTXIx08b6zO6Xs1FZ16Wy xwjEl6f+Lc5xemO5UpdPixUrAOM6SmMRx/Wr9DMGdONB+uecftUvP9TvnhY10DGdI5Ct cEomqIZzsSesiedSZOHeBR0TC3IiBWPebiTED74pD2LboEM5XXACIsiN7u9mRPiD+xrn /6YnvFSl6HLXYUdVnQ+XarxmZ/5sVOYZvIoK5eW/qhwUpgmWfimL6hGsstAEcWxAL2mr dgjZoQhmugVYaIhRFCDzMHN5IRqH7DBmZ3qpZ3E4MpPFJK+QyUTxK0vZijpFAIyHICoZ sfXw== X-Gm-Message-State: AOJu0YytkPuQbuvoqsyzyUplxjXru/7l8+C4WLjIeLDuIcno3hygm+qN 0bEbD/1RTLjIs0FSzA/b4PoCIPVR/OCCbyh54Pod5hRAAx0FYSRFFbcFA+isI0On X-Gm-Gg: AZuq6aLKHI9CMocU5t7KxZosqlRbphtsZtEkiccLqOVdOJxNLl2ZIEqWAmOukPu2N+b 6pW1E2BAiiDBFP1J89/Da/DWWLYvcPbQ5LHZ4dOVwnLM/WgMB2So+ozUoo9y04aeJp/51k71bKn 3bMwO/5CjzCYTBG7ANk2AvS1oNF7o69ROurYBimxgvr/+gkIoZd1upsklX+KuaOL/zmsixwJrkj hnQcmS27e/wtJsyNbYY0zONhsSkcWauG4xjCji7UgTp0za91I412etLKl5zuk9OJ5M7RlTeCWM2 1td8onJqhIdmI+4bDYWsyfp3IZ5mG+X+iSulAcSRbSAS53UvPAM9AZ2f6KCyAQZ/LBKHtKjCd7z CGI9DTBLyTko5rqBLu4vrwgZ6/en+TCI6iP74S5lE4YDMknDC3jDT/iz/tJEVzh5wU+bvCHoRYO KFLE0viJoWoN/F2bfkIzBG/qI/5XwedyEViHdAdloi8Q== X-Received: by 2002:a05:6a00:2e27:b0:81c:717b:9d29 with SMTP id d2e1a72fcca58-823412bc9dbmr3045269b3a.51.1769411191033; Sun, 25 Jan 2026 23:06:31 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 32/33] scripts: Add a script to run the wasm-compiled QEMU on node.js Date: Mon, 26 Jan 2026 07:03:45 +0000 Message-ID: <2af460d17a47ec69d691dfb876f834e4685f9d6d.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412166729154100 Content-Type: text/plain; charset="utf-8" run-emscripten.mjs is a Node.js script to quickly test the Wasm-compiled QEMU. This runs directly from the terminal using the node command so the HTTP server or the browser isn't needed. Node.js 24 or newer is needed to run wasm64 binaries. Also note that QEMU's "quit" monitor command doesn't work as of now because of the Emscripten's atexit issue [1]. Send SIGINT or SIGTERM to the node process to exit QEMU. [1] https://github.com/emscripten-core/emscripten/issues/26040 Signed-off-by: Kohei Tokunaga --- scripts/run-emscripten.mjs | 66 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 scripts/run-emscripten.mjs diff --git a/scripts/run-emscripten.mjs b/scripts/run-emscripten.mjs new file mode 100644 index 0000000000..330e31cfe3 --- /dev/null +++ b/scripts/run-emscripten.mjs @@ -0,0 +1,66 @@ +#!/usr/bin/env node + +import path from 'node:path'; +import { parseArgs } from "node:util"; + +function help() { + console.log(`Usage: run-emscripten.mjs [--preload FILE] [script.js] -- [= arguments] + +Options: + --preload FILE: Load the package created by Emscripten's file_packager.p= y`); +} + +const { values, positionals } =3D parseArgs({ + allowPositionals: true, + options: { + 'preload': { type: 'string' }, + 'help': { type: 'boolean' }, + }, +}) +if (values.help) { + help(); + process.exit(0); +} +const preload =3D values.preload; +const moduleFile =3D positionals[0]; +const moduleArgs =3D positionals.slice(1); +if ((!moduleFile) || (!moduleFile.match(/.*\.m?js$/))) { + console.error("module JS file must be specified as the first argument"); + help(); + process.exit(1); +} + +const targetModule =3D await import(path.resolve(moduleFile)); +let preloadModule; +if (preload) preloadModule =3D await import(path.resolve(preload)); + +var Module =3D { + preRun: [], + arguments: moduleArgs, + mainScriptUrlOrBlob: path.resolve(moduleFile), +}; +Module["preRun"].push((Module) =3D> { + const decoder =3D new TextDecoder('utf-8'); + Module.TTY.default_tty_ops.put_char =3D (tty, val) =3D> { + process.stdout.write(decoder.decode(new Uint8Array([val]))); + } + Module.TTY.default_tty1_ops.put_char =3D (tty, val) =3D> { + process.stderr.write(decoder.decode(new Uint8Array([val]))); + } +}); +if (preloadModule) preloadModule.default(Module); + +if (process.stdin.isTTY) { + process.stdin.setRawMode(true); +} +function restoreTTY() { + if (process.stdin.isTTY) { + process.stdin.setRawMode(false); + } + process.exit(0); +} +process.on('exit', restoreTTY); +process.on('SIGINT', restoreTTY); +process.on('SIGTERM', restoreTTY); + +await targetModule.default(Module); --=20 2.43.0 From nobody Sat Feb 7 08:44:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1769412288; cv=none; d=zohomail.com; s=zohoarc; b=ZQ2YHGZz2M2w8yHRZwLFxFcV3FBrPeOCiAYbYRsoqYwPiPnfD505SYGieF5VlGWHOIenMTwuFjqZ1DelKl4jZhHVe6j560HPnFAVmuo2KC2FfoJpOmrIbT0GuaCZ8zOORlh8ggseLoDsQ1XEnoSH0hlJlq9JNxV5dwnb6YNoHZ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769412288; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3j7udeVM6rKrCEa74dyypvfDYvQk1Jag50gmIaKtShw=; b=Cqx+Yqqtr2FC1SKG/d42uNEqOUmZV5W/kd1PClkTCgqBriJK9X5eZ34ROtuXCPYCEgKocAzCOs98kGFgpr/obgLdIAjxVWgaPe7fMl32bLtJxo1qZ9j/KOoKq04ms1yYhpSXRvtDkqMm38izrbE8+g2tbpI3i/kcb9FOHaJEtWE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769412288213552.2280107925311; Sun, 25 Jan 2026 23:24:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkGwo-0001qd-Ly; Mon, 26 Jan 2026 02:23:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkGgT-0003RH-Mx for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:06:59 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vkGgN-0004mR-It for qemu-devel@nongnu.org; Mon, 26 Jan 2026 02:06:47 -0500 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-8217f2ad01eso3630412b3a.2 for ; Sun, 25 Jan 2026 23:06:36 -0800 (PST) Received: from brahms.. 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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.06.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:06:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411195; x=1770015995; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3j7udeVM6rKrCEa74dyypvfDYvQk1Jag50gmIaKtShw=; b=i4t8D9eZaC13SZi1wkUTHnPi6ThFigwn9Y+drA2OtYXjS7TYTNnwn7TE9h1MpGH+Q0 kvkt9I8bB9fdvuYkJiOza8Z9T6AvK/DtlDA1XzvUgr3gnKieaumoImkLvksg8x8sGfZZ o6jiPaGQgPBChFPlafnnMgCqhf69F0cU8bvTZkf1fx9DE9urHAwMoLpRn9vqA5RnwHwV qePpRrFidvicHOrFU1KePOY9CltAziGev3GuPOEsW08W7awB9tetlYNozXbK7mNPIc8U sihkhwvoccKm0+HQdM4cyzi2gUbfl+hHikJnBNiMrEwzXDHIsTSDFluE7nzQDKGOERDO I1kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411195; x=1770015995; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=3j7udeVM6rKrCEa74dyypvfDYvQk1Jag50gmIaKtShw=; b=QoPL3bJhdUkEWibFGT/eG/iHSzFK3ZFg1XRWxDzSnfH+QK2bXX73v3Bkg66dYWY7rA Olc/QOE/PEu4H3JmrtOKbmtdDN5FLvrCLTHoRmcVx76vSfPr+Dm69avABdpi4pfxNCYW K+DMTMac/5+dcSbMkrdE+rG1SWZTT8pL1ag3Qn6zHOldbKM1MU33n4ac7J1slRkInSbB 3hlI53wbJQ6gEFiySeWJpiR9qXtkjlLC6hR4t4NkiQU8VLMTctR7WJCBRn2z8LyOM6FS hvCUD8SCI8I6Z9Ns8cMLWD+Wz7Ltg2EmDXVDCvt+erNM3+mddc0v6jwl2GD2ktxEVP5i /1gQ== X-Gm-Message-State: AOJu0Yx5vBw/2EYBIc5/fmBQeDevMYj3/QVzoFz9UdOjcLTfNJnmcmZk tEm5zH0inlkzZUF/ggQKrzC76pundjKuvcxez1yAiXX0R4W2WjonHvEhXBrMuTqk X-Gm-Gg: AZuq6aJvwvyRQJ1UHmmp6D6PuptPZ5/SyadeVyEWyP0FBvTKHQ6uJm7nJ1h0GK6+gvd tHzMk8w1delg6IbQDWTWwnH9M+slwSgw7mKqsOSnkTL8tTuJOVVQVornQg2MJyfTIWyKjq4Sqow Kq6qgCrgbg6Nm8F+xcUuTiGjCX14ZlMHCHj2+czHRRaHokxFNYHoewhpHAEQzdTK7ergmeD5MrD uSLZGRyF49gsYnaw8YjnUy97MnZo9X1ZBYP/ZeANn2k3QAFr4Rz/eiJxXikry3blWHWOX2oCwyo 1VxBBZH7Kc5QTG5OPMlORqrNC0xgrELK6TCt4RWQRolBGhsZJnE+28Gc7nMizlZjuTntwflWaGX X274s7cCSFRTFT2UaL79v1klPRvh3V9YXfZj3l5URZMWXTvBfdkeup0dtl1xcxGyWiSdK6ymNZ7 7wH1bm2nwXrm1oAczZgjKj8qvZ0s0TV7I4gcwP9moDqg== X-Received: by 2002:a05:6a00:1390:b0:81d:e9b1:b6e3 with SMTP id d2e1a72fcca58-823411d83b6mr3385121b3a.14.1769411195476; Sun, 25 Jan 2026 23:06:35 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 33/33] emsdk-wasm-cross.docker: Bump up emsdk to 4.0.23 Date: Mon, 26 Jan 2026 07:03:46 +0000 Message-ID: <8f1406ba3307a10c58be24a8ff00ab6a5d3b6169.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769412290487158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Kohei Tokunaga --- tests/docker/dockerfiles/emsdk-wasm-cross.docker | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/docker/dockerfiles/emsdk-wasm-cross.docker b/tests/docke= r/dockerfiles/emsdk-wasm-cross.docker index 8a924816f9..d1c0c4195e 100644 --- a/tests/docker/dockerfiles/emsdk-wasm-cross.docker +++ b/tests/docker/dockerfiles/emsdk-wasm-cross.docker @@ -1,6 +1,6 @@ # syntax =3D docker/dockerfile:1.5 =20 -ARG EMSDK_VERSION_QEMU=3D4.0.10 +ARG EMSDK_VERSION_QEMU=3D4.0.23 ARG ZLIB_VERSION=3D1.3.1 ARG GLIB_MINOR_VERSION=3D2.84 ARG GLIB_VERSION=3D${GLIB_MINOR_VERSION}.0 --=20 2.43.0