From nobody Sun Dec 14 06:34:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1763642641015869.9683984404612; Thu, 20 Nov 2025 04:44:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vM40K-0001yR-Kk; Thu, 20 Nov 2025 07:43:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vM40G-0001x7-SU for qemu-devel@nongnu.org; Thu, 20 Nov 2025 07:43:12 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vM40D-00043E-3O for qemu-devel@nongnu.org; Thu, 20 Nov 2025 07:43:12 -0500 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Bx39PQDB9pwBcmAA--.11637S3; Thu, 20 Nov 2025 20:42:56 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJBxysDPDB9plJg5AQ--.5496S3; Thu, 20 Nov 2025 20:42:55 +0800 (CST) From: Xianglai Li To: qemu-devel@nongnu.org, lixianglai@loongson.cn Cc: Bibo Mao , Jiaxun Yang , Song Gao Subject: [PATCH V4 1/2] Modify the interrupt trigger type in loongarch virt fdt to macro definition Date: Thu, 20 Nov 2025 20:18:41 +0800 Message-Id: <56832788ca15ee896e4e7bd2a635e65e188d75c2.1763434297.git.lixianglai@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxysDPDB9plJg5AQ--.5496S3 X-CM-SenderInfo: 5ol0xt5qjotxo6or00hjvr0hdfq/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=lixianglai@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1763642645052018900 Content-Type: text/plain; charset="utf-8" In the loongarch virt fdt file, the interrupt trigger type directly uses magic numbers. Now, refer to the definitions in the linux kernel and use macro definitions. Signed-off-by: Xianglai Li Reviewed-by: Bibo Mao --- Cc: Bibo Mao Cc: Jiaxun Yang Cc: Song Gao hw/loongarch/virt-fdt-build.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/loongarch/virt-fdt-build.c b/hw/loongarch/virt-fdt-build.c index 1f0ba01f71..7333019cf7 100644 --- a/hw/loongarch/virt-fdt-build.c +++ b/hw/loongarch/virt-fdt-build.c @@ -16,6 +16,11 @@ #include "system/reset.h" #include "target/loongarch/cpu.h" =20 +#define FDT_IRQ_TYPE_EDGE_RISING 1 +#define FDT_IRQ_TYPE_EDGE_FALLING 2 +#define FDT_IRQ_TYPE_LEVEL_HIGH 4 +#define FDT_IRQ_TYPE_LEVEL_LOW 8 + static void create_fdt(LoongArchVirtMachineState *lvms) { MachineState *ms =3D MACHINE(lvms); @@ -415,7 +420,8 @@ static void fdt_add_uart_node(LoongArchVirtMachineState= *lvms, if (chosen) { qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodenam= e); } - qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", irq, 0x4); + qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", irq, + FDT_IRQ_TYPE_LEVEL_HIGH); qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", *pch_pic_phandle); g_free(nodename); @@ -435,7 +441,8 @@ static void fdt_add_rtc_node(LoongArchVirtMachineState = *lvms, "loongson,ls7a-rtc"); qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, siz= e); qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", - VIRT_RTC_IRQ - VIRT_GSI_BASE , 0x4); + VIRT_RTC_IRQ - VIRT_GSI_BASE , + FDT_IRQ_TYPE_LEVEL_HIGH); qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", *pch_pic_phandle); g_free(nodename); --=20 2.39.1 From nobody Sun Dec 14 06:34:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1763642641013819.3506890294183; Thu, 20 Nov 2025 04:44:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vM40K-0001yA-KT; Thu, 20 Nov 2025 07:43:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vM40G-0001xA-SP for qemu-devel@nongnu.org; Thu, 20 Nov 2025 07:43:12 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vM40D-00043L-2y for qemu-devel@nongnu.org; Thu, 20 Nov 2025 07:43:12 -0500 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Bx3tLQDB9pwhcmAA--.16409S3; Thu, 20 Nov 2025 20:42:56 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJBxysDPDB9plJg5AQ--.5496S4; Thu, 20 Nov 2025 20:42:56 +0800 (CST) From: Xianglai Li To: qemu-devel@nongnu.org, lixianglai@loongson.cn Cc: Bibo Mao , Jiaxun Yang , Song Gao Subject: [PATCH V4 2/2] fix pci device can't alloc irq from fdt Date: Thu, 20 Nov 2025 20:18:42 +0800 Message-Id: <20726ae560966e7405c8f73a665c2f006c613623.1763434297.git.lixianglai@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxysDPDB9plJg5AQ--.5496S4 X-CM-SenderInfo: 5ol0xt5qjotxo6or00hjvr0hdfq/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=lixianglai@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1763642647713018900 Content-Type: text/plain; charset="utf-8" When we use the -kernel parameter to start an elf format kernel relying on fdt, we get the following error: pcieport 0000:00:01.0: of_irq_parse_pci: failed with rc=3D-22 pcieport 0000:00:01.0: enabling device (0000 -> 0003) pcieport 0000:00:01.0: PME: Signaling with IRQ 19 pcieport 0000:00:01.0: AER: enabled with IRQ 19 pcieport 0000:00:01.1: of_irq_parse_pci: failed with rc=3D-22 pcieport 0000:00:01.1: enabling device (0000 -> 0003) pcieport 0000:00:01.1: PME: Signaling with IRQ 20 pcieport 0000:00:01.1: AER: enabled with IRQ 20 pcieport 0000:00:01.2: of_irq_parse_pci: failed with rc=3D-22 pcieport 0000:00:01.2: enabling device (0000 -> 0003) pcieport 0000:00:01.2: PME: Signaling with IRQ 21 pcieport 0000:00:01.2: AER: enabled with IRQ 21 pcieport 0000:00:01.3: of_irq_parse_pci: failed with rc=3D-22 pcieport 0000:00:01.3: enabling device (0000 -> 0003) pcieport 0000:00:01.3: PME: Signaling with IRQ 22 pcieport 0000:00:01.3: AER: enabled with IRQ 22 pcieport 0000:00:01.4: of_irq_parse_pci: failed with rc=3D-22 This is because the description of interrupt-cell is missing in the pcie irq map. And there is a lack of a description of the interrupt trigger type. Now it is corrected and the correct interrupt-cell is added in the pcie irq map. Refer to the implementation in arm and add some comments. Signed-off-by: Xianglai Li Reviewed-by: Bibo Mao --- Cc: Bibo Mao Cc: Jiaxun Yang Cc: Song Gao hw/loongarch/virt-fdt-build.c | 44 ++++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 16 deletions(-) diff --git a/hw/loongarch/virt-fdt-build.c b/hw/loongarch/virt-fdt-build.c index 7333019cf7..e597b19dc3 100644 --- a/hw/loongarch/virt-fdt-build.c +++ b/hw/loongarch/virt-fdt-build.c @@ -321,6 +321,8 @@ static void fdt_add_pcie_irq_map_node(const LoongArchVi= rtMachineState *lvms, uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS * 10] =3D {}; uint32_t *irq_map =3D full_irq_map; const MachineState *ms =3D MACHINE(lvms); + uint32_t pin_mask; + uint32_t devfn_mask; =20 /* * This code creates a standard swizzle of interrupts such that @@ -333,37 +335,45 @@ static void fdt_add_pcie_irq_map_node(const LoongArch= VirtMachineState *lvms, */ =20 for (dev =3D 0; dev < PCI_NUM_PINS; dev++) { - int devfn =3D dev * 0x8; + int devfn =3D PCI_DEVFN(dev, 0); =20 for (pin =3D 0; pin < PCI_NUM_PINS; pin++) { - int irq_nr =3D 16 + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); + int irq_nr =3D VIRT_DEVICE_IRQS + \ + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); int i =3D 0; =20 - /* Fill PCI address cells */ - irq_map[i] =3D cpu_to_be32(devfn << 8); - i +=3D 3; - - /* Fill PCI Interrupt cells */ - irq_map[i] =3D cpu_to_be32(pin + 1); - i +=3D 1; - - /* Fill interrupt controller phandle and cells */ - irq_map[i++] =3D cpu_to_be32(*pch_pic_phandle); - irq_map[i++] =3D cpu_to_be32(irq_nr); + uint32_t map[] =3D { + devfn << 8, 0, 0, /* devfn */ + pin + 1, /* PCI pin */ + *pch_pic_phandle, /* interrupt controller hand= le */ + irq_nr, /* irq number */ + FDT_IRQ_TYPE_LEVEL_HIGH }; /* irq trigger level */ =20 if (!irq_map_stride) { - irq_map_stride =3D i; + irq_map_stride =3D sizeof(map) / sizeof(uint32_t); } + + /* Convert map to big endian */ + for (i =3D 0; i < irq_map_stride; i++) { + irq_map[i] =3D cpu_to_be32(map[i]); + } + irq_map +=3D irq_map_stride; } } =20 - qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", full_irq_map, PCI_NUM_PINS * PCI_NUM_PINS * irq_map_stride * sizeof(uint32_t)); + + /* Only need to match the pci slot bit */ + devfn_mask =3D PCI_DEVFN((PCI_NUM_PINS - 1), 0) << 8; + /* The pci interrupt only needs to match the specified low bit */ + pin_mask =3D (1 << ((PCI_NUM_PINS - 1))) - 1; + qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", - 0x1800, 0, 0, 0x7); + devfn_mask, 0, 0, /* address cells */ + pin_mask); } =20 static void fdt_add_pcie_node(const LoongArchVirtMachineState *lvms, @@ -400,6 +410,8 @@ static void fdt_add_pcie_node(const LoongArchVirtMachin= eState *lvms, 2, base_mmio, 2, size_mmio); qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 0, *pch_msi_phandle, 0, 0x10000); + + qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); fdt_add_pcie_irq_map_node(lvms, nodename, pch_pic_phandle); g_free(nodename); } --=20 2.39.1