From nobody Thu Dec 18 17:48:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174471103807197.07927018250496; Tue, 15 Apr 2025 02:57:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u4d20-0000BJ-J3; Tue, 15 Apr 2025 05:56:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u4d1u-00009U-S4; Tue, 15 Apr 2025 05:56:36 -0400 Received: from out28-147.mail.aliyun.com ([115.124.28.147]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u4d1q-0005z9-NG; Tue, 15 Apr 2025 05:56:33 -0400 Received: from TC-DZ-03-0020.tc.local(mailfrom:lc00631@tecorigin.com fp:SMTPD_---.cNCCBEo_1744710974 cluster:ay29) by smtp.aliyun-inc.com; Tue, 15 Apr 2025 17:56:15 +0800 From: Chao Liu To: alistair23@gmail.com, palmer@dabbelt.com Cc: zhiwei_liu@linux.alibaba.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, lc00631@tecorigin.com, zqz00548@tecorigin.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v0 1/1] hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly Date: Tue, 15 Apr 2025 17:53:58 +0800 Message-ID: <07a97219e3f7e342c668d6772acc4c0a8eb4d4f3.1744709888.git.lc00631@tecorigin.com> X-Mailer: git-send-email 2.47.0.windows.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.28.147; envelope-from=lc00631@tecorigin.com; helo=out28-147.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1744711038637019000 Content-Type: text/plain; charset="utf-8" riscv_plic_hart_config_string() when getting CPUState via qemu_get_cpu() should be consistent with keeping sifive_plic_realize() by hartid_base + cpu_index. For non-numa or multi-cluster machines, hartid_base should be 0. Also, to ensure that CPUState->cpu_index is set correctly, we need to update it with the value of mhartid during riscv_hart_realize(). Signed-off-by: Chao Liu Reviewed-by: zhaoqingze Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/boot.c | 4 ++-- hw/riscv/microchip_pfsoc.c | 2 +- hw/riscv/riscv_hart.c | 1 + hw/riscv/sifive_u.c | 5 +++-- hw/riscv/virt.c | 2 +- include/hw/riscv/boot.h | 2 +- 6 files changed, 9 insertions(+), 7 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 765b9e2b1a..d4c06e7530 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -44,13 +44,13 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) * Return the per-socket PLIC hart topology configuration string * (caller must free with g_free()) */ -char *riscv_plic_hart_config_string(int hart_count) +char *riscv_plic_hart_config_string(int hart_base, int hart_count) { g_autofree const char **vals =3D g_new(const char *, hart_count + 1); int i; =20 for (i =3D 0; i < hart_count; i++) { - CPUState *cs =3D qemu_get_cpu(i); + CPUState *cs =3D qemu_get_cpu(hart_base + i); CPURISCVState *env =3D &RISCV_CPU(cs)->env; =20 if (kvm_enabled()) { diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 9c846f9b5b..5269336346 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -275,7 +275,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *de= v, Error **errp) l2lim_mem); =20 /* create PLIC hart topology configuration string */ - plic_hart_config =3D riscv_plic_hart_config_string(ms->smp.cpus); + plic_hart_config =3D riscv_plic_hart_config_string(0, ms->smp.cpus); =20 /* PLIC */ s->plic =3D sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index a55d156668..522e795033 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -138,6 +138,7 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, = int idx, } =20 s->harts[idx].env.mhartid =3D s->hartid_base + idx; + CPU(&s->harts[idx])->cpu_index =3D s->harts[idx].env.mhartid; qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 679f2024bc..516912c4f4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -790,10 +790,11 @@ static void sifive_u_soc_realize(DeviceState *dev, Er= ror **errp) MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); MemoryRegion *l2lim_mem =3D g_new(MemoryRegion, 1); char *plic_hart_config; + int hartid_base =3D 1; int i, j; =20 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1= ); - qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", hartid_base); qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); =20 @@ -829,7 +830,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) l2lim_mem); =20 /* create PLIC hart topology configuration string */ - plic_hart_config =3D riscv_plic_hart_config_string(ms->smp.cpus); + plic_hart_config =3D riscv_plic_hart_config_string(hartid_base, ms->sm= p.cpus); =20 /* MMIO */ s->plic =3D sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e517002fdf..41fdfd2bc8 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1280,7 +1280,7 @@ static DeviceState *virt_create_plic(const MemMapEntr= y *memmap, int socket, g_autofree char *plic_hart_config =3D NULL; =20 /* Per-socket PLIC hart topology configuration string */ - plic_hart_config =3D riscv_plic_hart_config_string(hart_count); + plic_hart_config =3D riscv_plic_hart_config_string(base_hartid, hart_c= ount); =20 /* Per-socket PLIC */ ret =3D sifive_plic_create( diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 7d59b2e6c6..5937298646 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -40,7 +40,7 @@ typedef struct RISCVBootInfo { =20 bool riscv_is_32bit(RISCVHartArrayState *harts); =20 -char *riscv_plic_hart_config_string(int hart_count); +char *riscv_plic_hart_config_string(int hart_base, int hart_count); =20 void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts); target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info, --=20 2.48.1