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From: Chao Liu <lc00631@tecorigin.com>
To: bmeng.cn@gmail.com, liwei1518@gmail.com, palmer@dabbelt.com,
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Chao Liu <lc00631@tecorigin.com>
Subject: [PATCH v1 1/1] target/riscv: add VILL field for vtype register macro
definition
Date: Wed, 11 Dec 2024 21:47:15 +0800
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Signed-off-by: Chao Liu <lc00631@tecorigin.com>
---
target/riscv/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 284b112821..fc286484b8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -170,7 +170,8 @@ FIELD(VTYPE, VSEW, 3, 3)
FIELD(VTYPE, VTA, 6, 1)
FIELD(VTYPE, VMA, 7, 1)
FIELD(VTYPE, VEDIV, 8, 2)
-FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
+FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 12)
+FIELD(VTYPE, VILL, 63, 1)
=20
typedef struct PMUCTRState {
/* Current value of a counter */
--=20
2.47.0