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From: Pavel Pisa <pisa@fel.cvut.cz>
To: qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,
Gustavo Romero <gustavo.romero@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>, Jason Wang <jasowang@redhat.com>,
Francisco Iglesias <francisco.iglesias@amd.com>,
=?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.bennee@linaro.org>,
Pavel Pisa <pisa@cmp.felk.cvut.cz>
Subject: [RFC 1/3] hw/net/can: WIP CTU CAN FD IP core mapping to the platform
bus
Date: Tue, 10 Dec 2024 00:32:51 +0100
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<4baca743c8d3f6fa4ff10455560f940a84490aba.1733783500.git.pisa@cmp.felk.cvut.cz>
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From: Pavel Pisa <pisa@cmp.felk.cvut.cz>
It is initial attempt (IRQ not working yet) to provide
alternative to PCIe mapping. In this case, the platform
bus is used to match FPGA design for Xilinx Zynq MZ_APO
education kit with four CTU CAN FD cores on branch
mz_apo-2x-xcan-4x-ctu of repo
https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
The system is started by command
qemu-system-arm -m 1G -M xilinx-zynq-a9 \
-kernel kernel-zynq \
-dtb zynq-microzed-uart1-2x-xcan-4x-ctu-axi.dtb \
-initrd ramdisk.cpio \
-serial null -serial mon:stdio \
-nographic \
-object can-bus,id=3Dcanbus0-bus \
-object can-host-socketcan,if=3Dcan0,canbus=3Dcanbus0-bus,id=3Dcanbus=
0-socketcan \
-device ctucan_mm,iobase=3D0x43c30000,irq=3D29,canbus=3Dcanbus0-bus \
-device ctucan_mm,iobase=3D0x43c70000,irq=3D30,canbus=3Dcanbus0-bus \
-device ctucan_mm,iobase=3D0x43bf0000,irq=3D31,canbus=3Dcanbus0-bus \
-device ctucan_mm,iobase=3D0x43bb0000,irq=3D32,canbus=3Dcanbus0-bus \
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
---
hw/arm/xilinx_zynq.c | 1 +
hw/net/can/ctucan_mm.c | 279 +++++++++++++++++++++++++++++++++++++++++
hw/net/can/meson.build | 1 +
3 files changed, 281 insertions(+)
create mode 100644 hw/net/can/ctucan_mm.c
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index fde4d946b7..cd6444a6fe 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -473,6 +473,7 @@ static void zynq_machine_class_init(ObjectClass *oc, vo=
id *data)
"Supported boot modes:"
" jtag qspi sd nor");
object_property_set_default_str(prop, "qspi");
+ machine_class_allow_dynamic_sysbus_dev(mc, "ctucan_mm");
}
=20
static const TypeInfo zynq_machine_type =3D {
diff --git a/hw/net/can/ctucan_mm.c b/hw/net/can/ctucan_mm.c
new file mode 100644
index 0000000000..43e6823b73
--- /dev/null
+++ b/hw/net/can/ctucan_mm.c
@@ -0,0 +1,279 @@
+/*
+ * CTU CAN FD memory mapped device emulation
+ * http://canbus.pages.fel.cvut.cz/
+ *
+ * Copyright (c) 2024 Pavel Pisa (pisa@cmp.felk.cvut.cz)
+ *
+ * Based on Kvaser PCI CAN device (SJA1000 based) emulation implemented by
+ * Jin Yang and Pavel Pisa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a=
copy
+ * of this software and associated documentation files (the "Software"), t=
o deal
+ * in the Software without restriction, including without limitation the r=
ights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or se=
ll
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included=
in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS=
OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT=
HER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING=
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS =
IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/event_notifier.h"
+#include "qemu/module.h"
+#include "qemu/thread.h"
+#include "qemu/sockets.h"
+#include "qapi/error.h"
+#include "chardev/char.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+#include "net/can_emu.h"
+
+#include "ctucan_core.h"
+
+#define TYPE_CTUCAN_MM_DEV "ctucan_mm"
+
+typedef struct CtuCanMmState CtuCanMmState;
+DECLARE_INSTANCE_CHECKER(CtuCanMmState, CTUCAN_MM_DEV,
+ TYPE_CTUCAN_MM_DEV)
+
+#define CTUCAN_MM_CORE_COUNT 1
+#define CTUCAN_MM_CORE_RANGE 0x1000
+
+#define CTUCAN_MM_BYTES_PER_CORE 0x1000
+
+struct CtuCanMmState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ struct {
+ uint64_t iobase;
+ uint32_t irq;
+ } cfg;
+
+ MemoryRegion ctucan_io_region;
+
+ CtuCanCoreState ctucan_state[CTUCAN_MM_CORE_COUNT];
+ qemu_irq irq;
+
+ char *model;
+ CanBusState *canbus[CTUCAN_MM_CORE_COUNT];
+};
+
+static void ctucan_mm_reset(DeviceState *dev)
+{
+ CtuCanMmState *d =3D CTUCAN_MM_DEV(dev);
+ int i;
+
+ for (i =3D 0 ; i < CTUCAN_MM_CORE_COUNT; i++) {
+ ctucan_hardware_reset(&d->ctucan_state[i]);
+ }
+}
+
+static uint64_t ctucan_mm_cores_io_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ CtuCanMmState *d =3D opaque;
+ CtuCanCoreState *s;
+ hwaddr core_num =3D addr / CTUCAN_MM_BYTES_PER_CORE;
+
+ if (core_num >=3D CTUCAN_MM_CORE_COUNT) {
+ return 0;
+ }
+
+ s =3D &d->ctucan_state[core_num];
+
+ return ctucan_mem_read(s, addr % CTUCAN_MM_BYTES_PER_CORE, size);
+}
+
+static void ctucan_mm_cores_io_write(void *opaque, hwaddr addr, uint64_t d=
ata,
+ unsigned size)
+{
+ CtuCanMmState *d =3D opaque;
+ CtuCanCoreState *s;
+ hwaddr core_num =3D addr / CTUCAN_MM_BYTES_PER_CORE;
+
+ if (core_num >=3D CTUCAN_MM_CORE_COUNT) {
+ return;
+ }
+
+ s =3D &d->ctucan_state[core_num];
+
+ return ctucan_mem_write(s, addr % CTUCAN_MM_BYTES_PER_CORE, data, size=
);
+}
+
+static const MemoryRegionOps ctucan_mm_cores_io_ops =3D {
+ .read =3D ctucan_mm_cores_io_read,
+ .write =3D ctucan_mm_cores_io_write,
+ .endianness =3D DEVICE_LITTLE_ENDIAN,
+ .impl.min_access_size =3D 1,
+ .impl.max_access_size =3D 4,
+ .valid.min_access_size =3D 1,
+ .valid.max_access_size =3D 4,
+};
+
+static void ctucan_mm_realize(DeviceState *dev, Error **errp)
+{
+ CtuCanMmState *d =3D CTUCAN_MM_DEV(dev);
+ SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev);
+ int i;
+
+ for (i =3D 0 ; i < CTUCAN_MM_CORE_COUNT; i++) {
+ ctucan_init(&d->ctucan_state[i], d->irq);
+ }
+
+ for (i =3D 0 ; i < CTUCAN_MM_CORE_COUNT; i++) {
+ if (ctucan_connect_to_bus(&d->ctucan_state[i], d->canbus[i]) < 0) {
+ error_setg(errp, "ctucan_connect_to_bus failed");
+ return;
+ }
+ }
+
+ /* memory_region_add_subregion(get_system_memory(), 0x43c30000, &d->ct=
ucan_io_region); */
+ if (d->cfg.iobase !=3D 0) {
+ sysbus_mmio_map(sbd, 0, d->cfg.iobase);
+ }
+ if (d->cfg.irq !=3D 0) {
+ //const char *id =3D "/machine/unattached/device[3]/gic";
+ const char *id =3D "/machine/unattached/device[3]";
+ Object *obj =3D object_resolve_path_at(container_get(qdev_get_mach=
ine(), "/peripheral"), id);
+ DeviceState *gicdev;
+ if (!obj) {
+ error_set(errp, ERROR_CLASS_DEVICE_NOT_FOUND, "Device '%s' not=
found", id);
+ return;
+ }
+ gicdev =3D (DeviceState *)object_dynamic_cast(obj, TYPE_DEVICE);
+ if (!gicdev) {
+ error_setg(errp, "%s is not a hotpluggable device", id);
+ return;
+ }
+ sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(gicdev, d->cfg.irq));
+ }
+}
+
+/*
+static void ctucan_mm_exit(Object *obj)
+{
+ CtuCanMmState *d =3D CTUCAN_MM_DEV(obj);
+ int i;
+
+ for (i =3D 0 ; i < CTUCAN_MM_CORE_COUNT; i++) {
+ ctucan_disconnect(&d->ctucan_state[i]);
+ }
+
+ qemu_free_irq(d->irq);
+}
+*/
+
+static void ctucan_mm_reset_init(Object *obj, ResetType type)
+{
+ CtuCanMmState *d =3D CTUCAN_MM_DEV(obj);
+ unsigned int i;
+
+ for (i =3D 0 ; i < CTUCAN_MM_CORE_COUNT; i++) {
+ ctucan_init(&d->ctucan_state[i], d->irq);
+ }
+}
+
+static void ctucan_mm_reset_hold(Object *obj, ResetType type)
+{
+ CtuCanMmState *d =3D CTUCAN_MM_DEV(obj);
+ unsigned int i;
+
+ for (i =3D 0 ; i < CTUCAN_MM_CORE_COUNT; i++) {
+ ctucan_init(&d->ctucan_state[i], d->irq);
+ }
+}
+
+static const VMStateDescription vmstate_ctucan_mm =3D {
+ .name =3D "ctucan_mm",
+ .version_id =3D 1,
+ .minimum_version_id =3D 1,
+ .fields =3D (const VMStateField[]) {
+ VMSTATE_STRUCT(ctucan_state[0], CtuCanMmState, 0, vmstate_ctucan,
+ CtuCanCoreState),
+#if CTUCAN_MM_CORE_COUNT >=3D 2
+ VMSTATE_STRUCT(ctucan_state[1], CtuCanMmState, 0, vmstate_ctucan,
+ CtuCanCoreState),
+#endif
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void ctucan_mm_instance_init(Object *obj)
+{
+ CtuCanMmState *d =3D CTUCAN_MM_DEV(obj);
+ SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj);
+
+#if CTUCAN_MM_CORE_COUNT <=3D 1
+ object_property_add_link(obj, "canbus", TYPE_CAN_BUS,
+ (Object **)&d->canbus[0],
+ qdev_prop_allow_set_link_before_realize, 0);
+#else /* CTUCAN_MM_CORE_COUNT >=3D 2 */
+ object_property_add_link(obj, "canbus0", TYPE_CAN_BUS,
+ (Object **)&d->canbus[0],
+ qdev_prop_allow_set_link_before_realize, 0);
+ object_property_add_link(obj, "canbus1", TYPE_CAN_BUS,
+ (Object **)&d->canbus[1],
+ qdev_prop_allow_set_link_before_realize, 0);
+#endif
+ memory_region_init_io(&d->ctucan_io_region, OBJECT(d),
+ &ctucan_mm_cores_io_ops, d,
+ "ctucan_mm", CTUCAN_MM_CORE_RANGE);
+
+ sysbus_init_mmio(sbd, &d->ctucan_io_region);
+ sysbus_init_irq(sbd, &d->irq);
+}
+
+static Property ctucan_mm_properties[] =3D {
+ //DEFINE_PROP_UNSIGNED_NODEFAULT("base", CtuCanMmState, cfg.base,
+ // qdev_prop_uint64, uint64_t),
+ DEFINE_PROP_UINT64("iobase", CtuCanMmState, cfg.iobase, 0),
+ DEFINE_PROP_UINT32("irq", CtuCanMmState, cfg.irq, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ctucan_mm_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+ ResettableClass *rc =3D RESETTABLE_CLASS(klass);
+
+ rc->phases.enter =3D ctucan_mm_reset_init;
+ rc->phases.hold =3D ctucan_mm_reset_hold;
+ dc->realize =3D ctucan_mm_realize;
+ /* ->exit =3D ctucan_mm_exit; */
+ dc->desc =3D "CTU CAN MM";
+ dc->vmsd =3D &vmstate_ctucan_mm;
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+ dc->user_creatable =3D true;
+ /* dc->reset =3D ctucan_mm_reset; */
+ device_class_set_legacy_reset(dc, ctucan_mm_reset);
+
+ device_class_set_props(dc, ctucan_mm_properties);
+}
+
+static const TypeInfo ctucan_mm_info =3D {
+ .name =3D TYPE_CTUCAN_MM_DEV,
+ .parent =3D TYPE_SYS_BUS_DEVICE,
+ .instance_size =3D sizeof(CtuCanMmState),
+ .class_init =3D ctucan_mm_class_init,
+ .instance_init =3D ctucan_mm_instance_init,
+};
+
+static void ctucan_mm_register_types(void)
+{
+ type_register_static(&ctucan_mm_info);
+}
+
+type_init(ctucan_mm_register_types)
diff --git a/hw/net/can/meson.build b/hw/net/can/meson.build
index 7382344628..de25fdbd1c 100644
--- a/hw/net/can/meson.build
+++ b/hw/net/can/meson.build
@@ -3,6 +3,7 @@ system_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_k=
vaser_pci.c'))
system_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_pcm3680_pci.c'))
system_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_mioe3680_pci.c'))
system_ss.add(when: 'CONFIG_CAN_CTUCANFD', if_true: files('ctucan_core.c'))
+system_ss.add(when: 'CONFIG_CAN_CTUCANFD', if_true: files('ctucan_mm.c'))
system_ss.add(when: 'CONFIG_CAN_CTUCANFD_PCI', if_true: files('ctucan_pci.=
c'))
system_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-can.=
c'))
system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-canf=
d.c'))
--=20
2.39.5
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From: Pavel Pisa <pisa@fel.cvut.cz>
To: qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,
Gustavo Romero <gustavo.romero@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>, Jason Wang <jasowang@redhat.com>,
Francisco Iglesias <francisco.iglesias@amd.com>,
=?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.bennee@linaro.org>,
Pavel Pisa <pisa@cmp.felk.cvut.cz>
Subject: [RFC 2/3] hw/net/can: WIP CTU CAN FD mapping of IRQ for platform
device solved.
Date: Tue, 10 Dec 2024 00:32:52 +0100
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From: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
---
hw/net/can/ctucan_mm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/net/can/ctucan_mm.c b/hw/net/can/ctucan_mm.c
index 43e6823b73..6d6b8aecb8 100644
--- a/hw/net/can/ctucan_mm.c
+++ b/hw/net/can/ctucan_mm.c
@@ -160,6 +160,9 @@ static void ctucan_mm_realize(DeviceState *dev, Error *=
*errp)
}
sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(gicdev, d->cfg.irq));
}
+ for (i =3D 0 ; i < CTUCAN_MM_CORE_COUNT; i++) {
+ ctucan_init(&d->ctucan_state[i], d->irq);
+ }
}
=20
/*
--=20
2.39.5
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From: Pavel Pisa <pisa@fel.cvut.cz>
To: qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,
Gustavo Romero <gustavo.romero@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>, Jason Wang <jasowang@redhat.com>,
Francisco Iglesias <francisco.iglesias@amd.com>,
=?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.bennee@linaro.org>,
Pavel Pisa <pisa@cmp.felk.cvut.cz>
Subject: [RFC 3/3] hw/net/can: WIP CTU CAN FD add parameter to specify IRQ
controller on command line
Date: Tue, 10 Dec 2024 00:32:53 +0100
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From: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
---
hw/net/can/ctucan_mm.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/hw/net/can/ctucan_mm.c b/hw/net/can/ctucan_mm.c
index 6d6b8aecb8..e599df18be 100644
--- a/hw/net/can/ctucan_mm.c
+++ b/hw/net/can/ctucan_mm.c
@@ -59,7 +59,8 @@ struct CtuCanMmState {
=20
struct {
uint64_t iobase;
- uint32_t irq;
+ uint32_t irqnum;
+ char *irqctrl;
} cfg;
=20
MemoryRegion ctucan_io_region;
@@ -144,9 +145,16 @@ static void ctucan_mm_realize(DeviceState *dev, Error =
**errp)
if (d->cfg.iobase !=3D 0) {
sysbus_mmio_map(sbd, 0, d->cfg.iobase);
}
- if (d->cfg.irq !=3D 0) {
+ if (d->cfg.irqnum !=3D 0) {
//const char *id =3D "/machine/unattached/device[3]/gic";
- const char *id =3D "/machine/unattached/device[3]";
+ //const char *id =3D "/machine/unattached/device[3]";
+ char *id =3D d->cfg.irqctrl;
+
+ if (!id) {
+ error_setg(errp, "irqctrl object path is mandatory when irqnum=
is specified");
+ return;
+ }
+
Object *obj =3D object_resolve_path_at(container_get(qdev_get_mach=
ine(), "/peripheral"), id);
DeviceState *gicdev;
if (!obj) {
@@ -158,7 +166,7 @@ static void ctucan_mm_realize(DeviceState *dev, Error *=
*errp)
error_setg(errp, "%s is not a hotpluggable device", id);
return;
}
- sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(gicdev, d->cfg.irq));
+ sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(gicdev, d->cfg.irqnum)=
);
}
for (i =3D 0 ; i < CTUCAN_MM_CORE_COUNT; i++) {
ctucan_init(&d->ctucan_state[i], d->irq);
@@ -243,7 +251,8 @@ static Property ctucan_mm_properties[] =3D {
//DEFINE_PROP_UNSIGNED_NODEFAULT("base", CtuCanMmState, cfg.base,
// qdev_prop_uint64, uint64_t),
DEFINE_PROP_UINT64("iobase", CtuCanMmState, cfg.iobase, 0),
- DEFINE_PROP_UINT32("irq", CtuCanMmState, cfg.irq, 0),
+ DEFINE_PROP_UINT32("irqnum", CtuCanMmState, cfg.irqnum, 0),
+ DEFINE_PROP_STRING("irqctrl", CtuCanMmState, cfg.irqctrl),
DEFINE_PROP_END_OF_LIST(),
};
=20
--=20
2.39.5