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charset="utf-8" Rename CPUID_8000_0021_EAX_No_NESTED_DATA_BP to CPUID_8000_0021_EAX_NO_NESTED_DATA_BP. No functional change intended. Signed-off-by: Babu Moger Reviewed-by: Zhao Liu --- v3: New patch. --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1ff1af032e..94faff83cd 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5226,7 +5226,7 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, .features[FEAT_8000_0021_EAX] =3D - CPUID_8000_0021_EAX_No_NESTED_DATA_BP | + CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | CPUID_8000_0021_EAX_AUTO_IBRS, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 74886d1580..9eb45faa65 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1014,7 +1014,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); #define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28) =20 /* Processor ignores nested data breakpoints */ -#define CPUID_8000_0021_EAX_No_NESTED_DATA_BP (1U << 0) +#define CPUID_8000_0021_EAX_NO_NESTED_DATA_BP (1U << 0) /* LFENCE is always serializing */ #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2) /* Null Selector Clears Base */ --=20 2.34.1 From nobody Sat Nov 23 17:58:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Add the support for following RAS features bits on AMD guests. SUCCOR: Software uncorrectable error containment and recovery capability. The processor supports software containment of uncorrectable errors through context synchronizing data poisoning and deferred error interrupts. McaOverflowRecov: MCA overflow recovery support. Reviewed-by: Zhao Liu Signed-off-by: Babu Moger --- v3: No changes v2: Added reviewed by from Zhao. --- target/i386/cpu.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 94faff83cd..e88859056a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4974,6 +4974,16 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, .cache_info =3D &epyc_v4_cache_info }, + { + .version =3D 5, + .props =3D (PropValue[]) { + { "overflow-recov", "on" }, + { "succor", "on" }, + { "model-id", + "AMD EPYC-v5 Processor" }, + { /* end of list */ } + }, + }, { /* end of list */ } } }, @@ -5112,6 +5122,16 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } }, }, + { + .version =3D 5, + .props =3D (PropValue[]) { + { "overflow-recov", "on" }, + { "succor", "on" }, + { "model-id", + "AMD EPYC-Rome-v5 Processor" }, + { /* end of list */ } + }, + }, { /* end of list */ } } }, @@ -5187,6 +5207,16 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, .cache_info =3D &epyc_milan_v2_cache_info }, + { + .version =3D 3, + .props =3D (PropValue[]) { + { "overflow-recov", "on" }, + { "succor", "on" }, + { "model-id", + "AMD EPYC-Milan-v3 Processor" }, + { /* end of list */ } + }, + }, { /* end of list */ } } }, --=20 2.34.1 From nobody Sat Nov 23 17:58:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Sandipan Das CPUID leaf 0x80000022, i.e. ExtPerfMonAndDbg, advertises new performance monitoring features for AMD processors. Bit 0 of EAX indicates support for Performance Monitoring Version 2 (PerfMonV2) features. If found to be set during PMU initialization, the EBX bits can be used to determine the number of available counters for different PMUs. It also denotes the availability of global control and status registers. Add the required CPUID feature word and feature bit to allow guests to make use of the PerfMonV2 features. Signed-off-by: Sandipan Das Signed-off-by: Babu Moger Reviewed-by: Zhao Liu --- v3: No changes v2: Used OR instead of overwrite for eax and ebx. Added Zhao's Reviewed-by. --- target/i386/cpu.c | 26 ++++++++++++++++++++++++++ target/i386/cpu.h | 4 ++++ 2 files changed, 30 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e88859056a..d697c8ea6e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1227,6 +1227,22 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { .tcg_features =3D 0, .unmigratable_flags =3D 0, }, + [FEAT_8000_0022_EAX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + "perfmon-v2", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .cpuid =3D { .eax =3D 0x80000022, .reg =3D R_EAX, }, + .tcg_features =3D 0, + .unmigratable_flags =3D 0, + }, [FEAT_XSAVE] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -7040,6 +7056,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *edx =3D 0; } break; + case 0x80000022: + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + /* AMD Extended Performance Monitoring and Debug */ + if (kvm_enabled() && cpu->enable_pmu && + (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFM= ON_V2)) { + *eax |=3D CPUID_8000_0022_EAX_PERFMON_V2; + *ebx |=3D kvm_arch_get_supported_cpuid(cs->kvm_state, index, c= ount, + R_EBX) & 0xf; + } + break; case 0xC0000000: *eax =3D env->cpuid_xlevel2; *ebx =3D 0; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9eb45faa65..e0dea1ba54 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -634,6 +634,7 @@ typedef enum FeatureWord { FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */ + FEAT_8000_0022_EAX, /* CPUID[8000_0022].EAX */ FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ @@ -1022,6 +1023,9 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); 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charset="utf-8" Following feature bits are added on EPYC-Genoa-v2 model. perfmon-v2: Allow guests to make use of the PerfMonV2 features. SUCCOR : Software uncorrectable error containment and recovery capabilit= y. The processor supports software containment of uncorrectable er= rors through context synchronizing data poisoning and deferred error interrupts. McaOverflowRecov: MCA overflow recovery support. The feature details are available in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41. Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Reviewed-by: Zhao Liu Signed-off-by: Babu Moger --- v3: No changes v2: Minor typo. Added Reviewed-by from Zhao. --- target/i386/cpu.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d697c8ea6e..690efd4085 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5307,6 +5307,21 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { .xlevel =3D 0x80000022, .model_id =3D "AMD EPYC-Genoa Processor", .cache_info =3D &epyc_genoa_cache_info, + .versions =3D (X86CPUVersionDefinition[]) { + { .version =3D 1 }, + { + .version =3D 2, + .props =3D (PropValue[]) { + { "overflow-recov", "on" }, + { "succor", "on" }, + { "perfmon-v2", "on" }, + { "model-id", + "AMD EPYC-Genoa-v2 Processor" }, + { /* end of list */ } + }, + }, + { /* end of list */ } + } }, }; =20 --=20 2.34.1 From nobody Sat Nov 23 17:58:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Add following bits related Speculative Return Stack Overflow (SRSO). Guests can make use of these bits if supported. These bits are reported via CPUID Fn8000_0021_EAX. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bit Feature Description =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 27 SBPB Indicates support for the Selective Branch Predicto= r Barrier. 28 IBPB_BRTYPE MSR_PRED_CMD[IBPB] flushes all branch type predicti= ons. 29 SRSO_NO Not vulnerable to SRSO. 30 SRSO_USER_KERNEL_NO Not vulnerable to SRSO at the user-kernel boundary. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Link: https://www.amd.com/content/dam/amd/en/documents/corporate/cr/specula= tive-return-stack-overflow-whitepaper.pdf Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/= programmer-references/57238.zip Signed-off-by: Babu Moger --- v3: New patch --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 14 +++++++++++--- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 690efd4085..642e71b636 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1221,7 +1221,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "sbpb", - "ibpb-brtype", NULL, NULL, NULL, + "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, }, .cpuid =3D { .eax =3D 0x80000021, .reg =3D R_EAX, }, .tcg_features =3D 0, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e0dea1ba54..792518b62d 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1015,13 +1015,21 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU = *cpu, FeatureWord w); #define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28) =20 /* Processor ignores nested data breakpoints */ -#define CPUID_8000_0021_EAX_NO_NESTED_DATA_BP (1U << 0) +#define CPUID_8000_0021_EAX_NO_NESTED_DATA_BP (1U << 0) /* LFENCE is always serializing */ #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2) /* Null Selector Clears Base */ -#define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6) +#define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6) /* Automatic IBRS */ -#define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8) +#define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8) +/* Selective Branch Predictor Barrier */ +#define CPUID_8000_0021_EAX_SBPB (1U << 27) +/* IBPB includes branch type prediction flushing */ +#define CPUID_8000_0021_EAX_IBPB_BRTYPE (1U << 28) +/* Not vulnerable to Speculative Return Stack Overflow */ +#define CPUID_8000_0021_EAX_SRSO_NO (1U << 29) +/* Not vulnerable to SRSO at the user-kernel boundary */ +#define CPUID_8000_0021_EAX_SRSO_USER_KERNEL_NO (1U << 30) =20 /* Performance Monitoring Version 2 */ #define CPUID_8000_0022_EAX_PERFMON_V2 (1U << 0) --=20 2.34.1 From nobody Sat Nov 23 17:58:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Newer AMD CPUs support ERAPS (Enhanced Return Address Prediction Security) feature that enables the auto-clear of RSB entries on a TLB flush, context switches and VMEXITs. The number of default RSP entries is reflected in RapSize. Add the feature bit and feature word to support these features. CPUID_Fn80000021_EAX Bits Feature Description 24 ERAPS: Indicates support for enhanced return address predictor security. CPUID_Fn80000021_EBX Bits Feature Description 31-24 Reserved 23:16 RapSize: Return Address Predictor size. RapSize x 8 is the minimum number of CALL instructions software needs to execute to flush the RAP. 15-00 MicrocodePatchSize. Read-only. Reports the size of the Microcode patch in 16-byte multiples. If 0, the size of the patch is at most 5568 (15C0h) bytes. Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/= programmer-references/57238.zip Signed-off-by: Babu Moger --- v3: New patch --- target/i386/cpu.c | 11 +++++++++-- target/i386/cpu.h | 9 +++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 642e71b636..5bfa07adbf 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1220,13 +1220,19 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, "sbpb", + "eraps", NULL, NULL, "sbpb", "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, }, .cpuid =3D { .eax =3D 0x80000021, .reg =3D R_EAX, }, .tcg_features =3D 0, .unmigratable_flags =3D 0, }, + [FEAT_8000_0021_EBX] =3D { + .type =3D CPUID_FEATURE_WORD, + .cpuid =3D { .eax =3D 0x80000021, .reg =3D R_EBX, }, + .tcg_features =3D 0, + .unmigratable_flags =3D 0, + }, [FEAT_8000_0022_EAX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -7114,8 +7120,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, } break; case 0x80000021: + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; *eax =3D env->features[FEAT_8000_0021_EAX]; - *ebx =3D *ecx =3D *edx =3D 0; + *ebx =3D env->features[FEAT_8000_0021_EBX]; break; default: /* reserved values: zero */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 792518b62d..e2e10f55b2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -634,6 +634,7 @@ typedef enum FeatureWord { FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */ + FEAT_8000_0021_EBX, /* CPUID[8000_0021].EBX */ FEAT_8000_0022_EAX, /* CPUID[8000_0022].EAX */ FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ @@ -1022,6 +1023,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6) /* Automatic IBRS */ #define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8) +/* Enhanced Return Address Predictor Scurity */ +#define CPUID_8000_0021_EAX_ERAPS (1U << 24) /* Selective Branch Predictor Barrier */ #define CPUID_8000_0021_EAX_SBPB (1U << 27) /* IBPB includes branch type prediction flushing */ @@ -1031,6 +1034,12 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *= cpu, FeatureWord w); /* Not vulnerable to SRSO at the user-kernel boundary */ #define CPUID_8000_0021_EAX_SRSO_USER_KERNEL_NO (1U << 30) =20 +/* + * Return Address Predictor size. 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charset="utf-8" Add the support for AMD EPYC zen 5 processors (EPYC-Turin). Add the following new feature bits on top of the feature bits from the previous generation EPYC models. movdiri : Move Doubleword as Direct Store Instruction movdir64b : Move 64 Bytes as Direct Store Instruction avx512-vp2intersect : AVX512 Vector Pair Intersection to a Pair of Mask Register avx-vnni : AVX VNNI Instruction sbpb : Selective Branch Predictor Barrier ibpb-brtype : IBPB includes branch type prediction flushing srso-user-kernel-no : Not vulnerable to SRSO at the user-kernel boundary eraps : Enhanced Return Address Predictor Security rapsize : Return Address Predictor size. RapSize x 8 is the minimum number of CALL instructions software needs to execute to flush the RAP Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/= programmer-references/57238.zip Link: https://www.amd.com/content/dam/amd/en/documents/corporate/cr/specula= tive-return-stack-overflow-whitepaper.pdf Signed-off-by: Babu Moger --- v3: Removed Zhao's Reviewed-by as the patch has changed, Added sbpb, ibpb-brtype, srso-user-kernel-no, eraps, rapsize v2: Fixed minor typo. Added Zhao's Reviewed-by. --- target/i386/cpu.c | 136 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5bfa07adbf..eb49650450 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2411,6 +2411,60 @@ static const CPUCaches epyc_genoa_cache_info =3D { }, }; =20 +static const CPUCaches epyc_turin_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + .type =3D DATA_CACHE, + .level =3D 1, + .size =3D 48 * KiB, + .line_size =3D 64, + .associativity =3D 12, + .partitions =3D 1, + .sets =3D 64, + .lines_per_tag =3D 1, + .self_init =3D 1, + .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 64, + .lines_per_tag =3D 1, + .self_init =3D 1, + .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 2, + .size =3D 1 * MiB, + .line_size =3D 64, + .associativity =3D 16, + .partitions =3D 1, + .sets =3D 1024, + .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 3, + .size =3D 32 * MiB, + .line_size =3D 64, + .associativity =3D 16, + .partitions =3D 1, + .sets =3D 32768, + .lines_per_tag =3D 1, + .self_init =3D true, + .inclusive =3D true, + .complex_indexing =3D false, + .share_level =3D CPU_TOPO_LEVEL_DIE, + }, +}; + /* The following VMX features are not supported by KVM and are left out in= the * CPU definitions: * @@ -5329,6 +5383,88 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } } }, + { + .name =3D "EPYC-Turin", + .level =3D 0xd, + .vendor =3D CPUID_VENDOR_AMD, + .family =3D 26, + .model =3D 0, + .stepping =3D 0, + .features[FEAT_1_ECX] =3D + CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | + CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | + CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | + CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | + CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | + CPUID_EXT_SSE3, + .features[FEAT_1_EDX] =3D + CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUS= H | + CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | + CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | + CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | + CPUID_VME | CPUID_FP87, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AV= X2 | + CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | + CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | + CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_= ADX | + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | + CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | + CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | + CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, + .features[FEAT_7_0_ECX] =3D + CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX= _PKU | + CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | + CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | + CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | + CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | + CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_MOVDIRI | + CPUID_7_0_ECX_MOVDIR64B, + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_AVX512_VP2INTERSECT, + .features[FEAT_7_1_EAX] =3D + CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | + CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | + CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | + CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0007_EBX] =3D + CPUID_8000_0007_EBX_OVERFLOW_RECOV | CPUID_8000_0007_EBX_SUCCO= R, + .features[FEAT_8000_0008_EBX] =3D + CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | + CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | + CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | + CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | + CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, + .features[FEAT_8000_0021_EAX] =3D + CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | + CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | + CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | + CPUID_8000_0021_EAX_AUTO_IBRS | + CPUID_8000_0021_EAX_ERAPS | CPUID_8000_0021_EAX_SBPB | + CPUID_8000_0021_EAX_IBPB_BRTYPE | + CPUID_8000_0021_EAX_SRSO_USER_KERNEL_NO, + .features[FEAT_8000_0021_EBX] =3D + CPUID_8000_0021_EBX_RAPSIZE, + .features[FEAT_8000_0022_EAX] =3D + CPUID_8000_0022_EAX_PERFMON_V2, + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, + .features[FEAT_SVM] =3D + CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | + CPUID_SVM_SVME_ADDR_CHK, + .xlevel =3D 0x80000022, + .model_id =3D "AMD EPYC-Turin Processor", + .cache_info =3D &epyc_turin_cache_info, + }, }; =20 /* --=20 2.34.1