From nobody Sun Nov 24 10:49:18 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D11EE1AC42C for ; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591451; cv=none; b=W7021lWQdn2SWtfo9TXaTOQDZOGDrocvB668ZMIHJ202lwjZb2qamNM+VmcqIPk9sNkmrDcoVb9IHO+lQtLS5bdcc2tUsV+2Nw/6dOey+CdSa6L4Md9YgkpTjGC6lFzhlHrFPzrJo8K2NApb/bm5baxsAjVrFQTRoGqrWI0oSGY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591451; c=relaxed/simple; bh=CEl4oM3Rm1Ngnn1c1bxKZGz/K6MIliYHY5uTJrRSgeo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MdtmqGUFlbBnUfvtx0u9z3M0yTf00m2qA4U01+DdQYzNai+IbvP/+7RNz2LEMqEJ/GXqb1+cftou035wPCI5+qk6eeWS0xNOnbAWRulWu/nvA81XCMnuJZ2fD8J+T/6gC4ZMC4qzUFpQWuzw1OPvjItAVopK+bmoZuTcvDkygA0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l1Sb0/Ug; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l1Sb0/Ug" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6D896C4AF18; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723591451; bh=CEl4oM3Rm1Ngnn1c1bxKZGz/K6MIliYHY5uTJrRSgeo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l1Sb0/UgAp1j4TWTmQwWMZLBjlCigLckncY4u2VLeo8u85jUR50t9W2MfITOTjxjC OPNULN6qQGJUDWFwVUO8QZIgjiJQZo1tZIPR73rQk8Pu8XbM5SdBKM5qqXSFArwY5M OGansVLP2kQpE6L2qAufYT55Mx6vULSL3rEguxugBWLM+rlmZURvJI6BXHz1VahJfn EJzjPkVwdnAUZhBXZy49NiXHRm8HyBAjUPY/6i4MN37NhW4tP66h+a8aED+IjEM4a+ awWfBabLDWWLYeybHpO6IDTuloWBbDziRjVcpp1MQ8GOnwAd09uz8tfiopYcjbaldV 7jySQTa5RUcGg== Received: from mchehab by mail.kernel.org with local (Exim 4.98) (envelope-from ) id 1se0s5-00000002asA-1DSb; Wed, 14 Aug 2024 01:24:09 +0200 From: Mauro Carvalho Chehab To: Cc: Jonathan Cameron , Shiju Jose , Mauro Carvalho Chehab , "Michael S. Tsirkin" , Ani Sinha , Igor Mammedov , linux-kernel@vger.kernel.org, qemu-devel@nongnu.org Subject: [PATCH v7 01/10] acpi/generic_event_device: add an APEI error device Date: Wed, 14 Aug 2024 01:23:23 +0200 Message-ID: <0be6db8d06b3abab551f24dcc645d46d72d3f668.1723591201.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Adds a generic error device to handle generic hardware error events as specified at ACPI 6.5 specification at 18.3.2.7.2: https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html#event-not= ification-for-generic-error-sources using HID PNP0C33. The PNP0C33 device is used to report hardware errors to the guest via ACPI APEI Generic Hardware Error Source (GHES). Co-authored-by: Mauro Carvalho Chehab Co-authored-by: Jonathan Cameron Signed-off-by: Jonathan Cameron Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Igor Mammedov --- hw/acpi/aml-build.c | 10 ++++++++++ hw/acpi/generic_event_device.c | 8 ++++++++ include/hw/acpi/acpi_dev_interface.h | 1 + include/hw/acpi/aml-build.h | 2 ++ include/hw/acpi/generic_event_device.h | 1 + 5 files changed, 22 insertions(+) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 6d4517cfbe3d..cb167523859f 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -2520,3 +2520,13 @@ Aml *aml_i2c_serial_bus_device(uint16_t address, con= st char *resource_source) =20 return var; } + +/* ACPI 5.0: 18.3.2.6.2 Event Notification For Generic Error Sources */ +Aml *aml_error_device(void) +{ + Aml *dev =3D aml_device(ACPI_APEI_ERROR_DEVICE); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C33"))); + aml_append(dev, aml_name_decl("_UID", aml_int(0))); + + return dev; +} diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index 15b4c3ebbf24..1673e9695be3 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -26,6 +26,7 @@ static const uint32_t ged_supported_events[] =3D { ACPI_GED_PWR_DOWN_EVT, ACPI_GED_NVDIMM_HOTPLUG_EVT, ACPI_GED_CPU_HOTPLUG_EVT, + ACPI_GED_ERROR_EVT }; =20 /* @@ -116,6 +117,11 @@ void build_ged_aml(Aml *table, const char *name, Hotpl= ugHandler *hotplug_dev, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), aml_int(0x80))); break; + case ACPI_GED_ERROR_EVT: + aml_append(if_ctx, + aml_notify(aml_name(ACPI_APEI_ERROR_DEVICE), + aml_int(0x80))); + break; case ACPI_GED_NVDIMM_HOTPLUG_EVT: aml_append(if_ctx, aml_notify(aml_name("\\_SB.NVDR"), @@ -295,6 +301,8 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev, Acp= iEventStatusBits ev) sel =3D ACPI_GED_MEM_HOTPLUG_EVT; } else if (ev & ACPI_POWER_DOWN_STATUS) { sel =3D ACPI_GED_PWR_DOWN_EVT; + } else if (ev & ACPI_GENERIC_ERROR) { + sel =3D ACPI_GED_ERROR_EVT; } else if (ev & ACPI_NVDIMM_HOTPLUG_STATUS) { sel =3D ACPI_GED_NVDIMM_HOTPLUG_EVT; } else if (ev & ACPI_CPU_HOTPLUG_STATUS) { diff --git a/include/hw/acpi/acpi_dev_interface.h b/include/hw/acpi/acpi_de= v_interface.h index 68d9d15f50aa..8294f8f0ccca 100644 --- a/include/hw/acpi/acpi_dev_interface.h +++ b/include/hw/acpi/acpi_dev_interface.h @@ -13,6 +13,7 @@ typedef enum { ACPI_NVDIMM_HOTPLUG_STATUS =3D 16, ACPI_VMGENID_CHANGE_STATUS =3D 32, ACPI_POWER_DOWN_STATUS =3D 64, + ACPI_GENERIC_ERROR =3D 128, } AcpiEventStatusBits; =20 #define TYPE_ACPI_DEVICE_IF "acpi-device-interface" diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index a3784155cb33..44d1a6af0c69 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -252,6 +252,7 @@ struct CrsRangeSet { /* Consumer/Producer */ #define AML_SERIAL_BUS_FLAG_CONSUME_ONLY (1 << 1) =20 +#define ACPI_APEI_ERROR_DEVICE "GEDD" /** * init_aml_allocator: * @@ -382,6 +383,7 @@ Aml *aml_dma(AmlDmaType typ, AmlDmaBusMaster bm, AmlTra= nsferSize sz, uint8_t channel); Aml *aml_sleep(uint64_t msec); Aml *aml_i2c_serial_bus_device(uint16_t address, const char *resource_sour= ce); +Aml *aml_error_device(void); =20 /* Block AML object primitives */ Aml *aml_scope(const char *name_format, ...) G_GNUC_PRINTF(1, 2); diff --git a/include/hw/acpi/generic_event_device.h b/include/hw/acpi/gener= ic_event_device.h index 40af3550b56d..9ace8fe70328 100644 --- a/include/hw/acpi/generic_event_device.h +++ b/include/hw/acpi/generic_event_device.h @@ -98,6 +98,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED) #define ACPI_GED_PWR_DOWN_EVT 0x2 #define ACPI_GED_NVDIMM_HOTPLUG_EVT 0x4 #define ACPI_GED_CPU_HOTPLUG_EVT 0x8 +#define ACPI_GED_ERROR_EVT 0x10 =20 typedef struct GEDState { MemoryRegion evt; --=20 2.46.0 From nobody Sun Nov 24 10:49:18 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6D7D1ABED7 for ; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591451; cv=none; b=Om+07aXTZTvuVQE2Cn0lYTGZOh1zG75hHH7gXwTpzw6KixVYjCViMttI6Kn4LR6180bTPHIky8zOGhehdgv6cVALsKJFxVuSoGaxX2qaUd48zcCZyinYp1jxNkEhWVBbRQbsv+NYZACks7SXjq3Gd7gWuhSR/ZUEKjPK3976cho= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591451; c=relaxed/simple; bh=45MNHs7xwOCcf8jbuaI6e0aY9LF+xP8P0gDiRaHXf2s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MjIZmkqYKY2UTMR0dXtajnCt0DO4EqcpT7TlwlzeCGPortV4a5QXT3F3PK44MxatPfPn5OKP4oo47F1D0n9VgJ8TZaDo5BKaUVJ1XkEqczvsF/s+JkhjPg0kUq4vj/6NcESYgGQ92x8zvXH2Dolx1iPXB/bjQCja/wFGH4U8Hgs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Atx6KHHt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Atx6KHHt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4559EC4AF0C; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723591451; bh=45MNHs7xwOCcf8jbuaI6e0aY9LF+xP8P0gDiRaHXf2s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Atx6KHHtIoHUgD/4nzZ31kAnVXA6iKxU7WSpvFg2k9dn7aM76Do/ZsijOgH4ecFmE oNMnayp1HG0NSTLZ4pPlqWwS1Jd7z3TXGqGtw7TQRgvrLok5UCWkM2oCJqCbhxCRxw P3hpCkFN9PSDAc6HiwFE+KRQYT20PldRuJ9GVBvPwvD2OmAB+p8r7I+zZL6ZoehpHB P2hjZWZd2UZbAtdV0LieG6BWr27QtJJ855sbUbmC1VIvIe6wm6tJZJopc6XWhOzkiq LkqH/QgDD6d3suzn6+4LxuFsMaG2AmJznw71zkrWP7oBcc7gax28lLMHRzNYZA54KO IZKRKzpToFT8Q== Received: from mchehab by mail.kernel.org with local (Exim 4.98) (envelope-from ) id 1se0s5-00000002asD-1KPM; Wed, 14 Aug 2024 01:24:09 +0200 From: Mauro Carvalho Chehab To: Cc: Jonathan Cameron , Shiju Jose , Mauro Carvalho Chehab , "Michael S. Tsirkin" , Ani Sinha , Dongjiu Geng , Igor Mammedov , Peter Maydell , Shannon Zhao , linux-kernel@vger.kernel.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v7 02/10] arm/virt: Wire up a GED error device for ACPI / GHES Date: Wed, 14 Aug 2024 01:23:24 +0200 Message-ID: <41d72570cc4e1fa3239ebf61d91240ebbaba838f.1723591201.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Adds support to ARM virtualization to allow handling generic error ACPI Event via GED & error source device. It is aligned with Linux Kernel patch: https://lore.kernel.org/lkml/1272350481-27951-8-git-send-email-ying.huang@i= ntel.com/ Co-authored-by: Mauro Carvalho Chehab Co-authored-by: Jonathan Cameron Signed-off-by: Jonathan Cameron Signed-off-by: Mauro Carvalho Chehab Acked-by: Igor Mammedov --- hw/acpi/ghes.c | 3 +++ hw/arm/virt-acpi-build.c | 1 + hw/arm/virt.c | 12 +++++++++++- include/hw/acpi/ghes.h | 3 +++ include/hw/arm/virt.h | 1 + 5 files changed, 19 insertions(+), 1 deletion(-) diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index e9511d9b8f71..13b105c5d02d 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -444,6 +444,9 @@ int acpi_ghes_record_errors(uint8_t source_id, uint64_t= physical_address) return ret; } =20 +NotifierList acpi_generic_error_notifiers =3D + NOTIFIER_LIST_INITIALIZER(error_device_notifiers); + bool acpi_ghes_present(void) { AcpiGedState *acpi_ged_state; diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index f76fb117adff..1769467d23b2 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -858,6 +858,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } =20 acpi_dsdt_add_power_button(scope); + aml_append(scope, aml_error_device()); #ifdef CONFIG_TPM acpi_dsdt_add_tpm(scope, vms); #endif diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 687fe0bb8bc9..22448e5c5b73 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -677,7 +677,7 @@ static inline DeviceState *create_acpi_ged(VirtMachineS= tate *vms) DeviceState *dev; MachineState *ms =3D MACHINE(vms); int irq =3D vms->irqmap[VIRT_ACPI_GED]; - uint32_t event =3D ACPI_GED_PWR_DOWN_EVT; + uint32_t event =3D ACPI_GED_PWR_DOWN_EVT | ACPI_GED_ERROR_EVT; =20 if (ms->ram_slots) { event |=3D ACPI_GED_MEM_HOTPLUG_EVT; @@ -1009,6 +1009,13 @@ static void virt_powerdown_req(Notifier *n, void *op= aque) } } =20 +static void virt_generic_error_req(Notifier *n, void *opaque) +{ + VirtMachineState *s =3D container_of(n, VirtMachineState, generic_erro= r_notifier); + + acpi_send_event(s->acpi_dev, ACPI_GENERIC_ERROR); +} + static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, uint32_t phandle) { @@ -2385,6 +2392,9 @@ static void machvirt_init(MachineState *machine) =20 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)= ) { vms->acpi_dev =3D create_acpi_ged(vms); + vms->generic_error_notifier.notify =3D virt_generic_error_req; + notifier_list_add(&acpi_generic_error_notifiers, + &vms->generic_error_notifier); } else { create_gpio_devices(vms, VIRT_GPIO, sysmem); } diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h index 674f6958e905..fb80897e7eac 100644 --- a/include/hw/acpi/ghes.h +++ b/include/hw/acpi/ghes.h @@ -23,6 +23,9 @@ #define ACPI_GHES_H =20 #include "hw/acpi/bios-linker-loader.h" +#include "qemu/notify.h" + +extern NotifierList acpi_generic_error_notifiers; =20 /* * Values for Hardware Error Notification Type field diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index a4d937ed45ac..ad9f6e94dcc5 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -175,6 +175,7 @@ struct VirtMachineState { DeviceState *gic; DeviceState *acpi_dev; Notifier powerdown_notifier; + Notifier generic_error_notifier; PCIBus *bus; char *oem_id; char *oem_table_id; --=20 2.46.0 From nobody Sun Nov 24 10:49:18 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC81B1AC420 for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZUr+YmaJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6165BC4AF0F; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723591451; bh=Yx0IAnqY4alORAX037P9zQP5s04TdYEo59HvelobeeI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZUr+YmaJCFs7NxYF7N8cwQAzhPDgL1c4NtqDzd6X9FgnfgamSSCMERUwNVyBkZ92L xVbqxMzglhUTBnRE2SM2qdgfcjlTtj5+a+KHzXlOhUEVIJy1kVhIHKM66sEFWBs1df i4XHSdAChTUoi65BHlooq2JmfWk2eKOG7CgVjUIeFBCATRtLZglNS6erIoQVPRatwx l5TxDuDNYgL3kZ4OJ/pEETqXrOcmi/L+qG0F/0abrFI1dUnUwpt66VOaic41OHSLtC AUC67SSMzuwPFFszjIEr5QAu6lH4wAmhu9Hu2qq0H2mThYCqBy+tanlPO1/UU/VX0B HfA90xDUmTT5A== Received: from mchehab by mail.kernel.org with local (Exim 4.98) (envelope-from ) id 1se0s5-00000002asG-1RHx; Wed, 14 Aug 2024 01:24:09 +0200 From: Mauro Carvalho Chehab To: Cc: Jonathan Cameron , Shiju Jose , "Michael S. Tsirkin" , Ani Sinha , Dongjiu Geng , Igor Mammedov , linux-kernel@vger.kernel.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab Subject: [PATCH v7 03/10] acpi/ghes: Add support for GED error device Date: Wed, 14 Aug 2024 01:23:25 +0200 Message-ID: X-Mailer: git-send-email 2.46.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" From: Jonathan Cameron As a GED error device is now defined, add another type of notification. Add error notification to GHES v2 using a GED error device GED triggered via interrupt. [mchehab: do some cleanups at ACPI_HEST_SRC_ID_* checks and rename HEST event to better identify GED interrupt OSPM] Signed-off-by: Jonathan Cameron Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Igor Mammedov --- hw/acpi/ghes.c | 12 +++++++++--- include/hw/acpi/ghes.h | 3 ++- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index 13b105c5d02d..280674452a60 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -34,8 +34,8 @@ /* The max size in bytes for one error block */ #define ACPI_GHES_MAX_RAW_DATA_LENGTH (1 * KiB) =20 -/* Now only support ARMv8 SEA notification type error source */ -#define ACPI_GHES_ERROR_SOURCE_COUNT 1 +/* Support ARMv8 SEA notification type error source and GPIO interrupt. */ +#define ACPI_GHES_ERROR_SOURCE_COUNT 2 =20 /* Generic Hardware Error Source version 2 */ #define ACPI_GHES_SOURCE_GENERIC_ERROR_V2 10 @@ -290,6 +290,9 @@ void build_ghes_error_table(GArray *hardware_errors, BI= OSLinker *linker) static void build_ghes_v2(GArray *table_data, int source_id, BIOSLinker *l= inker) { uint64_t address_offset; + + assert(source_id < ACPI_HEST_SRC_ID_RESERVED); + /* * Type: * Generic Hardware Error Source version 2(GHESv2 - Type 10) @@ -327,6 +330,9 @@ static void build_ghes_v2(GArray *table_data, int sourc= e_id, BIOSLinker *linker) */ build_ghes_hw_error_notification(table_data, ACPI_GHES_NOTIFY_SEA); break; + case ACPI_HEST_SRC_ID_GED: + build_ghes_hw_error_notification(table_data, ACPI_GHES_NOTIFY_GPIO= ); + break; default: error_report("Not support this error source"); abort(); @@ -370,6 +376,7 @@ void acpi_build_hest(GArray *table_data, BIOSLinker *li= nker, /* Error Source Count */ build_append_int_noprefix(table_data, ACPI_GHES_ERROR_SOURCE_COUNT, 4); build_ghes_v2(table_data, ACPI_HEST_SRC_ID_SEA, linker); + build_ghes_v2(table_data, ACPI_HEST_SRC_ID_GED, linker); =20 acpi_table_end(linker, &table); } @@ -406,7 +413,6 @@ int acpi_ghes_record_errors(uint8_t source_id, uint64_t= physical_address) start_addr =3D le64_to_cpu(ags->ghes_addr_le); =20 if (physical_address) { - if (source_id < ACPI_HEST_SRC_ID_RESERVED) { start_addr +=3D source_id * sizeof(uint64_t); } diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h index fb80897e7eac..419a97d5cbd9 100644 --- a/include/hw/acpi/ghes.h +++ b/include/hw/acpi/ghes.h @@ -59,9 +59,10 @@ enum AcpiGhesNotifyType { ACPI_GHES_NOTIFY_RESERVED =3D 12 }; =20 +/* Those are used as table indexes when building GHES tables */ enum { ACPI_HEST_SRC_ID_SEA =3D 0, - /* future ids go here */ + ACPI_HEST_SRC_ID_GED, ACPI_HEST_SRC_ID_RESERVED, }; =20 --=20 2.46.0 From nobody Sun Nov 24 10:49:18 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D34CD1AC42E for ; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591451; cv=none; b=r6VOS2nXiRuLZBwgR8UNv2ldsgJsj/3jz3XKEw2puAmhRhildUpl6K5EfYinqm4f5haA5oTAQ+4OozQcMboLs4F9jmxqynVaaX7Xblp4gSEGEmjXEL7AX9R/OmLo4O64+Tk6ABlUJxzxzATfSAOS/rrxaw0qTgBIBrSlta2gW5o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591451; c=relaxed/simple; bh=2z1VY27Mlf+Ktflz2/S01CQWE6SvekaFwpMwQFZEF9g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VIvB5bIyrzQ0VJLJhB4bPAcX9atN0rk2rxXSxWd3Hh2J5q2/brgEygZlMj5tMearFoUdSy/ROTRZfm/qUcxarh6a/Aoz8P1He1+tAdmmxRduhQQEbizOzAWuGW1Le4HIlTOAVzHha1F4xQykxMkNPqzt0bDgkKIXsAxm9GfvuoA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=i/WiMJSv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i/WiMJSv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6A861C4AF15; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723591451; bh=2z1VY27Mlf+Ktflz2/S01CQWE6SvekaFwpMwQFZEF9g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i/WiMJSvuEsSk3SOEaoLvUhBQQTlA59MdGOB2LGDcxTWHu6PZNLNk7gX1J4ZIEVYl z5BeAFokMGZLhjpQyrLFy7zhKr6x4pJoeHNh3rnIFI5EKH43lCpD1RhnuVDVQJN6Dr ZMOqzNIe0Xf2VsGR66WSz29sk5ye8tqGpROr8Y7DLMlS0Lpx7ius/6F2JMmiLv/awL p9kHi2tE7xvNFBgLDOOuklaWxwY+kNMSAqXNo45dXRP18n/T2tOfFVtsMgHaxfCgJa mTSNt0QlQco9RtA3oMMx5faoyR79OMccGtiJ6Ss2v8QG+9jsIfg2x0q9UAXsClfJpt NbK7jtEcgqpVg== Received: from mchehab by mail.kernel.org with local (Exim 4.98) (envelope-from ) id 1se0s5-00000002asM-1YM1; Wed, 14 Aug 2024 01:24:09 +0200 From: Mauro Carvalho Chehab To: Cc: Jonathan Cameron , Shiju Jose , Mauro Carvalho Chehab , "Michael S. Tsirkin" , Ani Sinha , Dongjiu Geng , Eric Blake , Igor Mammedov , Markus Armbruster , Michael Roth , Paolo Bonzini , Peter Maydell , linux-kernel@vger.kernel.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v7 04/10] qapi/acpi-hest: add an interface to do generic CPER error injection Date: Wed, 14 Aug 2024 01:23:26 +0200 Message-ID: X-Mailer: git-send-email 2.46.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Creates a QMP command to be used for generic ACPI APEI hardware error injection (HEST) via GHESv2. The actual GHES code will be added at the followup patch. Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Shiju Jose Reviewed-by: Jonathan Cameron --- MAINTAINERS | 7 +++++++ hw/acpi/Kconfig | 5 +++++ hw/acpi/ghes_cper.c | 33 +++++++++++++++++++++++++++++++++ hw/acpi/ghes_cper_stub.c | 19 +++++++++++++++++++ hw/acpi/meson.build | 2 ++ hw/arm/Kconfig | 5 +++++ include/hw/acpi/ghes.h | 1 + qapi/acpi-hest.json | 36 ++++++++++++++++++++++++++++++++++++ qapi/meson.build | 1 + qapi/qapi-schema.json | 1 + 10 files changed, 110 insertions(+) create mode 100644 hw/acpi/ghes_cper.c create mode 100644 hw/acpi/ghes_cper_stub.c create mode 100644 qapi/acpi-hest.json diff --git a/MAINTAINERS b/MAINTAINERS index 3584d6a6c6da..1d8091818899 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2077,6 +2077,13 @@ F: hw/acpi/ghes.c F: include/hw/acpi/ghes.h F: docs/specs/acpi_hest_ghes.rst =20 +ACPI/HEST/GHES/ARM processor CPER +R: Mauro Carvalho Chehab +S: Maintained +F: hw/arm/ghes_cper.c +F: hw/acpi/ghes_cper_stub.c +F: qapi/acpi-hest.json + ppc4xx L: qemu-ppc@nongnu.org S: Orphan diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig index e07d3204eb36..73ffbb82c150 100644 --- a/hw/acpi/Kconfig +++ b/hw/acpi/Kconfig @@ -51,6 +51,11 @@ config ACPI_APEI bool depends on ACPI =20 +config GHES_CPER + bool + depends on ACPI_APEI + default y + config ACPI_PCI bool depends on ACPI && PCI diff --git a/hw/acpi/ghes_cper.c b/hw/acpi/ghes_cper.c new file mode 100644 index 000000000000..92ca84d738de --- /dev/null +++ b/hw/acpi/ghes_cper.c @@ -0,0 +1,33 @@ +/* + * CPER payload parser for error injection + * + * Copyright(C) 2024 Huawei LTD. + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" + +#include "qemu/base64.h" +#include "qemu/error-report.h" +#include "qemu/uuid.h" +#include "qapi/qapi-commands-acpi-hest.h" +#include "hw/acpi/ghes.h" + +void qmp_ghes_cper(const char *qmp_cper, + Error **errp) +{ + + uint8_t *cper; + size_t len; + + cper =3D qbase64_decode(qmp_cper, -1, &len, errp); + if (!cper) { + error_setg(errp, "missing GHES CPER payload"); + return; + } + + /* TODO: call a function at ghes */ +} diff --git a/hw/acpi/ghes_cper_stub.c b/hw/acpi/ghes_cper_stub.c new file mode 100644 index 000000000000..36138c462ac9 --- /dev/null +++ b/hw/acpi/ghes_cper_stub.c @@ -0,0 +1,19 @@ +/* + * Stub interface for CPER payload parser for error injection + * + * Copyright(C) 2024 Huawei LTD. + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qapi/qapi-commands-acpi-hest.h" +#include "hw/acpi/ghes.h" + +void qmp_ghes_cper(const char *cper, Error **errp) +{ + error_setg(errp, "GHES QMP error inject is not compiled in"); +} diff --git a/hw/acpi/meson.build b/hw/acpi/meson.build index fa5c07db9068..6cbf430eb66d 100644 --- a/hw/acpi/meson.build +++ b/hw/acpi/meson.build @@ -34,4 +34,6 @@ endif system_ss.add(when: 'CONFIG_ACPI', if_false: files('acpi-stub.c', 'aml-bui= ld-stub.c', 'ghes-stub.c', 'acpi_interface.c')) system_ss.add(when: 'CONFIG_ACPI_PCI_BRIDGE', if_false: files('pci-bridge-= stub.c')) system_ss.add_all(when: 'CONFIG_ACPI', if_true: acpi_ss) +system_ss.add(when: 'CONFIG_GHES_CPER', if_true: files('ghes_cper.c')) +system_ss.add(when: 'CONFIG_GHES_CPER', if_false: files('ghes_cper_stub.c'= )) system_ss.add(files('acpi-qmp-cmds.c')) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 1ad60da7aa2d..bed6ba27d715 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -712,3 +712,8 @@ config ARMSSE select UNIMP select SSE_COUNTER select SSE_TIMER + +config GHES_CPER + bool + depends on ARM + default y if AARCH64 diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h index 419a97d5cbd9..99d12d69c864 100644 --- a/include/hw/acpi/ghes.h +++ b/include/hw/acpi/ghes.h @@ -23,6 +23,7 @@ #define ACPI_GHES_H =20 #include "hw/acpi/bios-linker-loader.h" +#include "qapi/error.h" #include "qemu/notify.h" =20 extern NotifierList acpi_generic_error_notifiers; diff --git a/qapi/acpi-hest.json b/qapi/acpi-hest.json new file mode 100644 index 000000000000..91296755d285 --- /dev/null +++ b/qapi/acpi-hest.json @@ -0,0 +1,36 @@ +# -*- Mode: Python -*- +# vim: filetype=3Dpython + +## +# =3D GHESv2 CPER Error Injection +# +# Defined since ACPI Specification 6.2, +# section 18.3.2.8 Generic Hardware Error Source version 2. See: +# +# https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html#generi= c-hardware-error-source-version-2-ghesv2-type-10 +## + + +## +# @ghes-cper: +# +# Inject a CPER error data to be filled according to ACPI 6.2 +# spec via GHESv2. +# +# @cper: contains a base64 encoded string with raw data for a single CPER +# record with Generic Error Status Block, Generic Error Data Entry and +# generic error data payload, as described at +# https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.= html#format +# +# Features: +# +# @unstable: This command is experimental. +# +# Since: 9.2 +## +{ 'command': 'ghes-cper', + 'data': { + 'cper': 'str' + }, + 'features': [ 'unstable' ] +} diff --git a/qapi/meson.build b/qapi/meson.build index e7bc54e5d047..35cea6147262 100644 --- a/qapi/meson.build +++ b/qapi/meson.build @@ -59,6 +59,7 @@ qapi_all_modules =3D [ if have_system qapi_all_modules +=3D [ 'acpi', + 'acpi-hest', 'audio', 'cryptodev', 'qdev', diff --git a/qapi/qapi-schema.json b/qapi/qapi-schema.json index b1581988e4eb..baf19ab73afe 100644 --- a/qapi/qapi-schema.json +++ b/qapi/qapi-schema.json @@ -75,6 +75,7 @@ { 'include': 'misc-target.json' } { 'include': 'audio.json' } { 'include': 'acpi.json' } +{ 'include': 'acpi-hest.json' } { 'include': 'pci.json' } { 'include': 'stats.json' } { 'include': 'virtio.json' } --=20 2.46.0 From nobody Sun Nov 24 10:49:18 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E75B1AC43C for ; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591452; cv=none; b=TyuQo0+dV91oMxCItCKI1+/5VCvMQRDt8+QaneGivPmO36JpF+CIsN8vvI6uLONmiUynCxURQe5OqhirLYSwoOaKqLaQ5wgsOiyaVSXgRJECYFxXS+F95d7eTie0zy59KugX5gVvLXLvzEbKwAR9DuqhHOcttQvv7eCwYGY1uB4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591452; c=relaxed/simple; bh=bwenX6wHabHpmTrica6FvqsqNFRBHQuBfjqww4NqP6A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=G92rUeRDoyDGyj4u4XMO0zLdiyH0iyFnDcNJGnc6aPewSnNePAqcRQGRuEBPd5dY7FXKbetw1iLd4P0JjHM/EnWmJELFsL5vg7VNYUVOCFFacZwXWjc5UIyFnWpl6I7h7k6fnyZXg4oaFGsJVx8cfKKFiT7cSBa4+WsUeUP4mNU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Sll9plgX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Sll9plgX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5F569C4AF12; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723591451; bh=bwenX6wHabHpmTrica6FvqsqNFRBHQuBfjqww4NqP6A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Sll9plgXVrmRbPMFy9b7MlARCn2iU/5z6SpbKAxJWaayV1PxdhyD5Arc5x6z+aERM EMVeJ8P1WspoXhJK5fITj5JeBwJsxVgHr4VnvRFMHj/6av9/UJqWNgw1GtJn787WR6 g2QXNWbHOWLa/6ng70BDpNNXEe6MzuPOIagn5wz0PnDX0rPp2w0N1+9aMfSEmy+6J2 +IDpTAoQVdvTKovORFNhWb9P72X+uVOGgouxDK8JCV+Y21r352y5yMXeNbeGpbGbSY VkbO5Wt/xhkga0HVsu4Es26esD65AxL/7HtwMVJY4W1RB1w0A2msp7hrLiRZouBtIX 8sb+VgUsVdkew== Received: from mchehab by mail.kernel.org with local (Exim 4.98) (envelope-from ) id 1se0s5-00000002asQ-1fJg; Wed, 14 Aug 2024 01:24:09 +0200 From: Mauro Carvalho Chehab To: Cc: Jonathan Cameron , Shiju Jose , Mauro Carvalho Chehab , "Michael S. Tsirkin" , Ani Sinha , Dongjiu Geng , Igor Mammedov , Peter Maydell , Shannon Zhao , linux-kernel@vger.kernel.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v7 05/10] acpi/ghes: rework the logic to handle HEST source ID Date: Wed, 14 Aug 2024 01:23:27 +0200 Message-ID: <9f5843c6f774035e80a7a19e0091c347edff9d02.1723591201.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" The current logic is based on a lot of duct tape, with offsets calculated based on one define with the number of source IDs and an enum. Rewrite the logic in a way that it would be more resilient of code changes, by moving the source ID count to an enum and make the offset calculus more explicit. Such change was inspired on a patch from Jonathan Cameron splitting the logic to get the CPER address on a separate function, as this will be needed to support generic error injection. Signed-off-by: Mauro Carvalho Chehab --- hw/acpi/ghes-stub.c | 3 +- hw/acpi/ghes.c | 204 +++++++++++++++++++++++---------------- hw/arm/virt-acpi-build.c | 5 +- include/hw/acpi/ghes.h | 17 ++-- 4 files changed, 133 insertions(+), 96 deletions(-) diff --git a/hw/acpi/ghes-stub.c b/hw/acpi/ghes-stub.c index c315de1802d6..8762449870b5 100644 --- a/hw/acpi/ghes-stub.c +++ b/hw/acpi/ghes-stub.c @@ -11,7 +11,8 @@ #include "qemu/osdep.h" #include "hw/acpi/ghes.h" =20 -int acpi_ghes_record_errors(uint8_t source_id, uint64_t physical_address) +int acpi_ghes_record_errors(enum AcpiGhesNotifyType notify, + uint64_t physical_address) { return -1; } diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index 280674452a60..f93499d7d647 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -28,14 +28,23 @@ #include "hw/nvram/fw_cfg.h" #include "qemu/uuid.h" =20 -#define ACPI_GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors" -#define ACPI_GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" +#define ACPI_HW_ERROR_FW_CFG_FILE "etc/hardware_errors" +#define ACPI_HW_ERROR_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" +#define ACPI_HEST_ADDR_FW_CFG_FILE "etc/acpi_table_hest_addr" =20 /* The max size in bytes for one error block */ #define ACPI_GHES_MAX_RAW_DATA_LENGTH (1 * KiB) =20 -/* Support ARMv8 SEA notification type error source and GPIO interrupt. */ -#define ACPI_GHES_ERROR_SOURCE_COUNT 2 +/* + * ID numbers used to fill HEST source ID field + */ +enum AcpiHestSourceId { + ACPI_HEST_SRC_ID_SEA, + ACPI_HEST_SRC_ID_GED, + + /* Shall be the last one */ + ACPI_HEST_SRC_ID_COUNT +} AcpiHestSourceId; =20 /* Generic Hardware Error Source version 2 */ #define ACPI_GHES_SOURCE_GENERIC_ERROR_V2 10 @@ -63,6 +72,15 @@ */ #define ACPI_GHES_GESB_SIZE 20 =20 +/* + * Offsets with regards to the start of the HEST table stored at + * ags->hest_addr_le, according with the memory layout map at + * docs/specs/acpi_hest_ghes.rst. + */ +#define ACPI_HEST_TABLE_SIZE 40 +#define HEST_GHES_V2_TABLE_SIZE 92 +#define HEST_ACK_OFFSET (68 + ACPI_HEST_TABLE_SIZE) + /* * Values for error_severity field */ @@ -236,17 +254,17 @@ static int acpi_ghes_record_mem_error(uint64_t error_= block_address, * Initialize "etc/hardware_errors" and "etc/hardware_errors_addr" fw_cfg = blobs. * See docs/specs/acpi_hest_ghes.rst for blobs format. */ -void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *linker) +static void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *li= nker) { int i, error_status_block_offset; =20 /* Build error_block_address */ - for (i =3D 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) { + for (i =3D 0; i < ACPI_HEST_SRC_ID_COUNT; i++) { build_append_int_noprefix(hardware_errors, 0, sizeof(uint64_t)); } =20 /* Build read_ack_register */ - for (i =3D 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) { + for (i =3D 0; i < ACPI_HEST_SRC_ID_COUNT; i++) { /* * Initialize the value of read_ack_register to 1, so GHES can be * writable after (re)boot. @@ -261,20 +279,20 @@ void build_ghes_error_table(GArray *hardware_errors, = BIOSLinker *linker) =20 /* Reserve space for Error Status Data Block */ acpi_data_push(hardware_errors, - ACPI_GHES_MAX_RAW_DATA_LENGTH * ACPI_GHES_ERROR_SOURCE_COUNT); + ACPI_GHES_MAX_RAW_DATA_LENGTH * ACPI_HEST_SRC_ID_COUNT); =20 /* Tell guest firmware to place hardware_errors blob into RAM */ - bios_linker_loader_alloc(linker, ACPI_GHES_ERRORS_FW_CFG_FILE, + bios_linker_loader_alloc(linker, ACPI_HW_ERROR_FW_CFG_FILE, hardware_errors, sizeof(uint64_t), false); =20 - for (i =3D 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) { + for (i =3D 0; i < ACPI_HEST_SRC_ID_COUNT; i++) { /* * Tell firmware to patch error_block_address entries to point to * corresponding "Generic Error Status Block" */ bios_linker_loader_add_pointer(linker, - ACPI_GHES_ERRORS_FW_CFG_FILE, sizeof(uint64_t) * i, - sizeof(uint64_t), ACPI_GHES_ERRORS_FW_CFG_FILE, + ACPI_HW_ERROR_FW_CFG_FILE, sizeof(uint64_t) * i, + sizeof(uint64_t), ACPI_HW_ERROR_FW_CFG_FILE, error_status_block_offset + i * ACPI_GHES_MAX_RAW_DATA_LENGTH); } =20 @@ -282,16 +300,39 @@ void build_ghes_error_table(GArray *hardware_errors, = BIOSLinker *linker) * tell firmware to write hardware_errors GPA into * hardware_errors_addr fw_cfg, once the former has been initialized. */ - bios_linker_loader_write_pointer(linker, ACPI_GHES_DATA_ADDR_FW_CFG_FI= LE, - 0, sizeof(uint64_t), ACPI_GHES_ERRORS_FW_CFG_FILE, 0); + bios_linker_loader_write_pointer(linker, ACPI_HW_ERROR_ADDR_FW_CFG_FIL= E, 0, + sizeof(uint64_t), + ACPI_HW_ERROR_FW_CFG_FILE, 0); +} + +static bool ghes_notify_to_source_id(enum AcpiGhesNotifyType notify, + enum AcpiHestSourceId *source_id) +{ + switch (notify) { + case ACPI_GHES_NOTIFY_SEA: /* ARMv8 */ + *source_id =3D ACPI_HEST_SRC_ID_SEA; + return false; + case ACPI_GHES_NOTIFY_GPIO: + *source_id =3D ACPI_HEST_SRC_ID_GED; + return false; + default: + /* Unsupported notification types */ + return true; + } } =20 /* Build Generic Hardware Error Source version 2 (GHESv2) */ -static void build_ghes_v2(GArray *table_data, int source_id, BIOSLinker *l= inker) +static void build_ghes_v2(GArray *table_data, + enum AcpiGhesNotifyType notify, + BIOSLinker *linker) { uint64_t address_offset; + enum AcpiHestSourceId source_id; =20 - assert(source_id < ACPI_HEST_SRC_ID_RESERVED); + if (ghes_notify_to_source_id(notify, &source_id)) { + error_report("Error: notify %d not supported", notify); + abort(); + } =20 /* * Type: @@ -319,24 +360,13 @@ static void build_ghes_v2(GArray *table_data, int sou= rce_id, BIOSLinker *linker) build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */, 0); bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, - address_offset + GAS_ADDR_OFFSET, sizeof(uint64_t), - ACPI_GHES_ERRORS_FW_CFG_FILE, source_id * sizeof(uint64_t)); + address_offset + GAS_ADDR_OFFSET, + sizeof(uint64_t), + ACPI_HW_ERROR_FW_CFG_FILE, + source_id * sizeof(uint64_t)); =20 - switch (source_id) { - case ACPI_HEST_SRC_ID_SEA: - /* - * Notification Structure - * Now only enable ARMv8 SEA notification type - */ - build_ghes_hw_error_notification(table_data, ACPI_GHES_NOTIFY_SEA); - break; - case ACPI_HEST_SRC_ID_GED: - build_ghes_hw_error_notification(table_data, ACPI_GHES_NOTIFY_GPIO= ); - break; - default: - error_report("Not support this error source"); - abort(); - } + /* Notification Structure */ + build_ghes_hw_error_notification(table_data, notify); =20 /* Error Status Block Length */ build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4= ); @@ -350,9 +380,10 @@ static void build_ghes_v2(GArray *table_data, int sour= ce_id, BIOSLinker *linker) build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */, 0); bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, - address_offset + GAS_ADDR_OFFSET, - sizeof(uint64_t), ACPI_GHES_ERRORS_FW_CFG_FILE, - (ACPI_GHES_ERROR_SOURCE_COUNT + source_id) * sizeof(uint64_t)); + address_offset + GAS_ADDR_OFFSET, + sizeof(uint64_t), + ACPI_BUILD_TABLE_FILE, + address_offset + GAS_ADDR_OFFSET); =20 /* * Read Ack Preserve field @@ -365,89 +396,100 @@ static void build_ghes_v2(GArray *table_data, int so= urce_id, BIOSLinker *linker) } =20 /* Build Hardware Error Source Table */ -void acpi_build_hest(GArray *table_data, BIOSLinker *linker, +void acpi_build_hest(GArray *table_data, GArray *hardware_errors, + BIOSLinker *linker, const char *oem_id, const char *oem_table_id) { AcpiTable table =3D { .sig =3D "HEST", .rev =3D 1, .oem_id =3D oem_id, .oem_table_id =3D oem_table_id= }; =20 + build_ghes_error_table(hardware_errors, linker); + + int hest_offset =3D table_data->len; + acpi_table_begin(&table, table_data); =20 /* Error Source Count */ - build_append_int_noprefix(table_data, ACPI_GHES_ERROR_SOURCE_COUNT, 4); - build_ghes_v2(table_data, ACPI_HEST_SRC_ID_SEA, linker); - build_ghes_v2(table_data, ACPI_HEST_SRC_ID_GED, linker); + build_append_int_noprefix(table_data, ACPI_HEST_SRC_ID_COUNT, 4); + build_ghes_v2(table_data, ACPI_GHES_NOTIFY_SEA, linker); + build_ghes_v2(table_data, ACPI_GHES_NOTIFY_GPIO, linker); =20 acpi_table_end(linker, &table); + + /* + * tell firmware to write into GPA the address of HEST via fw_cfg, + * once initialized. + */ + bios_linker_loader_write_pointer(linker, + ACPI_HEST_ADDR_FW_CFG_FILE, 0, + sizeof(uint64_t), + ACPI_BUILD_TABLE_FILE, hest_offset); } =20 void acpi_ghes_add_fw_cfg(AcpiGhesState *ags, FWCfgState *s, GArray *hardware_error) { /* Create a read-only fw_cfg file for GHES */ - fw_cfg_add_file(s, ACPI_GHES_ERRORS_FW_CFG_FILE, hardware_error->data, + fw_cfg_add_file(s, ACPI_HW_ERROR_FW_CFG_FILE, hardware_error->data, hardware_error->len); =20 /* Create a read-write fw_cfg file for Address */ - fw_cfg_add_file_callback(s, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, NULL, NUL= L, + fw_cfg_add_file_callback(s, ACPI_HW_ERROR_ADDR_FW_CFG_FILE, NULL, NULL, NULL, &(ags->ghes_addr_le), sizeof(ags->ghes_addr_le), false); =20 + fw_cfg_add_file_callback(s, ACPI_HEST_ADDR_FW_CFG_FILE, NULL, NULL, + NULL, &(ags->hest_addr_le), sizeof(ags->hest_addr_le), false); + ags->present =3D true; } =20 -int acpi_ghes_record_errors(uint8_t source_id, uint64_t physical_address) +int acpi_ghes_record_errors(enum AcpiGhesNotifyType notify, + uint64_t physical_address) { - uint64_t error_block_addr, read_ack_register_addr, read_ack_register = =3D 0; - uint64_t start_addr; - bool ret =3D -1; + uint64_t cper_addr, read_ack_register =3D 0; + uint64_t read_ack_start_addr; + enum AcpiHestSourceId source; AcpiGedState *acpi_ged_state; AcpiGhesState *ags; =20 - assert(source_id < ACPI_HEST_SRC_ID_RESERVED); + if (ghes_notify_to_source_id(ACPI_HEST_SRC_ID_SEA, &source)) { + error_report("GHES: Invalid error block/ack address(es) for notify= %d", + notify); + return -1; + } =20 acpi_ged_state =3D ACPI_GED(object_resolve_path_type("", TYPE_ACPI_GED, NULL)); g_assert(acpi_ged_state); ags =3D &acpi_ged_state->ghes_state; =20 - start_addr =3D le64_to_cpu(ags->ghes_addr_le); + cper_addr =3D le64_to_cpu(ags->ghes_addr_le); + cper_addr +=3D 2 * ACPI_HEST_SRC_ID_COUNT * sizeof(uint64_t); + cper_addr +=3D source * ACPI_GHES_MAX_RAW_DATA_LENGTH; =20 - if (physical_address) { - if (source_id < ACPI_HEST_SRC_ID_RESERVED) { - start_addr +=3D source_id * sizeof(uint64_t); - } + read_ack_start_addr =3D le64_to_cpu(ags->hest_addr_le); + read_ack_start_addr +=3D source * HEST_GHES_V2_TABLE_SIZE + HEST_ACK_O= FFSET; =20 - cpu_physical_memory_read(start_addr, &error_block_addr, - sizeof(error_block_addr)); - - error_block_addr =3D le64_to_cpu(error_block_addr); - - read_ack_register_addr =3D start_addr + - ACPI_GHES_ERROR_SOURCE_COUNT * sizeof(uint64_t); - - cpu_physical_memory_read(read_ack_register_addr, - &read_ack_register, sizeof(read_ack_regis= ter)); - - /* zero means OSPM does not acknowledge the error */ - if (!read_ack_register) { - error_report("OSPM does not acknowledge previous error," - " so can not record CPER for current error anymore"); - } else if (error_block_addr) { - read_ack_register =3D cpu_to_le64(0); - /* - * Clear the Read Ack Register, OSPM will write it to 1 when - * it acknowledges this error. - */ - cpu_physical_memory_write(read_ack_register_addr, - &read_ack_register, sizeof(uint64_t)); - - ret =3D acpi_ghes_record_mem_error(error_block_addr, - physical_address); - } else - error_report("can not find Generic Error Status Block"); + if (!physical_address) { + error_report("can not find Generic Error Status Block for notify %= d", + notify); + return -1; } =20 - return ret; + cpu_physical_memory_read(read_ack_start_addr, + &read_ack_register, sizeof(read_ack_register)= ); + + /* zero means OSPM does not acknowledge the error */ + + read_ack_register =3D cpu_to_le64(0); + /* + * Clear the Read Ack Register, OSPM will write it to 1 when + * it acknowledges this error. + */ + cpu_physical_memory_write(read_ack_start_addr, + &read_ack_register, sizeof(uint64_t)); + + return acpi_ghes_record_mem_error(cper_addr, physical_address); } =20 NotifierList acpi_generic_error_notifiers =3D diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 1769467d23b2..79635bc7a0a8 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -944,10 +944,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildT= ables *tables) build_dbg2(tables_blob, tables->linker, vms); =20 if (vms->ras) { - build_ghes_error_table(tables->hardware_errors, tables->linker); acpi_add_table(table_offsets, tables_blob); - acpi_build_hest(tables_blob, tables->linker, vms->oem_id, - vms->oem_table_id); + acpi_build_hest(tables_blob, tables->hardware_errors, tables->link= er, + vms->oem_id, vms->oem_table_id); } =20 if (ms->numa_state->num_nodes > 0) { diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h index 99d12d69c864..2524b5e64624 100644 --- a/include/hw/acpi/ghes.h +++ b/include/hw/acpi/ghes.h @@ -29,7 +29,7 @@ extern NotifierList acpi_generic_error_notifiers; =20 /* - * Values for Hardware Error Notification Type field + * ACPI spec values for Hardware Error Notification Type field */ enum AcpiGhesNotifyType { /* Polled */ @@ -60,24 +60,19 @@ enum AcpiGhesNotifyType { ACPI_GHES_NOTIFY_RESERVED =3D 12 }; =20 -/* Those are used as table indexes when building GHES tables */ -enum { - ACPI_HEST_SRC_ID_SEA =3D 0, - ACPI_HEST_SRC_ID_GED, - ACPI_HEST_SRC_ID_RESERVED, -}; - typedef struct AcpiGhesState { + uint64_t hest_addr_le; uint64_t ghes_addr_le; bool present; /* True if GHES is present at all on this board */ } AcpiGhesState; =20 -void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *linker); -void acpi_build_hest(GArray *table_data, BIOSLinker *linker, +void acpi_build_hest(GArray *table_data, GArray *hardware_errors, + BIOSLinker *linker, const char *oem_id, const char *oem_table_id); void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState *s, GArray *hardware_errors); -int acpi_ghes_record_errors(uint8_t notify, uint64_t error_physical_addr); +int acpi_ghes_record_errors(enum AcpiGhesNotifyType notify, + uint64_t error_physical_addr); =20 /** * acpi_ghes_present: Report whether ACPI GHES table is present --=20 2.46.0 From nobody Sun Nov 24 10:49:18 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6DCA1ABEDC for ; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591451; cv=none; b=CwnJEUgjWru1tT3B+iaVgZV13AdsomNHVLKoMzyjVRizS4sAGd0CoyJ/cfomMOnwIxFAG6dHPK8PqZjn6cA32lAd+K7EsABjKJAqzbMRl/QGyB7i+NfivvXJbA4HLhcLoBneDW1KpdeJbGTyZTrJd0Xp+vFwilD7nkPPy9FuL8A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591451; c=relaxed/simple; bh=7SZ1So9xfJQq48rQZfysiQEF2+M+2VHIMENgBvOnmBs=; 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Wed, 14 Aug 2024 01:24:09 +0200 From: Mauro Carvalho Chehab To: Cc: Jonathan Cameron , Shiju Jose , Mauro Carvalho Chehab , "Michael S. Tsirkin" , Ani Sinha , Dongjiu Geng , Igor Mammedov , linux-kernel@vger.kernel.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v7 06/10] acpi/ghes: add support for generic error injection via QAPI Date: Wed, 14 Aug 2024 01:23:28 +0200 Message-ID: <2104a34f6233dc4a220739348f1a21689fbd3354.1723591201.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Provide a generic interface for error injection via GHESv2. This patch is co-authored: - original ghes logic to inject a simple ARM record by Shiju Jose; - generic logic to handle block addresses by Jonathan Cameron; - generic GHESv2 error inject by Mauro Carvalho Chehab; Co-authored-by: Jonathan Cameron Co-authored-by: Shiju Jose Co-authored-by: Mauro Carvalho Chehab Signed-off-by: Jonathan Cameron Signed-off-by: Shiju Jose Signed-off-by: Mauro Carvalho Chehab --- hw/acpi/ghes.c | 57 ++++++++++++++++++++++++++++++++++++++++++ hw/acpi/ghes_cper.c | 2 +- include/hw/acpi/ghes.h | 3 +++ 3 files changed, 61 insertions(+), 1 deletion(-) diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index f93499d7d647..2f6b50d57ed2 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -495,6 +495,63 @@ int acpi_ghes_record_errors(enum AcpiGhesNotifyType no= tify, NotifierList acpi_generic_error_notifiers =3D NOTIFIER_LIST_INITIALIZER(error_device_notifiers); =20 +void ghes_record_cper_errors(uint8_t *cper, size_t len, + enum AcpiGhesNotifyType notify, Error **errp) +{ + uint64_t cper_addr, read_ack_start_addr; + enum AcpiHestSourceId source; + AcpiGedState *acpi_ged_state; + AcpiGhesState *ags; + uint64_t read_ack; + + if (ghes_notify_to_source_id(notify, &source)) { + error_setg(errp, + "GHES: Invalid error block/ack address(es) for notify %= d", + notify); + return; + } + + acpi_ged_state =3D ACPI_GED(object_resolve_path_type("", TYPE_ACPI_GED, + NULL)); + g_assert(acpi_ged_state); + ags =3D &acpi_ged_state->ghes_state; + + cper_addr =3D le64_to_cpu(ags->ghes_addr_le); + cper_addr +=3D 2 * ACPI_HEST_SRC_ID_COUNT * sizeof(uint64_t); + cper_addr +=3D source * ACPI_GHES_MAX_RAW_DATA_LENGTH; + + read_ack_start_addr =3D le64_to_cpu(ags->hest_addr_le); + read_ack_start_addr +=3D source * HEST_GHES_V2_TABLE_SIZE + HEST_ACK_O= FFSET; + + cpu_physical_memory_read(read_ack_start_addr, + &read_ack, sizeof(uint64_t)); + + /* zero means OSPM does not acknowledge the error */ + if (!read_ack) { + error_setg(errp, + "Last CPER record was not acknowledged yet"); + read_ack =3D 1; + cpu_physical_memory_write(read_ack_start_addr, + &read_ack, sizeof(uint64_t)); + return; + } + + read_ack =3D cpu_to_le64(0); + cpu_physical_memory_write(read_ack_start_addr, + &read_ack, sizeof(uint64_t)); + + /* Build CPER record */ + + if (len > ACPI_GHES_MAX_RAW_DATA_LENGTH) { + error_setg(errp, "GHES CPER record is too big: %ld", len); + } + + /* Write the generic error data entry into guest memory */ + cpu_physical_memory_write(cper_addr, cper, len); + + notifier_list_notify(&acpi_generic_error_notifiers, NULL); +} + bool acpi_ghes_present(void) { AcpiGedState *acpi_ged_state; diff --git a/hw/acpi/ghes_cper.c b/hw/acpi/ghes_cper.c index 92ca84d738de..2328dbff7012 100644 --- a/hw/acpi/ghes_cper.c +++ b/hw/acpi/ghes_cper.c @@ -29,5 +29,5 @@ void qmp_ghes_cper(const char *qmp_cper, return; } =20 - /* TODO: call a function at ghes */ + ghes_record_cper_errors(cper, len, ACPI_GHES_NOTIFY_GPIO, errp); } diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h index 2524b5e64624..dacd82c6857e 100644 --- a/include/hw/acpi/ghes.h +++ b/include/hw/acpi/ghes.h @@ -74,6 +74,9 @@ void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState = *s, int acpi_ghes_record_errors(enum AcpiGhesNotifyType notify, uint64_t error_physical_addr); =20 +void ghes_record_cper_errors(uint8_t *cper, size_t len, + enum AcpiGhesNotifyType notify,Error **errp); + /** * acpi_ghes_present: Report whether ACPI GHES table is present * --=20 2.46.0 From nobody Sun Nov 24 10:49:18 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC8621AC421 for ; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591451; cv=none; b=sdEo4WbceAG2Kq9bqnxRUMTHiCcZT8i+4uvYvefI3wHc4bGQKwiY4NvrNPIbnNu5nEi0gX56KOXwwPD7312rbtOOkn4+Lb72BHhWB6lhyHoqCDmo6XV3PXb3f5H9qGjqA7L1zwCKNQ2Ps+2KsXL++4TBZqdQ5YN13IjVvQIr/94= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591451; c=relaxed/simple; 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Wed, 14 Aug 2024 01:24:09 +0200 From: Mauro Carvalho Chehab To: Cc: Jonathan Cameron , Shiju Jose , Mauro Carvalho Chehab , Dongjiu Geng , linux-kernel@vger.kernel.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, Igor Mammedov Subject: [PATCH v7 07/10] docs: acpi_hest_ghes: fix documentation for CPER size Date: Wed, 14 Aug 2024 01:23:29 +0200 Message-ID: <55354bc0c5cfed5f6f042ae746c84983263c8019.1723591201.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" While the spec defines a CPER size of 4KiB for each record, currently it is set to 1KiB. Fix the documentation and add a pointer to the macro name there, as this may help to keep it updated. Signed-off-by: Mauro Carvalho Chehab Acked-by: Igor Mammedov --- docs/specs/acpi_hest_ghes.rst | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/specs/acpi_hest_ghes.rst b/docs/specs/acpi_hest_ghes.rst index 68f1fbe0a4af..c3e9f8d9a702 100644 --- a/docs/specs/acpi_hest_ghes.rst +++ b/docs/specs/acpi_hest_ghes.rst @@ -67,8 +67,10 @@ Design Details (3) The address registers table contains N Error Block Address entries and N Read Ack Register entries. The size for each entry is 8-byte. The Error Status Data Block table contains N Error Status Data Block - entries. The size for each entry is 4096(0x1000) bytes. The total size - for the "etc/hardware_errors" fw_cfg blob is (N * 8 * 2 + N * 4096) by= tes. + entries. The size for each entry is defined at the source code as + ACPI_GHES_MAX_RAW_DATA_LENGTH (currently 1024 bytes). The total size + for the "etc/hardware_errors" fw_cfg blob is + (N * 8 * 2 + N * ACPI_GHES_MAX_RAW_DATA_LENGTH) bytes. N is the number of the kinds of hardware error sources. =20 (4) QEMU generates the ACPI linker/loader script for the firmware. The --=20 2.46.0 From nobody Sun Nov 24 10:49:18 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 395251AC443 for ; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591452; cv=none; b=mANrUkWpRtHwwGnnDRBPuNfG5yN3nOf4KAqRLVIPLu7R27cuY+OoFV5Db/+ug3EYuGC8YWm9PHx9XRjmf588i0NVxA3zHThlEeZbXUk/Xt8HwfdyaGXK+1CemRGLgzCONj+lavOlFlhHrjm6xoqQL4U+Y/NVBRpu89xbage27uA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591452; c=relaxed/simple; bh=NbGBn1U+519h8TMHQA6b+S45MXVRj5iApKZjKvJ/IKM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nb5ilFN8Px/vqpNQc92qJ1CvciB8euglbqglScXqeCjOsUC43u8gIIaM34xGcuqnjO37EeDAKJdVcePr5LYo5Zq5RM+Flnl5ptJD6aQCjzBx10O22koUk5xZNfH4R326Fb4BlfSwOiIFkWiY5Wfo35rxUyUAV9BvXDPIiPLOiH8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EPDaB/aJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EPDaB/aJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 67C29C4AF16; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723591451; bh=NbGBn1U+519h8TMHQA6b+S45MXVRj5iApKZjKvJ/IKM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EPDaB/aJsaUPTv8YdTrJZXFvwB8UPb2OFiRmESCNGuHi7mS4Lt2wGVw8tAt0wq28Y jxQL7Q5JukwfY3FDOCVkbyb41nR8Uy4EiQdwhsouCvzMtxCOv9TJ7layNJHfV15HrB nW/ubu7WxeZmtm9fcMwkXmQeik1cNl5le5WrY7XzhWxauB2sjv/sn+aGKf9CXcnxlk cw4AmiNfTGvpUmLVTIMyvtiXVPVuU8BLTv8OZmarbUT/yjqYhvQ4grZT7n4Y9UtHQ8 TjfYgOgWHsWdwOJPudUX7irqL9QJAvk6jjlbzFeIUkUIH4PCAkxy1EcqDYPoInWdju voQicc5xFNXVQ== Received: from mchehab by mail.kernel.org with local (Exim 4.98) (envelope-from ) id 1se0s5-00000002asc-1zvE; Wed, 14 Aug 2024 01:24:09 +0200 From: Mauro Carvalho Chehab To: Cc: Jonathan Cameron , Shiju Jose , Mauro Carvalho Chehab , Cleber Rosa , John Snow , linux-kernel@vger.kernel.org, qemu-devel@nongnu.org Subject: [PATCH v7 08/10] scripts/ghes_inject: add a script to generate GHES error inject Date: Wed, 14 Aug 2024 01:23:30 +0200 Message-ID: X-Mailer: git-send-email 2.46.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Using the QMP GHESv2 API requires preparing a raw data array containing a CPER record. Add a helper script with subcommands to prepare such data. Currently, only ARM Processor error CPER record is supported. Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 3 + scripts/arm_processor_error.py | 371 +++++++++++++++++++++++++ scripts/ghes_inject.py | 51 ++++ scripts/qmp_helper.py | 486 +++++++++++++++++++++++++++++++++ 4 files changed, 911 insertions(+) create mode 100644 scripts/arm_processor_error.py create mode 100755 scripts/ghes_inject.py create mode 100644 scripts/qmp_helper.py diff --git a/MAINTAINERS b/MAINTAINERS index 1d8091818899..249ed2858198 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2083,6 +2083,9 @@ S: Maintained F: hw/arm/ghes_cper.c F: hw/acpi/ghes_cper_stub.c F: qapi/acpi-hest.json +F: scripts/ghes_inject.py +F: scripts/arm_processor_error.py +F: scripts/qmp_helper.py =20 ppc4xx L: qemu-ppc@nongnu.org diff --git a/scripts/arm_processor_error.py b/scripts/arm_processor_error.py new file mode 100644 index 000000000000..2643e4ddc5f3 --- /dev/null +++ b/scripts/arm_processor_error.py @@ -0,0 +1,371 @@ +#!/usr/bin/env python3 +# +# pylint: disable=3DC0301,C0114,R0903,R0912,R0913,R0914,R0915,W0511 +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2024 Mauro Carvalho Chehab + +# TODO: current implementation has dummy defaults. +# +# For a better implementation, a QMP addition/call is needed to +# retrieve some data for ARM Processor Error injection: +# +# - ARM registers: power_state, mpidr. + +import argparse +import re + +from qmp_helper import qmp, util, cper_guid + +class ArmProcessorEinj: + """ + Implements ARM Processor Error injection via GHES + """ + + DESC =3D """ + Generates an ARM processor error CPER, compatible with + UEFI 2.9A Errata. + """ + + ACPI_GHES_ARM_CPER_LENGTH =3D 40 + ACPI_GHES_ARM_CPER_PEI_LENGTH =3D 32 + + # Context types + CONTEXT_AARCH32_EL1 =3D 1 + CONTEXT_AARCH64_EL1 =3D 5 + CONTEXT_MISC_REG =3D 8 + + def __init__(self, subparsers): + """Initialize the error injection class and add subparser""" + + # Valid choice values + self.arm_valid_bits =3D { + "mpidr": util.bit(0), + "affinity": util.bit(1), + "running": util.bit(2), + "vendor": util.bit(3), + } + + self.pei_flags =3D { + "first": util.bit(0), + "last": util.bit(1), + "propagated": util.bit(2), + "overflow": util.bit(3), + } + + self.pei_error_types =3D { + "cache": util.bit(1), + "tlb": util.bit(2), + "bus": util.bit(3), + "micro-arch": util.bit(4), + } + + self.pei_valid_bits =3D { + "multiple-error": util.bit(0), + "flags": util.bit(1), + "error-info": util.bit(2), + "virt-addr": util.bit(3), + "phy-addr": util.bit(4), + } + + self.data =3D bytearray() + + parser =3D subparsers.add_parser("arm", description=3Dself.DESC) + + arm_valid_bits =3D ",".join(self.arm_valid_bits.keys()) + flags =3D ",".join(self.pei_flags.keys()) + error_types =3D ",".join(self.pei_error_types.keys()) + pei_valid_bits =3D ",".join(self.pei_valid_bits.keys()) + + # UEFI N.16 ARM Validation bits + g_arm =3D parser.add_argument_group("ARM processor") + g_arm.add_argument("--arm", "--arm-valid", + help=3Df"ARM valid bits: {arm_valid_bits}") + g_arm.add_argument("-a", "--affinity", "--level", "--affinity-lev= el", + type=3Dlambda x: int(x, 0), + help=3D"Affinity level (when multiple levels ap= ply)") + g_arm.add_argument("-l", "--mpidr", type=3Dlambda x: int(x, 0), + help=3D"Multiprocessor Affinity Register") + g_arm.add_argument("-i", "--midr", type=3Dlambda x: int(x, 0), + help=3D"Main ID Register") + g_arm.add_argument("-r", "--running", + action=3Dargparse.BooleanOptionalAction, + default=3DNone, + help=3D"Indicates if the processor is running o= r not") + g_arm.add_argument("--psci", "--psci-state", + type=3Dlambda x: int(x, 0), + help=3D"Power State Coordination Interface - PS= CI state") + + # TODO: Add vendor-specific support + + # UEFI N.17 bitmaps (type and flags) + g_pei =3D parser.add_argument_group("ARM Processor Error Info (PEI= )") + g_pei.add_argument("-t", "--type", nargs=3D"+", + help=3Df"one or more error types: {error_types}") + g_pei.add_argument("-f", "--flags", nargs=3D"*", + help=3Df"zero or more error flags: {flags}") + g_pei.add_argument("-V", "--pei-valid", "--error-valid", nargs=3D"= *", + help=3Df"zero or more PEI valid bits: {pei_valid_b= its}") + + # UEFI N.17 Integer values + g_pei.add_argument("-m", "--multiple-error", nargs=3D"+", + help=3D"Number of errors: 0: Single error, 1: Mult= iple errors, 2-65535: Error count if known") + g_pei.add_argument("-e", "--error-info", nargs=3D"+", + help=3D"Error information (UEFI 2.10 tables N.18 t= o N.20)") + g_pei.add_argument("-p", "--physical-address", nargs=3D"+", + help=3D"Physical address") + g_pei.add_argument("-v", "--virtual-address", nargs=3D"+", + help=3D"Virtual address") + + # UEFI N.21 Context + g_ctx =3D parser.add_argument_group("Processor Context") + g_ctx.add_argument("--ctx-type", "--context-type", nargs=3D"*", + help=3D"Type of the context (0=3DARM32 GPR, 5=3DAR= M64 EL1, other values supported)") + g_ctx.add_argument("--ctx-size", "--context-size", nargs=3D"*", + help=3D"Minimal size of the context") + g_ctx.add_argument("--ctx-array", "--context-array", nargs=3D"*", + help=3D"Comma-separated arrays for each context") + + # Vendor-specific data + g_vendor =3D parser.add_argument_group("Vendor-specific data") + g_vendor.add_argument("--vendor", "--vendor-specific", nargs=3D"+", + help=3D"Vendor-specific byte arrays of data") + + parser.set_defaults(func=3Dself.send_cper) + + def send_cper(self, args): + """Parse subcommand arguments and send a CPER via QMP""" + + qmp_cmd =3D qmp(args.host, args.port, args.debug) + + is_cpu_type =3D re.compile(r"^([\w+]+\-)?arm\-cpu$") + cpus =3D qmp_cmd.search_qom("/machine/unattached/device", + "type", is_cpu_type) + + cper =3D {} + pei =3D {} + ctx =3D {} + vendor =3D {} + + arg =3D vars(args) + + # Handle global parameters + if args.arm: + arm_valid_init =3D False + cper["valid"] =3D util.get_choice(name=3D"valid", + value=3Dargs.arm, + choices=3Dself.arm_valid_bits, + suffixes=3D["-error", "-err"]) + else: + cper["valid"] =3D 0 + arm_valid_init =3D True + + if "running" in arg: + if args.running: + cper["running-state"] =3D util.bit(0) + else: + cper["running-state"] =3D 0 + else: + cper["running-state"] =3D 0 + + if arm_valid_init: + if args.affinity: + cper["valid"] |=3D self.arm_valid_bits["affinity"] + + if args.mpidr: + cper["valid"] |=3D self.arm_valid_bits["mpidr"] + + if "running-state" in cper: + cper["valid"] |=3D self.arm_valid_bits["running"] + + if args.psci: + cper["valid"] |=3D self.arm_valid_bits["running"] + + # Handle PEI + if not args.type: + args.type =3D ["cache-error"] + + util.get_mult_choices( + pei, + name=3D"valid", + values=3Dargs.pei_valid, + choices=3Dself.pei_valid_bits, + suffixes=3D["-valid", "--addr"], + ) + util.get_mult_choices( + pei, + name=3D"type", + values=3Dargs.type, + choices=3Dself.pei_error_types, + suffixes=3D["-error", "-err"], + ) + util.get_mult_choices( + pei, + name=3D"flags", + values=3Dargs.flags, + choices=3Dself.pei_flags, + suffixes=3D["-error", "-cap"], + ) + util.get_mult_int(pei, "error-info", args.error_info) + util.get_mult_int(pei, "multiple-error", args.multiple_error) + util.get_mult_int(pei, "phy-addr", args.physical_address) + util.get_mult_int(pei, "virt-addr", args.virtual_address) + + # Handle context + util.get_mult_int(ctx, "type", args.ctx_type, allow_zero=3DTrue) + util.get_mult_int(ctx, "minimal-size", args.ctx_size, allow_zero= =3DTrue) + util.get_mult_array(ctx, "register", args.ctx_array, allow_zero=3D= True) + + util.get_mult_array(vendor, "bytes", args.vendor, max_val=3D255) + + # Store PEI + pei_data =3D bytearray() + default_flags =3D self.pei_flags["first"] + default_flags |=3D self.pei_flags["last"] + + error_info_num =3D 0 + + for i, p in pei.items(): # pylint: disable=3DW0612 + error_info_num +=3D 1 + + # UEFI 2.10 doesn't define how to encode error information + # when multiple types are raised. So, provide a default only + # if a single type is there + if "error-info" not in p: + if p["type"] =3D=3D util.bit(1): + p["error-info"] =3D 0x0091000F + if p["type"] =3D=3D util.bit(2): + p["error-info"] =3D 0x0054007F + if p["type"] =3D=3D util.bit(3): + p["error-info"] =3D 0x80D6460FFF + if p["type"] =3D=3D util.bit(4): + p["error-info"] =3D 0x78DA03FF + + if "valid" not in p: + p["valid"] =3D 0 + if "multiple-error" in p: + p["valid"] |=3D self.pei_valid_bits["multiple-error"] + + if "flags" in p: + p["valid"] |=3D self.pei_valid_bits["flags"] + + if "error-info" in p: + p["valid"] |=3D self.pei_valid_bits["error-info"] + + if "phy-addr" in p: + p["valid"] |=3D self.pei_valid_bits["phy-addr"] + + if "virt-addr" in p: + p["valid"] |=3D self.pei_valid_bits["virt-addr"] + + # Version + util.data_add(pei_data, 0, 1) + + util.data_add(pei_data, + self.ACPI_GHES_ARM_CPER_PEI_LENGTH, 1) + + util.data_add(pei_data, p["valid"], 2) + util.data_add(pei_data, p["type"], 1) + util.data_add(pei_data, p.get("multiple-error", 1), 2) + util.data_add(pei_data, p.get("flags", default_flags), 1) + util.data_add(pei_data, p.get("error-info", 0), 8) + util.data_add(pei_data, p.get("virt-addr", 0xDEADBEEF), 8) + util.data_add(pei_data, p.get("phy-addr", 0xABBA0BAD), 8) + + # Store Context + ctx_data =3D bytearray() + context_info_num =3D 0 + + if ctx: + ret =3D qmp_cmd.send_cmd("query-target", may_open=3DTrue) + + default_ctx =3D self.CONTEXT_MISC_REG + + if "arch" in ret: + if ret["arch"] =3D=3D "aarch64": + default_ctx =3D self.CONTEXT_AARCH64_EL1 + elif ret["arch"] =3D=3D "arm": + default_ctx =3D self.CONTEXT_AARCH32_EL1 + + for k in sorted(ctx.keys()): + context_info_num +=3D 1 + + if "type" not in ctx[k]: + ctx[k]["type"] =3D default_ctx + + if "register" not in ctx[k]: + ctx[k]["register"] =3D [] + + reg_size =3D len(ctx[k]["register"]) + size =3D 0 + + if "minimal-size" in ctx: + size =3D ctx[k]["minimal-size"] + + size =3D max(size, reg_size) + + size =3D (size + 1) % 0xFFFE + + # Version + util.data_add(ctx_data, 0, 2) + + util.data_add(ctx_data, ctx[k]["type"], 2) + + util.data_add(ctx_data, 8 * size, 4) + + for r in ctx[k]["register"]: + util.data_add(ctx_data, r, 8) + + for i in range(reg_size, size): # pylint: disable=3DW0612 + util.data_add(ctx_data, 0, 8) + + # Vendor-specific bytes are not grouped + vendor_data =3D bytearray() + if vendor: + for k in sorted(vendor.keys()): + for b in vendor[k]["bytes"]: + util.data_add(vendor_data, b, 1) + + # Encode ARM Processor Error + data =3D bytearray() + + util.data_add(data, cper["valid"], 4) + + util.data_add(data, error_info_num, 2) + util.data_add(data, context_info_num, 2) + + # Calculate the length of the CPER data + cper_length =3D self.ACPI_GHES_ARM_CPER_LENGTH + cper_length +=3D len(pei_data) + cper_length +=3D len(vendor_data) + cper_length +=3D len(ctx_data) + util.data_add(data, cper_length, 4) + + util.data_add(data, arg.get("affinity-level", 0), 1) + + # Reserved + util.data_add(data, 0, 3) + + if "midr-el1" not in arg: + if cpus: + cmd_arg =3D { + 'path': cpus[0], + 'property': "midr" + } + ret =3D qmp_cmd.send_cmd("qom-get", cmd_arg, may_open=3DTr= ue) + if isinstance(ret, int): + arg["midr-el1"] =3D ret + + util.data_add(data, arg.get("mpidr-el1", 0), 8) + util.data_add(data, arg.get("midr-el1", 0), 8) + util.data_add(data, cper["running-state"], 4) + util.data_add(data, arg.get("psci-state", 0), 4) + + # Add PEI + data.extend(pei_data) + data.extend(ctx_data) + data.extend(vendor_data) + + self.data =3D data + + qmp_cmd.send_cper(cper_guid.CPER_PROC_ARM, self.data) diff --git a/scripts/ghes_inject.py b/scripts/ghes_inject.py new file mode 100755 index 000000000000..67cb6077bec8 --- /dev/null +++ b/scripts/ghes_inject.py @@ -0,0 +1,51 @@ +#!/usr/bin/env python3 +# +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2024 Mauro Carvalho Chehab + +""" +Handle ACPI GHESv2 error injection logic QEMU QMP interface. +""" + +import argparse +import sys + +from arm_processor_error import ArmProcessorEinj + +EINJ_DESC =3D """ +Handle ACPI GHESv2 error injection logic QEMU QMP interface. + +It allows using UEFI BIOS EINJ features to generate GHES records. + +It helps testing CPER and GHES drivers at the guest OS and how +userspace applications at the guest handle them. +""" + +def main(): + """Main program""" + + # Main parser - handle generic args like QEMU QMP TCP socket options + parser =3D argparse.ArgumentParser(formatter_class=3Dargparse.Argument= DefaultsHelpFormatter, + usage=3D"%(prog)s [options]", + description=3DEINJ_DESC) + + g_options =3D parser.add_argument_group("QEMU QMP socket options") + g_options.add_argument("-H", "--host", default=3D"localhost", type=3Ds= tr, + help=3D"host name") + g_options.add_argument("-P", "--port", default=3D4445, type=3Dint, + help=3D"TCP port number") + g_options.add_argument('-d', '--debug', action=3D'store_true') + + subparsers =3D parser.add_subparsers() + + ArmProcessorEinj(subparsers) + + args =3D parser.parse_args() + if "func" in args: + args.func(args) + else: + sys.exit(f"Please specify a valid command for {sys.argv[0]}") + +if __name__ =3D=3D "__main__": + main() diff --git a/scripts/qmp_helper.py b/scripts/qmp_helper.py new file mode 100644 index 000000000000..67b6aa4afa66 --- /dev/null +++ b/scripts/qmp_helper.py @@ -0,0 +1,486 @@ +#!/usr/bin/env python3 +# +# # pylint: disable=3DC0103,E0213,E1135,E1136,E1137,R0902,R0903,R0912,R0913 +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2024 Mauro Carvalho Chehab + +""" +Helper classes to be used by ghes_inject command classes. +""" + +import json +import sys + +from os import path as os_path + +try: + qemu_dir =3D os_path.abspath(os_path.dirname(os_path.dirname(__file__)= )) + sys.path.append(os_path.join(qemu_dir, 'python')) + + from qemu.qmp.legacy import QEMUMonitorProtocol + +except ModuleNotFoundError as exc: + print(f"Module '{exc.name}' not found.") + print("Try export PYTHONPATH=3Dtop-qemu-dir/python or run from top-qem= u-dir") + sys.exit(1) + +from base64 import b64encode + +class util: + """ + Ancillary functions to deal with bitmaps, parse arguments, + generate GUID and encode data on a bytearray buffer. + """ + + # + # Helper routines to handle multiple choice arguments + # + def get_choice(name, value, choices, suffixes=3DNone): + """Produce a list from multiple choice argument""" + + new_values =3D 0 + + if not value: + return new_values + + for val in value.split(","): + val =3D val.lower() + + if suffixes: + for suffix in suffixes: + val =3D val.removesuffix(suffix) + + if val not in choices.keys(): + if suffixes: + for suffix in suffixes: + if val + suffix in choices.keys(): + val +=3D suffix + break + + if val not in choices.keys(): + sys.exit(f"Error on '{name}': choice '{val}' is invalid.") + + val =3D choices[val] + + new_values |=3D val + + return new_values + + + def get_mult_array(mult, name, values, allow_zero=3DFalse, max_val=3DN= one): + """Add numbered hashes from integer lists""" + + if not allow_zero: + if not values: + return + else: + if values is None: + return + + if not values: + i =3D 0 + if i not in mult: + mult[i] =3D {} + + mult[i][name] =3D [] + return + + i =3D 0 + for value in values: + for val in value.split(","): + try: + val =3D int(val, 0) + except ValueError: + sys.exit(f"Error on '{name}': {val} is not an integer") + + if val < 0: + sys.exit(f"Error on '{name}': {val} is not unsigned") + + if max_val and val > max_val: + sys.exit(f"Error on '{name}': {val} is too little") + + if i not in mult: + mult[i] =3D {} + + if name not in mult[i]: + mult[i][name] =3D [] + + mult[i][name].append(val) + + i +=3D 1 + + + def get_mult_choices(mult, name, values, choices, + suffixes=3DNone, allow_zero=3DFalse): + """Add numbered hashes from multiple choice arguments""" + + if not allow_zero: + if not values: + return + else: + if values is None: + return + + i =3D 0 + for val in values: + new_values =3D util.get_choice(name, val, choices, suffixes) + + if i not in mult: + mult[i] =3D {} + + mult[i][name] =3D new_values + i +=3D 1 + + + def get_mult_int(mult, name, values, allow_zero=3DFalse): + """Add numbered hashes from integer arguments""" + if not allow_zero: + if not values: + return + else: + if values is None: + return + + i =3D 0 + for val in values: + try: + val =3D int(val, 0) + except ValueError: + sys.exit(f"Error on '{name}': {val} is not an integer") + + if val < 0: + sys.exit(f"Error on '{name}': {val} is not unsigned") + + if i not in mult: + mult[i] =3D {} + + mult[i][name] =3D val + i +=3D 1 + + + # + # Data encode helper functions + # + def bit(b): + """Simple macro to define a bit on a bitmask""" + return 1 << b + + + def data_add(data, value, num_bytes): + """Adds bytes from value inside a bitarray""" + + data.extend(value.to_bytes(num_bytes, byteorder=3D"little")) # py= lint: disable=3DE1101 + + def dump_bytearray(name, data): + """Does an hexdump of a byte array, grouping in bytes""" + + print(f"{name} ({len(data)} bytes):") + + for ln_start in range(0, len(data), 16): + ln_end =3D min(ln_start + 16, len(data)) + print(f" {ln_start:08x} ", end=3D"") + for i in range(ln_start, ln_end): + print(f"{data[i]:02x} ", end=3D"") + for i in range(ln_end, ln_start + 16): + print(" ", end=3D"") + print(" ", end=3D"") + for i in range(ln_start, ln_end): + if data[i] >=3D 32 and data[i] < 127: + print(chr(data[i]), end=3D"") + else: + print(".", end=3D"") + + print() + print() + +class guid: + """ + Simple class to handle GUID fields. + """ + + def __init__(self, time_low, time_mid, time_high, nodes): + """Initialize a GUID value""" + + assert len(nodes) =3D=3D 8 + + self.time_low =3D time_low + self.time_mid =3D time_mid + self.time_high =3D time_high + self.nodes =3D nodes + + def __str__(self): + """Output a GUID value on its default string representation""" + + clock =3D self.nodes[0] << 8 | self.nodes[1] + + node =3D 0 + for i in range(2, len(self.nodes)): + node =3D node << 8 | self.nodes[i] + + s =3D f"{self.time_low:08x}-{self.time_mid:04x}-" + s +=3D f"{self.time_high:04x}-{clock:04x}-{node:012x}" + return s + + def to_bytes(self): + """Output a GUID value in bytes""" + + data =3D bytearray() + + util.data_add(data, self.time_low, 4) + util.data_add(data, self.time_mid, 2) + util.data_add(data, self.time_high, 2) + data.extend(bytearray(self.nodes)) + + return data + +class qmp: + """ + Opens a connection and send/receive QMP commands. + """ + + def send_cmd(self, command, args=3DNone, may_open=3DFalse, return_erro= r=3DTrue): + """Send a command to QMP, optinally opening a connection""" + + if may_open: + self._connect() + elif not self.connected: + return False + + msg =3D { 'execute': command } + if args: + msg['arguments'] =3D args + + try: + obj =3D self.qmp_monitor.cmd_obj(msg) + # Can we use some other exception class here? + except Exception as e: # pylint: disable= =3DW0718 + print(f"Command: {command}") + print(f"Failed to inject error: {e}.") + return None + + if "return" in obj: + if isinstance(obj.get("return"), dict): + if obj["return"]: + return obj["return"] + return "OK" + + return obj["return"] + + if isinstance(obj.get("error"), dict): + error =3D obj["error"] + if return_error: + print(f"Command: {msg}") + print(f'{error["class"]}: {error["desc"]}') + else: + print(json.dumps(obj)) + + return None + + def _close(self): + """Shutdown and close the socket, if opened""" + if not self.connected: + return + + self.qmp_monitor.close() + self.connected =3D False + + def _connect(self): + """Connect to a QMP TCP/IP port, if not connected yet""" + + if self.connected: + return True + + try: + self.qmp_monitor.connect(negotiate=3DTrue) + except ConnectionError: + sys.exit(f"Can't connect to QMP host {self.host}:{self.port}") + + self.connected =3D True + + return True + + def __init__(self, host, port, debug=3DFalse): + """Initialize variables used by the QMP send logic""" + + self.connected =3D False + self.host =3D host + self.port =3D port + self.debug =3D debug + + # ACPI 6.1: 18.3.2.7.1 Generic Error Data: Generic Error Status Bl= ock + self.block_status =3D util.bit(0) # Uncorrectable + self.raw_data_offset =3D 0 + self.raw_data_length =3D 0 + self.error_severity =3D 0 # Recoverable + + # ACPI 6.1: 18.3.2.7.1 Generic Error Data: Generic Error Data Entry + self.validation_bits =3D 0 + self.flags =3D 0 + self.fru_id =3D bytearray(16) + self.fru_text =3D bytearray(20) + self.timestamp =3D 0 + + self.qmp_monitor =3D QEMUMonitorProtocol(address=3D(self.host, sel= f.port)) + + # + # Socket QMP send command + # + def send_cper_raw(self, cper_data): + """Send a raw CPER data to QEMU though QMP TCP socket""" + + data =3D b64encode(bytes(cper_data)).decode('ascii') + + cmd_arg =3D { + 'cper': data + } + + self._connect() + + if self.send_cmd("ghes-cper", cmd_arg): + print("Error injected.") + + def send_cper(self, notif_type, payload): + """Send commands to QEMU though QMP TCP socket""" + + # Fill CPER record header + + # Generic Error Status Block + gebs =3D bytearray() + + cper_length =3D len(payload) + data_length =3D cper_length + 72 # Size of Generic Error Data + + util.data_add(gebs, self.block_status, 4) + util.data_add(gebs, self.raw_data_offset, 4) + util.data_add(gebs, self.raw_data_length, 4) + util.data_add(gebs, data_length, 4) + util.data_add(gebs, self.error_severity, 4) + + + # Generic Error Data Entry + gede =3D bytearray() + + gede.extend(notif_type.to_bytes()) + util.data_add(gede, self.error_severity, 4) + util.data_add(gede, 0x300, 2) + util.data_add(gede, self.validation_bits, 1) + util.data_add(gede, self.flags, 1) + util.data_add(gede, cper_length, 4) + gede.extend(self.fru_id) + gede.extend(self.fru_text) + util.data_add(gede, self.timestamp, 8) + + cper_data =3D bytearray() + cper_data.extend(gebs) + cper_data.extend(gede) + cper_data.extend(bytearray(payload)) + + if self.debug: + print(f"GUID: {notif_type}") + + util.dump_bytearray("Generic Error Status Block", gebs) + util.dump_bytearray("Generic Error Data Entry", gede) + util.dump_bytearray("Payload", payload) + + self.send_cper_raw(cper_data) + + + def search_qom(self, path, prop, regex): + """ + Return a list of devices that match path array like: + + /machine/unattached/device + /machine/peripheral-anon/device + ... + """ + + found =3D [] + + i =3D 0 + while 1: + dev =3D f"{path}[{i}]" + args =3D { + 'path': dev, + 'property': prop + } + ret =3D self.send_cmd("qom-get", args, may_open=3DTrue, return= _error=3DFalse) + if not ret: + break + + if isinstance(ret, str): + if regex.search(ret): + found.append(dev) + + i +=3D 1 + if i > 10000: + print("Too many objects returned by qom-get!") + break + + return found + +class cper_guid: + """ + Contains CPER GUID, as per: + https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.ht= ml + """ + + CPER_PROC_GENERIC =3D guid(0x9876CCAD, 0x47B4, 0x4bdb, + [0xB6, 0x5E, 0x16, 0xF1, + 0x93, 0xC4, 0xF3, 0xDB]) + + CPER_PROC_X86 =3D guid(0xDC3EA0B0, 0xA144, 0x4797, + [0xB9, 0x5B, 0x53, 0xFA, + 0x24, 0x2B, 0x6E, 0x1D]) + + CPER_PROC_ITANIUM =3D guid(0xe429faf1, 0x3cb7, 0x11d4, + [0xbc, 0xa7, 0x00, 0x80, + 0xc7, 0x3c, 0x88, 0x81]) + + CPER_PROC_ARM =3D guid(0xE19E3D16, 0xBC11, 0x11E4, + [0x9C, 0xAA, 0xC2, 0x05, + 0x1D, 0x5D, 0x46, 0xB0]) + + CPER_PLATFORM_MEM =3D guid(0xA5BC1114, 0x6F64, 0x4EDE, + [0xB8, 0x63, 0x3E, 0x83, + 0xED, 0x7C, 0x83, 0xB1]) + + CPER_PLATFORM_MEM2 =3D guid(0x61EC04FC, 0x48E6, 0xD813, + [0x25, 0xC9, 0x8D, 0xAA, + 0x44, 0x75, 0x0B, 0x12]) + + CPER_PCIE =3D guid(0xD995E954, 0xBBC1, 0x430F, + [0xAD, 0x91, 0xB4, 0x4D, + 0xCB, 0x3C, 0x6F, 0x35]) + + CPER_PCI_BUS =3D guid(0xC5753963, 0x3B84, 0x4095, + [0xBF, 0x78, 0xED, 0xDA, + 0xD3, 0xF9, 0xC9, 0xDD]) + + CPER_PCI_DEV =3D guid(0xEB5E4685, 0xCA66, 0x4769, + [0xB6, 0xA2, 0x26, 0x06, + 0x8B, 0x00, 0x13, 0x26]) + + CPER_FW_ERROR =3D guid(0x81212A96, 0x09ED, 0x4996, + [0x94, 0x71, 0x8D, 0x72, + 0x9C, 0x8E, 0x69, 0xED]) + + CPER_DMA_GENERIC =3D guid(0x5B51FEF7, 0xC79D, 0x4434, + [0x8F, 0x1B, 0xAA, 0x62, + 0xDE, 0x3E, 0x2C, 0x64]) + + CPER_DMA_VT =3D guid(0x71761D37, 0x32B2, 0x45cd, + [0xA7, 0xD0, 0xB0, 0xFE, + 0xDD, 0x93, 0xE8, 0xCF]) + + CPER_DMA_IOMMU =3D guid(0x036F84E1, 0x7F37, 0x428c, + [0xA7, 0x9E, 0x57, 0x5F, + 0xDF, 0xAA, 0x84, 0xEC]) + + CPER_CCIX_PER =3D guid(0x91335EF6, 0xEBFB, 0x4478, + [0xA6, 0xA6, 0x88, 0xB7, + 0x28, 0xCF, 0x75, 0xD7]) + + CPER_CXL_PROT_ERR =3D guid(0x80B9EFB4, 0x52B5, 0x4DE3, + [0xA7, 0x77, 0x68, 0x78, + 0x4B, 0x77, 0x10, 0x48]) --=20 2.46.0 From nobody Sun Nov 24 10:49:18 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6D2B1AB53B for ; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none 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header.i=@kernel.org header.b="sagI4dlx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 59041C4AF0E; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723591451; bh=IYrtvsBCzlGe0MTkFkAK6noEUXQNZZJDowRzzCJAOeI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sagI4dlxetlku/RcQZDKH4+9wkeMTAjfuW0Z7K8tEg0ibY5f8yEyFHbPAbERsS4o3 fig0bcYP7/Kh6ECXL6aGGNDgUJmGo3+mbcBYXE3D39ulCXQuO4nxiCBNTM0136Vnxz CccOxVDAmWnQ0ir4y3KeGXJ6NTiBnaI0asqCRPGS3/ru5pksn1ocotIuDkRyQ69t8q rQjRl7/NOuCq751AF4LTx5KLb04s6nzD6iN9aKDakKMhgNiuhX8bofCioZl/Tel+jU MVE6yoE6LRlWMnWm9YO0nr2dkiEFrA2b1eZSxf5IPpHT4OHgmUtPzlRmTPb6+HQSZm Q0ZTRV/2GUNFQ== Received: from mchehab by mail.kernel.org with local (Exim 4.98) (envelope-from ) id 1se0s5-00000002asg-26g7; Wed, 14 Aug 2024 01:24:09 +0200 From: Mauro Carvalho Chehab To: Cc: Jonathan Cameron , Shiju Jose , Mauro Carvalho Chehab , Peter Maydell , linux-kernel@vger.kernel.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v7 09/10] target/arm: add an experimental mpidr arm cpu property object Date: Wed, 14 Aug 2024 01:23:31 +0200 Message-ID: X-Mailer: git-send-email 2.46.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Accurately injecting an ARM Processor error ACPI/APEI GHES error record requires the value of the ARM Multiprocessor Affinity Register (mpidr). While ARM implements it, this is currently not visible. Add a field at CPU storing it, and place it at arm_cpu_properties as experimental, thus allowing it to be queried via QMP using qom-get function. Signed-off-by: Mauro Carvalho Chehab --- target/arm/cpu.c | 1 + target/arm/cpu.h | 1 + target/arm/helper.c | 10 ++++++++-- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 19191c239181..30fcf0a10f46 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2619,6 +2619,7 @@ static ObjectClass *arm_cpu_class_by_name(const char = *cpu_model) =20 static Property arm_cpu_properties[] =3D { DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), + DEFINE_PROP_UINT64("x-mpidr", ARMCPU, mpidr, 0), DEFINE_PROP_UINT64("mp-affinity", ARMCPU, mp_affinity, ARM64_AFFINITY_INVALID), DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a12859fc5335..d2e86f0877cc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1033,6 +1033,7 @@ struct ArchCPU { uint64_t reset_pmcr_el0; } isar; uint64_t midr; + uint64_t mpidr; uint32_t revidr; uint32_t reset_fpsid; uint64_t ctr; diff --git a/target/arm/helper.c b/target/arm/helper.c index 8fb4b474e83f..16e75b7c5ed9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4692,7 +4692,7 @@ static uint64_t mpidr_read_val(CPUARMState *env) return mpidr; } =20 -static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) +static uint64_t mpidr_read(CPUARMState *env) { unsigned int cur_el =3D arm_current_el(env); =20 @@ -4702,6 +4702,11 @@ static uint64_t mpidr_read(CPUARMState *env, const A= RMCPRegInfo *ri) return mpidr_read_val(env); } =20 +static uint64_t mpidr_read_ri(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return mpidr_read(env); +} + static const ARMCPRegInfo lpae_cp_reginfo[] =3D { /* NOP AMAIR0/1 */ { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, @@ -9723,7 +9728,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "MPIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D = 5, .fgt =3D FGT_MPIDR_EL1, - .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_= NO_RAW }, + .access =3D PL1_R, .readfn =3D mpidr_read_ri, .type =3D ARM_= CP_NO_RAW }, }; #ifdef CONFIG_USER_ONLY static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] =3D { @@ -9733,6 +9738,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); #endif define_arm_cp_regs(cpu, mpidr_cp_reginfo); + cpu->mpidr =3D mpidr_read(env); } =20 if (arm_feature(env, ARM_FEATURE_AUXCR)) { --=20 2.46.0 From nobody Sun Nov 24 10:49:18 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D118D1AC42B for ; Tue, 13 Aug 2024 23:24:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591451; cv=none; b=pL3LV5Y1JGo5vhYFh3D3O1u9AX2HmX9SNH3DyKgCJWalpRdO+5w+Bsr/cHEdDsqEhApn4p+BSNDx4ylPnQe76d4dLzjdXIvrahF3R38+1VUkRgsZT/po4eP1S8rhSutiHEFiXtE2vOcqcSWHQKeJDpPwV0WIj0vhfkeaEJNNDEM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723591451; c=relaxed/simple; bh=j486ons4LyU7EE4gQ8GJy4aORh/7MBRYapAi7rAlR+o=; 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Wed, 14 Aug 2024 01:24:09 +0200 From: Mauro Carvalho Chehab To: Cc: Jonathan Cameron , Shiju Jose , Mauro Carvalho Chehab , Cleber Rosa , John Snow , linux-kernel@vger.kernel.org, qemu-devel@nongnu.org Subject: [PATCH v7 10/10] scripts/arm_processor_error.py: retrieve mpidr if not filled Date: Wed, 14 Aug 2024 01:23:32 +0200 Message-ID: <01a655b405ab098aed7396fe87f8fd406e966141.1723591201.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Add support to retrieve mpidr value via qom-get. Signed-off-by: Mauro Carvalho Chehab --- scripts/arm_processor_error.py | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/scripts/arm_processor_error.py b/scripts/arm_processor_error.py index 2643e4ddc5f3..f869f07860b8 100644 --- a/scripts/arm_processor_error.py +++ b/scripts/arm_processor_error.py @@ -5,12 +5,10 @@ # # Copyright (C) 2024 Mauro Carvalho Chehab =20 -# TODO: current implementation has dummy defaults. -# -# For a better implementation, a QMP addition/call is needed to -# retrieve some data for ARM Processor Error injection: -# -# - ARM registers: power_state, mpidr. +# Note: currently it lacks a method to fill the ARM Processor Error CPER +# psci field from emulation. On a real hardware, this is filled only +# when a CPU is not running. Implementing support for it to simulate a +# real hardware is not trivial. =20 import argparse import re @@ -168,11 +166,24 @@ def send_cper(self, args): else: cper["running-state"] =3D 0 =20 + if args.mpidr: + cper["mpidr-el1"] =3D arg["mpidr"] + elif cpus: + cmd_arg =3D { + 'path': cpus[0], + 'property': "x-mpidr" + } + ret =3D qmp_cmd.send_cmd("qom-get", cmd_arg, may_open=3DTrue) + if isinstance(ret, int): + cper["mpidr-el1"] =3D ret + else: + cper["mpidr-el1"] =3D 0 + if arm_valid_init: if args.affinity: cper["valid"] |=3D self.arm_valid_bits["affinity"] =20 - if args.mpidr: + if "mpidr-el1" in cper: cper["valid"] |=3D self.arm_valid_bits["mpidr"] =20 if "running-state" in cper: @@ -356,7 +367,7 @@ def send_cper(self, args): if isinstance(ret, int): arg["midr-el1"] =3D ret =20 - util.data_add(data, arg.get("mpidr-el1", 0), 8) + util.data_add(data, cper["mpidr-el1"], 8) util.data_add(data, arg.get("midr-el1", 0), 8) util.data_add(data, cper["running-state"], 4) util.data_add(data, arg.get("psci-state", 0), 4) --=20 2.46.0