From nobody Tue Nov 26 04:25:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1709610744617398.939196505101; Mon, 4 Mar 2024 19:52:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rhLq2-00086k-Ir; Mon, 04 Mar 2024 22:51:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rhLpy-00086M-U6 for qemu-devel@nongnu.org; Mon, 04 Mar 2024 22:51:31 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rhLpw-0001hW-Pw for qemu-devel@nongnu.org; Mon, 04 Mar 2024 22:51:30 -0500 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxqvC9luZly4sUAA--.51492S3; Tue, 05 Mar 2024 11:51:25 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxjhO3luZlTEdOAA--.20921S3; Tue, 05 Mar 2024 11:51:24 +0800 (CST) From: Xianglai Li To: qemu-devel@nongnu.org Cc: maobibo@loongson.cn, Song Gao , Xiaojuan Yang , zhaotianrui@loongson.cn Subject: [PATCH V2 1/1] target/loongarch: Fixed tlb huge page loading issue Date: Tue, 5 Mar 2024 11:51:11 +0800 Message-Id: <5b23421ee1ebf59142c7d7a3bc1082fff910f2fa.1709610311.git.lixianglai@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8AxjhO3luZlTEdOAA--.20921S3 X-CM-SenderInfo: 5ol0xt5qjotxo6or00hjvr0hdfq/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=lixianglai@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1709610748468100005 Content-Type: text/plain; charset="utf-8" When we use qemu tcg simulation, the page size of bios is 4KB. When using the level 2 super large page (page size is 1G) to create the pag= e table, it is found that the content of the corresponding address space is abnormal, resulting in the bios can not start the operating system and graphical inte= rface normally. The lddir and ldpte instruction emulation has a problem with the use of super large page processing above level 2. The page size is not correctly calculated, resulting in the wrong page size of the table entry found by tlb. Signed-off-by: Xianglai Li Cc: maobibo@loongson.cn Cc: Song Gao Cc: Xiaojuan Yang Cc: zhaotianrui@loongson.cn --- target/loongarch/cpu.h | 1 + target/loongarch/tcg/tlb_helper.c | 21 ++++++++++++--------- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index ec37579fd6..eab3e41c71 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -292,6 +292,7 @@ typedef struct CPUArchState { uint32_t fcsr0_mask; =20 uint32_t cpucfg[21]; + uint32_t lddir_ps; =20 uint64_t lladdr; /* LL virtual address compared against SC */ uint64_t llval; diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index a08c08b05a..3594c800b3 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -38,6 +38,7 @@ static void raise_mmu_exception(CPULoongArchState *env, t= arget_ulong address, cs->exception_index =3D EXCCODE_PIF; } env->CSR_TLBRERA =3D FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, IST= LBR, 1); + env->lddir_ps =3D 0; break; case TLBRET_INVALID: /* TLB match with no valid bit */ @@ -488,13 +489,6 @@ target_ulong helper_lddir(CPULoongArchState *env, targ= et_ulong base, uint64_t dir_base, dir_width; bool huge =3D (base >> LOONGARCH_PAGE_HUGE_SHIFT) & 0x1; =20 - badvaddr =3D env->CSR_TLBRBADV; - base =3D base & TARGET_PHYS_MASK; - - /* 0:64bit, 1:128bit, 2:192bit, 3:256bit */ - shift =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTEWIDTH); - shift =3D (shift + 1) * 3; - if (huge) { return base; } @@ -519,9 +513,18 @@ target_ulong helper_lddir(CPULoongArchState *env, targ= et_ulong base, do_raise_exception(env, EXCCODE_INE, GETPC()); return 0; } + + /* 0:64bit, 1:128bit, 2:192bit, 3:256bit */ + shift =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTEWIDTH); + shift =3D (shift + 1) * 3; + badvaddr =3D env->CSR_TLBRBADV; + base =3D base & TARGET_PHYS_MASK; index =3D (badvaddr >> dir_base) & ((1 << dir_width) - 1); phys =3D base | index << shift; ret =3D ldq_phys(cs->as, phys) & TARGET_PHYS_MASK; + if (ret & BIT_ULL(LOONGARCH_PAGE_HUGE_SHIFT)) { + env->lddir_ps =3D dir_base; + } return ret; } =20 @@ -538,13 +541,13 @@ void helper_ldpte(CPULoongArchState *env, target_ulon= g base, target_ulong odd, base =3D base & TARGET_PHYS_MASK; =20 if (huge) { - /* Huge Page. base is paddr */ tmp0 =3D base ^ (1 << LOONGARCH_PAGE_HUGE_SHIFT); /* Move Global bit */ tmp0 =3D ((tmp0 & (1 << LOONGARCH_HGLOBAL_SHIFT)) >> LOONGARCH_HGLOBAL_SHIFT) << R_TLBENTRY_G_SHIFT | (tmp0 & (~(1 << LOONGARCH_HGLOBAL_SHIFT))); - ps =3D ptbase + ptwidth - 1; + + ps =3D env->lddir_ps - 1; if (odd) { tmp0 +=3D MAKE_64BIT_MASK(ps, 1); } --=20 2.39.1