From nobody Sat May 18 09:01:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1692966120655497.7539019148951; Fri, 25 Aug 2023 05:22:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qZVot-0003xK-Af; Fri, 25 Aug 2023 08:21:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qZVoZ-0003wC-Ed; Fri, 25 Aug 2023 08:21:24 -0400 Received: from relay3-d.mail.gandi.net ([2001:4b98:dc4:8::223]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qZVoW-0004wV-Ka; Fri, 25 Aug 2023 08:21:22 -0400 Received: by mail.gandi.net (Postfix) with ESMTPSA id D79F060003; Fri, 25 Aug 2023 12:21:17 +0000 (UTC) From: Jean-Christophe Dubois To: qemu-arm@nongnu.org Cc: Jean-Christophe Dubois , qemu-devel@nongnu.org Subject: [PATCH v4 1/6] Remove i.MX7 IOMUX GPR device from i.MX6UL Date: Fri, 25 Aug 2023 14:20:51 +0200 Message-Id: <48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: jcd@tribudubois.net Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4b98:dc4:8::223; envelope-from=jcd@tribudubois.net; helo=relay3-d.mail.gandi.net X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1692966122684100006 Content-Type: text/plain; charset="utf-8" i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device. In particular, register 22 is not present on i.MX6UL and this is actualy The only register that is really emulated in the i.MX7 IOMUX GPR device. Note: The i.MX6UL code is actually also implementing the IOMUX GPR device as an unimplemented device at the same bus adress and the 2 instantiations were actualy colliding. So we go back to the unimplemented device for now. Signed-off-by: Jean-Christophe Dubois Reviewed-by: Peter Maydell --- hw/arm/fsl-imx6ul.c | 11 ----------- include/hw/arm/fsl-imx6ul.h | 2 -- 2 files changed, 13 deletions(-) diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 2189dcbb72..0fdd2782ba 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -63,11 +63,6 @@ static void fsl_imx6ul_init(Object *obj) */ object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); =20 - /* - * GPR - */ - object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); - /* * GPIOs 1 to 5 */ @@ -537,12 +532,6 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error= **errp) FSL_IMX6UL_WDOGn_IRQ[i])); } =20 - /* - * GPR - */ - sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR= ); - /* * SDMA */ diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 9ee15ae38d..3bec6bb3fb 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -22,7 +22,6 @@ #include "hw/misc/imx6ul_ccm.h" #include "hw/misc/imx6_src.h" #include "hw/misc/imx7_snvs.h" -#include "hw/misc/imx7_gpr.h" #include "hw/intc/imx_gpcv2.h" #include "hw/watchdog/wdt_imx2.h" #include "hw/gpio/imx_gpio.h" @@ -74,7 +73,6 @@ struct FslIMX6ULState { IMX6SRCState src; IMX7SNVSState snvs; IMXGPCv2State gpcv2; - IMX7GPRState gpr; IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS]; IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS]; IMXSerialState uart[FSL_IMX6UL_NUM_UARTS]; --=20 2.34.1 From nobody Sat May 18 09:01:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169296616817985.68961987324087; Fri, 25 Aug 2023 05:22:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qZVp2-00041V-Ix; Fri, 25 Aug 2023 08:21:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qZVoc-0003wU-FR; Fri, 25 Aug 2023 08:21:28 -0400 Received: from relay3-d.mail.gandi.net ([2001:4b98:dc4:8::223]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qZVoY-0004wo-IZ; Fri, 25 Aug 2023 08:21:26 -0400 Received: by mail.gandi.net (Postfix) with ESMTPSA id D9E5660005; Fri, 25 Aug 2023 12:21:19 +0000 (UTC) From: Jean-Christophe Dubois To: qemu-arm@nongnu.org Cc: Jean-Christophe Dubois , qemu-devel@nongnu.org Subject: [PATCH v4 2/6] Refactor i.MX6UL processor code Date: Fri, 25 Aug 2023 14:20:52 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: jcd@tribudubois.net Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4b98:dc4:8::223; envelope-from=jcd@tribudubois.net; helo=relay3-d.mail.gandi.net X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1692966168825100001 Content-Type: text/plain; charset="utf-8" * Add Addr and size definition for most i.MX6UL devices in i.MX6UL header f= ile. * Use those newly defined named constants whenever possible. * Standardize the way we init a familly of unimplemented devices - SAI - PWM - CAN * Add/rework few comments Signed-off-by: Jean-Christophe Dubois Reviewed-by: Peter Maydell --- hw/arm/fsl-imx6ul.c | 147 ++++++++++++++++++++++++------------ include/hw/arm/fsl-imx6ul.h | 134 +++++++++++++++++++++++++++++--- 2 files changed, 221 insertions(+), 60 deletions(-) diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 0fdd2782ba..06a32aff64 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -64,7 +64,7 @@ static void fsl_imx6ul_init(Object *obj) object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); =20 /* - * GPIOs 1 to 5 + * GPIOs */ for (i =3D 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { snprintf(name, NAME_SIZE, "gpio%d", i); @@ -72,7 +72,7 @@ static void fsl_imx6ul_init(Object *obj) } =20 /* - * GPT 1, 2 + * GPTs */ for (i =3D 0; i < FSL_IMX6UL_NUM_GPTS; i++) { snprintf(name, NAME_SIZE, "gpt%d", i); @@ -80,7 +80,7 @@ static void fsl_imx6ul_init(Object *obj) } =20 /* - * EPIT 1, 2 + * EPITs */ for (i =3D 0; i < FSL_IMX6UL_NUM_EPITS; i++) { snprintf(name, NAME_SIZE, "epit%d", i + 1); @@ -88,7 +88,7 @@ static void fsl_imx6ul_init(Object *obj) } =20 /* - * eCSPI + * eCSPIs */ for (i =3D 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { snprintf(name, NAME_SIZE, "spi%d", i + 1); @@ -96,7 +96,7 @@ static void fsl_imx6ul_init(Object *obj) } =20 /* - * I2C + * I2Cs */ for (i =3D 0; i < FSL_IMX6UL_NUM_I2CS; i++) { snprintf(name, NAME_SIZE, "i2c%d", i + 1); @@ -104,7 +104,7 @@ static void fsl_imx6ul_init(Object *obj) } =20 /* - * UART + * UARTs */ for (i =3D 0; i < FSL_IMX6UL_NUM_UARTS; i++) { snprintf(name, NAME_SIZE, "uart%d", i); @@ -112,25 +112,31 @@ static void fsl_imx6ul_init(Object *obj) } =20 /* - * Ethernet + * Ethernets */ for (i =3D 0; i < FSL_IMX6UL_NUM_ETHS; i++) { snprintf(name, NAME_SIZE, "eth%d", i); object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); } =20 - /* USB */ + /* + * USB PHYs + */ for (i =3D 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { snprintf(name, NAME_SIZE, "usbphy%d", i); object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); } + + /* + * USBs + */ for (i =3D 0; i < FSL_IMX6UL_NUM_USBS; i++) { snprintf(name, NAME_SIZE, "usb%d", i); object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); } =20 /* - * SDHCI + * SDHCIs */ for (i =3D 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { snprintf(name, NAME_SIZE, "usdhc%d", i); @@ -138,7 +144,7 @@ static void fsl_imx6ul_init(Object *obj) } =20 /* - * Watchdog + * Watchdogs */ for (i =3D 0; i < FSL_IMX6UL_NUM_WDTS; i++) { snprintf(name, NAME_SIZE, "wdt%d", i); @@ -184,10 +190,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Erro= r **errp) * A7MPCORE DAP */ create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_AD= DR, - 0x100000); + FSL_IMX6UL_A7MPCORE_DAP_SIZE); =20 /* - * GPT 1, 2 + * GPTs */ for (i =3D 0; i < FSL_IMX6UL_NUM_GPTS; i++) { static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] =3D { @@ -212,7 +218,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) } =20 /* - * EPIT 1, 2 + * EPITs */ for (i =3D 0; i < FSL_IMX6UL_NUM_EPITS; i++) { static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = =3D { @@ -237,7 +243,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) } =20 /* - * GPIO + * GPIOs */ for (i =3D 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = =3D { @@ -279,17 +285,12 @@ static void fsl_imx6ul_realize(DeviceState *dev, Erro= r **errp) } =20 /* - * IOMUXC and IOMUXC_GPR + * IOMUXC */ - for (i =3D 0; i < 1; i++) { - static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS= ] =3D { - FSL_IMX6UL_IOMUXC_ADDR, - FSL_IMX6UL_IOMUXC_GPR_ADDR, - }; - - snprintf(name, NAME_SIZE, "iomuxc%d", i); - create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x40= 00); - } + create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR, + FSL_IMX6UL_IOMUXC_SIZE); + create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR, + FSL_IMX6UL_IOMUXC_GPR_SIZE); =20 /* * CCM @@ -309,7 +310,9 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR); =20 - /* Initialize all ECSPI */ + /* + * ECSPIs + */ for (i =3D 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = =3D { FSL_IMX6UL_ECSPI1_ADDR, @@ -337,7 +340,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) } =20 /* - * I2C + * I2Cs */ for (i =3D 0; i < FSL_IMX6UL_NUM_I2CS; i++) { static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] =3D { @@ -363,7 +366,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) } =20 /* - * UART + * UARTs */ for (i =3D 0; i < FSL_IMX6UL_NUM_UARTS; i++) { static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = =3D { @@ -401,7 +404,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) } =20 /* - * Ethernet + * Ethernets * * We must use two loops since phy_connected affects the other interfa= ce * and we have to set all properties before calling sysbus_realize(). @@ -454,28 +457,45 @@ static void fsl_imx6ul_realize(DeviceState *dev, Erro= r **errp) FSL_IMX6UL_ENETn_TIMER_IRQ[i])= ); } =20 - /* USB */ + /* + * USB PHYs + */ for (i =3D 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { + static const hwaddr + FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] =3D= { + FSL_IMX6UL_USBPHY1_ADDR, + FSL_IMX6UL_USBPHY2_ADDR, + }; + sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, - FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000); + FSL_IMX6UL_USB_PHYn_ADDR[i]); } =20 + /* + * USBs + */ for (i =3D 0; i < FSL_IMX6UL_NUM_USBS; i++) { + static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS= ] =3D { + FSL_IMX6UL_USBO2_USB1_ADDR, + FSL_IMX6UL_USBO2_USB2_ADDR, + }; + static const int FSL_IMX6UL_USBn_IRQ[] =3D { FSL_IMX6UL_USB1_IRQ, FSL_IMX6UL_USB2_IRQ, }; + sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, - FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200); + FSL_IMX6UL_USB02_USBn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX6UL_USBn_IRQ[i])); } =20 /* - * USDHC + * USDHCs */ for (i =3D 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = =3D { @@ -507,7 +527,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR); =20 /* - * Watchdog + * Watchdogs */ for (i =3D 0; i < FSL_IMX6UL_NUM_WDTS; i++) { static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] =3D= { @@ -515,6 +535,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) FSL_IMX6UL_WDOG2_ADDR, FSL_IMX6UL_WDOG3_ADDR, }; + static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] =3D { FSL_IMX6UL_WDOG1_IRQ, FSL_IMX6UL_WDOG2_IRQ, @@ -535,33 +556,59 @@ static void fsl_imx6ul_realize(DeviceState *dev, Erro= r **errp) /* * SDMA */ - create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000); + create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, + FSL_IMX6UL_SDMA_SIZE); =20 /* - * SAI (Audio SSI (Synchronous Serial Interface)) + * SAIs (Audio SSI (Synchronous Serial Interface)) */ - create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000); - create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000); - create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000); + for (i =3D 0; i < FSL_IMX6UL_NUM_SAIS; i++) { + static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] =3D { + FSL_IMX6UL_SAI1_ADDR, + FSL_IMX6UL_SAI2_ADDR, + FSL_IMX6UL_SAI3_ADDR, + }; + + snprintf(name, NAME_SIZE, "sai%d", i); + create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i], + FSL_IMX6UL_SAIn_SIZE); + } =20 /* - * PWM + * PWMs */ - create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000); - create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000); - create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000); - create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000); + for (i =3D 0; i < FSL_IMX6UL_NUM_PWMS; i++) { + static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] =3D { + FSL_IMX6UL_PWM1_ADDR, + FSL_IMX6UL_PWM2_ADDR, + FSL_IMX6UL_PWM3_ADDR, + FSL_IMX6UL_PWM4_ADDR, + }; + + snprintf(name, NAME_SIZE, "pwm%d", i); + create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i], + FSL_IMX6UL_PWMn_SIZE); + } =20 /* * Audio ASRC (asynchronous sample rate converter) */ - create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000); + create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, + FSL_IMX6UL_ASRC_SIZE); =20 /* - * CAN + * CANs */ - create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000); - create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000); + for (i =3D 0; i < FSL_IMX6UL_NUM_CANS; i++) { + static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] =3D { + FSL_IMX6UL_CAN1_ADDR, + FSL_IMX6UL_CAN2_ADDR, + }; + + snprintf(name, NAME_SIZE, "can%d", i); + create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i], + FSL_IMX6UL_CANn_SIZE); + } =20 /* * APHB_DMA @@ -579,13 +626,15 @@ static void fsl_imx6ul_realize(DeviceState *dev, Erro= r **errp) }; =20 snprintf(name, NAME_SIZE, "adc%d", i); - create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000); + create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], + FSL_IMX6UL_ADCn_SIZE); } =20 /* * LCD */ - create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000); + create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, + FSL_IMX6UL_LCDIF_SIZE); =20 /* * ROM memory diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 3bec6bb3fb..f7bf684b42 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -37,6 +37,7 @@ #include "exec/memory.h" #include "cpu.h" #include "qom/object.h" +#include "qemu/units.h" =20 #define TYPE_FSL_IMX6UL "fsl-imx6ul" OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL) @@ -57,6 +58,9 @@ enum FslIMX6ULConfiguration { FSL_IMX6UL_NUM_ADCS =3D 2, FSL_IMX6UL_NUM_USB_PHYS =3D 2, FSL_IMX6UL_NUM_USBS =3D 2, + FSL_IMX6UL_NUM_SAIS =3D 3, + FSL_IMX6UL_NUM_CANS =3D 2, + FSL_IMX6UL_NUM_PWMS =3D 4, }; =20 struct FslIMX6ULState { @@ -92,119 +96,227 @@ struct FslIMX6ULState { =20 enum FslIMX6ULMemoryMap { FSL_IMX6UL_MMDC_ADDR =3D 0x80000000, - FSL_IMX6UL_MMDC_SIZE =3D 2 * 1024 * 1024 * 1024UL, + FSL_IMX6UL_MMDC_SIZE =3D (2 * GiB), =20 FSL_IMX6UL_QSPI1_MEM_ADDR =3D 0x60000000, + FSL_IMX6UL_QSPI1_MEM_SIZE =3D (256 * MiB), + FSL_IMX6UL_EIM_ALIAS_ADDR =3D 0x58000000, + FSL_IMX6UL_EIM_ALIAS_SIZE =3D (128 * MiB), + FSL_IMX6UL_EIM_CS_ADDR =3D 0x50000000, + FSL_IMX6UL_EIM_CS_SIZE =3D (128 * MiB), + FSL_IMX6UL_AES_ENCRYPT_ADDR =3D 0x10000000, + FSL_IMX6UL_AES_ENCRYPT_SIZE =3D (1 * MiB), + FSL_IMX6UL_QSPI1_RX_ADDR =3D 0x0C000000, + FSL_IMX6UL_QSPI1_RX_SIZE =3D (32 * MiB), =20 - /* AIPS-2 */ + /* AIPS-2 Begin */ FSL_IMX6UL_UART6_ADDR =3D 0x021FC000, + FSL_IMX6UL_I2C4_ADDR =3D 0x021F8000, + FSL_IMX6UL_UART5_ADDR =3D 0x021F4000, FSL_IMX6UL_UART4_ADDR =3D 0x021F0000, FSL_IMX6UL_UART3_ADDR =3D 0x021EC000, FSL_IMX6UL_UART2_ADDR =3D 0x021E8000, + FSL_IMX6UL_WDOG3_ADDR =3D 0x021E4000, + FSL_IMX6UL_QSPI_ADDR =3D 0x021E0000, + FSL_IMX6UL_QSPI_SIZE =3D 0x500, + FSL_IMX6UL_SYS_CNT_CTRL_ADDR =3D 0x021DC000, + FSL_IMX6UL_SYS_CNT_CTRL_SIZE =3D (16 * KiB), + FSL_IMX6UL_SYS_CNT_CMP_ADDR =3D 0x021D8000, + FSL_IMX6UL_SYS_CNT_CMP_SIZE =3D (16 * KiB), + FSL_IMX6UL_SYS_CNT_RD_ADDR =3D 0x021D4000, + FSL_IMX6UL_SYS_CNT_RD_SIZE =3D (16 * KiB), + FSL_IMX6UL_TZASC_ADDR =3D 0x021D0000, + FSL_IMX6UL_TZASC_SIZE =3D (16 * KiB), + FSL_IMX6UL_PXP_ADDR =3D 0x021CC000, + FSL_IMX6UL_PXP_SIZE =3D (16 * KiB), + FSL_IMX6UL_LCDIF_ADDR =3D 0x021C8000, + FSL_IMX6UL_LCDIF_SIZE =3D 0x100, + FSL_IMX6UL_CSI_ADDR =3D 0x021C4000, + FSL_IMX6UL_CSI_SIZE =3D 0x100, + FSL_IMX6UL_CSU_ADDR =3D 0x021C0000, + FSL_IMX6UL_CSU_SIZE =3D (16 * KiB), + FSL_IMX6UL_OCOTP_CTRL_ADDR =3D 0x021BC000, + FSL_IMX6UL_OCOTP_CTRL_SIZE =3D (4 * KiB), + FSL_IMX6UL_EIM_ADDR =3D 0x021B8000, + FSL_IMX6UL_EIM_SIZE =3D 0x100, + FSL_IMX6UL_SIM2_ADDR =3D 0x021B4000, + FSL_IMX6UL_MMDC_CFG_ADDR =3D 0x021B0000, + FSL_IMX6UL_MMDC_CFG_SIZE =3D (4 * KiB), + FSL_IMX6UL_ROMCP_ADDR =3D 0x021AC000, + FSL_IMX6UL_ROMCP_SIZE =3D 0x300, + FSL_IMX6UL_I2C3_ADDR =3D 0x021A8000, FSL_IMX6UL_I2C2_ADDR =3D 0x021A4000, FSL_IMX6UL_I2C1_ADDR =3D 0x021A0000, + FSL_IMX6UL_ADC2_ADDR =3D 0x0219C000, FSL_IMX6UL_ADC1_ADDR =3D 0x02198000, + FSL_IMX6UL_ADCn_SIZE =3D 0x100, + FSL_IMX6UL_USDHC2_ADDR =3D 0x02194000, FSL_IMX6UL_USDHC1_ADDR =3D 0x02190000, + FSL_IMX6UL_SIM1_ADDR =3D 0x0218C000, + FSL_IMX6UL_SIMn_SIZE =3D (16 * KiB), + FSL_IMX6UL_ENET1_ADDR =3D 0x02188000, + FSL_IMX6UL_USBO2_USBMISC_ADDR =3D 0x02184800, - FSL_IMX6UL_USBO2_USB_ADDR =3D 0x02184000, + FSL_IMX6UL_USBO2_USB1_ADDR =3D 0x02184000, + FSL_IMX6UL_USBO2_USB2_ADDR =3D 0x02184200, + FSL_IMX6UL_USBO2_PL301_ADDR =3D 0x02180000, + FSL_IMX6UL_USBO2_PL301_SIZE =3D (16 * KiB), + FSL_IMX6UL_AIPS2_CFG_ADDR =3D 0x0217C000, + FSL_IMX6UL_AIPS2_CFG_SIZE =3D 0x100, + FSL_IMX6UL_CAAM_ADDR =3D 0x02140000, + FSL_IMX6UL_CAAM_SIZE =3D (16 * KiB), + FSL_IMX6UL_A7MPCORE_DAP_ADDR =3D 0x02100000, + FSL_IMX6UL_A7MPCORE_DAP_SIZE =3D (4 * KiB), + /* AIPS-2 End */ =20 - /* AIPS-1 */ + /* AIPS-1 Begin */ FSL_IMX6UL_PWM8_ADDR =3D 0x020FC000, FSL_IMX6UL_PWM7_ADDR =3D 0x020F8000, FSL_IMX6UL_PWM6_ADDR =3D 0x020F4000, FSL_IMX6UL_PWM5_ADDR =3D 0x020F0000, + FSL_IMX6UL_SDMA_ADDR =3D 0x020EC000, + FSL_IMX6UL_SDMA_SIZE =3D 0x300, + FSL_IMX6UL_GPT2_ADDR =3D 0x020E8000, + FSL_IMX6UL_IOMUXC_GPR_ADDR =3D 0x020E4000, + FSL_IMX6UL_IOMUXC_GPR_SIZE =3D 0x40, + FSL_IMX6UL_IOMUXC_ADDR =3D 0x020E0000, + FSL_IMX6UL_IOMUXC_SIZE =3D 0x700, + FSL_IMX6UL_GPC_ADDR =3D 0x020DC000, + FSL_IMX6UL_SRC_ADDR =3D 0x020D8000, + FSL_IMX6UL_EPIT2_ADDR =3D 0x020D4000, FSL_IMX6UL_EPIT1_ADDR =3D 0x020D0000, + FSL_IMX6UL_SNVS_HP_ADDR =3D 0x020CC000, + FSL_IMX6UL_USBPHY2_ADDR =3D 0x020CA000, - FSL_IMX6UL_USBPHY2_SIZE =3D (4 * 1024), FSL_IMX6UL_USBPHY1_ADDR =3D 0x020C9000, - FSL_IMX6UL_USBPHY1_SIZE =3D (4 * 1024), + FSL_IMX6UL_ANALOG_ADDR =3D 0x020C8000, + FSL_IMX6UL_ANALOG_SIZE =3D 0x300, + FSL_IMX6UL_CCM_ADDR =3D 0x020C4000, + FSL_IMX6UL_WDOG2_ADDR =3D 0x020C0000, FSL_IMX6UL_WDOG1_ADDR =3D 0x020BC000, + FSL_IMX6UL_KPP_ADDR =3D 0x020B8000, + FSL_IMX6UL_KPP_SIZE =3D 0x10, + FSL_IMX6UL_ENET2_ADDR =3D 0x020B4000, + FSL_IMX6UL_SNVS_LP_ADDR =3D 0x020B0000, + FSL_IMX6UL_SNVS_LP_SIZE =3D (16 * KiB), + FSL_IMX6UL_GPIO5_ADDR =3D 0x020AC000, FSL_IMX6UL_GPIO4_ADDR =3D 0x020A8000, FSL_IMX6UL_GPIO3_ADDR =3D 0x020A4000, FSL_IMX6UL_GPIO2_ADDR =3D 0x020A0000, FSL_IMX6UL_GPIO1_ADDR =3D 0x0209C000, + FSL_IMX6UL_GPT1_ADDR =3D 0x02098000, + FSL_IMX6UL_CAN2_ADDR =3D 0x02094000, FSL_IMX6UL_CAN1_ADDR =3D 0x02090000, + FSL_IMX6UL_CANn_SIZE =3D (4 * KiB), + FSL_IMX6UL_PWM4_ADDR =3D 0x0208C000, FSL_IMX6UL_PWM3_ADDR =3D 0x02088000, FSL_IMX6UL_PWM2_ADDR =3D 0x02084000, FSL_IMX6UL_PWM1_ADDR =3D 0x02080000, + FSL_IMX6UL_PWMn_SIZE =3D 0x20, + FSL_IMX6UL_AIPS1_CFG_ADDR =3D 0x0207C000, + FSL_IMX6UL_AIPS1_CFG_SIZE =3D (16 * KiB), + FSL_IMX6UL_BEE_ADDR =3D 0x02044000, + FSL_IMX6UL_BEE_SIZE =3D (16 * KiB), + FSL_IMX6UL_TOUCH_CTRL_ADDR =3D 0x02040000, + FSL_IMX6UL_TOUCH_CTRL_SIZE =3D 0x100, + FSL_IMX6UL_SPBA_ADDR =3D 0x0203C000, + FSL_IMX6UL_SPBA_SIZE =3D 0x100, + FSL_IMX6UL_ASRC_ADDR =3D 0x02034000, + FSL_IMX6UL_ASRC_SIZE =3D 0x100, + FSL_IMX6UL_SAI3_ADDR =3D 0x02030000, FSL_IMX6UL_SAI2_ADDR =3D 0x0202C000, FSL_IMX6UL_SAI1_ADDR =3D 0x02028000, + FSL_IMX6UL_SAIn_SIZE =3D 0x200, + FSL_IMX6UL_UART8_ADDR =3D 0x02024000, FSL_IMX6UL_UART1_ADDR =3D 0x02020000, FSL_IMX6UL_UART7_ADDR =3D 0x02018000, + FSL_IMX6UL_ECSPI4_ADDR =3D 0x02014000, FSL_IMX6UL_ECSPI3_ADDR =3D 0x02010000, FSL_IMX6UL_ECSPI2_ADDR =3D 0x0200C000, FSL_IMX6UL_ECSPI1_ADDR =3D 0x02008000, + FSL_IMX6UL_SPDIF_ADDR =3D 0x02004000, + FSL_IMX6UL_SPDIF_SIZE =3D 0x100, + /* AIPS-1 End */ + + FSL_IMX6UL_BCH_ADDR =3D 0x01808000, + FSL_IMX6UL_BCH_SIZE =3D 0x200, + + FSL_IMX6UL_GPMI_ADDR =3D 0x01806000, + FSL_IMX6UL_GPMI_SIZE =3D 0x200, =20 FSL_IMX6UL_APBH_DMA_ADDR =3D 0x01804000, - FSL_IMX6UL_APBH_DMA_SIZE =3D (32 * 1024), + FSL_IMX6UL_APBH_DMA_SIZE =3D (4 * KiB), =20 FSL_IMX6UL_A7MPCORE_ADDR =3D 0x00A00000, =20 FSL_IMX6UL_OCRAM_ALIAS_ADDR =3D 0x00920000, - FSL_IMX6UL_OCRAM_ALIAS_SIZE =3D 0x00060000, + FSL_IMX6UL_OCRAM_ALIAS_SIZE =3D (384 * KiB), + FSL_IMX6UL_OCRAM_MEM_ADDR =3D 0x00900000, - FSL_IMX6UL_OCRAM_MEM_SIZE =3D 0x00020000, + FSL_IMX6UL_OCRAM_MEM_SIZE =3D (128 * KiB), + FSL_IMX6UL_CAAM_MEM_ADDR =3D 0x00100000, - FSL_IMX6UL_CAAM_MEM_SIZE =3D 0x00008000, + FSL_IMX6UL_CAAM_MEM_SIZE =3D (32 * KiB), + FSL_IMX6UL_ROM_ADDR =3D 0x00000000, - FSL_IMX6UL_ROM_SIZE =3D 0x00018000, + FSL_IMX6UL_ROM_SIZE =3D (96 * KiB), }; =20 enum FslIMX6ULIRQs { --=20 2.34.1 From nobody Sat May 18 09:01:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1692966168733776.3635609027879; Fri, 25 Aug 2023 05:22:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qZVp6-000473-TF; Fri, 25 Aug 2023 08:21:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qZVoi-0003wu-Ca; Fri, 25 Aug 2023 08:21:34 -0400 Received: from relay3-d.mail.gandi.net ([2001:4b98:dc4:8::223]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qZVob-0004xD-Ve; Fri, 25 Aug 2023 08:21:28 -0400 Received: by mail.gandi.net (Postfix) with ESMTPSA id E2E796000E; Fri, 25 Aug 2023 12:21:21 +0000 (UTC) From: Jean-Christophe Dubois To: qemu-arm@nongnu.org Cc: Jean-Christophe Dubois , qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 3/6] Add i.MX6UL missing devices. Date: Fri, 25 Aug 2023 14:20:53 +0200 Message-Id: <59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: jcd@tribudubois.net Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4b98:dc4:8::223; envelope-from=jcd@tribudubois.net; helo=relay3-d.mail.gandi.net X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1692966170969100009 * Add TZASC as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add CSU as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add 4 missing PWM devices Signed-off-by: Jean-Christophe Dubois Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/fsl-imx6ul.c | 16 ++++++++++++++++ include/hw/arm/fsl-imx6ul.h | 2 +- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 06a32aff64..e37b69a5e1 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -583,6 +583,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error= **errp) FSL_IMX6UL_PWM2_ADDR, FSL_IMX6UL_PWM3_ADDR, FSL_IMX6UL_PWM4_ADDR, + FSL_IMX6UL_PWM5_ADDR, + FSL_IMX6UL_PWM6_ADDR, + FSL_IMX6UL_PWM7_ADDR, + FSL_IMX6UL_PWM8_ADDR, }; =20 snprintf(name, NAME_SIZE, "pwm%d", i); @@ -636,6 +640,18 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error= **errp) create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, FSL_IMX6UL_LCDIF_SIZE); =20 + /* + * CSU + */ + create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR, + FSL_IMX6UL_CSU_SIZE); + + /* + * TZASC + */ + create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR, + FSL_IMX6UL_TZASC_SIZE); + /* * ROM memory */ diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index f7bf684b42..63012628ff 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -60,7 +60,7 @@ enum FslIMX6ULConfiguration { FSL_IMX6UL_NUM_USBS =3D 2, FSL_IMX6UL_NUM_SAIS =3D 3, FSL_IMX6UL_NUM_CANS =3D 2, - FSL_IMX6UL_NUM_PWMS =3D 4, + FSL_IMX6UL_NUM_PWMS =3D 8, }; =20 struct FslIMX6ULState { --=20 2.34.1 From nobody Sat May 18 09:01:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass 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+0000 (UTC) From: Jean-Christophe Dubois To: qemu-arm@nongnu.org Cc: Jean-Christophe Dubois , qemu-devel@nongnu.org Subject: [PATCH v4 4/6] Refactor i.MX7 processor code Date: Fri, 25 Aug 2023 14:20:54 +0200 Message-Id: <59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: jcd@tribudubois.net Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=217.70.183.195; envelope-from=jcd@tribudubois.net; helo=relay3-d.mail.gandi.net X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1692966190975100001 Content-Type: text/plain; charset="utf-8" * Add Addr and size definition for all i.MX7 devices in i.MX7 header file. * Use those newly defined named constants whenever possible. * Standardize the way we init a familly of unimplemented devices - SAI - PWM - CAN * Add/rework few comments Signed-off-by: Jean-Christophe Dubois Reviewed-by: Peter Maydell --- hw/arm/fsl-imx7.c | 130 ++++++++++----- include/hw/arm/fsl-imx7.h | 326 ++++++++++++++++++++++++++++---------- 2 files changed, 333 insertions(+), 123 deletions(-) diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 9e41d4b677..e976053539 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -36,6 +36,9 @@ static void fsl_imx7_init(Object *obj) char name[NAME_SIZE]; int i; =20 + /* + * CPUs + */ for (i =3D 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) { snprintf(name, NAME_SIZE, "cpu%d", i); object_initialize_child(obj, name, &s->cpu[i], @@ -49,7 +52,7 @@ static void fsl_imx7_init(Object *obj) TYPE_A15MPCORE_PRIV); =20 /* - * GPIOs 1 to 7 + * GPIOs */ for (i =3D 0; i < FSL_IMX7_NUM_GPIOS; i++) { snprintf(name, NAME_SIZE, "gpio%d", i); @@ -57,7 +60,7 @@ static void fsl_imx7_init(Object *obj) } =20 /* - * GPT1, 2, 3, 4 + * GPTs */ for (i =3D 0; i < FSL_IMX7_NUM_GPTS; i++) { snprintf(name, NAME_SIZE, "gpt%d", i); @@ -79,19 +82,24 @@ static void fsl_imx7_init(Object *obj) */ object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); =20 + /* + * ECSPIs + */ for (i =3D 0; i < FSL_IMX7_NUM_ECSPIS; i++) { snprintf(name, NAME_SIZE, "spi%d", i + 1); object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); } =20 - + /* + * I2Cs + */ for (i =3D 0; i < FSL_IMX7_NUM_I2CS; i++) { snprintf(name, NAME_SIZE, "i2c%d", i + 1); object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); } =20 /* - * UART + * UARTs */ for (i =3D 0; i < FSL_IMX7_NUM_UARTS; i++) { snprintf(name, NAME_SIZE, "uart%d", i); @@ -99,7 +107,7 @@ static void fsl_imx7_init(Object *obj) } =20 /* - * Ethernet + * Ethernets */ for (i =3D 0; i < FSL_IMX7_NUM_ETHS; i++) { snprintf(name, NAME_SIZE, "eth%d", i); @@ -107,7 +115,7 @@ static void fsl_imx7_init(Object *obj) } =20 /* - * SDHCI + * SDHCIs */ for (i =3D 0; i < FSL_IMX7_NUM_USDHCS; i++) { snprintf(name, NAME_SIZE, "usdhc%d", i); @@ -120,7 +128,7 @@ static void fsl_imx7_init(Object *obj) object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); =20 /* - * Watchdog + * Watchdogs */ for (i =3D 0; i < FSL_IMX7_NUM_WDTS; i++) { snprintf(name, NAME_SIZE, "wdt%d", i); @@ -132,8 +140,14 @@ static void fsl_imx7_init(Object *obj) */ object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); =20 + /* + * PCIE + */ object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HO= ST); =20 + /* + * USBs + */ for (i =3D 0; i < FSL_IMX7_NUM_USBS; i++) { snprintf(name, NAME_SIZE, "usb%d", i); object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); @@ -156,6 +170,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) return; } =20 + /* + * CPUs + */ for (i =3D 0; i < smp_cpus; i++) { o =3D OBJECT(&s->cpu[i]); =20 @@ -206,10 +223,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error = **errp) * A7MPCORE DAP */ create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR, - 0x100000); + FSL_IMX7_A7MPCORE_DAP_SIZE); =20 /* - * GPT1, 2, 3, 4 + * GPTs */ for (i =3D 0; i < FSL_IMX7_NUM_GPTS; i++) { static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] =3D { @@ -234,6 +251,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) FSL_IMX7_GPTn_IRQ[i])); } =20 + /* + * GPIOs + */ for (i =3D 0; i < FSL_IMX7_NUM_GPIOS; i++) { static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] =3D { FSL_IMX7_GPIO1_ADDR, @@ -281,16 +301,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error = **errp) /* * IOMUXC and IOMUXC_LPSR */ - for (i =3D 0; i < FSL_IMX7_NUM_IOMUXCS; i++) { - static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = =3D { - FSL_IMX7_IOMUXC_ADDR, - FSL_IMX7_IOMUXC_LPSR_ADDR, - }; - - snprintf(name, NAME_SIZE, "iomuxc%d", i); - create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i], - FSL_IMX7_IOMUXCn_SIZE); - } + create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR, + FSL_IMX7_IOMUXC_SIZE); + create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR, + FSL_IMX7_IOMUXC_LPSR_SIZE); =20 /* * CCM @@ -310,7 +324,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR); =20 - /* Initialize all ECSPI */ + /* + * ECSPIs + */ for (i =3D 0; i < FSL_IMX7_NUM_ECSPIS; i++) { static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] =3D { FSL_IMX7_ECSPI1_ADDR, @@ -335,6 +351,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) FSL_IMX7_SPIn_IRQ[i])); } =20 + /* + * I2Cs + */ for (i =3D 0; i < FSL_IMX7_NUM_I2CS; i++) { static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] =3D { FSL_IMX7_I2C1_ADDR, @@ -359,7 +378,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) } =20 /* - * UART + * UARTs */ for (i =3D 0; i < FSL_IMX7_NUM_UARTS; i++) { static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] =3D { @@ -394,7 +413,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) } =20 /* - * Ethernet + * Ethernets * * We must use two loops since phy_connected affects the other interfa= ce * and we have to set all properties before calling sysbus_realize(). @@ -434,7 +453,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) } =20 /* - * USDHC + * USDHCs */ for (i =3D 0; i < FSL_IMX7_NUM_USDHCS; i++) { static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] =3D { @@ -464,7 +483,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) * SNVS */ sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR); =20 /* * SRC @@ -472,7 +491,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZ= E); =20 /* - * Watchdog + * Watchdogs */ for (i =3D 0; i < FSL_IMX7_NUM_WDTS; i++) { static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] =3D { @@ -509,25 +528,49 @@ static void fsl_imx7_realize(DeviceState *dev, Error = **errp) create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_= SIZE); =20 /* - * PWM + * PWMs */ - create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_= SIZE); - create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_= SIZE); - create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_= SIZE); - create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_= SIZE); + for (i =3D 0; i < FSL_IMX7_NUM_PWMS; i++) { + static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] =3D { + FSL_IMX7_PWM1_ADDR, + FSL_IMX7_PWM2_ADDR, + FSL_IMX7_PWM3_ADDR, + FSL_IMX7_PWM4_ADDR, + }; + + snprintf(name, NAME_SIZE, "pwm%d", i); + create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i], + FSL_IMX7_PWMn_SIZE); + } =20 /* - * CAN + * CANs */ - create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_= SIZE); - create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_= SIZE); + for (i =3D 0; i < FSL_IMX7_NUM_CANS; i++) { + static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] =3D { + FSL_IMX7_CAN1_ADDR, + FSL_IMX7_CAN2_ADDR, + }; + + snprintf(name, NAME_SIZE, "can%d", i); + create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i], + FSL_IMX7_CANn_SIZE); + } =20 /* - * SAI (Audio SSI (Synchronous Serial Interface)) + * SAIs (Audio SSI (Synchronous Serial Interface)) */ - create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_= SIZE); - create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_= SIZE); - create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_= SIZE); + for (i =3D 0; i < FSL_IMX7_NUM_SAIS; i++) { + static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] =3D { + FSL_IMX7_SAI1_ADDR, + FSL_IMX7_SAI2_ADDR, + FSL_IMX7_SAI3_ADDR, + }; + + snprintf(name, NAME_SIZE, "sai%d", i); + create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i], + FSL_IMX7_SAIn_SIZE); + } =20 /* * OCOTP @@ -535,9 +578,15 @@ static void fsl_imx7_realize(DeviceState *dev, Error *= *errp) create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR, FSL_IMX7_OCOTP_SIZE); =20 + /* + * GPR + */ sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR); =20 + /* + * PCIE + */ sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR); =20 @@ -550,7 +599,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) irq =3D qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); =20 - + /* + * USBs + */ for (i =3D 0; i < FSL_IMX7_NUM_USBS; i++) { static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] =3D { FSL_IMX7_USBMISC1_ADDR, @@ -612,6 +663,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) */ create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, FSL_IMX7_PCIE_PHY_SIZE); + } =20 static Property fsl_imx7_properties[] =3D { diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index fcce6421c8..06b2c5e4ac 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -25,7 +25,6 @@ #include "hw/misc/imx7_ccm.h" #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx7_gpr.h" -#include "hw/misc/imx6_src.h" #include "hw/watchdog/wdt_imx2.h" #include "hw/gpio/imx_gpio.h" #include "hw/char/imx_serial.h" @@ -39,6 +38,7 @@ #include "hw/usb/chipidea.h" #include "cpu.h" #include "qom/object.h" +#include "qemu/units.h" =20 #define TYPE_FSL_IMX7 "fsl-imx7" OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7) @@ -57,6 +57,9 @@ enum FslIMX7Configuration { FSL_IMX7_NUM_ECSPIS =3D 4, FSL_IMX7_NUM_USBS =3D 3, FSL_IMX7_NUM_ADCS =3D 2, + FSL_IMX7_NUM_SAIS =3D 3, + FSL_IMX7_NUM_CANS =3D 2, + FSL_IMX7_NUM_PWMS =3D 4, }; =20 struct FslIMX7State { @@ -87,80 +90,106 @@ struct FslIMX7State { =20 enum FslIMX7MemoryMap { FSL_IMX7_MMDC_ADDR =3D 0x80000000, - FSL_IMX7_MMDC_SIZE =3D 2 * 1024 * 1024 * 1024UL, + FSL_IMX7_MMDC_SIZE =3D (2 * GiB), =20 - FSL_IMX7_GPIO1_ADDR =3D 0x30200000, - FSL_IMX7_GPIO2_ADDR =3D 0x30210000, - FSL_IMX7_GPIO3_ADDR =3D 0x30220000, - FSL_IMX7_GPIO4_ADDR =3D 0x30230000, - FSL_IMX7_GPIO5_ADDR =3D 0x30240000, - FSL_IMX7_GPIO6_ADDR =3D 0x30250000, - FSL_IMX7_GPIO7_ADDR =3D 0x30260000, + FSL_IMX7_QSPI1_MEM_ADDR =3D 0x60000000, + FSL_IMX7_QSPI1_MEM_SIZE =3D (256 * MiB), =20 - FSL_IMX7_IOMUXC_LPSR_GPR_ADDR =3D 0x30270000, + FSL_IMX7_PCIE1_MEM_ADDR =3D 0x40000000, + FSL_IMX7_PCIE1_MEM_SIZE =3D (256 * MiB), =20 - FSL_IMX7_WDOG1_ADDR =3D 0x30280000, - FSL_IMX7_WDOG2_ADDR =3D 0x30290000, - FSL_IMX7_WDOG3_ADDR =3D 0x302A0000, - FSL_IMX7_WDOG4_ADDR =3D 0x302B0000, + FSL_IMX7_QSPI1_RX_BUF_ADDR =3D 0x34000000, + FSL_IMX7_QSPI1_RX_BUF_SIZE =3D (32 * MiB), =20 - FSL_IMX7_IOMUXC_LPSR_ADDR =3D 0x302C0000, + /* PCIe Peripherals */ + FSL_IMX7_PCIE_REG_ADDR =3D 0x33800000, =20 - FSL_IMX7_GPT1_ADDR =3D 0x302D0000, - FSL_IMX7_GPT2_ADDR =3D 0x302E0000, - FSL_IMX7_GPT3_ADDR =3D 0x302F0000, - FSL_IMX7_GPT4_ADDR =3D 0x30300000, + /* MMAP Peripherals */ + FSL_IMX7_DMA_APBH_ADDR =3D 0x33000000, + FSL_IMX7_DMA_APBH_SIZE =3D 0x8000, + + /* GPV configuration */ + FSL_IMX7_GPV6_ADDR =3D 0x32600000, + FSL_IMX7_GPV5_ADDR =3D 0x32500000, + FSL_IMX7_GPV4_ADDR =3D 0x32400000, + FSL_IMX7_GPV3_ADDR =3D 0x32300000, + FSL_IMX7_GPV2_ADDR =3D 0x32200000, + FSL_IMX7_GPV1_ADDR =3D 0x32100000, + FSL_IMX7_GPV0_ADDR =3D 0x32000000, + FSL_IMX7_GPVn_SIZE =3D (1 * MiB), + + /* Arm Peripherals */ + FSL_IMX7_A7MPCORE_ADDR =3D 0x31000000, =20 - FSL_IMX7_IOMUXC_ADDR =3D 0x30330000, - FSL_IMX7_IOMUXC_GPR_ADDR =3D 0x30340000, - FSL_IMX7_IOMUXCn_SIZE =3D 0x1000, + /* AIPS-3 Begin */ =20 - FSL_IMX7_OCOTP_ADDR =3D 0x30350000, - FSL_IMX7_OCOTP_SIZE =3D 0x10000, + FSL_IMX7_ENET2_ADDR =3D 0x30BF0000, + FSL_IMX7_ENET1_ADDR =3D 0x30BE0000, =20 - FSL_IMX7_ANALOG_ADDR =3D 0x30360000, - FSL_IMX7_SNVS_ADDR =3D 0x30370000, - FSL_IMX7_CCM_ADDR =3D 0x30380000, + FSL_IMX7_SDMA_ADDR =3D 0x30BD0000, + FSL_IMX7_SDMA_SIZE =3D (4 * KiB), =20 - FSL_IMX7_SRC_ADDR =3D 0x30390000, - FSL_IMX7_SRC_SIZE =3D 0x1000, + FSL_IMX7_EIM_ADDR =3D 0x30BC0000, + FSL_IMX7_EIM_SIZE =3D (4 * KiB), =20 - FSL_IMX7_ADC1_ADDR =3D 0x30610000, - FSL_IMX7_ADC2_ADDR =3D 0x30620000, - FSL_IMX7_ADCn_SIZE =3D 0x1000, + FSL_IMX7_QSPI_ADDR =3D 0x30BB0000, + FSL_IMX7_QSPI_SIZE =3D 0x8000, =20 - FSL_IMX7_PWM1_ADDR =3D 0x30660000, - FSL_IMX7_PWM2_ADDR =3D 0x30670000, - FSL_IMX7_PWM3_ADDR =3D 0x30680000, - FSL_IMX7_PWM4_ADDR =3D 0x30690000, - FSL_IMX7_PWMn_SIZE =3D 0x10000, + FSL_IMX7_SIM2_ADDR =3D 0x30BA0000, + FSL_IMX7_SIM1_ADDR =3D 0x30B90000, + FSL_IMX7_SIMn_SIZE =3D (4 * KiB), =20 - FSL_IMX7_PCIE_PHY_ADDR =3D 0x306D0000, - FSL_IMX7_PCIE_PHY_SIZE =3D 0x10000, + FSL_IMX7_USDHC3_ADDR =3D 0x30B60000, + FSL_IMX7_USDHC2_ADDR =3D 0x30B50000, + FSL_IMX7_USDHC1_ADDR =3D 0x30B40000, =20 - FSL_IMX7_GPC_ADDR =3D 0x303A0000, + FSL_IMX7_USB3_ADDR =3D 0x30B30000, + FSL_IMX7_USBMISC3_ADDR =3D 0x30B30200, + FSL_IMX7_USB2_ADDR =3D 0x30B20000, + FSL_IMX7_USBMISC2_ADDR =3D 0x30B20200, + FSL_IMX7_USB1_ADDR =3D 0x30B10000, + FSL_IMX7_USBMISC1_ADDR =3D 0x30B10200, + FSL_IMX7_USBMISCn_SIZE =3D 0x200, =20 - FSL_IMX7_CAAM_ADDR =3D 0x30900000, - FSL_IMX7_CAAM_SIZE =3D 0x40000, + FSL_IMX7_USB_PL301_ADDR =3D 0x30AD0000, + FSL_IMX7_USB_PL301_SIZE =3D (64 * KiB), =20 - FSL_IMX7_CAN1_ADDR =3D 0x30A00000, - FSL_IMX7_CAN2_ADDR =3D 0x30A10000, - FSL_IMX7_CANn_SIZE =3D 0x10000, + FSL_IMX7_SEMAPHORE_HS_ADDR =3D 0x30AC0000, + FSL_IMX7_SEMAPHORE_HS_SIZE =3D (64 * KiB), + + FSL_IMX7_MUB_ADDR =3D 0x30AB0000, + FSL_IMX7_MUA_ADDR =3D 0x30AA0000, + FSL_IMX7_MUn_SIZE =3D (KiB), + + FSL_IMX7_UART7_ADDR =3D 0x30A90000, + FSL_IMX7_UART6_ADDR =3D 0x30A80000, + FSL_IMX7_UART5_ADDR =3D 0x30A70000, + FSL_IMX7_UART4_ADDR =3D 0x30A60000, =20 - FSL_IMX7_I2C1_ADDR =3D 0x30A20000, - FSL_IMX7_I2C2_ADDR =3D 0x30A30000, - FSL_IMX7_I2C3_ADDR =3D 0x30A40000, FSL_IMX7_I2C4_ADDR =3D 0x30A50000, + FSL_IMX7_I2C3_ADDR =3D 0x30A40000, + FSL_IMX7_I2C2_ADDR =3D 0x30A30000, + FSL_IMX7_I2C1_ADDR =3D 0x30A20000, =20 - FSL_IMX7_ECSPI1_ADDR =3D 0x30820000, - FSL_IMX7_ECSPI2_ADDR =3D 0x30830000, - FSL_IMX7_ECSPI3_ADDR =3D 0x30840000, - FSL_IMX7_ECSPI4_ADDR =3D 0x30630000, + FSL_IMX7_CAN2_ADDR =3D 0x30A10000, + FSL_IMX7_CAN1_ADDR =3D 0x30A00000, + FSL_IMX7_CANn_SIZE =3D (4 * KiB), =20 - FSL_IMX7_LCDIF_ADDR =3D 0x30730000, - FSL_IMX7_LCDIF_SIZE =3D 0x1000, + FSL_IMX7_AIPS3_CONF_ADDR =3D 0x309F0000, + FSL_IMX7_AIPS3_CONF_SIZE =3D (64 * KiB), =20 - FSL_IMX7_UART1_ADDR =3D 0x30860000, + FSL_IMX7_CAAM_ADDR =3D 0x30900000, + FSL_IMX7_CAAM_SIZE =3D (256 * KiB), + + FSL_IMX7_SPBA_ADDR =3D 0x308F0000, + FSL_IMX7_SPBA_SIZE =3D (4 * KiB), + + FSL_IMX7_SAI3_ADDR =3D 0x308C0000, + FSL_IMX7_SAI2_ADDR =3D 0x308B0000, + FSL_IMX7_SAI1_ADDR =3D 0x308A0000, + FSL_IMX7_SAIn_SIZE =3D (4 * KiB), + + FSL_IMX7_UART3_ADDR =3D 0x30880000, /* * Some versions of the reference manual claim that UART2 is @ * 0x30870000, but experiments with HW + DT files in upstream @@ -168,45 +197,174 @@ enum FslIMX7MemoryMap { * actually located @ 0x30890000 */ FSL_IMX7_UART2_ADDR =3D 0x30890000, - FSL_IMX7_UART3_ADDR =3D 0x30880000, - FSL_IMX7_UART4_ADDR =3D 0x30A60000, - FSL_IMX7_UART5_ADDR =3D 0x30A70000, - FSL_IMX7_UART6_ADDR =3D 0x30A80000, - FSL_IMX7_UART7_ADDR =3D 0x30A90000, + FSL_IMX7_UART1_ADDR =3D 0x30860000, =20 - FSL_IMX7_SAI1_ADDR =3D 0x308A0000, - FSL_IMX7_SAI2_ADDR =3D 0x308B0000, - FSL_IMX7_SAI3_ADDR =3D 0x308C0000, - FSL_IMX7_SAIn_SIZE =3D 0x10000, + FSL_IMX7_ECSPI3_ADDR =3D 0x30840000, + FSL_IMX7_ECSPI2_ADDR =3D 0x30830000, + FSL_IMX7_ECSPI1_ADDR =3D 0x30820000, + FSL_IMX7_ECSPIn_SIZE =3D (4 * KiB), =20 - FSL_IMX7_ENET1_ADDR =3D 0x30BE0000, - FSL_IMX7_ENET2_ADDR =3D 0x30BF0000, + /* AIPS-3 End */ =20 - FSL_IMX7_USB1_ADDR =3D 0x30B10000, - FSL_IMX7_USBMISC1_ADDR =3D 0x30B10200, - FSL_IMX7_USB2_ADDR =3D 0x30B20000, - FSL_IMX7_USBMISC2_ADDR =3D 0x30B20200, - FSL_IMX7_USB3_ADDR =3D 0x30B30000, - FSL_IMX7_USBMISC3_ADDR =3D 0x30B30200, - FSL_IMX7_USBMISCn_SIZE =3D 0x200, + /* AIPS-2 Begin */ =20 - FSL_IMX7_USDHC1_ADDR =3D 0x30B40000, - FSL_IMX7_USDHC2_ADDR =3D 0x30B50000, - FSL_IMX7_USDHC3_ADDR =3D 0x30B60000, + FSL_IMX7_AXI_DEBUG_MON_ADDR =3D 0x307E0000, + FSL_IMX7_AXI_DEBUG_MON_SIZE =3D (64 * KiB), =20 - FSL_IMX7_SDMA_ADDR =3D 0x30BD0000, - FSL_IMX7_SDMA_SIZE =3D 0x1000, + FSL_IMX7_PERFMON2_ADDR =3D 0x307D0000, + FSL_IMX7_PERFMON1_ADDR =3D 0x307C0000, + FSL_IMX7_PERFMONn_SIZE =3D (64 * KiB), + + FSL_IMX7_DDRC_ADDR =3D 0x307A0000, + FSL_IMX7_DDRC_SIZE =3D (4 * KiB), + + FSL_IMX7_DDRC_PHY_ADDR =3D 0x30790000, + FSL_IMX7_DDRC_PHY_SIZE =3D (4 * KiB), + + FSL_IMX7_TZASC_ADDR =3D 0x30780000, + FSL_IMX7_TZASC_SIZE =3D (64 * KiB), + + FSL_IMX7_MIPI_DSI_ADDR =3D 0x30760000, + FSL_IMX7_MIPI_DSI_SIZE =3D (4 * KiB), + + FSL_IMX7_MIPI_CSI_ADDR =3D 0x30750000, + FSL_IMX7_MIPI_CSI_SIZE =3D 0x4000, + + FSL_IMX7_LCDIF_ADDR =3D 0x30730000, + FSL_IMX7_LCDIF_SIZE =3D 0x8000, + + FSL_IMX7_CSI_ADDR =3D 0x30710000, + FSL_IMX7_CSI_SIZE =3D (4 * KiB), + + FSL_IMX7_PXP_ADDR =3D 0x30700000, + FSL_IMX7_PXP_SIZE =3D 0x4000, + + FSL_IMX7_EPDC_ADDR =3D 0x306F0000, + FSL_IMX7_EPDC_SIZE =3D (4 * KiB), + + FSL_IMX7_PCIE_PHY_ADDR =3D 0x306D0000, + FSL_IMX7_PCIE_PHY_SIZE =3D (4 * KiB), + + FSL_IMX7_SYSCNT_CTRL_ADDR =3D 0x306C0000, + FSL_IMX7_SYSCNT_CMP_ADDR =3D 0x306B0000, + FSL_IMX7_SYSCNT_RD_ADDR =3D 0x306A0000, + + FSL_IMX7_PWM4_ADDR =3D 0x30690000, + FSL_IMX7_PWM3_ADDR =3D 0x30680000, + FSL_IMX7_PWM2_ADDR =3D 0x30670000, + FSL_IMX7_PWM1_ADDR =3D 0x30660000, + FSL_IMX7_PWMn_SIZE =3D (4 * KiB), + + FSL_IMX7_FlEXTIMER2_ADDR =3D 0x30650000, + FSL_IMX7_FlEXTIMER1_ADDR =3D 0x30640000, + FSL_IMX7_FLEXTIMERn_SIZE =3D (4 * KiB), + + FSL_IMX7_ECSPI4_ADDR =3D 0x30630000, + + FSL_IMX7_ADC2_ADDR =3D 0x30620000, + FSL_IMX7_ADC1_ADDR =3D 0x30610000, + FSL_IMX7_ADCn_SIZE =3D (4 * KiB), + + FSL_IMX7_AIPS2_CONF_ADDR =3D 0x305F0000, + FSL_IMX7_AIPS2_CONF_SIZE =3D (64 * KiB), + + /* AIPS-2 End */ + + /* AIPS-1 Begin */ + + FSL_IMX7_CSU_ADDR =3D 0x303E0000, + FSL_IMX7_CSU_SIZE =3D (64 * KiB), + + FSL_IMX7_RDC_ADDR =3D 0x303D0000, + FSL_IMX7_RDC_SIZE =3D (4 * KiB), + + FSL_IMX7_SEMAPHORE2_ADDR =3D 0x303C0000, + FSL_IMX7_SEMAPHORE1_ADDR =3D 0x303B0000, + FSL_IMX7_SEMAPHOREn_SIZE =3D (4 * KiB), + + FSL_IMX7_GPC_ADDR =3D 0x303A0000, + + FSL_IMX7_SRC_ADDR =3D 0x30390000, + FSL_IMX7_SRC_SIZE =3D (4 * KiB), + + FSL_IMX7_CCM_ADDR =3D 0x30380000, + + FSL_IMX7_SNVS_HP_ADDR =3D 0x30370000, + + FSL_IMX7_ANALOG_ADDR =3D 0x30360000, + + FSL_IMX7_OCOTP_ADDR =3D 0x30350000, + FSL_IMX7_OCOTP_SIZE =3D 0x10000, + + FSL_IMX7_IOMUXC_GPR_ADDR =3D 0x30340000, + FSL_IMX7_IOMUXC_GPR_SIZE =3D (4 * KiB), + + FSL_IMX7_IOMUXC_ADDR =3D 0x30330000, + FSL_IMX7_IOMUXC_SIZE =3D (4 * KiB), + + FSL_IMX7_KPP_ADDR =3D 0x30320000, + FSL_IMX7_KPP_SIZE =3D (4 * KiB), + + FSL_IMX7_ROMCP_ADDR =3D 0x30310000, + FSL_IMX7_ROMCP_SIZE =3D (4 * KiB), + + FSL_IMX7_GPT4_ADDR =3D 0x30300000, + FSL_IMX7_GPT3_ADDR =3D 0x302F0000, + FSL_IMX7_GPT2_ADDR =3D 0x302E0000, + FSL_IMX7_GPT1_ADDR =3D 0x302D0000, + + FSL_IMX7_IOMUXC_LPSR_ADDR =3D 0x302C0000, + FSL_IMX7_IOMUXC_LPSR_SIZE =3D (4 * KiB), + + FSL_IMX7_WDOG4_ADDR =3D 0x302B0000, + FSL_IMX7_WDOG3_ADDR =3D 0x302A0000, + FSL_IMX7_WDOG2_ADDR =3D 0x30290000, + FSL_IMX7_WDOG1_ADDR =3D 0x30280000, + + FSL_IMX7_IOMUXC_LPSR_GPR_ADDR =3D 0x30270000, + + FSL_IMX7_GPIO7_ADDR =3D 0x30260000, + FSL_IMX7_GPIO6_ADDR =3D 0x30250000, + FSL_IMX7_GPIO5_ADDR =3D 0x30240000, + FSL_IMX7_GPIO4_ADDR =3D 0x30230000, + FSL_IMX7_GPIO3_ADDR =3D 0x30220000, + FSL_IMX7_GPIO2_ADDR =3D 0x30210000, + FSL_IMX7_GPIO1_ADDR =3D 0x30200000, + + FSL_IMX7_AIPS1_CONF_ADDR =3D 0x301F0000, + FSL_IMX7_AIPS1_CONF_SIZE =3D (64 * KiB), =20 - FSL_IMX7_A7MPCORE_ADDR =3D 0x31000000, FSL_IMX7_A7MPCORE_DAP_ADDR =3D 0x30000000, + FSL_IMX7_A7MPCORE_DAP_SIZE =3D (1 * MiB), =20 - FSL_IMX7_PCIE_REG_ADDR =3D 0x33800000, - FSL_IMX7_PCIE_REG_SIZE =3D 16 * 1024, + /* AIPS-1 End */ =20 - FSL_IMX7_GPR_ADDR =3D 0x30340000, + FSL_IMX7_EIM_CS0_ADDR =3D 0x28000000, + FSL_IMX7_EIM_CS0_SIZE =3D (128 * MiB), =20 - FSL_IMX7_DMA_APBH_ADDR =3D 0x33000000, - FSL_IMX7_DMA_APBH_SIZE =3D 0x2000, + FSL_IMX7_OCRAM_PXP_ADDR =3D 0x00940000, + FSL_IMX7_OCRAM_PXP_SIZE =3D (32 * KiB), + + FSL_IMX7_OCRAM_EPDC_ADDR =3D 0x00920000, + FSL_IMX7_OCRAM_EPDC_SIZE =3D (128 * KiB), + + FSL_IMX7_OCRAM_MEM_ADDR =3D 0x00900000, + FSL_IMX7_OCRAM_MEM_SIZE =3D (128 * KiB), + + FSL_IMX7_TCMU_ADDR =3D 0x00800000, + FSL_IMX7_TCMU_SIZE =3D (32 * KiB), + + FSL_IMX7_TCML_ADDR =3D 0x007F8000, + FSL_IMX7_TCML_SIZE =3D (32 * KiB), + + FSL_IMX7_OCRAM_S_ADDR =3D 0x00180000, + FSL_IMX7_OCRAM_S_SIZE =3D (32 * KiB), + + FSL_IMX7_CAAM_MEM_ADDR =3D 0x00100000, + FSL_IMX7_CAAM_MEM_SIZE =3D (32 * KiB), + + FSL_IMX7_ROM_ADDR =3D 0x00000000, + FSL_IMX7_ROM_SIZE =3D (96 * KiB), }; =20 enum FslIMX7IRQs { --=20 2.34.1 From nobody Sat May 18 09:01:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1692966169832475.91962785784654; Fri, 25 Aug 2023 05:22:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qZVp3-00042O-Cx; Fri, 25 Aug 2023 08:21:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qZVos-0003zU-2K; Fri, 25 Aug 2023 08:21:43 -0400 Received: from relay3-d.mail.gandi.net ([217.70.183.195]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qZVoi-0004xm-Tu; Fri, 25 Aug 2023 08:21:37 -0400 Received: by mail.gandi.net (Postfix) with ESMTPSA id 8523260003; Fri, 25 Aug 2023 12:21:26 +0000 (UTC) From: Jean-Christophe Dubois To: qemu-arm@nongnu.org Cc: Jean-Christophe Dubois , qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 5/6] Add i.MX7 missing TZ devices and memory regions Date: Fri, 25 Aug 2023 14:20:55 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: jcd@tribudubois.net Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=217.70.183.195; envelope-from=jcd@tribudubois.net; helo=relay3-d.mail.gandi.net X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1692966171988100011 * Add TZASC as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add CSU as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add various memory segments - OCRAM - OCRAM EPDC - OCRAM PXP - OCRAM S - ROM - CAAM Signed-off-by: Jean-Christophe Dubois Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/fsl-imx7.c | 63 +++++++++++++++++++++++++++++++++++++++ include/hw/arm/fsl-imx7.h | 7 +++++ 2 files changed, 70 insertions(+) diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index e976053539..97e982bf06 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -664,6 +664,69 @@ static void fsl_imx7_realize(DeviceState *dev, Error *= *errp) create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, FSL_IMX7_PCIE_PHY_SIZE); =20 + /* + * CSU + */ + create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR, + FSL_IMX7_CSU_SIZE); + + /* + * TZASC + */ + create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR, + FSL_IMX7_TZASC_SIZE); + + /* + * OCRAM memory + */ + memory_region_init_ram(&s->ocram, NULL, "imx7.ocram", + FSL_IMX7_OCRAM_MEM_SIZE, + &error_abort); + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_AD= DR, + &s->ocram); + + /* + * OCRAM EPDC memory + */ + memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc", + FSL_IMX7_OCRAM_EPDC_SIZE, + &error_abort); + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_A= DDR, + &s->ocram_epdc); + + /* + * OCRAM PXP memory + */ + memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp", + FSL_IMX7_OCRAM_PXP_SIZE, + &error_abort); + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_AD= DR, + &s->ocram_pxp); + + /* + * OCRAM_S memory + */ + memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s", + FSL_IMX7_OCRAM_S_SIZE, + &error_abort); + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR, + &s->ocram_s); + + /* + * ROM memory + */ + memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom", + FSL_IMX7_ROM_SIZE, &error_abort); + memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR, + &s->rom); + + /* + * CAAM memory + */ + memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam", + FSL_IMX7_CAAM_MEM_SIZE, &error_abort); + memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADD= R, + &s->caam); } =20 static Property fsl_imx7_properties[] =3D { diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 06b2c5e4ac..01e15004d7 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -84,6 +84,13 @@ struct FslIMX7State { IMX7GPRState gpr; ChipideaState usb[FSL_IMX7_NUM_USBS]; DesignwarePCIEHost pcie; + MemoryRegion rom; + MemoryRegion caam; + MemoryRegion ocram; + MemoryRegion ocram_epdc; + MemoryRegion ocram_pxp; + MemoryRegion ocram_s; + uint32_t phy_num[FSL_IMX7_NUM_ETHS]; bool phy_connected[FSL_IMX7_NUM_ETHS]; }; --=20 2.34.1 From nobody Sat May 18 09:01:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1692966195843334.5059603606296; Fri, 25 Aug 2023 05:23:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qZVp7-00047D-Bl; Fri, 25 Aug 2023 08:21:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qZVos-0003zW-Iu; Fri, 25 Aug 2023 08:21:43 -0400 Received: from relay3-d.mail.gandi.net ([2001:4b98:dc4:8::223]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qZVoj-0004y8-2a; Fri, 25 Aug 2023 08:21:37 -0400 Received: by mail.gandi.net (Postfix) with ESMTPSA id C357160005; Fri, 25 Aug 2023 12:21:28 +0000 (UTC) From: Jean-Christophe Dubois To: qemu-arm@nongnu.org Cc: Jean-Christophe Dubois , qemu-devel@nongnu.org, Peter Maydell Subject: [PATCH v4 6/6] Add i.MX7 SRC device implementation Date: Fri, 25 Aug 2023 14:20:56 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: jcd@tribudubois.net Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4b98:dc4:8::223; envelope-from=jcd@tribudubois.net; helo=relay3-d.mail.gandi.net X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1692966197916100003 Content-Type: text/plain; charset="utf-8" The SRC device is normally used to start the secondary CPU. When running Linux directly, QEMU is emulating a PSCI interface that UBOOT is installing at boot time and therefore the fact that the SRC device is unimplemented is hidden as Qemu respond directly to PSCI requets without using the SRC device. But if you try to run a more bare metal application (maybe uboot itself), then it is not possible to start the secondary CPU as the SRC is an unimplemented device. This patch adds the ability to start the secondary CPU through the SRC device so that you can use this feature in bare metal applications. Signed-off-by: Jean-Christophe Dubois Reviewed-by: Peter Maydell --- hw/arm/fsl-imx7.c | 8 +- hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + hw/misc/trace-events | 4 + include/hw/arm/fsl-imx7.h | 3 +- include/hw/misc/imx7_src.h | 66 +++++++++ 6 files changed, 356 insertions(+), 2 deletions(-) create mode 100644 hw/misc/imx7_src.c create mode 100644 include/hw/misc/imx7_src.h diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 97e982bf06..474cfdc87c 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -82,6 +82,11 @@ static void fsl_imx7_init(Object *obj) */ object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); =20 + /* + * SRC + */ + object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC); + /* * ECSPIs */ @@ -488,7 +493,8 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) /* * SRC */ - create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZ= E); + sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR); =20 /* * Watchdogs diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c new file mode 100644 index 0000000000..983251e86f --- /dev/null +++ b/hw/misc/imx7_src.c @@ -0,0 +1,276 @@ +/* + * IMX7 System Reset Controller + * + * Copyright (c) 2023 Jean-Christophe Dubois + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/misc/imx7_src.h" +#include "migration/vmstate.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qemu/main-loop.h" +#include "qemu/module.h" +#include "target/arm/arm-powerctl.h" +#include "hw/core/cpu.h" +#include "hw/registerfields.h" + +#include "trace.h" + +static const char *imx7_src_reg_name(uint32_t reg) +{ + static char unknown[20]; + + switch (reg) { + case SRC_SCR: + return "SRC_SCR"; + case SRC_A7RCR0: + return "SRC_A7RCR0"; + case SRC_A7RCR1: + return "SRC_A7RCR1"; + case SRC_M4RCR: + return "SRC_M4RCR"; + case SRC_ERCR: + return "SRC_ERCR"; + case SRC_HSICPHY_RCR: + return "SRC_HSICPHY_RCR"; + case SRC_USBOPHY1_RCR: + return "SRC_USBOPHY1_RCR"; + case SRC_USBOPHY2_RCR: + return "SRC_USBOPHY2_RCR"; + case SRC_PCIEPHY_RCR: + return "SRC_PCIEPHY_RCR"; + case SRC_SBMR1: + return "SRC_SBMR1"; + case SRC_SRSR: + return "SRC_SRSR"; + case SRC_SISR: + return "SRC_SISR"; + case SRC_SIMR: + return "SRC_SIMR"; + case SRC_SBMR2: + return "SRC_SBMR2"; + case SRC_GPR1: + return "SRC_GPR1"; + case SRC_GPR2: + return "SRC_GPR2"; + case SRC_GPR3: + return "SRC_GPR3"; + case SRC_GPR4: + return "SRC_GPR4"; + case SRC_GPR5: + return "SRC_GPR5"; + case SRC_GPR6: + return "SRC_GPR6"; + case SRC_GPR7: + return "SRC_GPR7"; + case SRC_GPR8: + return "SRC_GPR8"; + case SRC_GPR9: + return "SRC_GPR9"; + case SRC_GPR10: + return "SRC_GPR10"; + default: + sprintf(unknown, "%u ?", reg); + return unknown; + } +} + +static const VMStateDescription vmstate_imx7_src =3D { + .name =3D TYPE_IMX7_SRC, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_MAX), + VMSTATE_END_OF_LIST() + }, +}; + +static void imx7_src_reset(DeviceState *dev) +{ + IMX7SRCState *s =3D IMX7_SRC(dev); + + memset(s->regs, 0, sizeof(s->regs)); + + /* Set reset values */ + s->regs[SRC_SCR] =3D 0xA0; + s->regs[SRC_SRSR] =3D 0x1; + s->regs[SRC_SIMR] =3D 0x1F; +} + +static uint64_t imx7_src_read(void *opaque, hwaddr offset, unsigned size) +{ + uint32_t value =3D 0; + IMX7SRCState *s =3D (IMX7SRCState *)opaque; + uint32_t index =3D offset >> 2; + + if (index < SRC_MAX) { + value =3D s->regs[index]; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" + HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset); + } + + trace_imx7_src_read(imx7_src_reg_name(index), value); + + return value; +} + + +/* + * The reset is asynchronous so we need to defer clearing the reset + * bit until the work is completed. + */ + +struct SRCSCRResetInfo { + IMX7SRCState *s; + uint32_t reset_bit; +}; + +static void imx7_clear_reset_bit(CPUState *cpu, run_on_cpu_data data) +{ + struct SRCSCRResetInfo *ri =3D data.host_ptr; + IMX7SRCState *s =3D ri->s; + + assert(qemu_mutex_iothread_locked()); + + s->regs[SRC_A7RCR0] =3D deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, = 1, 0); + + trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0= ]); + + g_free(ri); +} + +static void imx7_defer_clear_reset_bit(uint32_t cpuid, + IMX7SRCState *s, + uint32_t reset_shift) +{ + struct SRCSCRResetInfo *ri; + CPUState *cpu =3D arm_get_cpu_by_id(cpuid); + + if (!cpu) { + return; + } + + ri =3D g_new(struct SRCSCRResetInfo, 1); + ri->s =3D s; + ri->reset_bit =3D reset_shift; + + async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri)); +} + + +static void imx7_src_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + IMX7SRCState *s =3D (IMX7SRCState *)opaque; + uint32_t index =3D offset >> 2; + long unsigned int change_mask; + uint32_t current_value =3D value; + + if (index >=3D SRC_MAX) { + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" + HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset); + return; + } + + trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0= ]); + + change_mask =3D s->regs[index] ^ (uint32_t)current_value; + + switch (index) { + case SRC_A7RCR0: + if (FIELD_EX32(change_mask, CORE0, RST)) { + arm_reset_cpu(0); + imx7_defer_clear_reset_bit(0, s, R_CORE0_RST_SHIFT); + } + if (FIELD_EX32(change_mask, CORE1, RST)) { + arm_reset_cpu(1); + imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT); + } + s->regs[index] =3D current_value; + break; + case SRC_A7RCR1: + /* + * On real hardware when the system reset controller starts a + * secondary CPU it runs through some boot ROM code which reads + * the SRC_GPRX registers controlling the start address and branch= es + * to it. + * Here we are taking a short cut and branching directly to the + * requested address (we don't want to run the boot ROM code inside + * QEMU) + */ + if (FIELD_EX32(change_mask, CORE1, ENABLE)) { + if (FIELD_EX32(current_value, CORE1, ENABLE)) { + /* CORE 1 is brought up */ + arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4], + 3, false); + } else { + /* CORE 1 is shut down */ + arm_set_cpu_off(1); + } + /* We clear the reset bits as the processor changed state */ + imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT); + clear_bit(R_CORE1_RST_SHIFT, &change_mask); + } + s->regs[index] =3D current_value; + break; + default: + s->regs[index] =3D current_value; + break; + } +} + +static const struct MemoryRegionOps imx7_src_ops =3D { + .read =3D imx7_src_read, + .write =3D imx7_src_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + /* + * Our device would not work correctly if the guest was doing + * unaligned access. This might not be a limitation on the real + * device but in practice there is no reason for a guest to access + * this device unaligned. + */ + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void imx7_src_realize(DeviceState *dev, Error **errp) +{ + IMX7SRCState *s =3D IMX7_SRC(dev); + + memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s, + TYPE_IMX7_SRC, 0x1000); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); +} + +static void imx7_src_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D imx7_src_realize; + dc->reset =3D imx7_src_reset; + dc->vmsd =3D &vmstate_imx7_src; + dc->desc =3D "i.MX6 System Reset Controller"; +} + +static const TypeInfo imx7_src_info =3D { + .name =3D TYPE_IMX7_SRC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IMX7SRCState), + .class_init =3D imx7_src_class_init, +}; + +static void imx7_src_register_types(void) +{ + type_register_static(&imx7_src_info); +} + +type_init(imx7_src_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 892f8b91c5..d9a370c1de 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -60,6 +60,7 @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( 'imx6_src.c', 'imx6ul_ccm.c', 'imx7_ccm.c', + 'imx7_src.c', 'imx7_gpr.c', 'imx7_snvs.c', 'imx_ccm.c', diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 4d1a0e17af..e8b2be14c0 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -199,6 +199,10 @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = =3D %d) =3D %d" ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <=3D 0x%" PRIx= 32 ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] =3D> 0x%" PRI= x32 =20 +# imx7_src.c +imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] =3D> 0x%" PRI= x32 +imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <=3D 0x%" PR= Ix32 + # iotkit-sysinfo.c iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit= SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKi= t SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 01e15004d7..2cbfc6b2b2 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -25,6 +25,7 @@ #include "hw/misc/imx7_ccm.h" #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx7_gpr.h" +#include "hw/misc/imx7_src.h" #include "hw/watchdog/wdt_imx2.h" #include "hw/gpio/imx_gpio.h" #include "hw/char/imx_serial.h" @@ -74,6 +75,7 @@ struct FslIMX7State { IMX7CCMState ccm; IMX7AnalogState analog; IMX7SNVSState snvs; + IMX7SRCState src; IMXGPCv2State gpcv2; IMXSPIState spi[FSL_IMX7_NUM_ECSPIS]; IMXI2CState i2c[FSL_IMX7_NUM_I2CS]; @@ -292,7 +294,6 @@ enum FslIMX7MemoryMap { FSL_IMX7_GPC_ADDR =3D 0x303A0000, =20 FSL_IMX7_SRC_ADDR =3D 0x30390000, - FSL_IMX7_SRC_SIZE =3D (4 * KiB), =20 FSL_IMX7_CCM_ADDR =3D 0x30380000, =20 diff --git a/include/hw/misc/imx7_src.h b/include/hw/misc/imx7_src.h new file mode 100644 index 0000000000..b4b97dcb1c --- /dev/null +++ b/include/hw/misc/imx7_src.h @@ -0,0 +1,66 @@ +/* + * IMX7 System Reset Controller + * + * Copyright (C) 2023 Jean-Christophe Dubois + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef IMX7_SRC_H +#define IMX7_SRC_H + +#include "hw/sysbus.h" +#include "qemu/bitops.h" +#include "qom/object.h" + +#define SRC_SCR 0 +#define SRC_A7RCR0 1 +#define SRC_A7RCR1 2 +#define SRC_M4RCR 3 +#define SRC_ERCR 5 +#define SRC_HSICPHY_RCR 7 +#define SRC_USBOPHY1_RCR 8 +#define SRC_USBOPHY2_RCR 9 +#define SRC_MPIPHY_RCR 10 +#define SRC_PCIEPHY_RCR 11 +#define SRC_SBMR1 22 +#define SRC_SRSR 23 +#define SRC_SISR 26 +#define SRC_SIMR 27 +#define SRC_SBMR2 28 +#define SRC_GPR1 29 +#define SRC_GPR2 30 +#define SRC_GPR3 31 +#define SRC_GPR4 32 +#define SRC_GPR5 33 +#define SRC_GPR6 34 +#define SRC_GPR7 35 +#define SRC_GPR8 36 +#define SRC_GPR9 37 +#define SRC_GPR10 38 +#define SRC_MAX 39 + +/* SRC_A7SCR1 */ +#define R_CORE1_ENABLE_SHIFT 1 +#define R_CORE1_ENABLE_LENGTH 1 +/* SRC_A7SCR0 */ +#define R_CORE1_RST_SHIFT 5 +#define R_CORE1_RST_LENGTH 1 +#define R_CORE0_RST_SHIFT 4 +#define R_CORE0_RST_LENGTH 1 + +#define TYPE_IMX7_SRC "imx7.src" +OBJECT_DECLARE_SIMPLE_TYPE(IMX7SRCState, IMX7_SRC) + +struct IMX7SRCState { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion iomem; + + uint32_t regs[SRC_MAX]; +}; + +#endif /* IMX7_SRC_H */ --=20 2.34.1