From nobody Mon Feb 9 18:01:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686778580002931.7123467571099; Wed, 14 Jun 2023 14:36:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9Y87-0004UA-NI; Wed, 14 Jun 2023 17:34:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y86-0004TV-M9; Wed, 14 Jun 2023 17:34:14 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y85-0003mN-4A; Wed, 14 Jun 2023 17:34:14 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 0F8AB746377; Wed, 14 Jun 2023 23:34:06 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id DA322746369; Wed, 14 Jun 2023 23:34:05 +0200 (CEST) Message-Id: <8384ed0f7335093012bbd3d28fb2a543a2e7346c.1686776990.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 01/10] target/ppc: Remove some superfluous parentheses MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Greg Kurz , Daniel Henrique Barboza , Nicholas Piggin Date: Wed, 14 Jun 2023 23:34:05 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686778581754100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: BALATON Zoltan Acked-by: Nicholas Piggin --- target/ppc/excp_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 12d8a7257b..8298217e78 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1009,7 +1009,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) { int lev =3D env->error_code; =20 - if ((lev =3D=3D 1) && cpu->vhyp) { + if (lev =3D=3D 1 && cpu->vhyp) { dump_hcall(env); } else { dump_syscall(env); @@ -1027,7 +1027,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) * uses VOF and the 74xx CPUs, so although the 74xx don't have * HV mode, we need to keep hypercall support. */ - if ((lev =3D=3D 1) && cpu->vhyp) { + if (lev =3D=3D 1 && cpu->vhyp) { PPCVirtualHypervisorClass *vhc =3D PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); vhc->hypercall(cpu->vhyp, cpu); @@ -1481,7 +1481,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) case POWERPC_EXCP_SYSCALL: /* System call exception = */ lev =3D env->error_code; =20 - if ((lev =3D=3D 1) && cpu->vhyp) { + if (lev =3D=3D 1 && cpu->vhyp) { dump_hcall(env); } else { dump_syscall(env); @@ -1494,7 +1494,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) env->nip +=3D 4; =20 /* "PAPR mode" built-in hypercall emulation */ - if ((lev =3D=3D 1) && books_vhyp_handles_hcall(cpu)) { + if (lev =3D=3D 1 && books_vhyp_handles_hcall(cpu)) { PPCVirtualHypervisorClass *vhc =3D PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); vhc->hypercall(cpu->vhyp, cpu); --=20 2.30.9 From nobody Mon Feb 9 18:01:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168677854225488.04727054391174; Wed, 14 Jun 2023 14:35:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9Y88-0004Ua-HH; Wed, 14 Jun 2023 17:34:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y86-0004TX-Qe; Wed, 14 Jun 2023 17:34:14 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y85-0003mY-AR; Wed, 14 Jun 2023 17:34:14 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 0FA70746369; Wed, 14 Jun 2023 23:34:07 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id E5C7D746335; Wed, 14 Jun 2023 23:34:06 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 02/10] target/ppc: Remove unneeded parameter from powerpc_reset_wakeup() MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Greg Kurz , Daniel Henrique Barboza , Nicholas Piggin Date: Wed, 14 Jun 2023 23:34:06 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686778544232100003 Content-Type: text/plain; charset="utf-8" CPUState is rarely needed by this function (only for logging a fatal error) and it's easy to get from the env parameter so passing it separately is not necessary. Signed-off-by: BALATON Zoltan Acked-by: Nicholas Piggin --- target/ppc/excp_helper.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 8298217e78..3783315fdb 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -166,8 +166,7 @@ static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int= excp) } =20 #if defined(TARGET_PPC64) -static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp, - target_ulong *msr) +static int powerpc_reset_wakeup(CPUPPCState *env, int excp, target_ulong *= msr) { /* We no longer are in a PM state */ env->resume_as_sreset =3D false; @@ -202,8 +201,8 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCSta= te *env, int excp, *msr |=3D SRR1_WAKEHVI; break; default: - cpu_abort(cs, "Unsupported exception %d in Power Save mode\n", - excp); + cpu_abort(env_cpu(env), + "Unsupported exception %d in Power Save mode\n", excp); } return POWERPC_EXCP_RESET; } @@ -1353,7 +1352,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) * P7/P8/P9 */ if (env->resume_as_sreset) { - excp =3D powerpc_reset_wakeup(cs, env, excp, &msr); + excp =3D powerpc_reset_wakeup(env, excp, &msr); } =20 /* --=20 2.30.9 From nobody Mon Feb 9 18:01:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686778523238788.8995934602385; Wed, 14 Jun 2023 14:35:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9Y8A-0004Vw-6v; Wed, 14 Jun 2023 17:34:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y88-0004UH-Am; Wed, 14 Jun 2023 17:34:16 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y86-0003mx-GA; Wed, 14 Jun 2023 17:34:16 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 2FEEE748A55; Wed, 14 Jun 2023 23:34:08 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id F001A748A4D; Wed, 14 Jun 2023 23:34:07 +0200 (CEST) Message-Id: <9cfffaa35aa894086dd092af6b0b26f2d62ff3de.1686776990.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 03/10] target/ppc: Move common check in exception handlers to a function MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Greg Kurz , Daniel Henrique Barboza , Nicholas Piggin Date: Wed, 14 Jun 2023 23:34:07 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686778524314100001 Content-Type: text/plain; charset="utf-8" All powerpc exception handlers share some code when handling machine check exceptions. Move this to a common function. Signed-off-by: BALATON Zoltan Reviewed-by: Nicholas Piggin --- target/ppc/excp_helper.c | 114 +++++++++------------------------------ 1 file changed, 25 insertions(+), 89 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 3783315fdb..79f5ca1034 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -403,6 +403,25 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu, ta= rget_ulong vector, env->reserve_addr =3D -1; } =20 +static void powerpc_mcheck_checkstop(CPUPPCState *env) +{ + CPUState *cs =3D env_cpu(env); + + if (FIELD_EX64(env->msr, MSR, ME)) { + return; + } + + /* Machine check exception is not enabled. Enter checkstop state. */ + fprintf(stderr, "Machine check while not allowed. " + "Entering checkstop state\n"); + if (qemu_log_separate()) { + qemu_log("Machine check while not allowed. " + "Entering checkstop state\n"); + } + cs->halted =3D 1; + cpu_interrupt_exittb(cs); +} + static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) { CPUState *cs =3D CPU(cpu); @@ -445,21 +464,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) srr1 =3D SPR_40x_SRR3; break; case POWERPC_EXCP_MCHECK: /* Machine check exception = */ - if (!FIELD_EX64(env->msr, MSR, ME)) { - /* - * Machine check exception is not enabled. Enter - * checkstop state. - */ - fprintf(stderr, "Machine check while not allowed. " - "Entering checkstop state\n"); - if (qemu_log_separate()) { - qemu_log("Machine check while not allowed. " - "Entering checkstop state\n"); - } - cs->halted =3D 1; - cpu_interrupt_exittb(cs); - } - + powerpc_mcheck_checkstop(env); /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); =20 @@ -576,21 +581,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_CRITICAL: /* Critical input = */ break; case POWERPC_EXCP_MCHECK: /* Machine check exception = */ - if (!FIELD_EX64(env->msr, MSR, ME)) { - /* - * Machine check exception is not enabled. Enter - * checkstop state. - */ - fprintf(stderr, "Machine check while not allowed. " - "Entering checkstop state\n"); - if (qemu_log_separate()) { - qemu_log("Machine check while not allowed. " - "Entering checkstop state\n"); - } - cs->halted =3D 1; - cpu_interrupt_exittb(cs); - } - + powerpc_mcheck_checkstop(env); /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); =20 @@ -749,21 +740,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) =20 switch (excp) { case POWERPC_EXCP_MCHECK: /* Machine check exception = */ - if (!FIELD_EX64(env->msr, MSR, ME)) { - /* - * Machine check exception is not enabled. Enter - * checkstop state. - */ - fprintf(stderr, "Machine check while not allowed. " - "Entering checkstop state\n"); - if (qemu_log_separate()) { - qemu_log("Machine check while not allowed. " - "Entering checkstop state\n"); - } - cs->halted =3D 1; - cpu_interrupt_exittb(cs); - } - + powerpc_mcheck_checkstop(env); /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); =20 @@ -934,21 +911,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int exc= p) =20 switch (excp) { case POWERPC_EXCP_MCHECK: /* Machine check exception = */ - if (!FIELD_EX64(env->msr, MSR, ME)) { - /* - * Machine check exception is not enabled. Enter - * checkstop state. - */ - fprintf(stderr, "Machine check while not allowed. " - "Entering checkstop state\n"); - if (qemu_log_separate()) { - qemu_log("Machine check while not allowed. " - "Entering checkstop state\n"); - } - cs->halted =3D 1; - cpu_interrupt_exittb(cs); - } - + powerpc_mcheck_checkstop(env); /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); =20 @@ -1129,21 +1092,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int = excp) srr1 =3D SPR_BOOKE_CSRR1; break; case POWERPC_EXCP_MCHECK: /* Machine check exception = */ - if (!FIELD_EX64(env->msr, MSR, ME)) { - /* - * Machine check exception is not enabled. Enter - * checkstop state. - */ - fprintf(stderr, "Machine check while not allowed. " - "Entering checkstop state\n"); - if (qemu_log_separate()) { - qemu_log("Machine check while not allowed. " - "Entering checkstop state\n"); - } - cs->halted =3D 1; - cpu_interrupt_exittb(cs); - } - + powerpc_mcheck_checkstop(env); /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); =20 @@ -1376,20 +1325,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int = excp) =20 switch (excp) { case POWERPC_EXCP_MCHECK: /* Machine check exception = */ - if (!FIELD_EX64(env->msr, MSR, ME)) { - /* - * Machine check exception is not enabled. Enter - * checkstop state. - */ - fprintf(stderr, "Machine check while not allowed. " - "Entering checkstop state\n"); - if (qemu_log_separate()) { - qemu_log("Machine check while not allowed. " - "Entering checkstop state\n"); - } - cs->halted =3D 1; - cpu_interrupt_exittb(cs); - } + powerpc_mcheck_checkstop(env); if (env->msr_mask & MSR_HVB) { /* * ISA specifies HV, but can be delivered to guest with HV --=20 2.30.9 From nobody Mon Feb 9 18:01:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686778511293438.2734062856093; Wed, 14 Jun 2023 14:35:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9Y8B-0004Wl-OQ; Wed, 14 Jun 2023 17:34:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y8A-0004Vy-A3; Wed, 14 Jun 2023 17:34:18 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y87-0003n9-Kx; Wed, 14 Jun 2023 17:34:18 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 3959E748A59; Wed, 14 Jun 2023 23:34:09 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 046E0748A4D; Wed, 14 Jun 2023 23:34:09 +0200 (CEST) Message-Id: <455daa044e616caddb87dec33074f29196a1b560.1686776990.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 04/10] target/ppc: Use env_cpu for cpu_abort in excp_helper MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Greg Kurz , Daniel Henrique Barboza , Nicholas Piggin Date: Wed, 14 Jun 2023 23:34:09 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686778513695100003 Content-Type: text/plain; charset="utf-8" Use the env_cpu function to get the CPUState for cpu_abort. These are only needed in case of fatal errors so this allows to avoid casting and storing CPUState in a local variable wnen not needed. Signed-off-by: BALATON Zoltan --- target/ppc/excp_helper.c | 118 +++++++++++++++++++++------------------ 1 file changed, 63 insertions(+), 55 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 79f5ca1034..122e2a6e41 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -424,7 +424,6 @@ static void powerpc_mcheck_checkstop(CPUPPCState *env) =20 static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) { - CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; int srr0, srr1; @@ -452,8 +451,8 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) =20 vector =3D env->excp_vectors[excp]; if (vector =3D=3D (target_ulong)-1ULL) { - cpu_abort(cs, "Raised an exception without defined vector %d\n", - excp); + cpu_abort(env_cpu(env), + "Raised an exception without defined vector %d\n", excp); } =20 vector |=3D env->excp_prefix; @@ -502,7 +501,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) env->spr[SPR_40x_ESR] =3D ESR_PTR; break; default: - cpu_abort(cs, "Invalid program exception %d. Aborting\n", + cpu_abort(env_cpu(env), "Invalid program exception %d. Abortin= g\n", env->error_code); break; } @@ -529,11 +528,12 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int exc= p) trace_ppc_excp_print("PIT"); break; case POWERPC_EXCP_DEBUG: /* Debug interrupt = */ - cpu_abort(cs, "%s exception not implemented\n", + cpu_abort(env_cpu(env), "%s exception not implemented\n", powerpc_excp_name(excp)); break; default: - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); + cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n", + excp); break; } =20 @@ -548,7 +548,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) =20 static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) { - CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; =20 @@ -571,8 +570,8 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) =20 vector =3D env->excp_vectors[excp]; if (vector =3D=3D (target_ulong)-1ULL) { - cpu_abort(cs, "Raised an exception without defined vector %d\n", - excp); + cpu_abort(env_cpu(env), + "Raised an exception without defined vector %d\n", excp); } =20 vector |=3D env->excp_prefix; @@ -632,7 +631,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) break; default: /* Should never occur */ - cpu_abort(cs, "Invalid program exception %d. Aborting\n", + cpu_abort(env_cpu(env), "Invalid program exception %d. Abortin= g\n", env->error_code); break; } @@ -654,8 +653,9 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) break; case POWERPC_EXCP_RESET: /* System reset exception = */ if (FIELD_EX64(env->msr, MSR, POW)) { - cpu_abort(cs, "Trying to deliver power-saving system reset " - "exception %d with no HV support\n", excp); + cpu_abort(env_cpu(env), + "Trying to deliver power-saving system reset excepti= on " + "%d with no HV support\n", excp); } break; case POWERPC_EXCP_TRACE: /* Trace exception = */ @@ -682,11 +682,12 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int exc= p) case POWERPC_EXCP_SMI: /* System management interrupt = */ case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint = */ case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint = */ - cpu_abort(cs, "%s exception not implemented\n", + cpu_abort(env_cpu(env), "%s exception not implemented\n", powerpc_excp_name(excp)); break; default: - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); + cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n", + excp); break; } =20 @@ -709,7 +710,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) =20 static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) { - CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; =20 @@ -732,8 +732,8 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) =20 vector =3D env->excp_vectors[excp]; if (vector =3D=3D (target_ulong)-1ULL) { - cpu_abort(cs, "Raised an exception without defined vector %d\n", - excp); + cpu_abort(env_cpu(env), + "Raised an exception without defined vector %d\n", excp); } =20 vector |=3D env->excp_prefix; @@ -791,7 +791,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) break; default: /* Should never occur */ - cpu_abort(cs, "Invalid program exception %d. Aborting\n", + cpu_abort(env_cpu(env), "Invalid program exception %d. Abortin= g\n", env->error_code); break; } @@ -832,8 +832,9 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) break; case POWERPC_EXCP_RESET: /* System reset exception = */ if (FIELD_EX64(env->msr, MSR, POW)) { - cpu_abort(cs, "Trying to deliver power-saving system reset " - "exception %d with no HV support\n", excp); + cpu_abort(env_cpu(env), + "Trying to deliver power-saving system reset excepti= on " + "%d with no HV support\n", excp); } break; case POWERPC_EXCP_TRACE: /* Trace exception = */ @@ -853,11 +854,12 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int exc= p) case POWERPC_EXCP_SMI: /* System management interrupt = */ case POWERPC_EXCP_THERM: /* Thermal interrupt = */ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt= */ - cpu_abort(cs, "%s exception not implemented\n", + cpu_abort(env_cpu(env), "%s exception not implemented\n", powerpc_excp_name(excp)); break; default: - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); + cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n", + excp); break; } =20 @@ -880,7 +882,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) =20 static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) { - CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; =20 @@ -903,8 +904,8 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) =20 vector =3D env->excp_vectors[excp]; if (vector =3D=3D (target_ulong)-1ULL) { - cpu_abort(cs, "Raised an exception without defined vector %d\n", - excp); + cpu_abort(env_cpu(env), + "Raised an exception without defined vector %d\n", excp); } =20 vector |=3D env->excp_prefix; @@ -962,7 +963,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) break; default: /* Should never occur */ - cpu_abort(cs, "Invalid program exception %d. Aborting\n", + cpu_abort(env_cpu(env), "Invalid program exception %d. Abortin= g\n", env->error_code); break; } @@ -1003,7 +1004,8 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) break; case POWERPC_EXCP_RESET: /* System reset exception = */ if (FIELD_EX64(env->msr, MSR, POW)) { - cpu_abort(cs, "Trying to deliver power-saving system reset " + cpu_abort(env_cpu(env), + "Trying to deliver power-saving system reset " "exception %d with no HV support\n", excp); } break; @@ -1016,11 +1018,12 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int = excp) case POWERPC_EXCP_THERM: /* Thermal interrupt = */ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt= */ case POWERPC_EXCP_VPUA: /* Vector assist exception = */ - cpu_abort(cs, "%s exception not implemented\n", + cpu_abort(env_cpu(env), "%s exception not implemented\n", powerpc_excp_name(excp)); break; default: - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); + cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n", + excp); break; } =20 @@ -1043,7 +1046,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) =20 static void powerpc_excp_booke(PowerPCCPU *cpu, int excp) { - CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; int srr0, srr1; @@ -1080,8 +1082,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int e= xcp) =20 vector =3D env->excp_vectors[excp]; if (vector =3D=3D (target_ulong)-1ULL) { - cpu_abort(cs, "Raised an exception without defined vector %d\n", - excp); + cpu_abort(env_cpu(env), + "Raised an exception without defined vector %d\n", excp); } =20 vector |=3D env->excp_prefix; @@ -1112,6 +1114,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int e= xcp) break; case POWERPC_EXCP_EXTERNAL: /* External input = */ if (env->mpic_proxy) { + CPUState *cs =3D env_cpu(env); /* IACK the IRQ on delivery */ env->spr[SPR_BOOKE_EPR] =3D ldl_phys(cs->as, env->mpic_iack); } @@ -1150,7 +1153,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int e= xcp) break; default: /* Should never occur */ - cpu_abort(cs, "Invalid program exception %d. Aborting\n", + cpu_abort(env_cpu(env), "Invalid program exception %d. Abortin= g\n", env->error_code); break; } @@ -1191,7 +1194,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int e= xcp) =20 /* DBSR already modified by caller */ } else { - cpu_abort(cs, "Debug exception triggered on unsupported model\= n"); + cpu_abort(env_cpu(env), + "Debug exception triggered on unsupported model\n"); } break; case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/V= PU */ @@ -1205,17 +1209,19 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int= excp) break; case POWERPC_EXCP_RESET: /* System reset exception = */ if (FIELD_EX64(env->msr, MSR, POW)) { - cpu_abort(cs, "Trying to deliver power-saving system reset " + cpu_abort(env_cpu(env), + "Trying to deliver power-saving system reset " "exception %d with no HV support\n", excp); } break; case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt= */ case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrup= t */ - cpu_abort(cs, "%s exception not implemented\n", + cpu_abort(env_cpu(env), "%s exception not implemented\n", powerpc_excp_name(excp)); break; default: - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); + cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n", + excp); break; } =20 @@ -1278,7 +1284,6 @@ static bool books_vhyp_handles_hv_excp(PowerPCCPU *cp= u) =20 static void powerpc_excp_books(PowerPCCPU *cpu, int excp) { - CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; int srr0, srr1, lev =3D -1; @@ -1317,8 +1322,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) =20 vector =3D env->excp_vectors[excp]; if (vector =3D=3D (target_ulong)-1ULL) { - cpu_abort(cs, "Raised an exception without defined vector %d\n", - excp); + cpu_abort(env_cpu(env), + "Raised an exception without defined vector %d\n", excp); } =20 vector |=3D env->excp_prefix; @@ -1408,7 +1413,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) break; default: /* Should never occur */ - cpu_abort(cs, "Invalid program exception %d. Aborting\n", + cpu_abort(env_cpu(env), "Invalid program exception %d. Abortin= g\n", env->error_code); break; } @@ -1469,7 +1474,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) new_msr |=3D (target_ulong)MSR_HVB; } else { if (FIELD_EX64(env->msr, MSR, POW)) { - cpu_abort(cs, "Trying to deliver power-saving system reset= " + cpu_abort(env_cpu(env), + "Trying to deliver power-saving system reset " "exception %d with no HV support\n", excp); } } @@ -1524,11 +1530,12 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int= excp) case POWERPC_EXCP_VPUA: /* Vector assist exception = */ case POWERPC_EXCP_MAINT: /* Maintenance exception = */ case POWERPC_EXCP_HV_MAINT: /* Hypervisor Maintenance exception = */ - cpu_abort(cs, "%s exception not implemented\n", + cpu_abort(env_cpu(env), "%s exception not implemented\n", powerpc_excp_name(excp)); break; default: - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); + cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n", + excp); break; } =20 @@ -1561,8 +1568,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) } else { /* Sanity check */ if (!(env->msr_mask & MSR_HVB) && srr0 =3D=3D SPR_HSRR0) { - cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with " - "no HV support\n", excp); + cpu_abort(env_cpu(env), "Trying to deliver HV exception (HSRR)= %d " + "with no HV support\n", excp); } =20 /* This can update new_msr and vector if AIL applies */ @@ -1580,11 +1587,11 @@ static inline void powerpc_excp_books(PowerPCCPU *c= pu, int excp) =20 static void powerpc_excp(PowerPCCPU *cpu, int excp) { - CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; =20 if (excp <=3D POWERPC_EXCP_NONE || excp >=3D POWERPC_EXCP_NB) { - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); + cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n", + excp); } =20 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx @@ -2118,7 +2125,6 @@ void ppc_maybe_interrupt(CPUPPCState *env) static void p7_deliver_interrupt(CPUPPCState *env, int interrupt) { PowerPCCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D env_cpu(env); =20 switch (interrupt) { case PPC_INTERRUPT_MCK: /* Machine check exception */ @@ -2162,14 +2168,14 @@ static void p7_deliver_interrupt(CPUPPCState *env, = int interrupt) assert(!env->resume_as_sreset); break; default: - cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrup= t); + cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n", + interrupt); } } =20 static void p8_deliver_interrupt(CPUPPCState *env, int interrupt) { PowerPCCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D env_cpu(env); =20 switch (interrupt) { case PPC_INTERRUPT_MCK: /* Machine check exception */ @@ -2233,7 +2239,8 @@ static void p8_deliver_interrupt(CPUPPCState *env, in= t interrupt) assert(!env->resume_as_sreset); break; default: - cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrup= t); + cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n", + interrupt); } } =20 @@ -2312,7 +2319,8 @@ static void p9_deliver_interrupt(CPUPPCState *env, in= t interrupt) assert(!env->resume_as_sreset); break; default: - cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrup= t); + cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n", + interrupt); } } #endif @@ -2320,7 +2328,6 @@ static void p9_deliver_interrupt(CPUPPCState *env, in= t interrupt) static void ppc_deliver_interrupt_generic(CPUPPCState *env, int interrupt) { PowerPCCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D env_cpu(env); =20 switch (interrupt) { case PPC_INTERRUPT_RESET: /* External reset */ @@ -2417,7 +2424,8 @@ static void ppc_deliver_interrupt_generic(CPUPPCState= *env, int interrupt) assert(!env->resume_as_sreset); break; default: - cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrup= t); + cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n", + interrupt); } } =20 --=20 2.30.9 From nobody Mon Feb 9 18:01:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686778496636585.4038785943452; Wed, 14 Jun 2023 14:34:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9Y8D-0004c0-3H; Wed, 14 Jun 2023 17:34:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y8A-0004W0-EA; Wed, 14 Jun 2023 17:34:18 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y88-0003nW-J2; Wed, 14 Jun 2023 17:34:18 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 34EF0748A5B; Wed, 14 Jun 2023 23:34:10 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 0E742748A4D; Wed, 14 Jun 2023 23:34:10 +0200 (CEST) Message-Id: <78ecd505a8b523e236cbeab335aa0621f7834cc5.1686776990.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 05/10] target/ppc: Change parameter of cpu_interrupt_exittb() to an env pointer MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Greg Kurz , Daniel Henrique Barboza , Nicholas Piggin Date: Wed, 14 Jun 2023 23:34:10 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686778498236100001 Content-Type: text/plain; charset="utf-8" Changing the parameter of cpu_interrupt_exittb() from CPUState to env allows removing some more local CPUState variables in callers. Signed-off-by: BALATON Zoltan --- target/ppc/excp_helper.c | 9 +++------ target/ppc/helper_regs.c | 15 ++++++--------- target/ppc/helper_regs.h | 2 +- 3 files changed, 10 insertions(+), 16 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 122e2a6e41..49ed3e1825 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -419,7 +419,7 @@ static void powerpc_mcheck_checkstop(CPUPPCState *env) "Entering checkstop state\n"); } cs->halted =3D 1; - cpu_interrupt_exittb(cs); + cpu_interrupt_exittb(env); } =20 static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) @@ -2551,8 +2551,7 @@ void helper_store_msr(CPUPPCState *env, target_ulong = val) uint32_t excp =3D hreg_store_msr(env, val, 0); =20 if (excp !=3D 0) { - CPUState *cs =3D env_cpu(env); - cpu_interrupt_exittb(cs); + cpu_interrupt_exittb(env); raise_exception(env, excp); } } @@ -2589,8 +2588,6 @@ void helper_pminsn(CPUPPCState *env, uint32_t insn) =20 static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr) { - CPUState *cs =3D env_cpu(env); - /* MSR:POW cannot be set by any form of rfi */ msr &=3D ~(1ULL << MSR_POW); =20 @@ -2614,7 +2611,7 @@ static void do_rfi(CPUPPCState *env, target_ulong nip= , target_ulong msr) * No need to raise an exception here, as rfi is always the last * insn of a TB */ - cpu_interrupt_exittb(cs); + cpu_interrupt_exittb(env); /* Reset the reservation */ env->reserve_addr =3D -1; =20 diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index bc7e9d7eda..ffedd38985 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -237,7 +237,7 @@ void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulon= g *pc, } #endif =20 -void cpu_interrupt_exittb(CPUState *cs) +void cpu_interrupt_exittb(CPUPPCState *env) { /* * We don't need to worry about translation blocks @@ -245,18 +245,14 @@ void cpu_interrupt_exittb(CPUState *cs) */ if (tcg_enabled()) { QEMU_IOTHREAD_LOCK_GUARD(); - cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_EXITTB); } } =20 int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv) { - int excp; -#if !defined(CONFIG_USER_ONLY) - CPUState *cs =3D env_cpu(env); -#endif + int excp =3D 0; =20 - excp =3D 0; value &=3D env->msr_mask; #if !defined(CONFIG_USER_ONLY) /* Neither mtmsr nor guest state can alter HV */ @@ -265,12 +261,12 @@ int hreg_store_msr(CPUPPCState *env, target_ulong val= ue, int alter_hv) value |=3D env->msr & MSR_HVB; } if ((value ^ env->msr) & (R_MSR_IR_MASK | R_MSR_DR_MASK)) { - cpu_interrupt_exittb(cs); + cpu_interrupt_exittb(env); } if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE || env->mmu_model =3D=3D POWERPC_MMU_BOOKE206) && ((value ^ env->msr) & R_MSR_GS_MASK)) { - cpu_interrupt_exittb(cs); + cpu_interrupt_exittb(env); } if (unlikely((env->flags & POWERPC_FLAG_TGPR) && ((value ^ env->msr) & (1 << MSR_TGPR)))) { @@ -301,6 +297,7 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value= , int alter_hv) =20 if (unlikely(FIELD_EX64(env->msr, MSR, POW))) { if (!env->pending_interrupts && (*env->check_pow)(env)) { + CPUState *cs =3D env_cpu(env); cs->halted =3D 1; excp =3D EXCP_HALTED; } diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index 8196c1346d..3e1606f293 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -23,7 +23,7 @@ void hreg_swap_gpr_tgpr(CPUPPCState *env); void hreg_compute_hflags(CPUPPCState *env); void hreg_update_pmu_hflags(CPUPPCState *env); -void cpu_interrupt_exittb(CPUState *cs); +void cpu_interrupt_exittb(CPUPPCState *env); int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv); =20 #ifdef CONFIG_USER_ONLY --=20 2.30.9 From nobody Mon Feb 9 18:01:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686778536046688.8346132142257; Wed, 14 Jun 2023 14:35:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9Y8E-0004hZ-RN; Wed, 14 Jun 2023 17:34:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y8C-0004ah-Je; Wed, 14 Jun 2023 17:34:20 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y89-0003nn-Kl; Wed, 14 Jun 2023 17:34:20 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 50C74748A5C; Wed, 14 Jun 2023 23:34:11 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 17BD4748A4D; Wed, 14 Jun 2023 23:34:11 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 06/10] target/ppc: Readability improvements in exception handlers MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Greg Kurz , Daniel Henrique Barboza , Nicholas Piggin Date: Wed, 14 Jun 2023 23:34:11 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686778537623100003 Content-Type: text/plain; charset="utf-8" Improve readability by shortening some long comments, removing comments that state the obvious and dropping some empty lines so they don't distract when reading the code. Signed-off-by: BALATON Zoltan Acked-by: Nicholas Piggin --- target/ppc/cpu.h | 1 + target/ppc/excp_helper.c | 180 +++++++-------------------------------- 2 files changed, 33 insertions(+), 148 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 0ee2adc105..d7acd65176 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2739,6 +2739,7 @@ static inline bool ppc_has_spr(PowerPCCPU *cpu, int s= pr) } =20 #if !defined(CONFIG_USER_ONLY) +/* Sort out endianness of interrupt. Depends on the CPU, HV mode, etc. */ static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv) { PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 49ed3e1825..74113958b5 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -382,9 +382,8 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu, tar= get_ulong vector, * We don't use hreg_store_msr here as already have treated any * special case that could occur. Just store MSR and update hflags * - * Note: We *MUST* not use hreg_store_msr() as-is anyway because it - * will prevent setting of the HV bit which some exceptions might need - * to do. + * Note: We *MUST* not use hreg_store_msr() as-is anyway because it wi= ll + * prevent setting of the HV bit which some exceptions might need to d= o. */ env->nip =3D vector; env->msr =3D msr; @@ -426,25 +425,15 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int exc= p) { CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; - int srr0, srr1; + int srr0 =3D SPR_SRR0, srr1 =3D SPR_SRR1; =20 /* new srr1 value excluding must-be-zero bits */ msr =3D env->msr & ~0x783f0000ULL; =20 - /* - * new interrupt handler msr preserves existing ME unless - * explicitly overriden. - */ + /* new interrupt handler msr preserves ME unless explicitly overriden = */ new_msr =3D env->msr & (((target_ulong)1 << MSR_ME)); =20 - /* target registers */ - srr0 =3D SPR_SRR0; - srr1 =3D SPR_SRR1; - - /* - * Hypervisor emulation assistance interrupt only exists on server - * arch 2.05 server or later. - */ + /* HV emu assistance interrupt only exists on server arch 2.05 or late= r */ if (excp =3D=3D POWERPC_EXCP_HV_EMU) { excp =3D POWERPC_EXCP_PROGRAM; } @@ -454,7 +443,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) cpu_abort(env_cpu(env), "Raised an exception without defined vector %d\n", excp); } - vector |=3D env->excp_prefix; =20 switch (excp) { @@ -466,7 +454,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) powerpc_mcheck_checkstop(env); /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); - srr0 =3D SPR_40x_SRR2; srr1 =3D SPR_40x_SRR3; break; @@ -537,12 +524,8 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) break; } =20 - /* Save PC */ env->spr[srr0] =3D env->nip; - - /* Save MSR */ env->spr[srr1] =3D msr; - powerpc_set_excp_state(cpu, vector, new_msr); } =20 @@ -554,16 +537,10 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int exc= p) /* new srr1 value excluding must-be-zero bits */ msr =3D env->msr & ~0x783f0000ULL; =20 - /* - * new interrupt handler msr preserves existing ME unless - * explicitly overriden - */ + /* new interrupt handler msr preserves ME unless explicitly overriden = */ new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); =20 - /* - * Hypervisor emulation assistance interrupt only exists on server - * arch 2.05 server or later. - */ + /* HV emu assistance interrupt only exists on server arch 2.05 or late= r */ if (excp =3D=3D POWERPC_EXCP_HV_EMU) { excp =3D POWERPC_EXCP_PROGRAM; } @@ -573,7 +550,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) cpu_abort(env_cpu(env), "Raised an exception without defined vector %d\n", excp); } - vector |=3D env->excp_prefix; =20 switch (excp) { @@ -583,7 +559,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) powerpc_mcheck_checkstop(env); /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); - break; case POWERPC_EXCP_DSI: /* Data storage exception = */ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); @@ -611,11 +586,9 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) powerpc_reset_excp_state(cpu); return; } - /* - * FP exceptions always have NIP pointing to the faulting - * instruction, so always use store_next and claim we are - * precise in the MSR. + * NIP always points to the faulting instruction for FP except= ions, + * so always use store_next and claim we are precise in the MS= R. */ msr |=3D 0x00100000; break; @@ -691,20 +664,11 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int exc= p) break; } =20 - /* - * Sort out endianness of interrupt, this differs depending on the - * CPU, the HV mode, etc... - */ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { new_msr |=3D (target_ulong)1 << MSR_LE; } - - /* Save PC */ env->spr[SPR_SRR0] =3D env->nip; - - /* Save MSR */ env->spr[SPR_SRR1] =3D msr; - powerpc_set_excp_state(cpu, vector, new_msr); } =20 @@ -716,16 +680,10 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int exc= p) /* new srr1 value excluding must-be-zero bits */ msr =3D env->msr & ~0x783f0000ULL; =20 - /* - * new interrupt handler msr preserves existing ME unless - * explicitly overriden - */ + /* new interrupt handler msr preserves ME unless explicitly overriden = */ new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); =20 - /* - * Hypervisor emulation assistance interrupt only exists on server - * arch 2.05 server or later. - */ + /* HV emu assistance interrupt only exists on server arch 2.05 or late= r */ if (excp =3D=3D POWERPC_EXCP_HV_EMU) { excp =3D POWERPC_EXCP_PROGRAM; } @@ -735,7 +693,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) cpu_abort(env_cpu(env), "Raised an exception without defined vector %d\n", excp); } - vector |=3D env->excp_prefix; =20 switch (excp) { @@ -743,7 +700,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) powerpc_mcheck_checkstop(env); /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); - break; case POWERPC_EXCP_DSI: /* Data storage exception = */ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); @@ -771,11 +727,9 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) powerpc_reset_excp_state(cpu); return; } - /* - * FP exceptions always have NIP pointing to the faulting - * instruction, so always use store_next and claim we are - * precise in the MSR. + * NIP always points to the faulting instruction for FP except= ions, + * so always use store_next and claim we are precise in the MS= R. */ msr |=3D 0x00100000; break; @@ -843,12 +797,10 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int exc= p) case POWERPC_EXCP_DLTLB: /* Data load TLB miss = */ case POWERPC_EXCP_DSTLB: /* Data store TLB miss = */ ppc_excp_debug_sw_tlb(env, excp); - msr |=3D env->crf[0] << 28; msr |=3D env->error_code; /* key, D/I, S/L bits */ /* Set way using a LRU mechanism */ msr |=3D ((env->last_way + 1) & (env->nb_ways - 1)) << 17; - break; case POWERPC_EXCP_IABR: /* Instruction address breakpoint = */ case POWERPC_EXCP_SMI: /* System management interrupt = */ @@ -863,20 +815,11 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int exc= p) break; } =20 - /* - * Sort out endianness of interrupt, this differs depending on the - * CPU, the HV mode, etc... - */ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { new_msr |=3D (target_ulong)1 << MSR_LE; } - - /* Save PC */ env->spr[SPR_SRR0] =3D env->nip; - - /* Save MSR */ env->spr[SPR_SRR1] =3D msr; - powerpc_set_excp_state(cpu, vector, new_msr); } =20 @@ -888,16 +831,10 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) /* new srr1 value excluding must-be-zero bits */ msr =3D env->msr & ~0x783f0000ULL; =20 - /* - * new interrupt handler msr preserves existing ME unless - * explicitly overriden - */ + /* new interrupt handler msr preserves ME unless explicitly overriden = */ new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); =20 - /* - * Hypervisor emulation assistance interrupt only exists on server - * arch 2.05 server or later. - */ + /* HV emu assistance interrupt only exists on server arch 2.05 or late= r */ if (excp =3D=3D POWERPC_EXCP_HV_EMU) { excp =3D POWERPC_EXCP_PROGRAM; } @@ -907,7 +844,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) cpu_abort(env_cpu(env), "Raised an exception without defined vector %d\n", excp); } - vector |=3D env->excp_prefix; =20 switch (excp) { @@ -915,7 +851,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) powerpc_mcheck_checkstop(env); /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); - break; case POWERPC_EXCP_DSI: /* Data storage exception = */ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); @@ -943,11 +878,9 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int exc= p) powerpc_reset_excp_state(cpu); return; } - /* - * FP exceptions always have NIP pointing to the faulting - * instruction, so always use store_next and claim we are - * precise in the MSR. + * NIP always points to the faulting instruction for FP except= ions, + * so always use store_next and claim we are precise in the MS= R. */ msr |=3D 0x00100000; break; @@ -1027,20 +960,11 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int e= xcp) break; } =20 - /* - * Sort out endianness of interrupt, this differs depending on the - * CPU, the HV mode, etc... - */ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { new_msr |=3D (target_ulong)1 << MSR_LE; } - - /* Save PC */ env->spr[SPR_SRR0] =3D env->nip; - - /* Save MSR */ env->spr[SPR_SRR1] =3D msr; - powerpc_set_excp_state(cpu, vector, new_msr); } =20 @@ -1048,24 +972,18 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int = excp) { CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; - int srr0, srr1; - - msr =3D env->msr; + int srr0 =3D SPR_SRR0, srr1 =3D SPR_SRR1; =20 /* - * new interrupt handler msr preserves existing ME unless - * explicitly overriden + * Book E does not play games with certain bits of xSRR1 being MSR save + * bits and others being error status. xSRR1 is the old MSR, period. */ - new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); + msr =3D env->msr; =20 - /* target registers */ - srr0 =3D SPR_SRR0; - srr1 =3D SPR_SRR1; + /* new interrupt handler msr preserves ME unless explicitly overriden = */ + new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); =20 - /* - * Hypervisor emulation assistance interrupt only exists on server - * arch 2.05 server or later. - */ + /* HV emu assistance interrupt only exists on server arch 2.05 or late= r */ if (excp =3D=3D POWERPC_EXCP_HV_EMU) { excp =3D POWERPC_EXCP_PROGRAM; } @@ -1085,7 +1003,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int e= xcp) cpu_abort(env_cpu(env), "Raised an exception without defined vector %d\n", excp); } - vector |=3D env->excp_prefix; =20 switch (excp) { @@ -1129,11 +1046,9 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int = excp) powerpc_reset_excp_state(cpu); return; } - /* - * FP exceptions always have NIP pointing to the faulting - * instruction, so always use store_next and claim we are - * precise in the MSR. + * NIP always points to the faulting instruction for FP except= ions, + * so always use store_next and claim we are precise in the MS= R. */ msr |=3D 0x00100000; env->spr[SPR_BOOKE_ESR] =3D ESR_FP; @@ -1234,12 +1149,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int = excp) } #endif =20 - /* Save PC */ env->spr[srr0] =3D env->nip; - - /* Save MSR */ env->spr[srr1] =3D msr; - powerpc_set_excp_state(cpu, vector, new_msr); } =20 @@ -1286,21 +1197,17 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int= excp) { CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; - int srr0, srr1, lev =3D -1; + int srr0 =3D SPR_SRR0, srr1 =3D SPR_SRR1, lev =3D -1; =20 /* new srr1 value excluding must-be-zero bits */ msr =3D env->msr & ~0x783f0000ULL; =20 /* - * new interrupt handler msr preserves existing HV and ME unless - * explicitly overriden + * new interrupt handler msr preserves HV and ME unless explicitly + * overriden */ new_msr =3D env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); =20 - /* target registers */ - srr0 =3D SPR_SRR0; - srr1 =3D SPR_SRR1; - /* * check for special resume at 0x100 from doze/nap/sleep/winkle on * P7/P8/P9 @@ -1325,7 +1232,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) cpu_abort(env_cpu(env), "Raised an exception without defined vector %d\n", excp); } - vector |=3D env->excp_prefix; =20 switch (excp) { @@ -1338,10 +1244,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int = excp) */ new_msr |=3D (target_ulong)MSR_HVB; } - /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); - break; case POWERPC_EXCP_DSI: /* Data storage exception = */ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); @@ -1354,23 +1258,17 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int= excp) { bool lpes0; =20 - /* - * LPES0 is only taken into consideration if we support HV - * mode for this CPU. - */ + /* LPES0 is only taken into consideration if we support HV mode */ if (!env->has_hv_mode) { break; } - lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); - if (!lpes0) { new_msr |=3D (target_ulong)MSR_HVB; new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); srr0 =3D SPR_HSRR0; srr1 =3D SPR_HSRR1; } - break; } case POWERPC_EXCP_ALIGN: /* Alignment exception = */ @@ -1393,11 +1291,9 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int = excp) powerpc_reset_excp_state(cpu); return; } - /* - * FP exceptions always have NIP pointing to the faulting - * instruction, so always use store_next and claim we are - * precise in the MSR. + * NIP always points to the faulting instruction for FP except= ions, + * so always use store_next and claim we are precise in the MS= R. */ msr |=3D 0x00100000; break; @@ -1539,21 +1435,13 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int= excp) break; } =20 - /* - * Sort out endianness of interrupt, this differs depending on the - * CPU, the HV mode, etc... - */ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { new_msr |=3D (target_ulong)1 << MSR_LE; } - new_msr |=3D (target_ulong)1 << MSR_SF; =20 if (excp !=3D POWERPC_EXCP_SYSCALL_VECTORED) { - /* Save PC */ env->spr[srr0] =3D env->nip; - - /* Save MSR */ env->spr[srr1] =3D msr; } =20 @@ -1562,19 +1450,15 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int= excp) PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); /* Deliver interrupt to L1 by returning from the H_ENTER_NESTED ca= ll */ vhc->deliver_hv_excp(cpu, excp); - powerpc_reset_excp_state(cpu); - } else { /* Sanity check */ if (!(env->msr_mask & MSR_HVB) && srr0 =3D=3D SPR_HSRR0) { cpu_abort(env_cpu(env), "Trying to deliver HV exception (HSRR)= %d " "with no HV support\n", excp); } - /* This can update new_msr and vector if AIL applies */ ppc_excp_apply_ail(cpu, excp, msr, &new_msr, &vector); - powerpc_set_excp_state(cpu, vector, new_msr); } } --=20 2.30.9 From nobody Mon Feb 9 18:01:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686778501069968.8011708800914; Wed, 14 Jun 2023 14:35:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9Y8F-0004i5-I6; Wed, 14 Jun 2023 17:34:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y8C-0004a1-C4; Wed, 14 Jun 2023 17:34:20 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y8A-0003o0-Mz; Wed, 14 Jun 2023 17:34:19 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 47E73748A5D; Wed, 14 Jun 2023 23:34:12 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 22238748A4D; Wed, 14 Jun 2023 23:34:12 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 07/10] target/ppd: Remove unused define MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Greg Kurz , Daniel Henrique Barboza , Nicholas Piggin Date: Wed, 14 Jun 2023 23:34:12 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686778501930100001 Commit 7a3fe174b12d removed usage of POWERPC_SYSCALL_VECTORED, drop the unused define as well. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Nicholas Piggin --- target/ppc/translate.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b591f2e496..a32a9b8a5f 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4416,7 +4416,6 @@ static void gen_hrfid(DisasContext *ctx) #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER #else #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL -#define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED #endif static void gen_sc(DisasContext *ctx) { --=20 2.30.9 From nobody Mon Feb 9 18:01:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168677855483382.0062888107226; Wed, 14 Jun 2023 14:35:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9Y8Z-0004z4-Cl; Wed, 14 Jun 2023 17:34:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y8D-0004eL-Ls; Wed, 14 Jun 2023 17:34:21 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y8B-0003oN-M0; Wed, 14 Jun 2023 17:34:21 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 4F3D9748A5E; Wed, 14 Jun 2023 23:34:13 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 2A679748A4D; Wed, 14 Jun 2023 23:34:13 +0200 (CEST) Message-Id: <3bfe9472e8d52811a2dbc0290fa2fba7308872ce.1686776990.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 08/10] target/ppc: Fix gen_sc to use correct nip MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Greg Kurz , Daniel Henrique Barboza , Nicholas Piggin Date: Wed, 14 Jun 2023 23:34:13 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686778556951100003 Content-Type: text/plain; charset="utf-8" Most exceptions are raised with nip pointing to the faulting instruction but the sc instruction generating a syscall exception leaves nip pointing to next instruction. Fix gen_sc to not use gen_exception_err() which sets nip back but correctly set nip to pc_next so we don't have to patch this in the exception handlers. This changes the nip logged in dump_syscall and dump_hcall debug functions but now this matches how nip would be on a real CPU. Signed-off-by: BALATON Zoltan --- target/ppc/excp_helper.c | 39 --------------------------------------- target/ppc/translate.c | 8 +++++--- 2 files changed, 5 insertions(+), 42 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 74113958b5..1682b988ba 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -495,12 +495,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) break; case POWERPC_EXCP_SYSCALL: /* System call exception = */ dump_syscall(env); - - /* - * We need to correct the NIP which in this case is supposed - * to point to the next instruction - */ - env->nip +=3D 4; break; case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt = */ trace_ppc_excp_print("FIT"); @@ -611,12 +605,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) break; case POWERPC_EXCP_SYSCALL: /* System call exception = */ dump_syscall(env); - - /* - * We need to correct the NIP which in this case is supposed - * to point to the next instruction - */ - env->nip +=3D 4; break; case POWERPC_EXCP_FPU: /* Floating-point unavailable exception = */ case POWERPC_EXCP_DECR: /* Decrementer exception = */ @@ -759,13 +747,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) } else { dump_syscall(env); } - - /* - * We need to correct the NIP which in this case is supposed - * to point to the next instruction - */ - env->nip +=3D 4; - /* * The Virtual Open Firmware (VOF) relies on the 'sc 1' * instruction to communicate with QEMU. The pegasos2 machine @@ -910,13 +891,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int exc= p) } else { dump_syscall(env); } - - /* - * We need to correct the NIP which in this case is supposed - * to point to the next instruction - */ - env->nip +=3D 4; - /* * The Virtual Open Firmware (VOF) relies on the 'sc 1' * instruction to communicate with QEMU. The pegasos2 machine @@ -1075,12 +1049,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int = excp) break; case POWERPC_EXCP_SYSCALL: /* System call exception = */ dump_syscall(env); - - /* - * We need to correct the NIP which in this case is supposed - * to point to the next instruction - */ - env->nip +=3D 4; break; case POWERPC_EXCP_FPU: /* Floating-point unavailable exception = */ case POWERPC_EXCP_APU: /* Auxiliary processor unavailable = */ @@ -1322,13 +1290,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int = excp) } else { dump_syscall(env); } - - /* - * We need to correct the NIP which in this case is supposed - * to point to the next instruction - */ - env->nip +=3D 4; - /* "PAPR mode" built-in hypercall emulation */ if (lev =3D=3D 1 && books_vhyp_handles_hcall(cpu)) { PPCVirtualHypervisorClass *vhc =3D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a32a9b8a5f..4260d3d66f 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4419,10 +4419,12 @@ static void gen_hrfid(DisasContext *ctx) #endif static void gen_sc(DisasContext *ctx) { - uint32_t lev; + uint32_t lev =3D (ctx->opcode >> 5) & 0x7F; =20 - lev =3D (ctx->opcode >> 5) & 0x7F; - gen_exception_err(ctx, POWERPC_SYSCALL, lev); + gen_update_nip(ctx, ctx->base.pc_next); + gen_helper_raise_exception_err(cpu_env, tcg_constant_i32(POWERPC_SYSCA= LL), + tcg_constant_i32(lev)); + ctx->base.is_jmp =3D DISAS_NORETURN; } =20 #if defined(TARGET_PPC64) --=20 2.30.9 From nobody Mon Feb 9 18:01:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686778506652175.59378275297695; Wed, 14 Jun 2023 14:35:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9Y8e-00054a-KR; Wed, 14 Jun 2023 17:34:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y8E-0004hF-IM; Wed, 14 Jun 2023 17:34:22 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y8C-0003oq-QE; Wed, 14 Jun 2023 17:34:22 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 68AFC748A5F; Wed, 14 Jun 2023 23:34:14 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 3506F748A4D; Wed, 14 Jun 2023 23:34:14 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 09/10] target/ppc: Simplify syscall exception handlers MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Greg Kurz , Daniel Henrique Barboza , Nicholas Piggin Date: Wed, 14 Jun 2023 23:34:14 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686778508832100001 Content-Type: text/plain; charset="utf-8" After previous changes the hypercall handling in 7xx and 74xx exception handlers can be folded into one if statement to simpilfy this code. Signed-off-by: BALATON Zoltan --- target/ppc/excp_helper.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 1682b988ba..662457f342 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -740,26 +740,23 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int exc= p) break; case POWERPC_EXCP_SYSCALL: /* System call exception = */ { - int lev =3D env->error_code; + PowerPCCPU *cpu =3D env_archcpu(env); =20 - if (lev =3D=3D 1 && cpu->vhyp) { - dump_hcall(env); - } else { - dump_syscall(env); - } /* * The Virtual Open Firmware (VOF) relies on the 'sc 1' * instruction to communicate with QEMU. The pegasos2 machine * uses VOF and the 7xx CPUs, so although the 7xx don't have * HV mode, we need to keep hypercall support. */ - if (lev =3D=3D 1 && cpu->vhyp) { + if (unlikely(env->error_code =3D=3D 1 && cpu->vhyp)) { PPCVirtualHypervisorClass *vhc =3D PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); + dump_hcall(env); vhc->hypercall(cpu->vhyp, cpu); return; + } else { + dump_syscall(env); } - break; } case POWERPC_EXCP_FPU: /* Floating-point unavailable exception = */ @@ -884,26 +881,23 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) break; case POWERPC_EXCP_SYSCALL: /* System call exception = */ { - int lev =3D env->error_code; + PowerPCCPU *cpu =3D env_archcpu(env); =20 - if (lev =3D=3D 1 && cpu->vhyp) { - dump_hcall(env); - } else { - dump_syscall(env); - } /* * The Virtual Open Firmware (VOF) relies on the 'sc 1' * instruction to communicate with QEMU. The pegasos2 machine * uses VOF and the 74xx CPUs, so although the 74xx don't have * HV mode, we need to keep hypercall support. */ - if (lev =3D=3D 1 && cpu->vhyp) { + if (unlikely(env->error_code =3D=3D 1 && cpu->vhyp)) { PPCVirtualHypervisorClass *vhc =3D PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); + dump_hcall(env); vhc->hypercall(cpu->vhyp, cpu); return; + } else { + dump_syscall(env); } - break; } case POWERPC_EXCP_FPU: /* Floating-point unavailable exception = */ --=20 2.30.9 From nobody Mon Feb 9 18:01:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686778562042456.15363821676203; Wed, 14 Jun 2023 14:36:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9Y8f-0005CY-TX; Wed, 14 Jun 2023 17:34:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y8d-00053w-JF; Wed, 14 Jun 2023 17:34:47 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9Y8E-0003pH-A4; Wed, 14 Jun 2023 17:34:23 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 5C55C748A5D; Wed, 14 Jun 2023 23:34:15 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 3EAE1748A4D; Wed, 14 Jun 2023 23:34:15 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 10/10] target/ppc: Get CPUState in one step MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Greg Kurz , Daniel Henrique Barboza , Nicholas Piggin Date: Wed, 14 Jun 2023 23:34:15 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686778562771100001 Content-Type: text/plain; charset="utf-8" We can get CPUState from env with env_cpu without going through PowerPCCPU and casting that. Signed-off-by: BALATON Zoltan Acked-by: Nicholas Piggin --- target/ppc/excp_helper.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 662457f342..5edf06210f 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1506,8 +1506,8 @@ static int p7_interrupt_powersave(CPUPPCState *env) =20 static int p7_next_unmasked_interrupt(CPUPPCState *env) { - PowerPCCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + /* Ignore MSR[EE] when coming out of some power management states */ bool msr_ee =3D FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; =20 @@ -1596,8 +1596,8 @@ static int p8_interrupt_powersave(CPUPPCState *env) =20 static int p8_next_unmasked_interrupt(CPUPPCState *env) { - PowerPCCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + /* Ignore MSR[EE] when coming out of some power management states */ bool msr_ee =3D FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; =20 @@ -1717,8 +1717,8 @@ static int p9_interrupt_powersave(CPUPPCState *env) =20 static int p9_next_unmasked_interrupt(CPUPPCState *env) { - PowerPCCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + /* Ignore MSR[EE] when coming out of some power management states */ bool msr_ee =3D FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; =20 @@ -2412,9 +2412,8 @@ void helper_scv(CPUPPCState *env, uint32_t lev) =20 void helper_pminsn(CPUPPCState *env, uint32_t insn) { - CPUState *cs; + CPUState *cs =3D env_cpu(env); =20 - cs =3D env_cpu(env); cs->halted =3D 1; =20 /* Condition for waking up at 0x100 */ --=20 2.30.9