From nobody Sun Apr 28 23:39:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678025245584738.9705597704733; Sun, 5 Mar 2023 06:07:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYp04-0007Du-JP; Sun, 05 Mar 2023 09:06:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYp00-00077G-6g; Sun, 05 Mar 2023 09:06:04 -0500 Received: from zero.eik.bme.hu ([152.66.115.2]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYozw-0000d2-SA; Sun, 05 Mar 2023 09:06:03 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 455A374635C; Sun, 5 Mar 2023 15:05:47 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 14BBB74634B; Sun, 5 Mar 2023 15:05:47 +0100 (CET) Message-Id: <47ff2293c9a49645060556c83373b8c72c958da6.1678023358.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v7 1/6] hw/display/sm501: Add debug property to control pixman usage MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Gerd Hoffmann , Daniel Henrique Barboza , Bernhard Beschow , Peter Maydell , philmd@linaro.org, ReneEngel80@emailn.de Date: Sun, 5 Mar 2023 15:05:47 +0100 (CET) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1678025245860100001 Content-Type: text/plain; charset="utf-8" Add a property to allow disabling pixman and always use the fallbacks for different operations which is useful for testing different drawing methods or debugging pixman related issues. Signed-off-by: BALATON Zoltan Tested-by: Rene Engel --- hw/display/sm501.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 17835159fc..dbabbc4339 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -465,6 +465,7 @@ typedef struct SM501State { uint32_t last_width; uint32_t last_height; bool do_full_update; /* perform a full update next time */ + uint8_t use_pixman; I2CBus *i2c_bus; =20 /* mmio registers */ @@ -827,7 +828,7 @@ static void sm501_2d_operation(SM501State *s) de =3D db + (width + (height - 1) * dst_pitch) * bypp; overlap =3D (db < se && sb < de); } - if (overlap) { + if (overlap && (s->use_pixman & BIT(2))) { /* pixman can't do reverse blit: copy via temporary */ int tmp_stride =3D DIV_ROUND_UP(width * bypp, sizeof(uint3= 2_t)); uint32_t *tmp =3D tmp_buf; @@ -852,13 +853,15 @@ static void sm501_2d_operation(SM501State *s) if (tmp !=3D tmp_buf) { g_free(tmp); } - } else { + } else if (!overlap && (s->use_pixman & BIT(1))) { fallback =3D !pixman_blt((uint32_t *)&s->local_mem[src_bas= e], (uint32_t *)&s->local_mem[dst_base], src_pitch * bypp / sizeof(uint32_t), dst_pitch * bypp / sizeof(uint32_t), 8 * bypp, 8 * bypp, src_x, src_y, dst_x, dst_y, width, height); + } else { + fallback =3D true; } if (fallback) { uint8_t *sp =3D s->local_mem + src_base; @@ -891,7 +894,7 @@ static void sm501_2d_operation(SM501State *s) color =3D cpu_to_le16(color); } =20 - if ((width =3D=3D 1 && height =3D=3D 1) || + if (!(s->use_pixman & BIT(0)) || (width =3D=3D 1 && height =3D=3D = 1) || !pixman_fill((uint32_t *)&s->local_mem[dst_base], dst_pitch * bypp / sizeof(uint32_t), 8 * bypp, dst_x, dst_y, width, height, color)) { @@ -2035,6 +2038,7 @@ static void sm501_realize_sysbus(DeviceState *dev, Er= ror **errp) =20 static Property sm501_sysbus_properties[] =3D { DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0), + DEFINE_PROP_UINT8("x-pixman", SM501SysBusState, state.use_pixman, 7), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -2122,6 +2126,7 @@ static void sm501_realize_pci(PCIDevice *dev, Error *= *errp) =20 static Property sm501_pci_properties[] =3D { DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * MiB), + DEFINE_PROP_UINT8("x-pixman", SM501PCIState, state.use_pixman, 7), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -2162,11 +2167,18 @@ static void sm501_pci_class_init(ObjectClass *klass= , void *data) dc->vmsd =3D &vmstate_sm501_pci; } =20 +static void sm501_pci_init(Object *o) +{ + object_property_set_description(o, "x-pixman", "Use pixman for: " + "1: fill, 2: blit, 4: overlap blit"); +} + static const TypeInfo sm501_pci_info =3D { .name =3D TYPE_PCI_SM501, .parent =3D TYPE_PCI_DEVICE, .instance_size =3D sizeof(SM501PCIState), .class_init =3D sm501_pci_class_init, + .instance_init =3D sm501_pci_init, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { }, --=20 2.30.8 From nobody Sun Apr 28 23:39:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678025225712632.9888176969234; Sun, 5 Mar 2023 06:07:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYp02-0007Bh-Ib; Sun, 05 Mar 2023 09:06:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYozz-00076z-2M; Sun, 05 Mar 2023 09:06:03 -0500 Received: from zero.eik.bme.hu ([152.66.115.2]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYozw-0000dC-Qc; Sun, 05 Mar 2023 09:06:02 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 4475D74638A; Sun, 5 Mar 2023 15:05:49 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 2313874634B; Sun, 5 Mar 2023 15:05:48 +0100 (CET) Message-Id: <5669136061a691de47f83ba113bff8d40e3fb464.1678023358.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v7 2/6] hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Gerd Hoffmann , Daniel Henrique Barboza , Bernhard Beschow , Peter Maydell , philmd@linaro.org, ReneEngel80@emailn.de, David Woodhouse , Michael S. Tsirkin , Paolo Bonzini Date: Sun, 5 Mar 2023 15:05:48 +0100 (CET) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1678025227776100003 Content-Type: text/plain; charset="utf-8" From: David Woodhouse Back in the mists of time, before EISA came along and required per-pin level control in the ELCR register, the i8259 had a single chip-wide level-mode control in bit 3 of ICW1. Even in the PIIX3 datasheet from 1996 this is documented as 'This bit is disabled', but apparently MorphOS is using it in the version of the i8259 which is in the Pegasos2 board as part of the VT8231 chipset. It's easy enough to implement, and I think it's harmless enough to do so unconditionally. Signed-off-by: David Woodhouse [balaton: updated commit message as asked by author] Tested-by: BALATON Zoltan Signed-off-by: BALATON Zoltan --- hw/intc/i8259.c | 10 ++++------ hw/intc/i8259_common.c | 24 +++++++++++++++++++++++- include/hw/isa/i8259_internal.h | 1 + 3 files changed, 28 insertions(+), 7 deletions(-) diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 17910f3bcb..bbae2d87f4 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -133,7 +133,7 @@ static void pic_set_irq(void *opaque, int irq, int leve= l) } #endif =20 - if (s->elcr & mask) { + if (s->ltim || (s->elcr & mask)) { /* level triggered */ if (level) { s->irr |=3D mask; @@ -167,7 +167,7 @@ static void pic_intack(PICCommonState *s, int irq) s->isr |=3D (1 << irq); } /* We don't clear a level sensitive interrupt here */ - if (!(s->elcr & (1 << irq))) { + if (!s->ltim && !(s->elcr & (1 << irq))) { s->irr &=3D ~(1 << irq); } pic_update_irq(s); @@ -224,6 +224,7 @@ static void pic_reset(DeviceState *dev) PICCommonState *s =3D PIC_COMMON(dev); =20 s->elcr =3D 0; + s->ltim =3D 0; pic_init_reset(s); } =20 @@ -243,10 +244,7 @@ static void pic_ioport_write(void *opaque, hwaddr addr= 64, s->init_state =3D 1; s->init4 =3D val & 1; s->single_mode =3D val & 2; - if (val & 0x08) { - qemu_log_mask(LOG_UNIMP, - "i8259: level sensitive irq not supported\n"= ); - } + s->ltim =3D val & 8; } else if (val & 0x08) { if (val & 0x04) { s->poll =3D 1; diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index af2e4a2241..c931dc2d07 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -51,7 +51,7 @@ void pic_reset_common(PICCommonState *s) s->special_fully_nested_mode =3D 0; s->init4 =3D 0; s->single_mode =3D 0; - /* Note: ELCR is not reset */ + /* Note: ELCR and LTIM are not reset */ } =20 static int pic_dispatch_pre_save(void *opaque) @@ -144,6 +144,24 @@ static void pic_print_info(InterruptStatsProvider *obj= , Monitor *mon) s->special_fully_nested_mode); } =20 +static bool ltim_state_needed(void *opaque) +{ + PICCommonState *s =3D PIC_COMMON(opaque); + + return !!s->ltim; +} + +static const VMStateDescription vmstate_pic_ltim =3D { + .name =3D "i8259/ltim", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D ltim_state_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8(ltim, PICCommonState), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_pic_common =3D { .name =3D "i8259", .version_id =3D 1, @@ -168,6 +186,10 @@ static const VMStateDescription vmstate_pic_common =3D= { VMSTATE_UINT8(single_mode, PICCommonState), VMSTATE_UINT8(elcr, PICCommonState), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription*[]) { + &vmstate_pic_ltim, + NULL } }; =20 diff --git a/include/hw/isa/i8259_internal.h b/include/hw/isa/i8259_interna= l.h index 155b098452..f9dcc4163e 100644 --- a/include/hw/isa/i8259_internal.h +++ b/include/hw/isa/i8259_internal.h @@ -61,6 +61,7 @@ struct PICCommonState { uint8_t single_mode; /* true if slave pic is not initialized */ uint8_t elcr; /* PIIX edge/trigger selection*/ uint8_t elcr_mask; + uint8_t ltim; /* Edge/Level Bank Select (pre-PIIX, chip-wide) */ qemu_irq int_out[1]; uint32_t master; /* reflects /SP input pin */ uint32_t iobase; --=20 2.30.8 From nobody Sun Apr 28 23:39:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16780252325211004.9111010993151; Sun, 5 Mar 2023 06:07:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYp02-0007A8-A1; Sun, 05 Mar 2023 09:06:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYp00-00077C-2F; Sun, 05 Mar 2023 09:06:04 -0500 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYozw-0000dJ-SE; Sun, 05 Mar 2023 09:06:03 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 22000746361; Sun, 5 Mar 2023 15:05:50 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 2DB8C746376; Sun, 5 Mar 2023 15:05:49 +0100 (CET) Message-Id: <2c1aa2fad58fffa4e26e8e271243ed30ecd9d41d.1678023358.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v7 3/6] hw/isa/vt82c686: Implement PCI IRQ routing MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Gerd Hoffmann , Daniel Henrique Barboza , Bernhard Beschow , Peter Maydell , philmd@linaro.org, ReneEngel80@emailn.de Date: Sun, 5 Mar 2023 15:05:49 +0100 (CET) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1678025233782100001 Content-Type: text/plain; charset="utf-8" The real VIA south bridges implement a PCI IRQ router which is configured by the BIOS or the OS. In order to respect these configurations, QEMU needs to implement it as well. The real chip may allow routing IRQs from internal functions independently of PCI interrupts but since guests usually configute it to a single shared interrupt we don't model that here for simplicity. Note: The implementation was taken from piix4_set_irq() in hw/isa/piix4. Suggested-by: Bernhard Beschow Signed-off-by: BALATON Zoltan Tested-by: Rene Engel --- hw/isa/vt82c686.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 8900d87f59..e5aa467506 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -600,6 +600,46 @@ void via_isa_set_irq(PCIDevice *d, int n, int level) qemu_set_irq(s->isa_irqs_in[n], level); } =20 +static int via_isa_get_pci_irq(const ViaISAState *s, int irq_num) +{ + switch (irq_num) { + case 0: + return s->dev.config[0x55] >> 4; + case 1: + return s->dev.config[0x56] & 0xf; + case 2: + return s->dev.config[0x56] >> 4; + case 3: + return s->dev.config[0x57] >> 4; + } + return 0; +} + +static void via_isa_set_pci_irq(void *opaque, int irq_num, int level) +{ + ViaISAState *s =3D opaque; + PCIBus *bus =3D pci_get_bus(&s->dev); + int i, pic_level, pic_irq =3D via_isa_get_pci_irq(s, irq_num); + + /* IRQ 0 and 15 mean disabled, IRQ 2 is reserved */ + if (unlikely(pic_irq =3D=3D 0 || pic_irq =3D=3D 2 || pic_irq > 14)) { + if (pic_irq =3D=3D 2) { + qemu_log_mask(LOG_GUEST_ERROR, "Invalid ISA IRQ routing"); + } + return; + } + + /* The pic level is the logical OR of all the PCI irqs mapped to it. */ + pic_level =3D 0; + for (i =3D 0; i < PCI_NUM_PINS; i++) { + if (pic_irq =3D=3D via_isa_get_pci_irq(s, i)) { + pic_level |=3D pci_bus_get_irq_level(bus, i); + } + } + /* Now we change the pic irq level according to the via irq mappings. = */ + qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level); +} + static void via_isa_realize(PCIDevice *d, Error **errp) { ViaISAState *s =3D VIA_ISA(d); @@ -620,6 +660,8 @@ static void via_isa_realize(PCIDevice *d, Error **errp) i8254_pit_init(isa_bus, 0x40, 0, NULL); i8257_dma_init(isa_bus, 0); =20 + qdev_init_gpio_in_named(dev, via_isa_set_pci_irq, "pirq", PCI_NUM_PINS= ); + /* RTC */ qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { --=20 2.30.8 From nobody Sun Apr 28 23:39:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16780252513961.681138751936146; Sun, 5 Mar 2023 06:07:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYp02-0007A3-9d; Sun, 05 Mar 2023 09:06:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYp00-00077H-8d; Sun, 05 Mar 2023 09:06:04 -0500 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYozx-0000dL-1l; Sun, 05 Mar 2023 09:06:03 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 6424C7466FF; Sun, 5 Mar 2023 15:05:50 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 395C974645F; Sun, 5 Mar 2023 15:05:50 +0100 (CET) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v7 4/6] hw/ppc/pegasos2: Fix PCI interrupt routing MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Gerd Hoffmann , Daniel Henrique Barboza , Bernhard Beschow , Peter Maydell , philmd@linaro.org, ReneEngel80@emailn.de Date: Sun, 5 Mar 2023 15:05:50 +0100 (CET) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1678025251878100001 Content-Type: text/plain; charset="utf-8" According to the PegasosII schematics the PCI interrupt lines are connected to both the gpp pins of the Mv64361 north bridge and the PINT pins of the VT8231 south bridge so guests can get interrupts from either of these. So far we only had the MV64361 connections which worked for on board devices but for additional PCI devices (such as network or sound card added with -device) guest OSes expect interrupt from the ISA IRQ 9 where the firmware routes these PCI interrupts in VT8231 ISA bridge. After the previous patches we can now model this and also remove the board specific connection from mv64361. Also configure routing of these lines when using Virtual Open Firmware to match board firmware for guests that expect this. This fixes PCI interrupts on pegasos2 under Linux, MorphOS and AmigaOS. Signed-off-by: BALATON Zoltan Reviewed-by: Daniel Henrique Barboza Tested-by: Rene Engel --- hw/pci-host/mv64361.c | 4 ---- hw/ppc/pegasos2.c | 26 +++++++++++++++++++++++++- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c index 298564f1f5..19e8031a3f 100644 --- a/hw/pci-host/mv64361.c +++ b/hw/pci-host/mv64361.c @@ -873,10 +873,6 @@ static void mv64361_realize(DeviceState *dev, Error **= errp) } sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cpu_irq); qdev_init_gpio_in_named(dev, mv64361_gpp_irq, "gpp", 32); - /* FIXME: PCI IRQ connections may be board specific */ - for (i =3D 0; i < PCI_NUM_PINS; i++) { - s->pci[1].irq[i] =3D qdev_get_gpio_in_named(dev, "gpp", 12 + i); - } } =20 static void mv64361_reset(DeviceState *dev) diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index b0ada9c963..ded5dc2dc9 100644 --- a/hw/ppc/pegasos2.c +++ b/hw/ppc/pegasos2.c @@ -73,6 +73,8 @@ struct Pegasos2MachineState { MachineState parent_obj; PowerPCCPU *cpu; DeviceState *mv; + qemu_irq mv_pirq[PCI_NUM_PINS]; + qemu_irq via_pirq[PCI_NUM_PINS]; Vof *vof; void *fdt_blob; uint64_t kernel_addr; @@ -95,6 +97,15 @@ static void pegasos2_cpu_reset(void *opaque) } } =20 +static void pegasos2_pci_irq(void *opaque, int n, int level) +{ + Pegasos2MachineState *pm =3D opaque; + + /* PCI interrupt lines are connected to both MV64361 and VT8231 */ + qemu_set_irq(pm->mv_pirq[n], level); + qemu_set_irq(pm->via_pirq[n], level); +} + static void pegasos2_init(MachineState *machine) { Pegasos2MachineState *pm =3D PEGASOS2_MACHINE(machine); @@ -106,7 +117,7 @@ static void pegasos2_init(MachineState *machine) I2CBus *i2c_bus; const char *fwname =3D machine->firmware ?: PROM_FILENAME; char *filename; - int sz; + int i, sz; uint8_t *spd_data; =20 /* init CPU */ @@ -156,7 +167,11 @@ static void pegasos2_init(MachineState *machine) /* Marvell Discovery II system controller */ pm->mv =3D DEVICE(sysbus_create_simple(TYPE_MV64361, -1, qdev_get_gpio_in(DEVICE(pm->cpu), PPC6xx_INPUT_I= NT))); + for (i =3D 0; i < PCI_NUM_PINS; i++) { + pm->mv_pirq[i] =3D qdev_get_gpio_in_named(pm->mv, "gpp", 12 + i); + } pci_bus =3D mv64361_get_pci_bus(pm->mv, 1); + pci_bus_irqs(pci_bus, pegasos2_pci_irq, pm, PCI_NUM_PINS); =20 /* VIA VT8231 South Bridge (multifunction PCI device) */ via =3D OBJECT(pci_new_multifunction(PCI_DEVFN(12, 0), true, @@ -164,6 +179,9 @@ static void pegasos2_init(MachineState *machine) qdev_connect_gpio_out(DEVICE(via), 0, qdev_get_gpio_in_named(pm->mv, "gpp", 31)); pci_realize_and_unref(PCI_DEVICE(via), pci_bus, &error_fatal); + for (i =3D 0; i < PCI_NUM_PINS; i++) { + pm->via_pirq[i] =3D qdev_get_gpio_in_named(DEVICE(via), "pirq", i); + } =20 object_property_add_alias(OBJECT(machine), "rtc-time", object_resolve_path_component(via, "rtc"), @@ -269,6 +287,12 @@ static void pegasos2_machine_reset(MachineState *machi= ne, ShutdownCause reason) PCI_INTERRUPT_LINE, 2, 0x9); pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 0x50, 1, 0x2); + pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | + 0x55, 1, 0x90); + pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | + 0x56, 1, 0x99); + pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | + 0x57, 1, 0x90); =20 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | PCI_INTERRUPT_LINE, 2, 0x109); --=20 2.30.8 From nobody Sun Apr 28 23:39:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678025206276678.7781624604069; Sun, 5 Mar 2023 06:06:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYp05-0007F7-OJ; Sun, 05 Mar 2023 09:06:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYp01-00078G-K9; Sun, 05 Mar 2023 09:06:05 -0500 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYp00-0000eB-4y; Sun, 05 Mar 2023 09:06:05 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 7C7F9746E06; Sun, 5 Mar 2023 15:05:51 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 47FA6746D65; Sun, 5 Mar 2023 15:05:51 +0100 (CET) Message-Id: <5bc0b857894a28ecfcb76463ecf2c17ad8c40082.1678023358.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v7 5/6] hw/usb/vt82c686-uhci-pci: Use PCI IRQ routing MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Gerd Hoffmann , Daniel Henrique Barboza , Bernhard Beschow , Peter Maydell , philmd@linaro.org, ReneEngel80@emailn.de Date: Sun, 5 Mar 2023 15:05:51 +0100 (CET) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1678025209702100002 Content-Type: text/plain; charset="utf-8" From: Bernhard Beschow According to the PCI specification, PCI_INTERRUPT_LINE shall have no effect on hardware operations. Now that the VIA south bridges implement the internal PCI interrupt router let's be more conformant to the PCI specification. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland Signed-off-by: BALATON Zoltan Tested-by: Rene Engel --- hw/usb/vt82c686-uhci-pci.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/hw/usb/vt82c686-uhci-pci.c b/hw/usb/vt82c686-uhci-pci.c index 46a901f56f..b4884c9011 100644 --- a/hw/usb/vt82c686-uhci-pci.c +++ b/hw/usb/vt82c686-uhci-pci.c @@ -1,17 +1,7 @@ #include "qemu/osdep.h" -#include "hw/irq.h" #include "hw/isa/vt82c686.h" #include "hcd-uhci.h" =20 -static void uhci_isa_set_irq(void *opaque, int irq_num, int level) -{ - UHCIState *s =3D opaque; - uint8_t irq =3D pci_get_byte(s->dev.config + PCI_INTERRUPT_LINE); - if (irq > 0 && irq < 15) { - via_isa_set_irq(pci_get_function_0(&s->dev), irq, level); - } -} - static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp) { UHCIState *s =3D UHCI(dev); @@ -25,8 +15,6 @@ static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Er= ror **errp) pci_set_long(pci_conf + 0xc0, 0x00002000); =20 usb_uhci_common_realize(dev, errp); - object_unref(s->irq); - s->irq =3D qemu_allocate_irq(uhci_isa_set_irq, s, 0); } =20 static UHCIInfo uhci_info[] =3D { --=20 2.30.8 From nobody Sun Apr 28 23:39:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678025215896756.6823333190679; Sun, 5 Mar 2023 06:06:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYp09-0007H3-Uc; Sun, 05 Mar 2023 09:06:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYp03-0007DA-4U; Sun, 05 Mar 2023 09:06:07 -0500 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYp00-0000eA-5O; Sun, 05 Mar 2023 09:06:06 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 9CD77746F63; Sun, 5 Mar 2023 15:05:52 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 53490746F34; Sun, 5 Mar 2023 15:05:52 +0100 (CET) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v7 6/6] hw/audio/via-ac97: Basic implementation of audio playback MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Gerd Hoffmann , Daniel Henrique Barboza , Bernhard Beschow , Peter Maydell , philmd@linaro.org, ReneEngel80@emailn.de Date: Sun, 5 Mar 2023 15:05:52 +0100 (CET) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1678025217739100001 Add basic implementation of the AC'97 sound part used in VIA south bridge chips. Not all features of the device is emulated, only one playback channel is supported for now but this is enough to get sound output from some guests using this device on pegasos2. Signed-off-by: BALATON Zoltan Reviewed-by: Volker R=C3=BCmelin Tested-by: Rene Engel --- hw/audio/trace-events | 6 + hw/audio/via-ac97.c | 455 +++++++++++++++++++++++++++++++++++++- hw/isa/trace-events | 1 + hw/isa/vt82c686.c | 2 +- include/hw/isa/vt82c686.h | 25 +++ 5 files changed, 482 insertions(+), 7 deletions(-) diff --git a/hw/audio/trace-events b/hw/audio/trace-events index e0e71cd9b1..4dec48a4fd 100644 --- a/hw/audio/trace-events +++ b/hw/audio/trace-events @@ -11,3 +11,9 @@ hda_audio_running(const char *stream, int nr, bool runnin= g) "st %s, nr %d, run % hda_audio_format(const char *stream, int chan, const char *fmt, int freq) = "st %s, %d x %s @ %d Hz" hda_audio_adjust(const char *stream, int pos) "st %s, pos %d" hda_audio_overrun(const char *stream) "st %s" + +#via-ac97.c +via_ac97_codec_write(uint8_t addr, uint16_t val) "0x%x <- 0x%x" +via_ac97_sgd_fetch(uint32_t curr, uint32_t addr, char stop, char eol, char= flag, uint32_t len) "curr=3D0x%x addr=3D0x%x %c%c%c len=3D%d" +via_ac97_sgd_read(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64"= %d -> 0x%"PRIx64 +via_ac97_sgd_write(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64= " %d <- 0x%"PRIx64 diff --git a/hw/audio/via-ac97.c b/hw/audio/via-ac97.c index d1a856f63d..676254b7a4 100644 --- a/hw/audio/via-ac97.c +++ b/hw/audio/via-ac97.c @@ -1,39 +1,482 @@ /* * VIA south bridges sound support * + * Copyright (c) 2022-2023 BALATON Zoltan + * * This work is licensed under the GNU GPL license version 2 or later. */ =20 /* - * TODO: This is entirely boiler plate just registering empty PCI devices - * with the right ID guests expect, functionality should be added here. + * TODO: This is only a basic implementation of one audio playback channel + * more functionality should be added here. */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" #include "hw/isa/vt82c686.h" -#include "hw/pci/pci_device.h" +#include "ac97.h" +#include "trace.h" + +#define CLEN_IS_EOL(x) ((x)->clen & BIT(31)) +#define CLEN_IS_FLAG(x) ((x)->clen & BIT(30)) +#define CLEN_IS_STOP(x) ((x)->clen & BIT(29)) +#define CLEN_LEN(x) ((x)->clen & 0xffffff) + +#define STAT_ACTIVE BIT(7) +#define STAT_PAUSED BIT(6) +#define STAT_TRIG BIT(3) +#define STAT_STOP BIT(2) +#define STAT_EOL BIT(1) +#define STAT_FLAG BIT(0) + +#define CNTL_START BIT(7) +#define CNTL_TERM BIT(6) +#define CNTL_PAUSE BIT(3) + +static void open_voice_out(ViaAC97State *s); + +static uint16_t codec_rates[] =3D { 8000, 11025, 16000, 22050, 32000, 4410= 0, + 48000 }; + +#define CODEC_REG(s, o) ((s)->codec_regs[(o) / 2]) +#define CODEC_VOL(vol, mask) ((255 * ((vol) & mask)) / mask) + +static void codec_volume_set_out(ViaAC97State *s) +{ + int lvol, rvol, mute; + + lvol =3D 255 - CODEC_VOL(CODEC_REG(s, AC97_Master_Volume_Mute) >> 8, 0= x1f); + lvol *=3D 255 - CODEC_VOL(CODEC_REG(s, AC97_PCM_Out_Volume_Mute) >> 8,= 0x1f); + lvol /=3D 255; + rvol =3D 255 - CODEC_VOL(CODEC_REG(s, AC97_Master_Volume_Mute), 0x1f); + rvol *=3D 255 - CODEC_VOL(CODEC_REG(s, AC97_PCM_Out_Volume_Mute), 0x1f= ); + rvol /=3D 255; + mute =3D CODEC_REG(s, AC97_Master_Volume_Mute) >> MUTE_SHIFT; + mute |=3D CODEC_REG(s, AC97_PCM_Out_Volume_Mute) >> MUTE_SHIFT; + AUD_set_volume_out(s->vo, mute, lvol, rvol); +} + +static void codec_reset(ViaAC97State *s) +{ + memset(s->codec_regs, 0, sizeof(s->codec_regs)); + CODEC_REG(s, AC97_Reset) =3D 0x6a90; + CODEC_REG(s, AC97_Master_Volume_Mute) =3D 0x8000; + CODEC_REG(s, AC97_Headphone_Volume_Mute) =3D 0x8000; + CODEC_REG(s, AC97_Master_Volume_Mono_Mute) =3D 0x8000; + CODEC_REG(s, AC97_Phone_Volume_Mute) =3D 0x8008; + CODEC_REG(s, AC97_Mic_Volume_Mute) =3D 0x8008; + CODEC_REG(s, AC97_Line_In_Volume_Mute) =3D 0x8808; + CODEC_REG(s, AC97_CD_Volume_Mute) =3D 0x8808; + CODEC_REG(s, AC97_Video_Volume_Mute) =3D 0x8808; + CODEC_REG(s, AC97_Aux_Volume_Mute) =3D 0x8808; + CODEC_REG(s, AC97_PCM_Out_Volume_Mute) =3D 0x8808; + CODEC_REG(s, AC97_Record_Gain_Mute) =3D 0x8000; + CODEC_REG(s, AC97_Powerdown_Ctrl_Stat) =3D 0x000f; + CODEC_REG(s, AC97_Extended_Audio_ID) =3D 0x0a05; + CODEC_REG(s, AC97_Extended_Audio_Ctrl_Stat) =3D 0x0400; + CODEC_REG(s, AC97_PCM_Front_DAC_Rate) =3D 48000; + CODEC_REG(s, AC97_PCM_LR_ADC_Rate) =3D 48000; + /* Sigmatel 9766 (STAC9766) */ + CODEC_REG(s, AC97_Vendor_ID1) =3D 0x8384; + CODEC_REG(s, AC97_Vendor_ID2) =3D 0x7666; +} + +static uint16_t codec_read(ViaAC97State *s, uint8_t addr) +{ + return CODEC_REG(s, addr); +} + +static void codec_write(ViaAC97State *s, uint8_t addr, uint16_t val) +{ + trace_via_ac97_codec_write(addr, val); + switch (addr) { + case AC97_Reset: + codec_reset(s); + return; + case AC97_Master_Volume_Mute: + case AC97_PCM_Out_Volume_Mute: + if (addr =3D=3D AC97_Master_Volume_Mute) { + if (val & BIT(13)) { + val |=3D 0x1f00; + } + if (val & BIT(5)) { + val |=3D 0x1f; + } + } + CODEC_REG(s, addr) =3D val & 0x9f1f; + codec_volume_set_out(s); + return; + case AC97_Extended_Audio_Ctrl_Stat: + CODEC_REG(s, addr) &=3D ~EACS_VRA; + CODEC_REG(s, addr) |=3D val & EACS_VRA; + if (!(val & EACS_VRA)) { + CODEC_REG(s, AC97_PCM_Front_DAC_Rate) =3D 48000; + CODEC_REG(s, AC97_PCM_LR_ADC_Rate) =3D 48000; + open_voice_out(s); + } + return; + case AC97_PCM_Front_DAC_Rate: + case AC97_PCM_LR_ADC_Rate: + if (CODEC_REG(s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) { + int i; + uint16_t rate =3D val; + + for (i =3D 0; i < ARRAY_SIZE(codec_rates) - 1; i++) { + if (rate < codec_rates[i] + + (codec_rates[i + 1] - codec_rates[i]) / 2) { + rate =3D codec_rates[i]; + break; + } + } + if (rate > 48000) { + rate =3D 48000; + } + CODEC_REG(s, addr) =3D rate; + open_voice_out(s); + } + return; + case AC97_Powerdown_Ctrl_Stat: + CODEC_REG(s, addr) =3D (val & 0xff00) | (CODEC_REG(s, addr) & 0xff= ); + return; + case AC97_Extended_Audio_ID: + case AC97_Vendor_ID1: + case AC97_Vendor_ID2: + /* Read only registers */ + return; + default: + qemu_log_mask(LOG_UNIMP, + "via-ac97: Unimplemented codec register 0x%x\n", add= r); + CODEC_REG(s, addr) =3D val; + } +} + +static void fetch_sgd(ViaAC97SGDChannel *c, PCIDevice *d) +{ + uint32_t b[2]; + + if (c->curr < c->base) { + c->curr =3D c->base; + } + if (unlikely(pci_dma_read(d, c->curr, b, sizeof(b)) !=3D MEMTX_OK)) { + qemu_log_mask(LOG_GUEST_ERROR, + "via-ac97: DMA error reading SGD table\n"); + return; + } + c->addr =3D le32_to_cpu(b[0]); + c->clen =3D le32_to_cpu(b[1]); + trace_via_ac97_sgd_fetch(c->curr, c->addr, CLEN_IS_STOP(c) ? 'S' : '-', + CLEN_IS_EOL(c) ? 'E' : '-', + CLEN_IS_FLAG(c) ? 'F' : '-', CLEN_LEN(c)); +} + +static void out_cb(void *opaque, int avail) +{ + ViaAC97State *s =3D opaque; + ViaAC97SGDChannel *c =3D &s->aur; + int temp, to_copy, copied; + bool stop =3D false; + uint8_t tmpbuf[4096]; + + if (c->stat & STAT_PAUSED) { + return; + } + c->stat |=3D STAT_ACTIVE; + while (avail && !stop) { + if (!c->clen) { + fetch_sgd(c, &s->dev); + } + temp =3D MIN(CLEN_LEN(c), avail); + while (temp) { + to_copy =3D MIN(temp, sizeof(tmpbuf)); + pci_dma_read(&s->dev, c->addr, tmpbuf, to_copy); + copied =3D AUD_write(s->vo, tmpbuf, to_copy); + if (!copied) { + stop =3D true; + break; + } + temp -=3D copied; + avail -=3D copied; + c->addr +=3D copied; + c->clen -=3D copied; + } + if (CLEN_LEN(c) =3D=3D 0) { + c->curr +=3D 8; + if (CLEN_IS_EOL(c)) { + c->stat |=3D STAT_EOL; + if (c->type & CNTL_START) { + c->curr =3D c->base; + c->stat |=3D STAT_PAUSED; + } else { + c->stat &=3D ~STAT_ACTIVE; + AUD_set_active_out(s->vo, 0); + } + if (c->type & STAT_EOL) { + pci_set_irq(&s->dev, 1); + } + } + if (CLEN_IS_FLAG(c)) { + c->stat |=3D STAT_FLAG; + c->stat |=3D STAT_PAUSED; + if (c->type & STAT_FLAG) { + pci_set_irq(&s->dev, 1); + } + } + if (CLEN_IS_STOP(c)) { + c->stat |=3D STAT_STOP; + c->stat |=3D STAT_PAUSED; + } + c->clen =3D 0; + stop =3D true; + } + } +} + +static void open_voice_out(ViaAC97State *s) +{ + struct audsettings as =3D { + .freq =3D CODEC_REG(s, AC97_PCM_Front_DAC_Rate), + .nchannels =3D s->aur.type & BIT(4) ? 2 : 1, + .fmt =3D s->aur.type & BIT(5) ? AUDIO_FORMAT_S16 : AUDIO_FORMAT_S8, + .endianness =3D 0, + }; + s->vo =3D AUD_open_out(&s->card, s->vo, "via-ac97.out", s, out_cb, &as= ); +} + +static uint64_t sgd_read(void *opaque, hwaddr addr, unsigned size) +{ + ViaAC97State *s =3D opaque; + uint64_t val =3D 0; + + switch (addr) { + case 0: + val =3D s->aur.stat; + if (s->aur.type & CNTL_START) { + val |=3D STAT_TRIG; + } + break; + case 1: + val =3D s->aur.stat & STAT_PAUSED ? BIT(3) : 0; + break; + case 2: + val =3D s->aur.type; + break; + case 4: + val =3D s->aur.curr; + break; + case 0xc: + val =3D CLEN_LEN(&s->aur); + break; + case 0x10: + /* silence unimplemented log message that happens at every IRQ */ + break; + case 0x80: + val =3D s->ac97_cmd; + break; + case 0x84: + val =3D s->aur.stat & STAT_FLAG; + if (s->aur.stat & STAT_EOL) { + val |=3D BIT(4); + } + if (s->aur.stat & STAT_STOP) { + val |=3D BIT(8); + } + if (s->aur.stat & STAT_ACTIVE) { + val |=3D BIT(12); + } + break; + default: + qemu_log_mask(LOG_UNIMP, "via-ac97: Unimplemented register read 0x= %" + HWADDR_PRIx"\n", addr); + } + trace_via_ac97_sgd_read(addr, size, val); + return val; +} + +static void sgd_write(void *opaque, hwaddr addr, uint64_t val, unsigned si= ze) +{ + ViaAC97State *s =3D opaque; + + trace_via_ac97_sgd_write(addr, size, val); + switch (addr) { + case 0: + if (val & STAT_STOP) { + s->aur.stat &=3D ~STAT_PAUSED; + } + if (val & STAT_EOL) { + s->aur.stat &=3D ~(STAT_EOL | STAT_PAUSED); + if (s->aur.type & STAT_EOL) { + pci_set_irq(&s->dev, 0); + } + } + if (val & STAT_FLAG) { + s->aur.stat &=3D ~(STAT_FLAG | STAT_PAUSED); + if (s->aur.type & STAT_FLAG) { + pci_set_irq(&s->dev, 0); + } + } + break; + case 1: + if (val & CNTL_START) { + AUD_set_active_out(s->vo, 1); + s->aur.stat =3D STAT_ACTIVE; + } + if (val & CNTL_TERM) { + AUD_set_active_out(s->vo, 0); + s->aur.stat &=3D ~(STAT_ACTIVE | STAT_PAUSED); + s->aur.clen =3D 0; + } + if (val & CNTL_PAUSE) { + AUD_set_active_out(s->vo, 0); + s->aur.stat &=3D ~STAT_ACTIVE; + s->aur.stat |=3D STAT_PAUSED; + } else if (!(val & CNTL_PAUSE) && (s->aur.stat & STAT_PAUSED)) { + AUD_set_active_out(s->vo, 1); + s->aur.stat |=3D STAT_ACTIVE; + s->aur.stat &=3D ~STAT_PAUSED; + } + break; + case 2: + { + uint32_t oldval =3D s->aur.type; + s->aur.type =3D val; + if ((oldval & 0x30) !=3D (val & 0x30)) { + open_voice_out(s); + } + break; + } + case 4: + s->aur.base =3D val & ~1ULL; + s->aur.curr =3D s->aur.base; + break; + case 0x80: + if (val >> 30) { + /* we only have primary codec */ + break; + } + if (val & BIT(23)) { /* read reg */ + s->ac97_cmd =3D val & 0xc0ff0000ULL; + s->ac97_cmd |=3D codec_read(s, (val >> 16) & 0x7f); + s->ac97_cmd |=3D BIT(25); /* data valid */ + } else { + s->ac97_cmd =3D val & 0xc0ffffffULL; + codec_write(s, (val >> 16) & 0x7f, val); + } + break; + case 0xc: + case 0x84: + /* Read only */ + break; + default: + qemu_log_mask(LOG_UNIMP, "via-ac97: Unimplemented register write 0= x%" + HWADDR_PRIx"\n", addr); + } +} + +static const MemoryRegionOps sgd_ops =3D { + .read =3D sgd_read, + .write =3D sgd_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static uint64_t fm_read(void *opaque, hwaddr addr, unsigned size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%"HWADDR_PRIx" %d\n", __func__, addr, = size); + return 0; +} + +static void fm_write(void *opaque, hwaddr addr, uint64_t val, unsigned siz= e) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%"HWADDR_PRIx" %d <=3D 0x%"PRIX64"\n", + __func__, addr, size, val); +} + +static const MemoryRegionOps fm_ops =3D { + .read =3D fm_read, + .write =3D fm_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static uint64_t midi_read(void *opaque, hwaddr addr, unsigned size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%"HWADDR_PRIx" %d\n", __func__, addr, = size); + return 0; +} + +static void midi_write(void *opaque, hwaddr addr, uint64_t val, unsigned s= ize) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%"HWADDR_PRIx" %d <=3D 0x%"PRIX64"\n", + __func__, addr, size, val); +} + +static const MemoryRegionOps midi_ops =3D { + .read =3D midi_read, + .write =3D midi_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void via_ac97_reset(DeviceState *dev) +{ + ViaAC97State *s =3D VIA_AC97(dev); + + codec_reset(s); +} =20 static void via_ac97_realize(PCIDevice *pci_dev, Error **errp) { - pci_set_word(pci_dev->config + PCI_COMMAND, - PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY); + ViaAC97State *s =3D VIA_AC97(pci_dev); + Object *o =3D OBJECT(s); + + /* + * Command register Bus Master bit is documented to be fixed at 0 but = it's + * needed for PCI DMA to work in QEMU. The pegasos2 firmware writes 0 = here + * and the AmigaOS driver writes 1 only enabling IO bit which works on + * real hardware. So set it here and fix it to 1 to allow DMA. + */ + pci_set_word(pci_dev->config + PCI_COMMAND, PCI_COMMAND_MASTER); + pci_set_word(pci_dev->wmask + PCI_COMMAND, PCI_COMMAND_IO); pci_set_word(pci_dev->config + PCI_STATUS, PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_MEDIUM); pci_set_long(pci_dev->config + PCI_INTERRUPT_PIN, 0x03); + pci_set_byte(pci_dev->config + 0x40, 1); /* codec ready */ + + memory_region_init_io(&s->sgd, o, &sgd_ops, s, "via-ac97.sgd", 256); + pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->sgd); + memory_region_init_io(&s->fm, o, &fm_ops, s, "via-ac97.fm", 4); + pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->fm); + memory_region_init_io(&s->midi, o, &midi_ops, s, "via-ac97.midi", 4); + pci_register_bar(pci_dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &s->midi); + + AUD_register_card ("via-ac97", &s->card); } =20 +static void via_ac97_exit(PCIDevice *dev) +{ + ViaAC97State *s =3D VIA_AC97(dev); + + AUD_close_out(&s->card, s->vo); + AUD_remove_card(&s->card); +} + +static Property via_ac97_properties[] =3D { + DEFINE_AUDIO_PROPERTIES(ViaAC97State, card), + DEFINE_PROP_END_OF_LIST(), +}; + static void via_ac97_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 k->realize =3D via_ac97_realize; + k->exit =3D via_ac97_exit; k->vendor_id =3D PCI_VENDOR_ID_VIA; k->device_id =3D PCI_DEVICE_ID_VIA_AC97; k->revision =3D 0x50; k->class_id =3D PCI_CLASS_MULTIMEDIA_AUDIO; + device_class_set_props(dc, via_ac97_properties); set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->desc =3D "VIA AC97"; + dc->reset =3D via_ac97_reset; /* Reason: Part of a south bridge chip */ dc->user_creatable =3D false; } @@ -41,7 +484,7 @@ static void via_ac97_class_init(ObjectClass *klass, void= *data) static const TypeInfo via_ac97_info =3D { .name =3D TYPE_VIA_AC97, .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PCIDevice), + .instance_size =3D sizeof(ViaAC97State), .class_init =3D via_ac97_class_init, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, diff --git a/hw/isa/trace-events b/hw/isa/trace-events index c4567a9b47..1816e8307a 100644 --- a/hw/isa/trace-events +++ b/hw/isa/trace-events @@ -16,6 +16,7 @@ apm_io_write(uint8_t addr, uint8_t val) "write addr=3D0x%= x val=3D0x%02x" =20 # vt82c686.c via_isa_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x le= n 0x%x" +via_pm_read(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len = 0x%x" via_pm_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len= 0x%x" via_pm_io_read(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x l= en 0x%x" via_pm_io_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x = len 0x%x" diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index e5aa467506..896f279332 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -554,7 +554,7 @@ struct ViaISAState { PCIIDEState ide; UHCIState uhci[2]; ViaPMState pm; - PCIDevice ac97; + ViaAC97State ac97; PCIDevice mc97; }; =20 diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h index e273cd38dc..da1722daf2 100644 --- a/include/hw/isa/vt82c686.h +++ b/include/hw/isa/vt82c686.h @@ -1,6 +1,8 @@ #ifndef HW_VT82C686_H #define HW_VT82C686_H =20 +#include "hw/pci/pci_device.h" +#include "audio/audio.h" =20 #define TYPE_VT82C686B_ISA "vt82c686b-isa" #define TYPE_VT82C686B_USB_UHCI "vt82c686b-usb-uhci" @@ -9,6 +11,29 @@ #define TYPE_VIA_IDE "via-ide" #define TYPE_VIA_MC97 "via-mc97" =20 +typedef struct { + uint8_t stat; + uint8_t type; + uint32_t base; + uint32_t curr; + uint32_t addr; + uint32_t clen; +} ViaAC97SGDChannel; + +OBJECT_DECLARE_SIMPLE_TYPE(ViaAC97State, VIA_AC97); + +struct ViaAC97State { + PCIDevice dev; + QEMUSoundCard card; + MemoryRegion sgd; + MemoryRegion fm; + MemoryRegion midi; + SWVoiceOut *vo; + ViaAC97SGDChannel aur; + uint16_t codec_regs[128]; + uint32_t ac97_cmd; +}; + void via_isa_set_irq(PCIDevice *d, int n, int level); =20 #endif --=20 2.30.8