From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663094272421804.1552799406725; Tue, 13 Sep 2022 11:37:52 -0700 (PDT) Received: from localhost ([::1]:38856 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYAn8-0004SQ-D4 for importer@patchew.org; Tue, 13 Sep 2022 14:37:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40424) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAYx-0006IA-KL; Tue, 13 Sep 2022 14:23:12 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:15164) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAYu-0007bt-Jm; Tue, 13 Sep 2022 14:23:10 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id D057E74633F; Tue, 13 Sep 2022 20:23:01 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 9A65D74633E; Tue, 13 Sep 2022 20:23:01 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 01/18] ppc440_bamboo: Remove unnecessary memsets MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:01 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663094273562100001 Content-Type: text/plain; charset="utf-8" In ppc4xx_sdram_init() the struct is allocated with g_new0() so no need to clear its elements. In the bamboo machine init memset can be replaced with array initialiser which is shorter. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440_bamboo.c | 6 ++---- hw/ppc/ppc4xx_devs.c | 8 ++------ 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index ea945a1c99..5ec82fa8c2 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -169,8 +169,8 @@ static void bamboo_init(MachineState *machine) MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *isa =3D g_new(MemoryRegion, 1); MemoryRegion *ram_memories =3D g_new(MemoryRegion, PPC440EP_SDRAM_NR_B= ANKS); - hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS]; - hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS]; + hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS] =3D {0}; + hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS] =3D {0}; PCIBus *pcibus; PowerPCCPU *cpu; CPUPPCState *env; @@ -205,8 +205,6 @@ static void bamboo_init(MachineState *machine) qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); =20 /* SDRAM controller */ - memset(ram_bases, 0, sizeof(ram_bases)); - memset(ram_sizes, 0, sizeof(ram_sizes)); ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories, ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes); /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0= . */ diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index ce38ae65e6..b4cd10f735 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -363,12 +363,8 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq,= int nbanks, sdram->irq =3D irq; sdram->nbanks =3D nbanks; sdram->ram_memories =3D ram_memories; - memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr)); - memcpy(sdram->ram_bases, ram_bases, - nbanks * sizeof(hwaddr)); - memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr)); - memcpy(sdram->ram_sizes, ram_sizes, - nbanks * sizeof(hwaddr)); + memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr)); + memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr)); qemu_register_reset(&sdram_reset, sdram); ppc_dcr_register(env, SDRAM0_CFGADDR, sdram, &dcr_read_sdram, &dcr_write_sdram); --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663094341916624.9594777660318; Tue, 13 Sep 2022 11:39:01 -0700 (PDT) Received: from localhost ([::1]:35842 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYAoG-0007Gm-N7 for importer@patchew.org; Tue, 13 Sep 2022 14:39:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAYy-0006JG-SU; Tue, 13 Sep 2022 14:23:12 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:15167) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAYu-0007c0-Jl; Tue, 13 Sep 2022 14:23:12 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id F406474635D; Tue, 13 Sep 2022 20:23:02 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id B218474633E; Tue, 13 Sep 2022 20:23:02 +0200 (CEST) Message-Id: <4b02098ad024805527137d0a9c97edf591e4dd43.1663092335.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 02/18] ppc4xx: Introduce Ppc4xxSdramBank struct MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:02 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663094343440100001 Instead of storing sdram bank parameters in unrelated arrays put them in a struct so it's clear they belong to the same bank and simplify the state struct using this bank type. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/ppc/ppc440_uc.c | 49 +++++++++++++++++----------------- hw/ppc/ppc4xx_devs.c | 59 ++++++++++++++++++++--------------------- include/hw/ppc/ppc4xx.h | 8 ++++++ 3 files changed, 61 insertions(+), 55 deletions(-) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 53e981ddf4..db33334e29 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -16,7 +16,7 @@ #include "qemu/module.h" #include "hw/irq.h" #include "exec/memory.h" -#include "hw/ppc/ppc.h" +#include "hw/ppc/ppc4xx.h" #include "hw/qdev-properties.h" #include "hw/pci/pci.h" #include "sysemu/block-backend.h" @@ -485,11 +485,7 @@ void ppc4xx_sdr_init(CPUPPCState *env) typedef struct ppc440_sdram_t { uint32_t addr; int nbanks; - MemoryRegion containers[4]; /* used for clipping */ - MemoryRegion *ram_memories; - hwaddr ram_bases[4]; - hwaddr ram_sizes[4]; - uint32_t bcr[4]; + Ppc4xxSdramBank bank[4]; } ppc440_sdram_t; =20 enum { @@ -570,23 +566,23 @@ static uint64_t sdram_size(uint32_t bcr) static void sdram_set_bcr(ppc440_sdram_t *sdram, int i, uint32_t bcr, int enabled) { - if (sdram->bcr[i] & 1) { + if (sdram->bank[i].bcr & 1) { /* First unmap RAM if enabled */ memory_region_del_subregion(get_system_memory(), - &sdram->containers[i]); - memory_region_del_subregion(&sdram->containers[i], - &sdram->ram_memories[i]); - object_unparent(OBJECT(&sdram->containers[i])); + &sdram->bank[i].container); + memory_region_del_subregion(&sdram->bank[i].container, + &sdram->bank[i].ram); + object_unparent(OBJECT(&sdram->bank[i].container)); } - sdram->bcr[i] =3D bcr & 0xffe0ffc1; + sdram->bank[i].bcr =3D bcr & 0xffe0ffc1; if (enabled && (bcr & 1)) { - memory_region_init(&sdram->containers[i], NULL, "sdram-containers", + memory_region_init(&sdram->bank[i].container, NULL, "sdram-contain= er", sdram_size(bcr)); - memory_region_add_subregion(&sdram->containers[i], 0, - &sdram->ram_memories[i]); + memory_region_add_subregion(&sdram->bank[i].container, 0, + &sdram->bank[i].ram); memory_region_add_subregion(get_system_memory(), sdram_base(bcr), - &sdram->containers[i]); + &sdram->bank[i].container); } } =20 @@ -595,9 +591,9 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram) int i; =20 for (i =3D 0; i < sdram->nbanks; i++) { - if (sdram->ram_sizes[i] !=3D 0) { - sdram_set_bcr(sdram, i, sdram_bcr(sdram->ram_bases[i], - sdram->ram_sizes[i]), 1); + if (sdram->bank[i].size !=3D 0) { + sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base, + sdram->bank[i].size), 1); } else { sdram_set_bcr(sdram, i, 0, 0); } @@ -614,9 +610,9 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn) case SDRAM_R1BAS: case SDRAM_R2BAS: case SDRAM_R3BAS: - if (sdram->ram_sizes[dcrn - SDRAM_R0BAS]) { - ret =3D sdram_bcr(sdram->ram_bases[dcrn - SDRAM_R0BAS], - sdram->ram_sizes[dcrn - SDRAM_R0BAS]); + if (sdram->bank[dcrn - SDRAM_R0BAS].size) { + ret =3D sdram_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base, + sdram->bank[dcrn - SDRAM_R0BAS].size); } break; case SDRAM_CONF1HB: @@ -701,12 +697,15 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks, int do_init) { ppc440_sdram_t *sdram; + int i; =20 sdram =3D g_malloc0(sizeof(*sdram)); sdram->nbanks =3D nbanks; - sdram->ram_memories =3D ram_memories; - memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr)); - memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr)); + for (i =3D 0; i < nbanks; i++) { + sdram->bank[i].ram =3D ram_memories[i]; + sdram->bank[i].base =3D ram_bases[i]; + sdram->bank[i].size =3D ram_sizes[i]; + } qemu_register_reset(&sdram_reset, sdram); ppc_dcr_register(env, SDRAM0_CFGADDR, sdram, &dcr_read_sdram, &dcr_write_sdram); diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index b4cd10f735..1226ec4aa9 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -42,10 +42,7 @@ typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; struct ppc4xx_sdram_t { uint32_t addr; int nbanks; - MemoryRegion containers[4]; /* used for clipping */ - MemoryRegion *ram_memories; - hwaddr ram_bases[4]; - hwaddr ram_sizes[4]; + Ppc4xxSdramBank bank[4]; uint32_t besr0; uint32_t besr1; uint32_t bear; @@ -53,7 +50,6 @@ struct ppc4xx_sdram_t { uint32_t status; uint32_t rtr; uint32_t pmit; - uint32_t bcr[4]; uint32_t tr; uint32_t ecccfg; uint32_t eccesr; @@ -131,26 +127,26 @@ static target_ulong sdram_size(uint32_t bcr) static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i, uint32_t bcr, int enabled) { - if (sdram->bcr[i] & 0x00000001) { + if (sdram->bank[i].bcr & 0x00000001) { /* Unmap RAM */ - trace_ppc4xx_sdram_unmap(sdram_base(sdram->bcr[i]), - sdram_size(sdram->bcr[i])); + trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr), + sdram_size(sdram->bank[i].bcr)); memory_region_del_subregion(get_system_memory(), - &sdram->containers[i]); - memory_region_del_subregion(&sdram->containers[i], - &sdram->ram_memories[i]); - object_unparent(OBJECT(&sdram->containers[i])); + &sdram->bank[i].container); + memory_region_del_subregion(&sdram->bank[i].container, + &sdram->bank[i].ram); + object_unparent(OBJECT(&sdram->bank[i].container)); } - sdram->bcr[i] =3D bcr & 0xFFDEE001; + sdram->bank[i].bcr =3D bcr & 0xFFDEE001; if (enabled && (bcr & 0x00000001)) { trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr)); - memory_region_init(&sdram->containers[i], NULL, "sdram-containers", + memory_region_init(&sdram->bank[i].container, NULL, "sdram-contain= er", sdram_size(bcr)); - memory_region_add_subregion(&sdram->containers[i], 0, - &sdram->ram_memories[i]); + memory_region_add_subregion(&sdram->bank[i].container, 0, + &sdram->bank[i].ram); memory_region_add_subregion(get_system_memory(), sdram_base(bcr), - &sdram->containers[i]); + &sdram->bank[i].container); } } =20 @@ -159,9 +155,9 @@ static void sdram_map_bcr(ppc4xx_sdram_t *sdram) int i; =20 for (i =3D 0; i < sdram->nbanks; i++) { - if (sdram->ram_sizes[i] !=3D 0) { - sdram_set_bcr(sdram, i, sdram_bcr(sdram->ram_bases[i], - sdram->ram_sizes[i]), 1); + if (sdram->bank[i].size !=3D 0) { + sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base, + sdram->bank[i].size), 1); } else { sdram_set_bcr(sdram, i, 0x00000000, 0); } @@ -173,10 +169,10 @@ static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram) int i; =20 for (i =3D 0; i < sdram->nbanks; i++) { - trace_ppc4xx_sdram_unmap(sdram_base(sdram->bcr[i]), - sdram_size(sdram->bcr[i])); + trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr), + sdram_size(sdram->bank[i].bcr)); memory_region_del_subregion(get_system_memory(), - &sdram->ram_memories[i]); + &sdram->bank[i].ram); } } =20 @@ -214,16 +210,16 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn) ret =3D sdram->pmit; break; case 0x40: /* SDRAM_B0CR */ - ret =3D sdram->bcr[0]; + ret =3D sdram->bank[0].bcr; break; case 0x44: /* SDRAM_B1CR */ - ret =3D sdram->bcr[1]; + ret =3D sdram->bank[1].bcr; break; case 0x48: /* SDRAM_B2CR */ - ret =3D sdram->bcr[2]; + ret =3D sdram->bank[2].bcr; break; case 0x4C: /* SDRAM_B3CR */ - ret =3D sdram->bcr[3]; + ret =3D sdram->bank[3].bcr; break; case 0x80: /* SDRAM_TR */ ret =3D -1; /* ? */ @@ -358,13 +354,16 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq= , int nbanks, int do_init) { ppc4xx_sdram_t *sdram; + int i; =20 sdram =3D g_new0(ppc4xx_sdram_t, 1); sdram->irq =3D irq; sdram->nbanks =3D nbanks; - sdram->ram_memories =3D ram_memories; - memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr)); - memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr)); + for (i =3D 0; i < nbanks; i++) { + sdram->bank[i].ram =3D ram_memories[i]; + sdram->bank[i].base =3D ram_bases[i]; + sdram->bank[i].size =3D ram_sizes[i]; + } qemu_register_reset(&sdram_reset, sdram); ppc_dcr_register(env, SDRAM0_CFGADDR, sdram, &dcr_read_sdram, &dcr_write_sdram); diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index a1781afa8e..2af0d60577 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -29,6 +29,14 @@ #include "exec/memory.h" #include "hw/sysbus.h" =20 +typedef struct { + MemoryRegion ram; + MemoryRegion container; /* used for clipping */ + hwaddr base; + hwaddr size; + uint32_t bcr; +} Ppc4xxSdramBank; + void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, MemoryRegion ram_memories[], hwaddr ram_bases[], hwaddr ram_sizes[], --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663094388685536.7964485636397; Tue, 13 Sep 2022 11:39:48 -0700 (PDT) Received: from localhost ([::1]:48816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYAp0-0000Rd-Hz for importer@patchew.org; Tue, 13 Sep 2022 14:39:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAYy-0006Im-OB; Tue, 13 Sep 2022 14:23:12 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:15175) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAYu-0007c5-Ja; Tue, 13 Sep 2022 14:23:11 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 1C5CA74637E; Tue, 13 Sep 2022 20:23:04 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id C494774633E; Tue, 13 Sep 2022 20:23:03 +0200 (CEST) Message-Id: <554b4cde6c026bb7ba4bfbaa6d3e1e6019b40409.1663092335.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 03/18] ppc4xx_sdram: Get rid of the init RAM hack MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:03 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663094389521100001 Content-Type: text/plain; charset="utf-8" The do_init parameter of ppc4xx_sdram_init() is used to map memory regions that is normally done by the firmware by programming the SDRAM controller. This is needed when booting a kernel directly from -kernel without a firmware. Do this from board code accesing normal SDRAM controller registers the same way as firmware would do, so we can get rid of this hack. Signed-off-by: BALATON Zoltan --- v2: Fix ref405ep boot with -kernel and U-Boot hw/ppc/ppc405.h | 1 - hw/ppc/ppc405_boards.c | 12 ++++++++++-- hw/ppc/ppc405_uc.c | 4 +--- hw/ppc/ppc440_bamboo.c | 8 +++++++- hw/ppc/ppc440_uc.c | 2 -- hw/ppc/ppc4xx_devs.c | 11 +---------- include/hw/ppc/ppc4xx.h | 8 ++++++-- 7 files changed, 25 insertions(+), 21 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 1e558c7831..756865621b 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -169,7 +169,6 @@ struct Ppc405SoCState { /* Public */ MemoryRegion ram_banks[2]; hwaddr ram_bases[2], ram_sizes[2]; - bool do_dram_init; =20 MemoryRegion *dram_mr; hwaddr ram_size; diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 083f12b23e..bf02a71c6d 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -274,6 +274,7 @@ static void ppc405_init(MachineState *machine) MachineClass *mc =3D MACHINE_GET_CLASS(machine); const char *kernel_filename =3D machine->kernel_filename; MemoryRegion *sysmem =3D get_system_memory(); + CPUPPCState *env; =20 if (machine->ram_size !=3D mc->default_ram_size) { char *sz =3D size_to_str(mc->default_ram_size); @@ -288,12 +289,19 @@ static void ppc405_init(MachineState *machine) machine->ram_size, &error_fatal); object_property_set_link(OBJECT(&ppc405->soc), "dram", OBJECT(machine->ram), &error_abort); - object_property_set_bool(OBJECT(&ppc405->soc), "dram-init", - kernel_filename !=3D NULL, &error_abort); object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333, &error_abort); qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal); =20 + /* Enable SDRAM memory regions */ + /* FIXME This shouldn't be needed with firmware but we lack SPD data */ + env =3D &ppc405->soc.cpu.env; + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) || + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) { + error_report("Could not enable memory regions"); + exit(1); + } + /* allocate and load BIOS */ if (machine->firmware) { MemoryRegion *bios =3D g_new(MemoryRegion, 1); diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 2ca42fdef6..1e02347e57 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1081,8 +1081,7 @@ static void ppc405_soc_realize(DeviceState *dev, Erro= r **errp) s->ram_bases[0], s->ram_sizes[0]); =20 ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1, - s->ram_banks, s->ram_bases, s->ram_sizes, - s->do_dram_init); + s->ram_banks, s->ram_bases, s->ram_sizes); =20 /* External bus controller */ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) { @@ -1160,7 +1159,6 @@ static void ppc405_soc_realize(DeviceState *dev, Erro= r **errp) static Property ppc405_soc_properties[] =3D { DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0), DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 5ec82fa8c2..e3412c4fcd 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -211,7 +211,13 @@ static void bamboo_init(MachineState *machine) ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14), PPC440EP_SDRAM_NR_BANKS, ram_memories, - ram_bases, ram_sizes, 1); + ram_bases, ram_sizes); + /* Enable SDRAM memory regions, this should be done by the firmware */ + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) || + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) { + error_report("couldn't enable memory regions"); + exit(1); + } =20 /* PCI */ dev =3D sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE, diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index db33334e29..6ab0ad7985 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -489,8 +489,6 @@ typedef struct ppc440_sdram_t { } ppc440_sdram_t; =20 enum { - SDRAM0_CFGADDR =3D 0x10, - SDRAM0_CFGDATA, SDRAM_R0BAS =3D 0x40, SDRAM_R1BAS, SDRAM_R2BAS, diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 1226ec4aa9..936d6f77fe 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -56,11 +56,6 @@ struct ppc4xx_sdram_t { qemu_irq irq; }; =20 -enum { - SDRAM0_CFGADDR =3D 0x010, - SDRAM0_CFGDATA =3D 0x011, -}; - /* * XXX: TOFIX: some patches have made this code become inconsistent: * there are type inconsistencies, mixing hwaddr, target_ulong @@ -350,8 +345,7 @@ static void sdram_reset(void *opaque) void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks, MemoryRegion *ram_memories, hwaddr *ram_bases, - hwaddr *ram_sizes, - int do_init) + hwaddr *ram_sizes) { ppc4xx_sdram_t *sdram; int i; @@ -369,9 +363,6 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, = int nbanks, sdram, &dcr_read_sdram, &dcr_write_sdram); ppc_dcr_register(env, SDRAM0_CFGDATA, sdram, &dcr_read_sdram, &dcr_write_sdram); - if (do_init) { - sdram_map_bcr(sdram); - } } =20 /* diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 2af0d60577..a5e6c185af 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -37,6 +37,11 @@ typedef struct { uint32_t bcr; } Ppc4xxSdramBank; =20 +enum { + SDRAM0_CFGADDR =3D 0x010, + SDRAM0_CFGDATA =3D 0x011, +}; + void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, MemoryRegion ram_memories[], hwaddr ram_bases[], hwaddr ram_sizes[], @@ -45,8 +50,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, MemoryRegion ram_memories[], hwaddr *ram_bases, - hwaddr *ram_sizes, - int do_init); + hwaddr *ram_sizes); =20 #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" =20 --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663094346274138.08246023853803; Tue, 13 Sep 2022 11:39:06 -0700 (PDT) Received: from localhost ([::1]:40054 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYAoL-0007ap-68 for importer@patchew.org; Tue, 13 Sep 2022 14:39:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40430) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAYy-0006JC-SY; Tue, 13 Sep 2022 14:23:12 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:15180) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAYu-0007cE-Jl; Tue, 13 Sep 2022 14:23:12 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 1421774637F; Tue, 13 Sep 2022 20:23:05 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id D0B2674633E; Tue, 13 Sep 2022 20:23:04 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 04/18] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks() MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:04 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663094347532100001 Content-Type: text/plain; charset="utf-8" Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead of the separate arrays and adjust ppc4xx_sdram_init() and ppc440_sdram_init() accordingly as well as machines using these. Signed-off-by: BALATON Zoltan --- v2: Use pointer for ram_banks in the prototype of the init funcs as an array of struct seems to confuse gcc 12.2.1 and provoke a warning hw/ppc/ppc405.h | 4 +--- hw/ppc/ppc405_uc.c | 10 +++++----- hw/ppc/ppc440.h | 5 ++--- hw/ppc/ppc440_bamboo.c | 15 ++++++--------- hw/ppc/ppc440_uc.c | 9 ++++----- hw/ppc/ppc4xx_devs.c | 21 +++++++++------------ hw/ppc/sam460ex.c | 15 +++++---------- include/hw/ppc/ppc4xx.h | 9 +++------ 8 files changed, 35 insertions(+), 53 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 756865621b..ca0972b88b 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -167,9 +167,7 @@ struct Ppc405SoCState { DeviceState parent_obj; =20 /* Public */ - MemoryRegion ram_banks[2]; - hwaddr ram_bases[2], ram_sizes[2]; - + Ppc4xxSdramBank ram_banks[2]; MemoryRegion *dram_mr; hwaddr ram_size; =20 diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 1e02347e57..bcbf35bc14 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1074,14 +1074,14 @@ static void ppc405_soc_realize(DeviceState *dev, Er= ror **errp) =20 /* SDRAM controller */ /* XXX 405EP has no ECC interrupt */ - s->ram_bases[0] =3D 0; - s->ram_sizes[0] =3D s->ram_size; - memory_region_init_alias(&s->ram_banks[0], OBJECT(s), + s->ram_banks[0].base =3D 0; + s->ram_banks[0].size =3D s->ram_size; + memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s), "ppc405.sdram0", s->dram_mr, - s->ram_bases[0], s->ram_sizes[0]); + s->ram_banks[0].base, s->ram_banks[0].size); =20 ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1, - s->ram_banks, s->ram_bases, s->ram_sizes); + s->ram_banks); =20 /* External bus controller */ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) { diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h index 7cef936125..e6c905b7d6 100644 --- a/hw/ppc/ppc440.h +++ b/hw/ppc/ppc440.h @@ -11,14 +11,13 @@ #ifndef PPC440_H #define PPC440_H =20 -#include "hw/ppc/ppc.h" +#include "hw/ppc/ppc4xx.h" =20 void ppc4xx_l2sram_init(CPUPPCState *env); void ppc4xx_cpr_init(CPUPPCState *env); void ppc4xx_sdr_init(CPUPPCState *env); void ppc440_sdram_init(CPUPPCState *env, int nbanks, - MemoryRegion *ram_memories, - hwaddr *ram_bases, hwaddr *ram_sizes, + Ppc4xxSdramBank *ram_banks, int do_init); void ppc4xx_ahb_init(CPUPPCState *env); void ppc4xx_dma_init(CPUPPCState *env, int dcr_base); diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index e3412c4fcd..2aac8a3fe9 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -168,9 +168,8 @@ static void bamboo_init(MachineState *machine) unsigned int pci_irq_nrs[4] =3D { 28, 27, 26, 25 }; MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *isa =3D g_new(MemoryRegion, 1); - MemoryRegion *ram_memories =3D g_new(MemoryRegion, PPC440EP_SDRAM_NR_B= ANKS); - hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS] =3D {0}; - hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS] =3D {0}; + Ppc4xxSdramBank *ram_banks =3D g_new0(Ppc4xxSdramBank, + PPC440EP_SDRAM_NR_BANKS); PCIBus *pcibus; PowerPCCPU *cpu; CPUPPCState *env; @@ -205,13 +204,11 @@ static void bamboo_init(MachineState *machine) qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); =20 /* SDRAM controller */ - ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories, - ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes); + ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_banks, + ppc440ep_sdram_bank_sizes); /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0= . */ - ppc4xx_sdram_init(env, - qdev_get_gpio_in(uicdev, 14), - PPC440EP_SDRAM_NR_BANKS, ram_memories, - ram_bases, ram_sizes); + ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14), + PPC440EP_SDRAM_NR_BANKS, ram_banks); /* Enable SDRAM memory regions, this should be done by the firmware */ if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) || ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) { diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 6ab0ad7985..5db59d1190 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -690,8 +690,7 @@ static void sdram_reset(void *opaque) } =20 void ppc440_sdram_init(CPUPPCState *env, int nbanks, - MemoryRegion *ram_memories, - hwaddr *ram_bases, hwaddr *ram_sizes, + Ppc4xxSdramBank *ram_banks, int do_init) { ppc440_sdram_t *sdram; @@ -700,9 +699,9 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks, sdram =3D g_malloc0(sizeof(*sdram)); sdram->nbanks =3D nbanks; for (i =3D 0; i < nbanks; i++) { - sdram->bank[i].ram =3D ram_memories[i]; - sdram->bank[i].base =3D ram_bases[i]; - sdram->bank[i].size =3D ram_sizes[i]; + sdram->bank[i].ram =3D ram_banks[i].ram; + sdram->bank[i].base =3D ram_banks[i].base; + sdram->bank[i].size =3D ram_banks[i].size; } qemu_register_reset(&sdram_reset, sdram); ppc_dcr_register(env, SDRAM0_CFGADDR, diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 936d6f77fe..7bdcbd6fac 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -343,9 +343,7 @@ static void sdram_reset(void *opaque) } =20 void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks, - MemoryRegion *ram_memories, - hwaddr *ram_bases, - hwaddr *ram_sizes) + Ppc4xxSdramBank *ram_banks) { ppc4xx_sdram_t *sdram; int i; @@ -354,9 +352,9 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, = int nbanks, sdram->irq =3D irq; sdram->nbanks =3D nbanks; for (i =3D 0; i < nbanks; i++) { - sdram->bank[i].ram =3D ram_memories[i]; - sdram->bank[i].base =3D ram_bases[i]; - sdram->bank[i].size =3D ram_sizes[i]; + sdram->bank[i].ram =3D ram_banks[i].ram; + sdram->bank[i].base =3D ram_banks[i].base; + sdram->bank[i].size =3D ram_banks[i].size; } qemu_register_reset(&sdram_reset, sdram); ppc_dcr_register(env, SDRAM0_CFGADDR, @@ -376,8 +374,7 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, = int nbanks, * sizes varies by SoC. */ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, - MemoryRegion ram_memories[], - hwaddr ram_bases[], hwaddr ram_sizes[], + Ppc4xxSdramBank ram_banks[], const ram_addr_t sdram_bank_sizes[]) { ram_addr_t size_left =3D memory_region_size(ram); @@ -392,13 +389,13 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_ban= ks, if (bank_size <=3D size_left) { char name[32]; =20 - ram_bases[i] =3D base; - ram_sizes[i] =3D bank_size; + ram_banks[i].base =3D base; + ram_banks[i].size =3D bank_size; base +=3D bank_size; size_left -=3D bank_size; snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); - memory_region_init_alias(&ram_memories[i], NULL, name, ram, - ram_bases[i], ram_sizes[i]); + memory_region_init_alias(&ram_banks[i].ram, NULL, name, ra= m, + ram_banks[i].base, ram_banks[i].s= ize); break; } } diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 850bb3b817..f4c2a693fb 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -73,7 +73,6 @@ #define OPB_FREQ 115000000 #define EBC_FREQ 115000000 #define UART_FREQ 11059200 -#define SDRAM_NR_BANKS 4 =20 /* The SoC could also handle 4 GiB but firmware does not work with that. */ /* Maybe it overflows a signed 32 bit number somewhere? */ @@ -274,9 +273,7 @@ static void sam460ex_init(MachineState *machine) { MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *isa =3D g_new(MemoryRegion, 1); - MemoryRegion *ram_memories =3D g_new(MemoryRegion, SDRAM_NR_BANKS); - hwaddr ram_bases[SDRAM_NR_BANKS] =3D {0}; - hwaddr ram_sizes[SDRAM_NR_BANKS] =3D {0}; + Ppc4xxSdramBank *ram_banks =3D g_new0(Ppc4xxSdramBank, 1); MemoryRegion *l2cache_ram =3D g_new(MemoryRegion, 1); DeviceState *uic[4]; int i; @@ -345,20 +342,18 @@ static void sam460ex_init(MachineState *machine) /* SDRAM controller */ /* put all RAM on first bank because board has one slot * and firmware only checks that */ - ppc4xx_sdram_banks(machine->ram, 1, ram_memories, ram_bases, ram_sizes, - ppc460ex_sdram_bank_sizes); + ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_siz= es); =20 /* FIXME: does 460EX have ECC interrupts? */ - ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories, - ram_bases, ram_sizes, 1); + ppc440_sdram_init(env, 1, ram_banks, 1); =20 /* IIC controllers and devices */ dev =3D sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, qdev_get_gpio_in(uic[0], 2)); i2c =3D PPC4xx_I2C(dev)->bus; /* SPD EEPROM on RAM module */ - spd_data =3D spd_data_generate(ram_sizes[0] < 128 * MiB ? DDR : DDR2, - ram_sizes[0]); + spd_data =3D spd_data_generate(ram_banks->size < 128 * MiB ? DDR : DDR= 2, + ram_banks->size); spd_data[20] =3D 4; /* SO-DIMM module */ smbus_eeprom_init_one(i2c, 0x50, spd_data); /* RTC */ diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index a5e6c185af..5013b8bf3a 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -43,14 +43,11 @@ enum { }; =20 void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, - MemoryRegion ram_memories[], - hwaddr ram_bases[], hwaddr ram_sizes[], + Ppc4xxSdramBank ram_banks[], const ram_addr_t sdram_bank_sizes[]); =20 -void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, - MemoryRegion ram_memories[], - hwaddr *ram_bases, - hwaddr *ram_sizes); +void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks, + Ppc4xxSdramBank *ram_banks); =20 #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" =20 --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663094639571131.96978340771147; Tue, 13 Sep 2022 11:43:59 -0700 (PDT) Received: from localhost ([::1]:58058 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYAt2-0006lh-IX for importer@patchew.org; Tue, 13 Sep 2022 14:43:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40438) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ0-0006MK-Jv; Tue, 13 Sep 2022 14:23:14 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:15207) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAYy-0007co-Ul; Tue, 13 Sep 2022 14:23:14 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 129EB746381; Tue, 13 Sep 2022 20:23:06 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id E162B74633E; Tue, 13 Sep 2022 20:23:05 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 05/18] ppc440_bamboo: Add missing 4 MiB valid memory size MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:05 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663094641047100001 Signed-off-by: BALATON Zoltan Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/ppc440_bamboo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 2aac8a3fe9..2bd5e41140 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -51,7 +51,7 @@ #define PPC440EP_SDRAM_NR_BANKS 4 =20 static const ram_addr_t ppc440ep_sdram_bank_sizes[] =3D { - 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0 + 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0 }; =20 static hwaddr entry; --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663094512066401.1495719998193; Tue, 13 Sep 2022 11:41:52 -0700 (PDT) Received: from localhost ([::1]:41700 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYAr0-0002u9-RJ for importer@patchew.org; Tue, 13 Sep 2022 14:41:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40436) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ0-0006Lx-Ez; Tue, 13 Sep 2022 14:23:14 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:15206) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAYy-0007cm-FI; Tue, 13 Sep 2022 14:23:14 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 3341C746396; Tue, 13 Sep 2022 20:23:07 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id EE57274633E; Tue, 13 Sep 2022 20:23:06 +0200 (CEST) Message-Id: <19af91ba9c33db88b703c5176b1c00c0d1d1d9ac.1663092335.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 06/18] ppc4xx_sdram: Move size check to ppc4xx_sdram_init() MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:06 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663094512907100001 Content-Type: text/plain; charset="utf-8" Instead of checking if memory size is valid in board code move this check to ppc4xx_sdram_init() as this is a restriction imposed by the SDRAM controller. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 2 -- hw/ppc/ppc405_boards.c | 10 ---------- hw/ppc/ppc405_uc.c | 11 ++--------- hw/ppc/ppc440_bamboo.c | 10 +--------- hw/ppc/ppc4xx_devs.c | 14 ++++++-------- include/hw/ppc/ppc4xx.h | 2 +- 6 files changed, 10 insertions(+), 39 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index ca0972b88b..ad54dff542 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -167,9 +167,7 @@ struct Ppc405SoCState { DeviceState parent_obj; =20 /* Public */ - Ppc4xxSdramBank ram_banks[2]; MemoryRegion *dram_mr; - hwaddr ram_size; =20 PowerPCCPU cpu; PPCUIC uic; diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index bf02a71c6d..cdd4e0cb4c 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -271,22 +271,12 @@ static void boot_from_kernel(MachineState *machine, P= owerPCCPU *cpu) static void ppc405_init(MachineState *machine) { Ppc405MachineState *ppc405 =3D PPC405_MACHINE(machine); - MachineClass *mc =3D MACHINE_GET_CLASS(machine); const char *kernel_filename =3D machine->kernel_filename; MemoryRegion *sysmem =3D get_system_memory(); CPUPPCState *env; =20 - if (machine->ram_size !=3D mc->default_ram_size) { - char *sz =3D size_to_str(mc->default_ram_size); - error_report("Invalid RAM size, should be %s", sz); - g_free(sz); - exit(EXIT_FAILURE); - } - object_initialize_child(OBJECT(machine), "soc", &ppc405->soc, TYPE_PPC405_SOC); - object_property_set_uint(OBJECT(&ppc405->soc), "ram-size", - machine->ram_size, &error_fatal); object_property_set_link(OBJECT(&ppc405->soc), "dram", OBJECT(machine->ram), &error_abort); object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333, diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index bcbf35bc14..e1c7188e61 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1073,15 +1073,9 @@ static void ppc405_soc_realize(DeviceState *dev, Err= or **errp) qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT= )); =20 /* SDRAM controller */ - /* XXX 405EP has no ECC interrupt */ - s->ram_banks[0].base =3D 0; - s->ram_banks[0].size =3D s->ram_size; - memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s), - "ppc405.sdram0", s->dram_mr, - s->ram_banks[0].base, s->ram_banks[0].size); - + /* XXX 405EP has no ECC interrupt */ ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1, - s->ram_banks); + s->dram_mr); =20 /* External bus controller */ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) { @@ -1159,7 +1153,6 @@ static void ppc405_soc_realize(DeviceState *dev, Erro= r **errp) static Property ppc405_soc_properties[] =3D { DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 2bd5e41140..9b456f1819 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -50,10 +50,6 @@ =20 #define PPC440EP_SDRAM_NR_BANKS 4 =20 -static const ram_addr_t ppc440ep_sdram_bank_sizes[] =3D { - 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0 -}; - static hwaddr entry; =20 static int bamboo_load_device_tree(hwaddr addr, @@ -168,8 +164,6 @@ static void bamboo_init(MachineState *machine) unsigned int pci_irq_nrs[4] =3D { 28, 27, 26, 25 }; MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *isa =3D g_new(MemoryRegion, 1); - Ppc4xxSdramBank *ram_banks =3D g_new0(Ppc4xxSdramBank, - PPC440EP_SDRAM_NR_BANKS); PCIBus *pcibus; PowerPCCPU *cpu; CPUPPCState *env; @@ -204,11 +198,9 @@ static void bamboo_init(MachineState *machine) qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); =20 /* SDRAM controller */ - ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_banks, - ppc440ep_sdram_bank_sizes); /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0= . */ ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14), - PPC440EP_SDRAM_NR_BANKS, ram_banks); + PPC440EP_SDRAM_NR_BANKS, machine->ram); /* Enable SDRAM memory regions, this should be done by the firmware */ if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) || ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) { diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 7bdcbd6fac..eb3aa97b16 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -41,7 +41,7 @@ typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; struct ppc4xx_sdram_t { uint32_t addr; - int nbanks; + int nbanks; /* Banks to use from the 4, e.g. when board has less slots= */ Ppc4xxSdramBank bank[4]; uint32_t besr0; uint32_t besr1; @@ -343,19 +343,17 @@ static void sdram_reset(void *opaque) } =20 void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks, - Ppc4xxSdramBank *ram_banks) + MemoryRegion *ram) { ppc4xx_sdram_t *sdram; - int i; + const ram_addr_t valid_bank_sizes[] =3D { + 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * M= iB, 0 + }; =20 sdram =3D g_new0(ppc4xx_sdram_t, 1); sdram->irq =3D irq; sdram->nbanks =3D nbanks; - for (i =3D 0; i < nbanks; i++) { - sdram->bank[i].ram =3D ram_banks[i].ram; - sdram->bank[i].base =3D ram_banks[i].base; - sdram->bank[i].size =3D ram_banks[i].size; - } + ppc4xx_sdram_banks(ram, sdram->nbanks, sdram->bank, valid_bank_sizes); qemu_register_reset(&sdram_reset, sdram); ppc_dcr_register(env, SDRAM0_CFGADDR, sdram, &dcr_read_sdram, &dcr_write_sdram); diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 5013b8bf3a..6007a8dd04 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -47,7 +47,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, const ram_addr_t sdram_bank_sizes[]); =20 void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks, - Ppc4xxSdramBank *ram_banks); + MemoryRegion *ram); =20 #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" =20 --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663094617548481.71536004591076; Tue, 13 Sep 2022 11:43:37 -0700 (PDT) Received: from localhost ([::1]:56116 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYAsi-0005d3-Fs for importer@patchew.org; Tue, 13 Sep 2022 14:43:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43952) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ2-0006Rk-Db; Tue, 13 Sep 2022 14:23:16 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:15212) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAYz-0007d7-U1; Tue, 13 Sep 2022 14:23:16 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 3C84B74633E; Tue, 13 Sep 2022 20:23:08 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 042A174763C; Tue, 13 Sep 2022 20:23:08 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 07/18] ppc4xx_sdram: QOM'ify MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:08 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663094619002100001 Change the ppc4xx_sdram model to a QOM class derived from the PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly modelling the DDR SDRAM controller found in the 440EP (used on the bamboo board) but also backward compatible with the older DDR controllers on some 405 SoCs so we also use it for those now. This likely does not cause problems for guests we run as the new features are just not accessed but to model 405 SoC accurately some features may have to be disabled or the model split between 440 and older. Newer SoCs (regardless of their PPC core, e.g. 405EX) may have an updated DDR2 SDRAM controller implemented by the ppc440_sdram model (only partially, enough for the 460EX on the sam460ex) that is not yet QOM'ified in this patch. That is intended to become ppc4xx-sdram-ddr2 when QOM'ified later. Signed-off-by: BALATON Zoltan Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/ppc405.h | 3 +- hw/ppc/ppc405_uc.c | 22 +++++---- hw/ppc/ppc440_bamboo.c | 10 +++-- hw/ppc/ppc4xx_devs.c | 99 ++++++++++++++++++++++------------------- include/hw/ppc/ppc4xx.h | 27 +++++++++-- 5 files changed, 98 insertions(+), 63 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index ad54dff542..9a4312691e 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -167,8 +167,6 @@ struct Ppc405SoCState { DeviceState parent_obj; =20 /* Public */ - MemoryRegion *dram_mr; - PowerPCCPU cpu; PPCUIC uic; Ppc405CpcState cpc; @@ -182,6 +180,7 @@ struct Ppc405SoCState { Ppc405PobState pob; Ppc4xxPlbState plb; Ppc4xxMalState mal; + Ppc4xxSdramDdrState sdram; }; =20 #endif /* PPC405_H */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index e1c7188e61..c973cfb04e 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1016,6 +1016,9 @@ static void ppc405_soc_instance_init(Object *obj) object_initialize_child(obj, "plb", &s->plb, TYPE_PPC4xx_PLB); =20 object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL); + + object_initialize_child(obj, "sdram", &s->sdram, TYPE_PPC4xx_SDRAM_DDR= ); + object_property_add_alias(obj, "dram", OBJECT(&s->sdram), "dram"); } =20 static void ppc405_reset(void *opaque) @@ -1073,9 +1076,17 @@ static void ppc405_soc_realize(DeviceState *dev, Err= or **errp) qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT= )); =20 /* SDRAM controller */ + /* + * We use the 440 DDR SDRAM controller which has more regs and features + * but it's compatible enough for now + */ + object_property_set_int(OBJECT(&s->sdram), "nbanks", 2, &error_abort); + if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->sdram), &s->cpu, errp)) { + return; + } /* XXX 405EP has no ECC interrupt */ - ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1, - s->dram_mr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdram), 0, + qdev_get_gpio_in(DEVICE(&s->uic), 17)); =20 /* External bus controller */ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) { @@ -1150,12 +1161,6 @@ static void ppc405_soc_realize(DeviceState *dev, Err= or **errp) /* Uses UIC IRQs 9, 15, 17 */ } =20 -static Property ppc405_soc_properties[] =3D { - DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION, - MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), -}; - static void ppc405_soc_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -1163,7 +1168,6 @@ static void ppc405_soc_class_init(ObjectClass *oc, vo= id *data) dc->realize =3D ppc405_soc_realize; /* Reason: only works as part of a ppc405 board/machine */ dc->user_creatable =3D false; - device_class_set_props(dc, ppc405_soc_properties); } =20 static const TypeInfo ppc405_types[] =3D { diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 9b456f1819..6052d3a2e0 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -48,8 +48,6 @@ #define PPC440EP_PCI_IO 0xe8000000 #define PPC440EP_PCI_IOLEN 0x00010000 =20 -#define PPC440EP_SDRAM_NR_BANKS 4 - static hwaddr entry; =20 static int bamboo_load_device_tree(hwaddr addr, @@ -198,9 +196,13 @@ static void bamboo_init(MachineState *machine) qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); =20 /* SDRAM controller */ + dev =3D qdev_new(TYPE_PPC4xx_SDRAM_DDR); + object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram), + &error_abort); + ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); + object_unref(OBJECT(dev)); /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0= . */ - ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14), - PPC440EP_SDRAM_NR_BANKS, machine->ram); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(uicdev, 14= )); /* Enable SDRAM memory regions, this should be done by the firmware */ if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) || ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) { diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index eb3aa97b16..375834a52b 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -38,30 +38,12 @@ =20 /*************************************************************************= ****/ /* SDRAM controller */ -typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; -struct ppc4xx_sdram_t { - uint32_t addr; - int nbanks; /* Banks to use from the 4, e.g. when board has less slots= */ - Ppc4xxSdramBank bank[4]; - uint32_t besr0; - uint32_t besr1; - uint32_t bear; - uint32_t cfg; - uint32_t status; - uint32_t rtr; - uint32_t pmit; - uint32_t tr; - uint32_t ecccfg; - uint32_t eccesr; - qemu_irq irq; -}; - /* * XXX: TOFIX: some patches have made this code become inconsistent: * there are type inconsistencies, mixing hwaddr, target_ulong * and uint32_t */ -static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size) +static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size) { uint32_t bcr; =20 @@ -119,7 +101,7 @@ static target_ulong sdram_size(uint32_t bcr) return size; } =20 -static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i, +static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i, uint32_t bcr, int enabled) { if (sdram->bank[i].bcr & 0x00000001) { @@ -145,21 +127,21 @@ static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int = i, } } =20 -static void sdram_map_bcr(ppc4xx_sdram_t *sdram) +static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram) { int i; =20 for (i =3D 0; i < sdram->nbanks; i++) { if (sdram->bank[i].size !=3D 0) { - sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base, - sdram->bank[i].size), 1); + sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base, + sdram->bank[i].size), 1); } else { sdram_set_bcr(sdram, i, 0x00000000, 0); } } } =20 -static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram) +static void sdram_unmap_bcr(Ppc4xxSdramDdrState *sdram) { int i; =20 @@ -171,12 +153,11 @@ static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram) } } =20 -static uint32_t dcr_read_sdram(void *opaque, int dcrn) +static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn) { - ppc4xx_sdram_t *sdram; + Ppc4xxSdramDdrState *sdram =3D opaque; uint32_t ret; =20 - sdram =3D opaque; switch (dcrn) { case SDRAM0_CFGADDR: ret =3D sdram->addr; @@ -239,11 +220,10 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn) return ret; } =20 -static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val) +static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val) { - ppc4xx_sdram_t *sdram; + Ppc4xxSdramDdrState *sdram =3D opaque; =20 - sdram =3D opaque; switch (dcrn) { case SDRAM0_CFGADDR: sdram->addr =3D val; @@ -322,11 +302,10 @@ static void dcr_write_sdram(void *opaque, int dcrn, u= int32_t val) } } =20 -static void sdram_reset(void *opaque) +static void ppc4xx_sdram_ddr_reset(DeviceState *dev) { - ppc4xx_sdram_t *sdram; + Ppc4xxSdramDdrState *sdram =3D PPC4xx_SDRAM_DDR(dev); =20 - sdram =3D opaque; sdram->addr =3D 0x00000000; sdram->bear =3D 0x00000000; sdram->besr0 =3D 0x00000000; /* No error */ @@ -342,23 +321,48 @@ static void sdram_reset(void *opaque) sdram->cfg =3D 0x00800000; } =20 -void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks, - MemoryRegion *ram) +static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp) { - ppc4xx_sdram_t *sdram; + Ppc4xxSdramDdrState *s =3D PPC4xx_SDRAM_DDR(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); const ram_addr_t valid_bank_sizes[] =3D { 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * M= iB, 0 }; =20 - sdram =3D g_new0(ppc4xx_sdram_t, 1); - sdram->irq =3D irq; - sdram->nbanks =3D nbanks; - ppc4xx_sdram_banks(ram, sdram->nbanks, sdram->bank, valid_bank_sizes); - qemu_register_reset(&sdram_reset, sdram); - ppc_dcr_register(env, SDRAM0_CFGADDR, - sdram, &dcr_read_sdram, &dcr_write_sdram); - ppc_dcr_register(env, SDRAM0_CFGDATA, - sdram, &dcr_read_sdram, &dcr_write_sdram); + if (s->nbanks < 1 || s->nbanks > 4) { + error_setg(errp, "Invalid number of RAM banks"); + return; + } + if (!s->dram_mr) { + error_setg(errp, "Missing dram memory region"); + return; + } + ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes); + + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); + + ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR, + s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA, + s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write); +} + +static Property ppc4xx_sdram_ddr_props[] =3D { + DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REG= ION, + MemoryRegion *), + DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc4xx_sdram_ddr_realize; + dc->reset =3D ppc4xx_sdram_ddr_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; + device_class_set_props(dc, ppc4xx_sdram_ddr_props); } =20 /* @@ -948,6 +952,11 @@ static void ppc4xx_dcr_class_init(ObjectClass *oc, voi= d *data) =20 static const TypeInfo ppc4xx_types[] =3D { { + .name =3D TYPE_PPC4xx_SDRAM_DDR, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc4xxSdramDdrState), + .class_init =3D ppc4xx_sdram_ddr_class_init, + }, { .name =3D TYPE_PPC4xx_MAL, .parent =3D TYPE_PPC4xx_DCR_DEVICE, .instance_size =3D sizeof(Ppc4xxMalState), diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 6007a8dd04..20d0cdde8a 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -46,9 +46,6 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, Ppc4xxSdramBank ram_banks[], const ram_addr_t sdram_bank_sizes[]); =20 -void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks, - MemoryRegion *ram); - #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" =20 /* @@ -118,4 +115,28 @@ struct Ppc4xxEbcState { uint32_t cfg; }; =20 +/* SDRAM DDR controller */ +#define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR); +struct Ppc4xxSdramDdrState { + Ppc4xxDcrDeviceState parent_obj; + + MemoryRegion *dram_mr; + uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slot= s */ + Ppc4xxSdramBank bank[4]; + qemu_irq irq; + + uint32_t addr; + uint32_t besr0; + uint32_t besr1; + uint32_t bear; + uint32_t cfg; + uint32_t status; + uint32_t rtr; + uint32_t pmit; + uint32_t tr; + uint32_t ecccfg; + uint32_t eccesr; +}; + #endif /* PPC4XX_H */ --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663094614614800.735118862558; Tue, 13 Sep 2022 11:43:34 -0700 (PDT) Received: from localhost ([::1]:56374 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYAsf-0005Qn-HP for importer@patchew.org; Tue, 13 Sep 2022 14:43:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43950) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ1-0006Q8-O3; Tue, 13 Sep 2022 14:23:15 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:15213) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAYz-0007d8-Ti; Tue, 13 Sep 2022 14:23:15 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 338A2747871; Tue, 13 Sep 2022 20:23:09 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 0F02074763E; Tue, 13 Sep 2022 20:23:09 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 08/18] ppc4xx_sdram: Drop extra zeros for readability MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:09 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663094614879100001 Content-Type: text/plain; charset="utf-8" Constants that are written zero padded for no good reason are hard to read, it's easier to see what is meant if it's just 0 or 1 instead. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc4xx_devs.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 375834a52b..bfe7b2d3a6 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -49,31 +49,31 @@ static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr r= am_size) =20 switch (ram_size) { case 4 * MiB: - bcr =3D 0x00000000; + bcr =3D 0; break; case 8 * MiB: - bcr =3D 0x00020000; + bcr =3D 0x20000; break; case 16 * MiB: - bcr =3D 0x00040000; + bcr =3D 0x40000; break; case 32 * MiB: - bcr =3D 0x00060000; + bcr =3D 0x60000; break; case 64 * MiB: - bcr =3D 0x00080000; + bcr =3D 0x80000; break; case 128 * MiB: - bcr =3D 0x000A0000; + bcr =3D 0xA0000; break; case 256 * MiB: - bcr =3D 0x000C0000; + bcr =3D 0xC0000; break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func_= _, ram_size); - return 0x00000000; + return 0; } bcr |=3D ram_base & 0xFF800000; bcr |=3D 1; @@ -104,7 +104,7 @@ static target_ulong sdram_size(uint32_t bcr) static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i, uint32_t bcr, int enabled) { - if (sdram->bank[i].bcr & 0x00000001) { + if (sdram->bank[i].bcr & 1) { /* Unmap RAM */ trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr), sdram_size(sdram->bank[i].bcr)); @@ -115,7 +115,7 @@ static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, i= nt i, object_unparent(OBJECT(&sdram->bank[i].container)); } sdram->bank[i].bcr =3D bcr & 0xFFDEE001; - if (enabled && (bcr & 0x00000001)) { + if (enabled && (bcr & 1)) { trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr)); memory_region_init(&sdram->bank[i].container, NULL, "sdram-contain= er", sdram_size(bcr)); @@ -136,7 +136,7 @@ static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram) sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base, sdram->bank[i].size), 1); } else { - sdram_set_bcr(sdram, i, 0x00000000, 0); + sdram_set_bcr(sdram, i, 0, 0); } } } @@ -213,7 +213,7 @@ static uint32_t sdram_ddr_dcr_read(void *opaque, int dc= rn) break; default: /* Avoid gcc warning */ - ret =3D 0x00000000; + ret =3D 0; break; } =20 @@ -306,18 +306,18 @@ static void ppc4xx_sdram_ddr_reset(DeviceState *dev) { Ppc4xxSdramDdrState *sdram =3D PPC4xx_SDRAM_DDR(dev); =20 - sdram->addr =3D 0x00000000; - sdram->bear =3D 0x00000000; - sdram->besr0 =3D 0x00000000; /* No error */ - sdram->besr1 =3D 0x00000000; /* No error */ - sdram->cfg =3D 0x00000000; - sdram->ecccfg =3D 0x00000000; /* No ECC */ - sdram->eccesr =3D 0x00000000; /* No error */ + sdram->addr =3D 0; + sdram->bear =3D 0; + sdram->besr0 =3D 0; /* No error */ + sdram->besr1 =3D 0; /* No error */ + sdram->cfg =3D 0; + sdram->ecccfg =3D 0; /* No ECC */ + sdram->eccesr =3D 0; /* No error */ sdram->pmit =3D 0x07C00000; sdram->rtr =3D 0x05F00000; sdram->tr =3D 0x00854009; /* We pre-initialize RAM banks */ - sdram->status =3D 0x00000000; + sdram->status =3D 0; sdram->cfg =3D 0x00800000; } =20 --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663094794925644.8970483712872; Tue, 13 Sep 2022 11:46:34 -0700 (PDT) Received: from localhost ([::1]:56244 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYAvY-0000ry-PC for importer@patchew.org; Tue, 13 Sep 2022 14:46:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43954) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ3-0006TM-1D; Tue, 13 Sep 2022 14:23:17 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:15216) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ0-0007dD-9q; Tue, 13 Sep 2022 14:23:16 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 3E699747DF7; Tue, 13 Sep 2022 20:23:10 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 1A253747644; Tue, 13 Sep 2022 20:23:10 +0200 (CEST) Message-Id: <4229345309c2320430c0649be5b02c8194d207f6.1663092335.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 09/18] ppc440_sdram: Split off map/unmap of sdram banks for later reuse MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:10 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663094796610100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440_uc.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 5db59d1190..01184e717b 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -561,26 +561,33 @@ static uint64_t sdram_size(uint32_t bcr) return size; } =20 +static void sdram_bank_map(Ppc4xxSdramBank *bank) +{ + memory_region_init(&bank->container, NULL, "sdram-container", bank->si= ze); + memory_region_add_subregion(&bank->container, 0, &bank->ram); + memory_region_add_subregion(get_system_memory(), bank->base, + &bank->container); +} + +static void sdram_bank_unmap(Ppc4xxSdramBank *bank) +{ + memory_region_del_subregion(get_system_memory(), &bank->container); + memory_region_del_subregion(&bank->container, &bank->ram); + object_unparent(OBJECT(&bank->container)); +} + static void sdram_set_bcr(ppc440_sdram_t *sdram, int i, uint32_t bcr, int enabled) { if (sdram->bank[i].bcr & 1) { /* First unmap RAM if enabled */ - memory_region_del_subregion(get_system_memory(), - &sdram->bank[i].container); - memory_region_del_subregion(&sdram->bank[i].container, - &sdram->bank[i].ram); - object_unparent(OBJECT(&sdram->bank[i].container)); + sdram_bank_unmap(&sdram->bank[i]); } sdram->bank[i].bcr =3D bcr & 0xffe0ffc1; + sdram->bank[i].base =3D sdram_base(bcr); + sdram->bank[i].size =3D sdram_size(bcr); if (enabled && (bcr & 1)) { - memory_region_init(&sdram->bank[i].container, NULL, "sdram-contain= er", - sdram_size(bcr)); - memory_region_add_subregion(&sdram->bank[i].container, 0, - &sdram->bank[i].ram); - memory_region_add_subregion(get_system_memory(), - sdram_base(bcr), - &sdram->bank[i].container); + sdram_bank_map(&sdram->bank[i]); } } =20 --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663094893926793.3989455537461; Tue, 13 Sep 2022 11:48:13 -0700 (PDT) Received: from localhost ([::1]:54866 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYAxA-0003dX-Gw for importer@patchew.org; Tue, 13 Sep 2022 14:48:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43956) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ3-0006UC-BO; Tue, 13 Sep 2022 14:23:17 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:15215) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ0-0007dC-5U; Tue, 13 Sep 2022 14:23:17 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 610C0747DFA; Tue, 13 Sep 2022 20:23:11 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 22BD8747644; Tue, 13 Sep 2022 20:23:11 +0200 (CEST) Message-Id: <925d4a2e2784ab2b3439678efe5313d9a1de272b.1663092335.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 10/18] ppc440_sdram: Implement enable bit in the DDR2 SDRAM controller MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:11 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663094896021100001 Content-Type: text/plain; charset="utf-8" To allow removing the do_init hack we need to improve the DDR2 SDRAM controller model to handle the enable/disable bit that it ignored so far. Signed-off-by: BALATON Zoltan --- v2: replace 0x08000000 with BIT(27) hw/ppc/ppc440.h | 3 +-- hw/ppc/ppc440_uc.c | 40 +++++++++++++++++++++++++++++++++------- hw/ppc/sam460ex.c | 8 +++++++- 3 files changed, 41 insertions(+), 10 deletions(-) diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h index e6c905b7d6..01d76b8000 100644 --- a/hw/ppc/ppc440.h +++ b/hw/ppc/ppc440.h @@ -17,8 +17,7 @@ void ppc4xx_l2sram_init(CPUPPCState *env); void ppc4xx_cpr_init(CPUPPCState *env); void ppc4xx_sdr_init(CPUPPCState *env); void ppc440_sdram_init(CPUPPCState *env, int nbanks, - Ppc4xxSdramBank *ram_banks, - int do_init); + Ppc4xxSdramBank *ram_banks); void ppc4xx_ahb_init(CPUPPCState *env); void ppc4xx_dma_init(CPUPPCState *env, int dcr_base); void ppc460ex_pcie_init(CPUPPCState *env); diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 01184e717b..b3f56c49b5 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -23,6 +23,7 @@ #include "sysemu/reset.h" #include "ppc440.h" #include "qom/object.h" +#include "trace.h" =20 /*************************************************************************= ****/ /* L2 Cache as SRAM */ @@ -484,6 +485,7 @@ void ppc4xx_sdr_init(CPUPPCState *env) /* SDRAM controller */ typedef struct ppc440_sdram_t { uint32_t addr; + uint32_t mcopt2; int nbanks; Ppc4xxSdramBank bank[4]; } ppc440_sdram_t; @@ -581,12 +583,15 @@ static void sdram_set_bcr(ppc440_sdram_t *sdram, int = i, { if (sdram->bank[i].bcr & 1) { /* First unmap RAM if enabled */ + trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr), + sdram_size(sdram->bank[i].bcr)); sdram_bank_unmap(&sdram->bank[i]); } sdram->bank[i].bcr =3D bcr & 0xffe0ffc1; sdram->bank[i].base =3D sdram_base(bcr); sdram->bank[i].size =3D sdram_size(bcr); if (enabled && (bcr & 1)) { + trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr)); sdram_bank_map(&sdram->bank[i]); } } @@ -596,7 +601,7 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram) int i; =20 for (i =3D 0; i < sdram->nbanks; i++) { - if (sdram->bank[i].size !=3D 0) { + if (sdram->bank[i].size) { sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base, sdram->bank[i].size), 1); } else { @@ -605,6 +610,17 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram) } } =20 +static void sdram_unmap_bcr(ppc440_sdram_t *sdram) +{ + int i; + + for (i =3D 0; i < sdram->nbanks; i++) { + if (sdram->bank[i].size) { + sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0); + } + } +} + static uint32_t dcr_read_sdram(void *opaque, int dcrn) { ppc440_sdram_t *sdram =3D opaque; @@ -636,7 +652,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn) ret =3D 0x80000000; break; case 0x21: /* SDRAM_MCOPT2 */ - ret =3D 0x08000000; + ret =3D sdram->mcopt2; break; case 0x40: /* SDRAM_MB0CF */ ret =3D 0x00008001; @@ -680,6 +696,19 @@ static void dcr_write_sdram(void *opaque, int dcrn, ui= nt32_t val) switch (sdram->addr) { case 0x00: /* B0CR */ break; + case 0x21: /* SDRAM_MCOPT2 */ + if (!(sdram->mcopt2 & BIT(27)) && (val & BIT(27))) { + trace_ppc4xx_sdram_enable("enable"); + /* validate all RAM mappings */ + sdram_map_bcr(sdram); + sdram->mcopt2 |=3D BIT(27); + } else if ((sdram->mcopt2 & BIT(27)) && !(val & BIT(27))) { + trace_ppc4xx_sdram_enable("disable"); + /* invalidate all RAM mappings */ + sdram_unmap_bcr(sdram); + sdram->mcopt2 &=3D ~BIT(27); + } + break; default: break; } @@ -694,11 +723,11 @@ static void sdram_reset(void *opaque) ppc440_sdram_t *sdram =3D opaque; =20 sdram->addr =3D 0; + sdram->mcopt2 =3D 0; } =20 void ppc440_sdram_init(CPUPPCState *env, int nbanks, - Ppc4xxSdramBank *ram_banks, - int do_init) + Ppc4xxSdramBank *ram_banks) { ppc440_sdram_t *sdram; int i; @@ -715,9 +744,6 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks, sdram, &dcr_read_sdram, &dcr_write_sdram); ppc_dcr_register(env, SDRAM0_CFGDATA, sdram, &dcr_read_sdram, &dcr_write_sdram); - if (do_init) { - sdram_map_bcr(sdram); - } =20 ppc_dcr_register(env, SDRAM_R0BAS, sdram, &dcr_read_sdram, &dcr_write_sdram); diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index f4c2a693fb..dac329d482 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -345,7 +345,13 @@ static void sam460ex_init(MachineState *machine) ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_siz= es); =20 /* FIXME: does 460EX have ECC interrupts? */ - ppc440_sdram_init(env, 1, ram_banks, 1); + ppc440_sdram_init(env, 1, ram_banks); + /* Enable SDRAM memory regions as we may boot without firmware */ + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21) || + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000)) { + error_report("Couldn't enable memory regions"); + exit(1); + } =20 /* IIC controllers and devices */ dev =3D sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663094919323149.61725335344192; Tue, 13 Sep 2022 11:48:39 -0700 (PDT) Received: from localhost ([::1]:50992 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYAxa-0004hv-6V for importer@patchew.org; Tue, 13 Sep 2022 14:48:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43960) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ3-0006Uz-N9; Tue, 13 Sep 2022 14:23:17 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:15220) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ0-0007dc-Ew; Tue, 13 Sep 2022 14:23:17 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 6D856747DFD; Tue, 13 Sep 2022 20:23:12 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 2C5D8747644; Tue, 13 Sep 2022 20:23:12 +0200 (CEST) Message-Id: <7a3c5b37e02c76ba2dd63dff5455c046e5d141cd.1663092335.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 11/18] ppc440_sdram: Rename local variable for readibility MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:12 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663094920113100001 Content-Type: text/plain; charset="utf-8" Rename local sdram variable in ppc440_sdram_init to s for readibility. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440_uc.c | 81 ++++++++++++++++++++++---------------------- hw/ppc/ppc4xx_devs.c | 44 ++++++++++++------------ 2 files changed, 63 insertions(+), 62 deletions(-) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index b3f56c49b5..565bfffc22 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -502,7 +502,7 @@ enum { SDRAM_PLBADDUHB =3D 0x50, }; =20 -static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size) +static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size) { uint32_t bcr; =20 @@ -547,12 +547,12 @@ static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram= _size) return bcr; } =20 -static inline hwaddr sdram_base(uint32_t bcr) +static inline hwaddr sdram_ddr2_base(uint32_t bcr) { return (bcr & 0xffe00000) << 2; } =20 -static uint64_t sdram_size(uint32_t bcr) +static uint64_t sdram_ddr2_size(uint32_t bcr) { uint64_t size; int sh; @@ -578,50 +578,51 @@ static void sdram_bank_unmap(Ppc4xxSdramBank *bank) object_unparent(OBJECT(&bank->container)); } =20 -static void sdram_set_bcr(ppc440_sdram_t *sdram, int i, - uint32_t bcr, int enabled) +static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i, + uint32_t bcr, int enabled) { if (sdram->bank[i].bcr & 1) { /* First unmap RAM if enabled */ - trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr), - sdram_size(sdram->bank[i].bcr)); + trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr), + sdram_ddr2_size(sdram->bank[i].bcr)); sdram_bank_unmap(&sdram->bank[i]); } sdram->bank[i].bcr =3D bcr & 0xffe0ffc1; - sdram->bank[i].base =3D sdram_base(bcr); - sdram->bank[i].size =3D sdram_size(bcr); + sdram->bank[i].base =3D sdram_ddr2_base(bcr); + sdram->bank[i].size =3D sdram_ddr2_size(bcr); if (enabled && (bcr & 1)) { - trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr)); + trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr)); sdram_bank_map(&sdram->bank[i]); } } =20 -static void sdram_map_bcr(ppc440_sdram_t *sdram) +static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram) { int i; =20 for (i =3D 0; i < sdram->nbanks; i++) { if (sdram->bank[i].size) { - sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base, + sdram_ddr2_set_bcr(sdram, i, + sdram_ddr2_bcr(sdram->bank[i].base, sdram->bank[i].size), 1); } else { - sdram_set_bcr(sdram, i, 0, 0); + sdram_ddr2_set_bcr(sdram, i, 0, 0); } } } =20 -static void sdram_unmap_bcr(ppc440_sdram_t *sdram) +static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram) { int i; =20 for (i =3D 0; i < sdram->nbanks; i++) { if (sdram->bank[i].size) { - sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0); + sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0); } } } =20 -static uint32_t dcr_read_sdram(void *opaque, int dcrn) +static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn) { ppc440_sdram_t *sdram =3D opaque; uint32_t ret =3D 0; @@ -632,8 +633,8 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn) case SDRAM_R2BAS: case SDRAM_R3BAS: if (sdram->bank[dcrn - SDRAM_R0BAS].size) { - ret =3D sdram_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base, - sdram->bank[dcrn - SDRAM_R0BAS].size); + ret =3D sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base, + sdram->bank[dcrn - SDRAM_R0BAS].size); } break; case SDRAM_CONF1HB: @@ -674,7 +675,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn) return ret; } =20 -static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val) +static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val) { ppc440_sdram_t *sdram =3D opaque; =20 @@ -700,12 +701,12 @@ static void dcr_write_sdram(void *opaque, int dcrn, u= int32_t val) if (!(sdram->mcopt2 & BIT(27)) && (val & BIT(27))) { trace_ppc4xx_sdram_enable("enable"); /* validate all RAM mappings */ - sdram_map_bcr(sdram); + sdram_ddr2_map_bcr(sdram); sdram->mcopt2 |=3D BIT(27); } else if ((sdram->mcopt2 & BIT(27)) && !(val & BIT(27))) { trace_ppc4xx_sdram_enable("disable"); /* invalidate all RAM mappings */ - sdram_unmap_bcr(sdram); + sdram_ddr2_unmap_bcr(sdram); sdram->mcopt2 &=3D ~BIT(27); } break; @@ -718,7 +719,7 @@ static void dcr_write_sdram(void *opaque, int dcrn, uin= t32_t val) } } =20 -static void sdram_reset(void *opaque) +static void sdram_ddr2_reset(void *opaque) { ppc440_sdram_t *sdram =3D opaque; =20 @@ -729,40 +730,40 @@ static void sdram_reset(void *opaque) void ppc440_sdram_init(CPUPPCState *env, int nbanks, Ppc4xxSdramBank *ram_banks) { - ppc440_sdram_t *sdram; + ppc440_sdram_t *s; int i; =20 - sdram =3D g_malloc0(sizeof(*sdram)); - sdram->nbanks =3D nbanks; + s =3D g_malloc0(sizeof(*s)); + s->nbanks =3D nbanks; for (i =3D 0; i < nbanks; i++) { - sdram->bank[i].ram =3D ram_banks[i].ram; - sdram->bank[i].base =3D ram_banks[i].base; - sdram->bank[i].size =3D ram_banks[i].size; + s->bank[i].ram =3D ram_banks[i].ram; + s->bank[i].base =3D ram_banks[i].base; + s->bank[i].size =3D ram_banks[i].size; } - qemu_register_reset(&sdram_reset, sdram); + qemu_register_reset(&sdram_ddr2_reset, s); ppc_dcr_register(env, SDRAM0_CFGADDR, - sdram, &dcr_read_sdram, &dcr_write_sdram); + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); ppc_dcr_register(env, SDRAM0_CFGDATA, - sdram, &dcr_read_sdram, &dcr_write_sdram); + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); =20 ppc_dcr_register(env, SDRAM_R0BAS, - sdram, &dcr_read_sdram, &dcr_write_sdram); + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); ppc_dcr_register(env, SDRAM_R1BAS, - sdram, &dcr_read_sdram, &dcr_write_sdram); + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); ppc_dcr_register(env, SDRAM_R2BAS, - sdram, &dcr_read_sdram, &dcr_write_sdram); + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); ppc_dcr_register(env, SDRAM_R3BAS, - sdram, &dcr_read_sdram, &dcr_write_sdram); + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); ppc_dcr_register(env, SDRAM_CONF1HB, - sdram, &dcr_read_sdram, &dcr_write_sdram); + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); ppc_dcr_register(env, SDRAM_PLBADDULL, - sdram, &dcr_read_sdram, &dcr_write_sdram); + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); ppc_dcr_register(env, SDRAM_CONF1LL, - sdram, &dcr_read_sdram, &dcr_write_sdram); + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); ppc_dcr_register(env, SDRAM_CONFPATHB, - sdram, &dcr_read_sdram, &dcr_write_sdram); + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); ppc_dcr_register(env, SDRAM_PLBADDUHB, - sdram, &dcr_read_sdram, &dcr_write_sdram); + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); } =20 /*************************************************************************= ****/ diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index bfe7b2d3a6..7655967351 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -81,12 +81,12 @@ static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr r= am_size) return bcr; } =20 -static inline hwaddr sdram_base(uint32_t bcr) +static inline hwaddr sdram_ddr_base(uint32_t bcr) { return bcr & 0xFF800000; } =20 -static target_ulong sdram_size(uint32_t bcr) +static target_ulong sdram_ddr_size(uint32_t bcr) { target_ulong size; int sh; @@ -101,13 +101,13 @@ static target_ulong sdram_size(uint32_t bcr) return size; } =20 -static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i, - uint32_t bcr, int enabled) +static void sdram_ddr_set_bcr(Ppc4xxSdramDdrState *sdram, int i, + uint32_t bcr, int enabled) { if (sdram->bank[i].bcr & 1) { /* Unmap RAM */ - trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr), - sdram_size(sdram->bank[i].bcr)); + trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr), + sdram_ddr_size(sdram->bank[i].bcr)); memory_region_del_subregion(get_system_memory(), &sdram->bank[i].container); memory_region_del_subregion(&sdram->bank[i].container, @@ -116,38 +116,38 @@ static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram,= int i, } sdram->bank[i].bcr =3D bcr & 0xFFDEE001; if (enabled && (bcr & 1)) { - trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr)); + trace_ppc4xx_sdram_map(sdram_ddr_base(bcr), sdram_ddr_size(bcr)); memory_region_init(&sdram->bank[i].container, NULL, "sdram-contain= er", - sdram_size(bcr)); + sdram_ddr_size(bcr)); memory_region_add_subregion(&sdram->bank[i].container, 0, &sdram->bank[i].ram); memory_region_add_subregion(get_system_memory(), - sdram_base(bcr), + sdram_ddr_base(bcr), &sdram->bank[i].container); } } =20 -static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram) +static void sdram_ddr_map_bcr(Ppc4xxSdramDdrState *sdram) { int i; =20 for (i =3D 0; i < sdram->nbanks; i++) { if (sdram->bank[i].size !=3D 0) { - sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base, - sdram->bank[i].size), 1); + sdram_ddr_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base, + sdram->bank[i].size)= , 1); } else { - sdram_set_bcr(sdram, i, 0, 0); + sdram_ddr_set_bcr(sdram, i, 0, 0); } } } =20 -static void sdram_unmap_bcr(Ppc4xxSdramDdrState *sdram) +static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram) { int i; =20 for (i =3D 0; i < sdram->nbanks; i++) { - trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr), - sdram_size(sdram->bank[i].bcr)); + trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr), + sdram_ddr_size(sdram->bank[i].bcr)); memory_region_del_subregion(get_system_memory(), &sdram->bank[i].ram); } @@ -244,12 +244,12 @@ static void sdram_ddr_dcr_write(void *opaque, int dcr= n, uint32_t val) if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { trace_ppc4xx_sdram_enable("enable"); /* validate all RAM mappings */ - sdram_map_bcr(sdram); + sdram_ddr_map_bcr(sdram); sdram->status &=3D ~0x80000000; } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { trace_ppc4xx_sdram_enable("disable"); /* invalidate all RAM mappings */ - sdram_unmap_bcr(sdram); + sdram_ddr_unmap_bcr(sdram); sdram->status |=3D 0x80000000; } if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) { @@ -269,16 +269,16 @@ static void sdram_ddr_dcr_write(void *opaque, int dcr= n, uint32_t val) sdram->pmit =3D (val & 0xF8000000) | 0x07C00000; break; case 0x40: /* SDRAM_B0CR */ - sdram_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000); + sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000); break; case 0x44: /* SDRAM_B1CR */ - sdram_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000); + sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000); break; case 0x48: /* SDRAM_B2CR */ - sdram_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000); + sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000); break; case 0x4C: /* SDRAM_B3CR */ - sdram_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000); + sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000); break; case 0x80: /* SDRAM_TR */ sdram->tr =3D val & 0x018FC01F; --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16630950140741016.7428105261615; Tue, 13 Sep 2022 11:50:14 -0700 (PDT) Received: from localhost ([::1]:35916 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYAz6-00004v-2B for importer@patchew.org; Tue, 13 Sep 2022 14:50:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43958) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ3-0006UE-BS; Tue, 13 Sep 2022 14:23:17 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:15222) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ1-0007du-41; Tue, 13 Sep 2022 14:23:17 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 63664747E0F; Tue, 13 Sep 2022 20:23:13 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 39ADA747644; Tue, 13 Sep 2022 20:23:13 +0200 (CEST) Message-Id: <129db1b6c797bc20bb48c85e4461484462e11c71.1663092335.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 12/18] ppc440_sdram: Move RAM size check to ppc440_sdram_init MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:13 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663095014965100001 Content-Type: text/plain; charset="utf-8" Move the check for valid memory sizes from board to sdram controller init. Board now only checks for additional restrictions imposed by firmware then sdram init checks for valid sizes for SoC. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440.h | 4 ++-- hw/ppc/ppc440_uc.c | 15 +++++++-------- hw/ppc/sam460ex.c | 32 +++++++++++++++++--------------- 3 files changed, 26 insertions(+), 25 deletions(-) diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h index 01d76b8000..29f6f14ed7 100644 --- a/hw/ppc/ppc440.h +++ b/hw/ppc/ppc440.h @@ -11,13 +11,13 @@ #ifndef PPC440_H #define PPC440_H =20 -#include "hw/ppc/ppc4xx.h" +#include "hw/ppc/ppc.h" =20 void ppc4xx_l2sram_init(CPUPPCState *env); void ppc4xx_cpr_init(CPUPPCState *env); void ppc4xx_sdr_init(CPUPPCState *env); void ppc440_sdram_init(CPUPPCState *env, int nbanks, - Ppc4xxSdramBank *ram_banks); + MemoryRegion *ram); void ppc4xx_ahb_init(CPUPPCState *env); void ppc4xx_dma_init(CPUPPCState *env, int dcr_base); void ppc460ex_pcie_init(CPUPPCState *env); diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 565bfffc22..f48eba215a 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -486,7 +486,7 @@ void ppc4xx_sdr_init(CPUPPCState *env) typedef struct ppc440_sdram_t { uint32_t addr; uint32_t mcopt2; - int nbanks; + int nbanks; /* Banks to use from the 4, e.g. when board has less slots= */ Ppc4xxSdramBank bank[4]; } ppc440_sdram_t; =20 @@ -728,18 +728,17 @@ static void sdram_ddr2_reset(void *opaque) } =20 void ppc440_sdram_init(CPUPPCState *env, int nbanks, - Ppc4xxSdramBank *ram_banks) + MemoryRegion *ram) { ppc440_sdram_t *s; - int i; + const ram_addr_t valid_bank_sizes[] =3D { + 4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * M= iB, + 32 * MiB, 16 * MiB, 8 * MiB, 0 + }; =20 s =3D g_malloc0(sizeof(*s)); s->nbanks =3D nbanks; - for (i =3D 0; i < nbanks; i++) { - s->bank[i].ram =3D ram_banks[i].ram; - s->bank[i].base =3D ram_banks[i].base; - s->bank[i].size =3D ram_banks[i].size; - } + ppc4xx_sdram_banks(ram, s->nbanks, s->bank, valid_bank_sizes); qemu_register_reset(&sdram_ddr2_reset, s); ppc_dcr_register(env, SDRAM0_CFGADDR, s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index dac329d482..9b850808a3 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -74,13 +74,6 @@ #define EBC_FREQ 115000000 #define UART_FREQ 11059200 =20 -/* The SoC could also handle 4 GiB but firmware does not work with that. */ -/* Maybe it overflows a signed 32 bit number somewhere? */ -static const ram_addr_t ppc460ex_sdram_bank_sizes[] =3D { - 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB, - 32 * MiB, 0 -}; - struct boot_info { uint32_t dt_base; uint32_t dt_size; @@ -273,7 +266,6 @@ static void sam460ex_init(MachineState *machine) { MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *isa =3D g_new(MemoryRegion, 1); - Ppc4xxSdramBank *ram_banks =3D g_new0(Ppc4xxSdramBank, 1); MemoryRegion *l2cache_ram =3D g_new(MemoryRegion, 1); DeviceState *uic[4]; int i; @@ -340,12 +332,22 @@ static void sam460ex_init(MachineState *machine) } =20 /* SDRAM controller */ - /* put all RAM on first bank because board has one slot - * and firmware only checks that */ - ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_siz= es); - + /* The SoC could also handle 4 GiB but firmware does not work with tha= t. */ + if (machine->ram_size > 2 * GiB) { + error_report("Memory over 2 GiB is not supported"); + exit(1); + } + /* Firmware needs at least 64 MiB */ + if (machine->ram_size < 64 * MiB) { + error_report("Memory below 64 MiB is not supported"); + exit(1); + } + /* + * Put all RAM on first bank because board has one slot + * and firmware only checks that + */ + ppc440_sdram_init(env, 1, machine->ram); /* FIXME: does 460EX have ECC interrupts? */ - ppc440_sdram_init(env, 1, ram_banks); /* Enable SDRAM memory regions as we may boot without firmware */ if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21) || ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000)) { @@ -358,8 +360,8 @@ static void sam460ex_init(MachineState *machine) qdev_get_gpio_in(uic[0], 2)); i2c =3D PPC4xx_I2C(dev)->bus; /* SPD EEPROM on RAM module */ - spd_data =3D spd_data_generate(ram_banks->size < 128 * MiB ? DDR : DDR= 2, - ram_banks->size); + spd_data =3D spd_data_generate(machine->ram_size < 128 * MiB ? DDR : D= DR2, + machine->ram_size); spd_data[20] =3D 4; /* SO-DIMM module */ smbus_eeprom_init_one(i2c, 0x50, spd_data); /* RTC */ --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663095029849354.6400799333628; Tue, 13 Sep 2022 11:50:29 -0700 (PDT) Received: from localhost ([::1]:56526 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYAzM-0000q7-Pd for importer@patchew.org; Tue, 13 Sep 2022 14:50:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43962) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ5-0006ZU-Ei; Tue, 13 Sep 2022 14:23:19 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:15227) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ2-0007eO-MZ; Tue, 13 Sep 2022 14:23:19 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 79587747F18; Tue, 13 Sep 2022 20:23:14 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 44B7B747644; Tue, 13 Sep 2022 20:23:14 +0200 (CEST) Message-Id: <409ac7da994edb8061757a3027daea71ca93834b.1663092335.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 13/18] ppc440_sdram: QOM'ify MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:14 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663095030892100001 Change the ppc440_sdram model to a QOM class derived from the PPC4xx-dcr-device and name it ppc4xx-sdram-ddr2. This is mostly modelling the DDR2 SDRAM controller found in the 460EX (used on the sam460ex board). Newer SoCs (regardless of their PPC core, e.g. 405EX) may have this controller but we only emulate enough of it for the sam460ex u-boot firmware. Signed-off-by: BALATON Zoltan Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/ppc440.h | 2 - hw/ppc/ppc440_uc.c | 115 +++++++++++++++++++++++++--------------- hw/ppc/sam460ex.c | 7 ++- include/hw/ppc/ppc4xx.h | 14 +++++ 4 files changed, 91 insertions(+), 47 deletions(-) diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h index 29f6f14ed7..7c24db8504 100644 --- a/hw/ppc/ppc440.h +++ b/hw/ppc/ppc440.h @@ -16,8 +16,6 @@ void ppc4xx_l2sram_init(CPUPPCState *env); void ppc4xx_cpr_init(CPUPPCState *env); void ppc4xx_sdr_init(CPUPPCState *env); -void ppc440_sdram_init(CPUPPCState *env, int nbanks, - MemoryRegion *ram); void ppc4xx_ahb_init(CPUPPCState *env); void ppc4xx_dma_init(CPUPPCState *env, int dcr_base); void ppc460ex_pcie_init(CPUPPCState *env); diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index f48eba215a..114c1a1b1c 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -483,13 +483,6 @@ void ppc4xx_sdr_init(CPUPPCState *env) =20 /*************************************************************************= ****/ /* SDRAM controller */ -typedef struct ppc440_sdram_t { - uint32_t addr; - uint32_t mcopt2; - int nbanks; /* Banks to use from the 4, e.g. when board has less slots= */ - Ppc4xxSdramBank bank[4]; -} ppc440_sdram_t; - enum { SDRAM_R0BAS =3D 0x40, SDRAM_R1BAS, @@ -578,7 +571,7 @@ static void sdram_bank_unmap(Ppc4xxSdramBank *bank) object_unparent(OBJECT(&bank->container)); } =20 -static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i, +static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i, uint32_t bcr, int enabled) { if (sdram->bank[i].bcr & 1) { @@ -596,7 +589,7 @@ static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, i= nt i, } } =20 -static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram) +static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram) { int i; =20 @@ -611,7 +604,7 @@ static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram) } } =20 -static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram) +static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram) { int i; =20 @@ -624,7 +617,7 @@ static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram) =20 static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn) { - ppc440_sdram_t *sdram =3D opaque; + Ppc4xxSdramDdr2State *sdram =3D opaque; uint32_t ret =3D 0; =20 switch (dcrn) { @@ -677,7 +670,7 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int d= crn) =20 static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val) { - ppc440_sdram_t *sdram =3D opaque; + Ppc4xxSdramDdr2State *sdram =3D opaque; =20 switch (dcrn) { case SDRAM_R0BAS: @@ -719,52 +712,86 @@ static void sdram_ddr2_dcr_write(void *opaque, int dc= rn, uint32_t val) } } =20 -static void sdram_ddr2_reset(void *opaque) +static void ppc4xx_sdram_ddr2_reset(DeviceState *dev) { - ppc440_sdram_t *sdram =3D opaque; + Ppc4xxSdramDdr2State *sdram =3D PPC4xx_SDRAM_DDR2(dev); =20 sdram->addr =3D 0; sdram->mcopt2 =3D 0; } =20 -void ppc440_sdram_init(CPUPPCState *env, int nbanks, - MemoryRegion *ram) +static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp) { - ppc440_sdram_t *s; + Ppc4xxSdramDdr2State *s =3D PPC4xx_SDRAM_DDR2(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); const ram_addr_t valid_bank_sizes[] =3D { 4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * M= iB, 32 * MiB, 16 * MiB, 8 * MiB, 0 }; =20 - s =3D g_malloc0(sizeof(*s)); - s->nbanks =3D nbanks; - ppc4xx_sdram_banks(ram, s->nbanks, s->bank, valid_bank_sizes); - qemu_register_reset(&sdram_ddr2_reset, s); - ppc_dcr_register(env, SDRAM0_CFGADDR, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc_dcr_register(env, SDRAM0_CFGDATA, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - - ppc_dcr_register(env, SDRAM_R0BAS, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc_dcr_register(env, SDRAM_R1BAS, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc_dcr_register(env, SDRAM_R2BAS, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc_dcr_register(env, SDRAM_R3BAS, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc_dcr_register(env, SDRAM_CONF1HB, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc_dcr_register(env, SDRAM_PLBADDULL, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc_dcr_register(env, SDRAM_CONF1LL, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc_dcr_register(env, SDRAM_CONFPATHB, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc_dcr_register(env, SDRAM_PLBADDUHB, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + if (s->nbanks < 1 || s->nbanks > 4) { + error_setg(errp, "Invalid number of RAM banks"); + return; + } + if (!s->dram_mr) { + error_setg(errp, "Missing dram memory region"); + return; + } + ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes); + + ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + + ppc4xx_dcr_register(dcr, SDRAM_R0BAS, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_R1BAS, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_R2BAS, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_R3BAS, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_CONF1HB, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_CONF1LL, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); +} + +static Property ppc4xx_sdram_ddr2_props[] =3D { + DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_RE= GION, + MemoryRegion *), + DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc4xx_sdram_ddr2_realize; + dc->reset =3D ppc4xx_sdram_ddr2_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; + device_class_set_props(dc, ppc4xx_sdram_ddr2_props); } =20 +static const TypeInfo ppc4xx_types[] =3D { + { + .name =3D TYPE_PPC4xx_SDRAM_DDR2, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc4xxSdramDdr2State), + .class_init =3D ppc4xx_sdram_ddr2_class_init, + } +}; +DEFINE_TYPES(ppc4xx_types) + /*************************************************************************= ****/ /* PLB to AHB bridge */ enum { diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 9b850808a3..ea06b099b2 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -342,11 +342,16 @@ static void sam460ex_init(MachineState *machine) error_report("Memory below 64 MiB is not supported"); exit(1); } + dev =3D qdev_new(TYPE_PPC4xx_SDRAM_DDR2); + object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram), + &error_abort); /* * Put all RAM on first bank because board has one slot * and firmware only checks that */ - ppc440_sdram_init(env, 1, machine->ram); + object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort); + ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); + object_unref(OBJECT(dev)); /* FIXME: does 460EX have ECC interrupts? */ /* Enable SDRAM memory regions as we may boot without firmware */ if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21) || diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 20d0cdde8a..7d3cfa7ad6 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -139,4 +139,18 @@ struct Ppc4xxSdramDdrState { uint32_t eccesr; }; =20 +/* SDRAM DDR2 controller */ +#define TYPE_PPC4xx_SDRAM_DDR2 "ppc4xx-sdram-ddr2" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdr2State, PPC4xx_SDRAM_DDR2); +struct Ppc4xxSdramDdr2State { + Ppc4xxDcrDeviceState parent_obj; + + MemoryRegion *dram_mr; + uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slot= s */ + Ppc4xxSdramBank bank[4]; + + uint32_t addr; + uint32_t mcopt2; +}; + #endif /* PPC4XX_H */ --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166309528098771.11596772475309; Tue, 13 Sep 2022 11:54:40 -0700 (PDT) Received: from localhost ([::1]:58974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYB3P-0006If-Od for importer@patchew.org; Tue, 13 Sep 2022 14:54:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55328) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZT-00075C-Ou; Tue, 13 Sep 2022 14:23:43 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:15232) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZN-0007eb-QD; Tue, 13 Sep 2022 14:23:43 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 8E9B5747F19; Tue, 13 Sep 2022 20:23:15 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 5A130747644; Tue, 13 Sep 2022 20:23:15 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 14/18] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:15 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663095282872100001 Move the PPC4xx DDR and DDR2 SDRAM contrller models into a new file called ppc4xx_sdram to separate from other device models and put them in one place allowing sharing some code between them. Signed-off-by: BALATON Zoltan --- hw/ppc/meson.build | 3 +- hw/ppc/ppc440_uc.c | 321 ----------------- hw/ppc/ppc4xx_devs.c | 403 --------------------- hw/ppc/ppc4xx_sdram.c | 752 ++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/ppc4xx.h | 34 +- 5 files changed, 771 insertions(+), 742 deletions(-) create mode 100644 hw/ppc/ppc4xx_sdram.c diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index 62801923f3..74720dd1e1 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -59,8 +59,9 @@ ppc_ss.add(when: 'CONFIG_PPC440', if_true: files( 'ppc440_bamboo.c', 'ppc440_pcix.c', 'ppc440_uc.c')) ppc_ss.add(when: 'CONFIG_PPC4XX', if_true: files( + 'ppc4xx_devs.c', 'ppc4xx_pci.c', - 'ppc4xx_devs.c')) + 'ppc4xx_sdram.c')) ppc_ss.add(when: 'CONFIG_SAM460EX', if_true: files('sam460ex.c')) # PReP ppc_ss.add(when: 'CONFIG_PREP', if_true: files('prep.c')) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 114c1a1b1c..651263926e 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -10,20 +10,14 @@ =20 #include "qemu/osdep.h" #include "qemu/units.h" -#include "qemu/error-report.h" #include "qapi/error.h" #include "qemu/log.h" -#include "qemu/module.h" #include "hw/irq.h" -#include "exec/memory.h" #include "hw/ppc/ppc4xx.h" #include "hw/qdev-properties.h" #include "hw/pci/pci.h" -#include "sysemu/block-backend.h" #include "sysemu/reset.h" #include "ppc440.h" -#include "qom/object.h" -#include "trace.h" =20 /*************************************************************************= ****/ /* L2 Cache as SRAM */ @@ -379,10 +373,6 @@ enum { PESDR1_RSTSTA =3D 0x365, }; =20 -#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29) -#define SDR0_DDR0_DDRM_DDR1 0x20000000 -#define SDR0_DDR0_DDRM_DDR2 0x40000000 - static uint32_t dcr_read_sdr(void *opaque, int dcrn) { ppc4xx_sdr_t *sdr =3D opaque; @@ -481,317 +471,6 @@ void ppc4xx_sdr_init(CPUPPCState *env) sdr, &dcr_read_sdr, &dcr_write_sdr); } =20 -/*************************************************************************= ****/ -/* SDRAM controller */ -enum { - SDRAM_R0BAS =3D 0x40, - SDRAM_R1BAS, - SDRAM_R2BAS, - SDRAM_R3BAS, - SDRAM_CONF1HB =3D 0x45, - SDRAM_PLBADDULL =3D 0x4a, - SDRAM_CONF1LL =3D 0x4b, - SDRAM_CONFPATHB =3D 0x4f, - SDRAM_PLBADDUHB =3D 0x50, -}; - -static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size) -{ - uint32_t bcr; - - switch (ram_size) { - case (8 * MiB): - bcr =3D 0xffc0; - break; - case (16 * MiB): - bcr =3D 0xff80; - break; - case (32 * MiB): - bcr =3D 0xff00; - break; - case (64 * MiB): - bcr =3D 0xfe00; - break; - case (128 * MiB): - bcr =3D 0xfc00; - break; - case (256 * MiB): - bcr =3D 0xf800; - break; - case (512 * MiB): - bcr =3D 0xf000; - break; - case (1 * GiB): - bcr =3D 0xe000; - break; - case (2 * GiB): - bcr =3D 0xc000; - break; - case (4 * GiB): - bcr =3D 0x8000; - break; - default: - error_report("invalid RAM size " TARGET_FMT_plx, ram_size); - return 0; - } - bcr |=3D ram_base >> 2 & 0xffe00000; - bcr |=3D 1; - - return bcr; -} - -static inline hwaddr sdram_ddr2_base(uint32_t bcr) -{ - return (bcr & 0xffe00000) << 2; -} - -static uint64_t sdram_ddr2_size(uint32_t bcr) -{ - uint64_t size; - int sh; - - sh =3D 1024 - ((bcr >> 6) & 0x3ff); - size =3D 8 * MiB * sh; - - return size; -} - -static void sdram_bank_map(Ppc4xxSdramBank *bank) -{ - memory_region_init(&bank->container, NULL, "sdram-container", bank->si= ze); - memory_region_add_subregion(&bank->container, 0, &bank->ram); - memory_region_add_subregion(get_system_memory(), bank->base, - &bank->container); -} - -static void sdram_bank_unmap(Ppc4xxSdramBank *bank) -{ - memory_region_del_subregion(get_system_memory(), &bank->container); - memory_region_del_subregion(&bank->container, &bank->ram); - object_unparent(OBJECT(&bank->container)); -} - -static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i, - uint32_t bcr, int enabled) -{ - if (sdram->bank[i].bcr & 1) { - /* First unmap RAM if enabled */ - trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr), - sdram_ddr2_size(sdram->bank[i].bcr)); - sdram_bank_unmap(&sdram->bank[i]); - } - sdram->bank[i].bcr =3D bcr & 0xffe0ffc1; - sdram->bank[i].base =3D sdram_ddr2_base(bcr); - sdram->bank[i].size =3D sdram_ddr2_size(bcr); - if (enabled && (bcr & 1)) { - trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr)); - sdram_bank_map(&sdram->bank[i]); - } -} - -static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram) -{ - int i; - - for (i =3D 0; i < sdram->nbanks; i++) { - if (sdram->bank[i].size) { - sdram_ddr2_set_bcr(sdram, i, - sdram_ddr2_bcr(sdram->bank[i].base, - sdram->bank[i].size), 1); - } else { - sdram_ddr2_set_bcr(sdram, i, 0, 0); - } - } -} - -static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram) -{ - int i; - - for (i =3D 0; i < sdram->nbanks; i++) { - if (sdram->bank[i].size) { - sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0); - } - } -} - -static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn) -{ - Ppc4xxSdramDdr2State *sdram =3D opaque; - uint32_t ret =3D 0; - - switch (dcrn) { - case SDRAM_R0BAS: - case SDRAM_R1BAS: - case SDRAM_R2BAS: - case SDRAM_R3BAS: - if (sdram->bank[dcrn - SDRAM_R0BAS].size) { - ret =3D sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base, - sdram->bank[dcrn - SDRAM_R0BAS].size); - } - break; - case SDRAM_CONF1HB: - case SDRAM_CONF1LL: - case SDRAM_CONFPATHB: - case SDRAM_PLBADDULL: - case SDRAM_PLBADDUHB: - break; - case SDRAM0_CFGADDR: - ret =3D sdram->addr; - break; - case SDRAM0_CFGDATA: - switch (sdram->addr) { - case 0x14: /* SDRAM_MCSTAT (405EX) */ - case 0x1F: - ret =3D 0x80000000; - break; - case 0x21: /* SDRAM_MCOPT2 */ - ret =3D sdram->mcopt2; - break; - case 0x40: /* SDRAM_MB0CF */ - ret =3D 0x00008001; - break; - case 0x7A: /* SDRAM_DLCR */ - ret =3D 0x02000000; - break; - case 0xE1: /* SDR0_DDR0 */ - ret =3D SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; - break; - default: - break; - } - break; - default: - break; - } - - return ret; -} - -static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val) -{ - Ppc4xxSdramDdr2State *sdram =3D opaque; - - switch (dcrn) { - case SDRAM_R0BAS: - case SDRAM_R1BAS: - case SDRAM_R2BAS: - case SDRAM_R3BAS: - case SDRAM_CONF1HB: - case SDRAM_CONF1LL: - case SDRAM_CONFPATHB: - case SDRAM_PLBADDULL: - case SDRAM_PLBADDUHB: - break; - case SDRAM0_CFGADDR: - sdram->addr =3D val; - break; - case SDRAM0_CFGDATA: - switch (sdram->addr) { - case 0x00: /* B0CR */ - break; - case 0x21: /* SDRAM_MCOPT2 */ - if (!(sdram->mcopt2 & BIT(27)) && (val & BIT(27))) { - trace_ppc4xx_sdram_enable("enable"); - /* validate all RAM mappings */ - sdram_ddr2_map_bcr(sdram); - sdram->mcopt2 |=3D BIT(27); - } else if ((sdram->mcopt2 & BIT(27)) && !(val & BIT(27))) { - trace_ppc4xx_sdram_enable("disable"); - /* invalidate all RAM mappings */ - sdram_ddr2_unmap_bcr(sdram); - sdram->mcopt2 &=3D ~BIT(27); - } - break; - default: - break; - } - break; - default: - break; - } -} - -static void ppc4xx_sdram_ddr2_reset(DeviceState *dev) -{ - Ppc4xxSdramDdr2State *sdram =3D PPC4xx_SDRAM_DDR2(dev); - - sdram->addr =3D 0; - sdram->mcopt2 =3D 0; -} - -static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp) -{ - Ppc4xxSdramDdr2State *s =3D PPC4xx_SDRAM_DDR2(dev); - Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); - const ram_addr_t valid_bank_sizes[] =3D { - 4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * M= iB, - 32 * MiB, 16 * MiB, 8 * MiB, 0 - }; - - if (s->nbanks < 1 || s->nbanks > 4) { - error_setg(errp, "Invalid number of RAM banks"); - return; - } - if (!s->dram_mr) { - error_setg(errp, "Missing dram memory region"); - return; - } - ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes); - - ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - - ppc4xx_dcr_register(dcr, SDRAM_R0BAS, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc4xx_dcr_register(dcr, SDRAM_R1BAS, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc4xx_dcr_register(dcr, SDRAM_R2BAS, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc4xx_dcr_register(dcr, SDRAM_R3BAS, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc4xx_dcr_register(dcr, SDRAM_CONF1HB, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc4xx_dcr_register(dcr, SDRAM_CONF1LL, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); - ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB, - s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); -} - -static Property ppc4xx_sdram_ddr2_props[] =3D { - DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_RE= GION, - MemoryRegion *), - DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4), - DEFINE_PROP_END_OF_LIST(), -}; - -static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(oc); - - dc->realize =3D ppc4xx_sdram_ddr2_realize; - dc->reset =3D ppc4xx_sdram_ddr2_reset; - /* Reason: only works as function of a ppc4xx SoC */ - dc->user_creatable =3D false; - device_class_set_props(dc, ppc4xx_sdram_ddr2_props); -} - -static const TypeInfo ppc4xx_types[] =3D { - { - .name =3D TYPE_PPC4xx_SDRAM_DDR2, - .parent =3D TYPE_PPC4xx_DCR_DEVICE, - .instance_size =3D sizeof(Ppc4xxSdramDdr2State), - .class_init =3D ppc4xx_sdram_ddr2_class_init, - } -}; -DEFINE_TYPES(ppc4xx_types) - /*************************************************************************= ****/ /* PLB to AHB bridge */ enum { diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 7655967351..c1d111465d 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -23,408 +23,10 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/units.h" -#include "sysemu/reset.h" #include "cpu.h" -#include "hw/irq.h" -#include "hw/ppc/ppc.h" #include "hw/ppc/ppc4xx.h" #include "hw/qdev-properties.h" -#include "qemu/log.h" -#include "exec/address-spaces.h" -#include "qemu/error-report.h" #include "qapi/error.h" -#include "trace.h" - -/*************************************************************************= ****/ -/* SDRAM controller */ -/* - * XXX: TOFIX: some patches have made this code become inconsistent: - * there are type inconsistencies, mixing hwaddr, target_ulong - * and uint32_t - */ -static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size) -{ - uint32_t bcr; - - switch (ram_size) { - case 4 * MiB: - bcr =3D 0; - break; - case 8 * MiB: - bcr =3D 0x20000; - break; - case 16 * MiB: - bcr =3D 0x40000; - break; - case 32 * MiB: - bcr =3D 0x60000; - break; - case 64 * MiB: - bcr =3D 0x80000; - break; - case 128 * MiB: - bcr =3D 0xA0000; - break; - case 256 * MiB: - bcr =3D 0xC0000; - break; - default: - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func_= _, - ram_size); - return 0; - } - bcr |=3D ram_base & 0xFF800000; - bcr |=3D 1; - - return bcr; -} - -static inline hwaddr sdram_ddr_base(uint32_t bcr) -{ - return bcr & 0xFF800000; -} - -static target_ulong sdram_ddr_size(uint32_t bcr) -{ - target_ulong size; - int sh; - - sh =3D (bcr >> 17) & 0x7; - if (sh =3D=3D 7) { - size =3D -1; - } else { - size =3D (4 * MiB) << sh; - } - - return size; -} - -static void sdram_ddr_set_bcr(Ppc4xxSdramDdrState *sdram, int i, - uint32_t bcr, int enabled) -{ - if (sdram->bank[i].bcr & 1) { - /* Unmap RAM */ - trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr), - sdram_ddr_size(sdram->bank[i].bcr)); - memory_region_del_subregion(get_system_memory(), - &sdram->bank[i].container); - memory_region_del_subregion(&sdram->bank[i].container, - &sdram->bank[i].ram); - object_unparent(OBJECT(&sdram->bank[i].container)); - } - sdram->bank[i].bcr =3D bcr & 0xFFDEE001; - if (enabled && (bcr & 1)) { - trace_ppc4xx_sdram_map(sdram_ddr_base(bcr), sdram_ddr_size(bcr)); - memory_region_init(&sdram->bank[i].container, NULL, "sdram-contain= er", - sdram_ddr_size(bcr)); - memory_region_add_subregion(&sdram->bank[i].container, 0, - &sdram->bank[i].ram); - memory_region_add_subregion(get_system_memory(), - sdram_ddr_base(bcr), - &sdram->bank[i].container); - } -} - -static void sdram_ddr_map_bcr(Ppc4xxSdramDdrState *sdram) -{ - int i; - - for (i =3D 0; i < sdram->nbanks; i++) { - if (sdram->bank[i].size !=3D 0) { - sdram_ddr_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base, - sdram->bank[i].size)= , 1); - } else { - sdram_ddr_set_bcr(sdram, i, 0, 0); - } - } -} - -static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram) -{ - int i; - - for (i =3D 0; i < sdram->nbanks; i++) { - trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr), - sdram_ddr_size(sdram->bank[i].bcr)); - memory_region_del_subregion(get_system_memory(), - &sdram->bank[i].ram); - } -} - -static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn) -{ - Ppc4xxSdramDdrState *sdram =3D opaque; - uint32_t ret; - - switch (dcrn) { - case SDRAM0_CFGADDR: - ret =3D sdram->addr; - break; - case SDRAM0_CFGDATA: - switch (sdram->addr) { - case 0x00: /* SDRAM_BESR0 */ - ret =3D sdram->besr0; - break; - case 0x08: /* SDRAM_BESR1 */ - ret =3D sdram->besr1; - break; - case 0x10: /* SDRAM_BEAR */ - ret =3D sdram->bear; - break; - case 0x20: /* SDRAM_CFG */ - ret =3D sdram->cfg; - break; - case 0x24: /* SDRAM_STATUS */ - ret =3D sdram->status; - break; - case 0x30: /* SDRAM_RTR */ - ret =3D sdram->rtr; - break; - case 0x34: /* SDRAM_PMIT */ - ret =3D sdram->pmit; - break; - case 0x40: /* SDRAM_B0CR */ - ret =3D sdram->bank[0].bcr; - break; - case 0x44: /* SDRAM_B1CR */ - ret =3D sdram->bank[1].bcr; - break; - case 0x48: /* SDRAM_B2CR */ - ret =3D sdram->bank[2].bcr; - break; - case 0x4C: /* SDRAM_B3CR */ - ret =3D sdram->bank[3].bcr; - break; - case 0x80: /* SDRAM_TR */ - ret =3D -1; /* ? */ - break; - case 0x94: /* SDRAM_ECCCFG */ - ret =3D sdram->ecccfg; - break; - case 0x98: /* SDRAM_ECCESR */ - ret =3D sdram->eccesr; - break; - default: /* Error */ - ret =3D -1; - break; - } - break; - default: - /* Avoid gcc warning */ - ret =3D 0; - break; - } - - return ret; -} - -static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val) -{ - Ppc4xxSdramDdrState *sdram =3D opaque; - - switch (dcrn) { - case SDRAM0_CFGADDR: - sdram->addr =3D val; - break; - case SDRAM0_CFGDATA: - switch (sdram->addr) { - case 0x00: /* SDRAM_BESR0 */ - sdram->besr0 &=3D ~val; - break; - case 0x08: /* SDRAM_BESR1 */ - sdram->besr1 &=3D ~val; - break; - case 0x10: /* SDRAM_BEAR */ - sdram->bear =3D val; - break; - case 0x20: /* SDRAM_CFG */ - val &=3D 0xFFE00000; - if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { - trace_ppc4xx_sdram_enable("enable"); - /* validate all RAM mappings */ - sdram_ddr_map_bcr(sdram); - sdram->status &=3D ~0x80000000; - } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { - trace_ppc4xx_sdram_enable("disable"); - /* invalidate all RAM mappings */ - sdram_ddr_unmap_bcr(sdram); - sdram->status |=3D 0x80000000; - } - if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) { - sdram->status |=3D 0x40000000; - } else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) { - sdram->status &=3D ~0x40000000; - } - sdram->cfg =3D val; - break; - case 0x24: /* SDRAM_STATUS */ - /* Read-only register */ - break; - case 0x30: /* SDRAM_RTR */ - sdram->rtr =3D val & 0x3FF80000; - break; - case 0x34: /* SDRAM_PMIT */ - sdram->pmit =3D (val & 0xF8000000) | 0x07C00000; - break; - case 0x40: /* SDRAM_B0CR */ - sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000); - break; - case 0x44: /* SDRAM_B1CR */ - sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000); - break; - case 0x48: /* SDRAM_B2CR */ - sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000); - break; - case 0x4C: /* SDRAM_B3CR */ - sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000); - break; - case 0x80: /* SDRAM_TR */ - sdram->tr =3D val & 0x018FC01F; - break; - case 0x94: /* SDRAM_ECCCFG */ - sdram->ecccfg =3D val & 0x00F00000; - break; - case 0x98: /* SDRAM_ECCESR */ - val &=3D 0xFFF0F000; - if (sdram->eccesr =3D=3D 0 && val !=3D 0) { - qemu_irq_raise(sdram->irq); - } else if (sdram->eccesr !=3D 0 && val =3D=3D 0) { - qemu_irq_lower(sdram->irq); - } - sdram->eccesr =3D val; - break; - default: /* Error */ - break; - } - break; - } -} - -static void ppc4xx_sdram_ddr_reset(DeviceState *dev) -{ - Ppc4xxSdramDdrState *sdram =3D PPC4xx_SDRAM_DDR(dev); - - sdram->addr =3D 0; - sdram->bear =3D 0; - sdram->besr0 =3D 0; /* No error */ - sdram->besr1 =3D 0; /* No error */ - sdram->cfg =3D 0; - sdram->ecccfg =3D 0; /* No ECC */ - sdram->eccesr =3D 0; /* No error */ - sdram->pmit =3D 0x07C00000; - sdram->rtr =3D 0x05F00000; - sdram->tr =3D 0x00854009; - /* We pre-initialize RAM banks */ - sdram->status =3D 0; - sdram->cfg =3D 0x00800000; -} - -static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp) -{ - Ppc4xxSdramDdrState *s =3D PPC4xx_SDRAM_DDR(dev); - Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); - const ram_addr_t valid_bank_sizes[] =3D { - 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * M= iB, 0 - }; - - if (s->nbanks < 1 || s->nbanks > 4) { - error_setg(errp, "Invalid number of RAM banks"); - return; - } - if (!s->dram_mr) { - error_setg(errp, "Missing dram memory region"); - return; - } - ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes); - - sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - - ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR, - s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write); - ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA, - s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write); -} - -static Property ppc4xx_sdram_ddr_props[] =3D { - DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REG= ION, - MemoryRegion *), - DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4), - DEFINE_PROP_END_OF_LIST(), -}; - -static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(oc); - - dc->realize =3D ppc4xx_sdram_ddr_realize; - dc->reset =3D ppc4xx_sdram_ddr_reset; - /* Reason: only works as function of a ppc4xx SoC */ - dc->user_creatable =3D false; - device_class_set_props(dc, ppc4xx_sdram_ddr_props); -} - -/* - * Split RAM between SDRAM banks. - * - * sdram_bank_sizes[] must be in descending order, that is sizes[i] > size= s[i+1] - * and must be 0-terminated. - * - * The 4xx SDRAM controller supports a small number of banks, and each bank - * must be one of a small set of sizes. The number of banks and the suppor= ted - * sizes varies by SoC. - */ -void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, - Ppc4xxSdramBank ram_banks[], - const ram_addr_t sdram_bank_sizes[]) -{ - ram_addr_t size_left =3D memory_region_size(ram); - ram_addr_t base =3D 0; - ram_addr_t bank_size; - int i; - int j; - - for (i =3D 0; i < nr_banks; i++) { - for (j =3D 0; sdram_bank_sizes[j] !=3D 0; j++) { - bank_size =3D sdram_bank_sizes[j]; - if (bank_size <=3D size_left) { - char name[32]; - - ram_banks[i].base =3D base; - ram_banks[i].size =3D bank_size; - base +=3D bank_size; - size_left -=3D bank_size; - snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); - memory_region_init_alias(&ram_banks[i].ram, NULL, name, ra= m, - ram_banks[i].base, ram_banks[i].s= ize); - break; - } - } - if (!size_left) { - /* No need to use the remaining banks. */ - break; - } - } - - if (size_left) { - ram_addr_t used_size =3D memory_region_size(ram) - size_left; - GString *s =3D g_string_new(NULL); - - for (i =3D 0; sdram_bank_sizes[i]; i++) { - g_string_append_printf(s, "%" PRIi64 "%s", - sdram_bank_sizes[i] / MiB, - sdram_bank_sizes[i + 1] ? ", " : ""); - } - error_report("at most %d bank%s of %s MiB each supported", - nr_banks, nr_banks =3D=3D 1 ? "" : "s", s->str); - error_printf("Possible valid RAM size: %" PRIi64 " MiB\n", - used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB); - - g_string_free(s, true); - exit(EXIT_FAILURE); - } -} =20 /*************************************************************************= ****/ /* MAL */ @@ -952,11 +554,6 @@ static void ppc4xx_dcr_class_init(ObjectClass *oc, voi= d *data) =20 static const TypeInfo ppc4xx_types[] =3D { { - .name =3D TYPE_PPC4xx_SDRAM_DDR, - .parent =3D TYPE_PPC4xx_DCR_DEVICE, - .instance_size =3D sizeof(Ppc4xxSdramDdrState), - .class_init =3D ppc4xx_sdram_ddr_class_init, - }, { .name =3D TYPE_PPC4xx_MAL, .parent =3D TYPE_PPC4xx_DCR_DEVICE, .instance_size =3D sizeof(Ppc4xxMalState), diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c new file mode 100644 index 0000000000..bc28d69a26 --- /dev/null +++ b/hw/ppc/ppc4xx_sdram.c @@ -0,0 +1,752 @@ +/* + * QEMU PowerPC 4xx embedded processors SDRAM controller emulation + * + * DDR SDRAM controller: + * Copyright (c) 2007 Jocelyn Mayer + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + * + * DDR2 SDRAM controller: + * Copyright (c) 2012 Fran=C3=A7ois Revol + * Copyright (c) 2016-2019 BALATON Zoltan + * + * This work is licensed under the GNU GPL license version 2 or later. + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "exec/address-spaces.h" /* get_system_memory() */ +#include "exec/cpu-defs.h" /* target_ulong */ +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "hw/ppc/ppc4xx.h" +#include "trace.h" + +/*************************************************************************= ****/ +/* Shared functions */ + +/* + * Split RAM between SDRAM banks. + * + * sdram_bank_sizes[] must be in descending order, that is sizes[i] > size= s[i+1] + * and must be 0-terminated. + * + * The 4xx SDRAM controller supports a small number of banks, and each bank + * must be one of a small set of sizes. The number of banks and the suppor= ted + * sizes varies by SoC. + */ +static void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, + Ppc4xxSdramBank ram_banks[], + const ram_addr_t sdram_bank_sizes[]) +{ + ram_addr_t size_left =3D memory_region_size(ram); + ram_addr_t base =3D 0; + ram_addr_t bank_size; + int i; + int j; + + for (i =3D 0; i < nr_banks; i++) { + for (j =3D 0; sdram_bank_sizes[j] !=3D 0; j++) { + bank_size =3D sdram_bank_sizes[j]; + if (bank_size <=3D size_left) { + char name[32]; + + ram_banks[i].base =3D base; + ram_banks[i].size =3D bank_size; + base +=3D bank_size; + size_left -=3D bank_size; + snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); + memory_region_init_alias(&ram_banks[i].ram, NULL, name, ra= m, + ram_banks[i].base, ram_banks[i].s= ize); + break; + } + } + if (!size_left) { + /* No need to use the remaining banks. */ + break; + } + } + + if (size_left) { + ram_addr_t used_size =3D memory_region_size(ram) - size_left; + GString *s =3D g_string_new(NULL); + + for (i =3D 0; sdram_bank_sizes[i]; i++) { + g_string_append_printf(s, "%" PRIi64 "%s", + sdram_bank_sizes[i] / MiB, + sdram_bank_sizes[i + 1] ? ", " : ""); + } + error_report("at most %d bank%s of %s MiB each supported", + nr_banks, nr_banks =3D=3D 1 ? "" : "s", s->str); + error_printf("Possible valid RAM size: %" PRIi64 " MiB\n", + used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB); + + g_string_free(s, true); + exit(EXIT_FAILURE); + } +} + +static void sdram_bank_map(Ppc4xxSdramBank *bank) +{ + memory_region_init(&bank->container, NULL, "sdram-container", bank->si= ze); + memory_region_add_subregion(&bank->container, 0, &bank->ram); + memory_region_add_subregion(get_system_memory(), bank->base, + &bank->container); +} + +static void sdram_bank_unmap(Ppc4xxSdramBank *bank) +{ + memory_region_del_subregion(get_system_memory(), &bank->container); + memory_region_del_subregion(&bank->container, &bank->ram); + object_unparent(OBJECT(&bank->container)); +} + +/*************************************************************************= ****/ +/* DDR SDRAM controller */ +/* + * XXX: TOFIX: some patches have made this code become inconsistent: + * there are type inconsistencies, mixing hwaddr, target_ulong + * and uint32_t + */ +static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size) +{ + uint32_t bcr; + + switch (ram_size) { + case 4 * MiB: + bcr =3D 0; + break; + case 8 * MiB: + bcr =3D 0x20000; + break; + case 16 * MiB: + bcr =3D 0x40000; + break; + case 32 * MiB: + bcr =3D 0x60000; + break; + case 64 * MiB: + bcr =3D 0x80000; + break; + case 128 * MiB: + bcr =3D 0xA0000; + break; + case 256 * MiB: + bcr =3D 0xC0000; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func_= _, + ram_size); + return 0; + } + bcr |=3D ram_base & 0xFF800000; + bcr |=3D 1; + + return bcr; +} + +static inline hwaddr sdram_ddr_base(uint32_t bcr) +{ + return bcr & 0xFF800000; +} + +static target_ulong sdram_ddr_size(uint32_t bcr) +{ + target_ulong size; + int sh; + + sh =3D (bcr >> 17) & 0x7; + if (sh =3D=3D 7) { + size =3D -1; + } else { + size =3D (4 * MiB) << sh; + } + + return size; +} + +static void sdram_ddr_set_bcr(Ppc4xxSdramDdrState *sdram, int i, + uint32_t bcr, int enabled) +{ + if (sdram->bank[i].bcr & 1) { + /* Unmap RAM */ + trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr), + sdram_ddr_size(sdram->bank[i].bcr)); + memory_region_del_subregion(get_system_memory(), + &sdram->bank[i].container); + memory_region_del_subregion(&sdram->bank[i].container, + &sdram->bank[i].ram); + object_unparent(OBJECT(&sdram->bank[i].container)); + } + sdram->bank[i].bcr =3D bcr & 0xFFDEE001; + if (enabled && (bcr & 1)) { + trace_ppc4xx_sdram_map(sdram_ddr_base(bcr), sdram_ddr_size(bcr)); + memory_region_init(&sdram->bank[i].container, NULL, "sdram-contain= er", + sdram_ddr_size(bcr)); + memory_region_add_subregion(&sdram->bank[i].container, 0, + &sdram->bank[i].ram); + memory_region_add_subregion(get_system_memory(), + sdram_ddr_base(bcr), + &sdram->bank[i].container); + } +} + +static void sdram_ddr_map_bcr(Ppc4xxSdramDdrState *sdram) +{ + int i; + + for (i =3D 0; i < sdram->nbanks; i++) { + if (sdram->bank[i].size !=3D 0) { + sdram_ddr_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base, + sdram->bank[i].size)= , 1); + } else { + sdram_ddr_set_bcr(sdram, i, 0, 0); + } + } +} + +static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram) +{ + int i; + + for (i =3D 0; i < sdram->nbanks; i++) { + trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr), + sdram_ddr_size(sdram->bank[i].bcr)); + memory_region_del_subregion(get_system_memory(), + &sdram->bank[i].ram); + } +} + +static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn) +{ + Ppc4xxSdramDdrState *sdram =3D opaque; + uint32_t ret; + + switch (dcrn) { + case SDRAM0_CFGADDR: + ret =3D sdram->addr; + break; + case SDRAM0_CFGDATA: + switch (sdram->addr) { + case 0x00: /* SDRAM_BESR0 */ + ret =3D sdram->besr0; + break; + case 0x08: /* SDRAM_BESR1 */ + ret =3D sdram->besr1; + break; + case 0x10: /* SDRAM_BEAR */ + ret =3D sdram->bear; + break; + case 0x20: /* SDRAM_CFG */ + ret =3D sdram->cfg; + break; + case 0x24: /* SDRAM_STATUS */ + ret =3D sdram->status; + break; + case 0x30: /* SDRAM_RTR */ + ret =3D sdram->rtr; + break; + case 0x34: /* SDRAM_PMIT */ + ret =3D sdram->pmit; + break; + case 0x40: /* SDRAM_B0CR */ + ret =3D sdram->bank[0].bcr; + break; + case 0x44: /* SDRAM_B1CR */ + ret =3D sdram->bank[1].bcr; + break; + case 0x48: /* SDRAM_B2CR */ + ret =3D sdram->bank[2].bcr; + break; + case 0x4C: /* SDRAM_B3CR */ + ret =3D sdram->bank[3].bcr; + break; + case 0x80: /* SDRAM_TR */ + ret =3D -1; /* ? */ + break; + case 0x94: /* SDRAM_ECCCFG */ + ret =3D sdram->ecccfg; + break; + case 0x98: /* SDRAM_ECCESR */ + ret =3D sdram->eccesr; + break; + default: /* Error */ + ret =3D -1; + break; + } + break; + default: + /* Avoid gcc warning */ + ret =3D 0; + break; + } + + return ret; +} + +static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val) +{ + Ppc4xxSdramDdrState *sdram =3D opaque; + + switch (dcrn) { + case SDRAM0_CFGADDR: + sdram->addr =3D val; + break; + case SDRAM0_CFGDATA: + switch (sdram->addr) { + case 0x00: /* SDRAM_BESR0 */ + sdram->besr0 &=3D ~val; + break; + case 0x08: /* SDRAM_BESR1 */ + sdram->besr1 &=3D ~val; + break; + case 0x10: /* SDRAM_BEAR */ + sdram->bear =3D val; + break; + case 0x20: /* SDRAM_CFG */ + val &=3D 0xFFE00000; + if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { + trace_ppc4xx_sdram_enable("enable"); + /* validate all RAM mappings */ + sdram_ddr_map_bcr(sdram); + sdram->status &=3D ~0x80000000; + } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { + trace_ppc4xx_sdram_enable("disable"); + /* invalidate all RAM mappings */ + sdram_ddr_unmap_bcr(sdram); + sdram->status |=3D 0x80000000; + } + if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) { + sdram->status |=3D 0x40000000; + } else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) { + sdram->status &=3D ~0x40000000; + } + sdram->cfg =3D val; + break; + case 0x24: /* SDRAM_STATUS */ + /* Read-only register */ + break; + case 0x30: /* SDRAM_RTR */ + sdram->rtr =3D val & 0x3FF80000; + break; + case 0x34: /* SDRAM_PMIT */ + sdram->pmit =3D (val & 0xF8000000) | 0x07C00000; + break; + case 0x40: /* SDRAM_B0CR */ + sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000); + break; + case 0x44: /* SDRAM_B1CR */ + sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000); + break; + case 0x48: /* SDRAM_B2CR */ + sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000); + break; + case 0x4C: /* SDRAM_B3CR */ + sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000); + break; + case 0x80: /* SDRAM_TR */ + sdram->tr =3D val & 0x018FC01F; + break; + case 0x94: /* SDRAM_ECCCFG */ + sdram->ecccfg =3D val & 0x00F00000; + break; + case 0x98: /* SDRAM_ECCESR */ + val &=3D 0xFFF0F000; + if (sdram->eccesr =3D=3D 0 && val !=3D 0) { + qemu_irq_raise(sdram->irq); + } else if (sdram->eccesr !=3D 0 && val =3D=3D 0) { + qemu_irq_lower(sdram->irq); + } + sdram->eccesr =3D val; + break; + default: /* Error */ + break; + } + break; + } +} + +static void ppc4xx_sdram_ddr_reset(DeviceState *dev) +{ + Ppc4xxSdramDdrState *sdram =3D PPC4xx_SDRAM_DDR(dev); + + sdram->addr =3D 0; + sdram->bear =3D 0; + sdram->besr0 =3D 0; /* No error */ + sdram->besr1 =3D 0; /* No error */ + sdram->cfg =3D 0; + sdram->ecccfg =3D 0; /* No ECC */ + sdram->eccesr =3D 0; /* No error */ + sdram->pmit =3D 0x07C00000; + sdram->rtr =3D 0x05F00000; + sdram->tr =3D 0x00854009; + /* We pre-initialize RAM banks */ + sdram->status =3D 0; + sdram->cfg =3D 0x00800000; +} + +static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp) +{ + Ppc4xxSdramDdrState *s =3D PPC4xx_SDRAM_DDR(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); + const ram_addr_t valid_bank_sizes[] =3D { + 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * M= iB, 0 + }; + + if (s->nbanks < 1 || s->nbanks > 4) { + error_setg(errp, "Invalid number of RAM banks"); + return; + } + if (!s->dram_mr) { + error_setg(errp, "Missing dram memory region"); + return; + } + ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes); + + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); + + ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR, + s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA, + s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write); +} + +static Property ppc4xx_sdram_ddr_props[] =3D { + DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REG= ION, + MemoryRegion *), + DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc4xx_sdram_ddr_realize; + dc->reset =3D ppc4xx_sdram_ddr_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; + device_class_set_props(dc, ppc4xx_sdram_ddr_props); +} + +/*************************************************************************= ****/ +/* DDR2 SDRAM controller */ +enum { + SDRAM_R0BAS =3D 0x40, + SDRAM_R1BAS, + SDRAM_R2BAS, + SDRAM_R3BAS, + SDRAM_CONF1HB =3D 0x45, + SDRAM_PLBADDULL =3D 0x4a, + SDRAM_CONF1LL =3D 0x4b, + SDRAM_CONFPATHB =3D 0x4f, + SDRAM_PLBADDUHB =3D 0x50, +}; + +static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size) +{ + uint32_t bcr; + + switch (ram_size) { + case 8 * MiB: + bcr =3D 0xffc0; + break; + case 16 * MiB: + bcr =3D 0xff80; + break; + case 32 * MiB: + bcr =3D 0xff00; + break; + case 64 * MiB: + bcr =3D 0xfe00; + break; + case 128 * MiB: + bcr =3D 0xfc00; + break; + case 256 * MiB: + bcr =3D 0xf800; + break; + case 512 * MiB: + bcr =3D 0xf000; + break; + case 1 * GiB: + bcr =3D 0xe000; + break; + case 2 * GiB: + bcr =3D 0xc000; + break; + case 4 * GiB: + bcr =3D 0x8000; + break; + default: + error_report("invalid RAM size " TARGET_FMT_plx, ram_size); + return 0; + } + bcr |=3D ram_base >> 2 & 0xffe00000; + bcr |=3D 1; + + return bcr; +} + +static inline hwaddr sdram_ddr2_base(uint32_t bcr) +{ + return (bcr & 0xffe00000) << 2; +} + +static uint64_t sdram_ddr2_size(uint32_t bcr) +{ + uint64_t size; + int sh; + + sh =3D 1024 - ((bcr >> 6) & 0x3ff); + size =3D 8 * MiB * sh; + + return size; +} + +static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i, + uint32_t bcr, int enabled) +{ + if (sdram->bank[i].bcr & 1) { + /* First unmap RAM if enabled */ + trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr), + sdram_ddr2_size(sdram->bank[i].bcr)); + sdram_bank_unmap(&sdram->bank[i]); + } + sdram->bank[i].bcr =3D bcr & 0xffe0ffc1; + sdram->bank[i].base =3D sdram_ddr2_base(bcr); + sdram->bank[i].size =3D sdram_ddr2_size(bcr); + if (enabled && (bcr & 1)) { + trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr)); + sdram_bank_map(&sdram->bank[i]); + } +} + +static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram) +{ + int i; + + for (i =3D 0; i < sdram->nbanks; i++) { + if (sdram->bank[i].size) { + sdram_ddr2_set_bcr(sdram, i, + sdram_ddr2_bcr(sdram->bank[i].base, + sdram->bank[i].size), 1); + } else { + sdram_ddr2_set_bcr(sdram, i, 0, 0); + } + } +} + +static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram) +{ + int i; + + for (i =3D 0; i < sdram->nbanks; i++) { + if (sdram->bank[i].size) { + sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0); + } + } +} + +static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn) +{ + Ppc4xxSdramDdr2State *sdram =3D opaque; + uint32_t ret =3D 0; + + switch (dcrn) { + case SDRAM_R0BAS: + case SDRAM_R1BAS: + case SDRAM_R2BAS: + case SDRAM_R3BAS: + if (sdram->bank[dcrn - SDRAM_R0BAS].size) { + ret =3D sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base, + sdram->bank[dcrn - SDRAM_R0BAS].size); + } + break; + case SDRAM_CONF1HB: + case SDRAM_CONF1LL: + case SDRAM_CONFPATHB: + case SDRAM_PLBADDULL: + case SDRAM_PLBADDUHB: + break; + case SDRAM0_CFGADDR: + ret =3D sdram->addr; + break; + case SDRAM0_CFGDATA: + switch (sdram->addr) { + case 0x14: /* SDRAM_MCSTAT (405EX) */ + case 0x1F: + ret =3D 0x80000000; + break; + case 0x21: /* SDRAM_MCOPT2 */ + ret =3D sdram->mcopt2; + break; + case 0x40: /* SDRAM_MB0CF */ + ret =3D 0x00008001; + break; + case 0x7A: /* SDRAM_DLCR */ + ret =3D 0x02000000; + break; + case 0xE1: /* SDR0_DDR0 */ + ret =3D SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; + break; + default: + break; + } + break; + default: + break; + } + + return ret; +} + +static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val) +{ + Ppc4xxSdramDdr2State *sdram =3D opaque; + + switch (dcrn) { + case SDRAM_R0BAS: + case SDRAM_R1BAS: + case SDRAM_R2BAS: + case SDRAM_R3BAS: + case SDRAM_CONF1HB: + case SDRAM_CONF1LL: + case SDRAM_CONFPATHB: + case SDRAM_PLBADDULL: + case SDRAM_PLBADDUHB: + break; + case SDRAM0_CFGADDR: + sdram->addr =3D val; + break; + case SDRAM0_CFGDATA: + switch (sdram->addr) { + case 0x00: /* B0CR */ + break; + case 0x21: /* SDRAM_MCOPT2 */ + if (!(sdram->mcopt2 & BIT(27)) && (val & BIT(27))) { + trace_ppc4xx_sdram_enable("enable"); + /* validate all RAM mappings */ + sdram_ddr2_map_bcr(sdram); + sdram->mcopt2 |=3D BIT(27); + } else if ((sdram->mcopt2 & BIT(27)) && !(val & BIT(27))) { + trace_ppc4xx_sdram_enable("disable"); + /* invalidate all RAM mappings */ + sdram_ddr2_unmap_bcr(sdram); + sdram->mcopt2 &=3D ~BIT(27); + } + break; + default: + break; + } + break; + default: + break; + } +} + +static void ppc4xx_sdram_ddr2_reset(DeviceState *dev) +{ + Ppc4xxSdramDdr2State *sdram =3D PPC4xx_SDRAM_DDR2(dev); + + sdram->addr =3D 0; + sdram->mcopt2 =3D 0; +} + +static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp) +{ + Ppc4xxSdramDdr2State *s =3D PPC4xx_SDRAM_DDR2(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); + const ram_addr_t valid_bank_sizes[] =3D { + 4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * M= iB, + 32 * MiB, 16 * MiB, 8 * MiB, 0 + }; + + if (s->nbanks < 1 || s->nbanks > 4) { + error_setg(errp, "Invalid number of RAM banks"); + return; + } + if (!s->dram_mr) { + error_setg(errp, "Missing dram memory region"); + return; + } + ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes); + + ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + + ppc4xx_dcr_register(dcr, SDRAM_R0BAS, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_R1BAS, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_R2BAS, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_R3BAS, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_CONF1HB, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_CONF1LL, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); + ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB, + s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); +} + +static Property ppc4xx_sdram_ddr2_props[] =3D { + DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_RE= GION, + MemoryRegion *), + DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc4xx_sdram_ddr2_realize; + dc->reset =3D ppc4xx_sdram_ddr2_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; + device_class_set_props(dc, ppc4xx_sdram_ddr2_props); +} + +static const TypeInfo ppc4xx_sdram_types[] =3D { + { + .name =3D TYPE_PPC4xx_SDRAM_DDR, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc4xxSdramDdrState), + .class_init =3D ppc4xx_sdram_ddr_class_init, + }, { + .name =3D TYPE_PPC4xx_SDRAM_DDR2, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc4xxSdramDdr2State), + .class_init =3D ppc4xx_sdram_ddr2_class_init, + } +}; + +DEFINE_TYPES(ppc4xx_sdram_types) diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 7d3cfa7ad6..7216d62882 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -29,23 +29,6 @@ #include "exec/memory.h" #include "hw/sysbus.h" =20 -typedef struct { - MemoryRegion ram; - MemoryRegion container; /* used for clipping */ - hwaddr base; - hwaddr size; - uint32_t bcr; -} Ppc4xxSdramBank; - -enum { - SDRAM0_CFGADDR =3D 0x010, - SDRAM0_CFGDATA =3D 0x011, -}; - -void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, - Ppc4xxSdramBank ram_banks[], - const ram_addr_t sdram_bank_sizes[]); - #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" =20 /* @@ -116,6 +99,23 @@ struct Ppc4xxEbcState { }; =20 /* SDRAM DDR controller */ +typedef struct { + MemoryRegion ram; + MemoryRegion container; /* used for clipping */ + hwaddr base; + hwaddr size; + uint32_t bcr; +} Ppc4xxSdramBank; + +enum { + SDRAM0_CFGADDR =3D 0x010, + SDRAM0_CFGDATA =3D 0x011, +}; + +#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29) +#define SDR0_DDR0_DDRM_DDR1 0x20000000 +#define SDR0_DDR0_DDRM_DDR2 0x40000000 + #define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr" OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR); struct Ppc4xxSdramDdrState { --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663095070669135.44530010772337; Tue, 13 Sep 2022 11:51:10 -0700 (PDT) Received: from localhost ([::1]:38762 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYB01-0001xx-MY for importer@patchew.org; Tue, 13 Sep 2022 14:51:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55326) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZQ-0006vE-0i; Tue, 13 Sep 2022 14:23:40 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:15237) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZO-0007ev-BV; Tue, 13 Sep 2022 14:23:39 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 8F35A747F1B; Tue, 13 Sep 2022 20:23:16 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 667D4747644; Tue, 13 Sep 2022 20:23:16 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 15/18] ppc4xx_sdram: Use hwaddr for memory bank size MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:16 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663095071298100001 This resolves the target_ulong dependency that's clearly wrong and was also noted in a fixme comment. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/ppc/ppc4xx_sdram.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c index bc28d69a26..242e2f4c6e 100644 --- a/hw/ppc/ppc4xx_sdram.c +++ b/hw/ppc/ppc4xx_sdram.c @@ -34,7 +34,6 @@ #include "qapi/error.h" #include "qemu/log.h" #include "exec/address-spaces.h" /* get_system_memory() */ -#include "exec/cpu-defs.h" /* target_ulong */ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "qapi/error.h" @@ -122,11 +121,6 @@ static void sdram_bank_unmap(Ppc4xxSdramBank *bank) =20 /*************************************************************************= ****/ /* DDR SDRAM controller */ -/* - * XXX: TOFIX: some patches have made this code become inconsistent: - * there are type inconsistencies, mixing hwaddr, target_ulong - * and uint32_t - */ static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size) { uint32_t bcr; @@ -170,9 +164,9 @@ static inline hwaddr sdram_ddr_base(uint32_t bcr) return bcr & 0xFF800000; } =20 -static target_ulong sdram_ddr_size(uint32_t bcr) +static hwaddr sdram_ddr_size(uint32_t bcr) { - target_ulong size; + hwaddr size; int sh; =20 sh =3D (bcr >> 17) & 0x7; @@ -513,9 +507,9 @@ static inline hwaddr sdram_ddr2_base(uint32_t bcr) return (bcr & 0xffe00000) << 2; } =20 -static uint64_t sdram_ddr2_size(uint32_t bcr) +static hwaddr sdram_ddr2_size(uint32_t bcr) { - uint64_t size; + hwaddr size; int sh; =20 sh =3D 1024 - ((bcr >> 6) & 0x3ff); --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166309527666673.48007836040631; Tue, 13 Sep 2022 11:54:36 -0700 (PDT) Received: from localhost ([::1]:58968 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYB3L-00065E-Av for importer@patchew.org; Tue, 13 Sep 2022 14:54:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55330) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZU-000762-Jc; Tue, 13 Sep 2022 14:23:44 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:15242) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZP-0007fQ-GB; Tue, 13 Sep 2022 14:23:44 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id A682C747F1C; Tue, 13 Sep 2022 20:23:17 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 71759747644; Tue, 13 Sep 2022 20:23:17 +0200 (CEST) Message-Id: <4bd0b39d4fe2f637556b260eaf81b940926679d4.1663092335.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 16/18] ppc4xx_sdram: Rename local state variable for brevity MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:17 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663095278916100001 Content-Type: text/plain; charset="utf-8" Rename the sdram local state variable to s in dcr read/write functions and reset methods for better readability and to match realize methods. Other places not converted will be changed or removed in subsequent patches. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc4xx_sdram.c | 158 +++++++++++++++++++++--------------------- 1 file changed, 79 insertions(+), 79 deletions(-) diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c index 242e2f4c6e..e36898a906 100644 --- a/hw/ppc/ppc4xx_sdram.c +++ b/hw/ppc/ppc4xx_sdram.c @@ -233,56 +233,56 @@ static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *= sdram) =20 static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn) { - Ppc4xxSdramDdrState *sdram =3D opaque; + Ppc4xxSdramDdrState *s =3D opaque; uint32_t ret; =20 switch (dcrn) { case SDRAM0_CFGADDR: - ret =3D sdram->addr; + ret =3D s->addr; break; case SDRAM0_CFGDATA: - switch (sdram->addr) { + switch (s->addr) { case 0x00: /* SDRAM_BESR0 */ - ret =3D sdram->besr0; + ret =3D s->besr0; break; case 0x08: /* SDRAM_BESR1 */ - ret =3D sdram->besr1; + ret =3D s->besr1; break; case 0x10: /* SDRAM_BEAR */ - ret =3D sdram->bear; + ret =3D s->bear; break; case 0x20: /* SDRAM_CFG */ - ret =3D sdram->cfg; + ret =3D s->cfg; break; case 0x24: /* SDRAM_STATUS */ - ret =3D sdram->status; + ret =3D s->status; break; case 0x30: /* SDRAM_RTR */ - ret =3D sdram->rtr; + ret =3D s->rtr; break; case 0x34: /* SDRAM_PMIT */ - ret =3D sdram->pmit; + ret =3D s->pmit; break; case 0x40: /* SDRAM_B0CR */ - ret =3D sdram->bank[0].bcr; + ret =3D s->bank[0].bcr; break; case 0x44: /* SDRAM_B1CR */ - ret =3D sdram->bank[1].bcr; + ret =3D s->bank[1].bcr; break; case 0x48: /* SDRAM_B2CR */ - ret =3D sdram->bank[2].bcr; + ret =3D s->bank[2].bcr; break; case 0x4C: /* SDRAM_B3CR */ - ret =3D sdram->bank[3].bcr; + ret =3D s->bank[3].bcr; break; case 0x80: /* SDRAM_TR */ ret =3D -1; /* ? */ break; case 0x94: /* SDRAM_ECCCFG */ - ret =3D sdram->ecccfg; + ret =3D s->ecccfg; break; case 0x98: /* SDRAM_ECCESR */ - ret =3D sdram->eccesr; + ret =3D s->eccesr; break; default: /* Error */ ret =3D -1; @@ -300,78 +300,78 @@ static uint32_t sdram_ddr_dcr_read(void *opaque, int = dcrn) =20 static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val) { - Ppc4xxSdramDdrState *sdram =3D opaque; + Ppc4xxSdramDdrState *s =3D opaque; =20 switch (dcrn) { case SDRAM0_CFGADDR: - sdram->addr =3D val; + s->addr =3D val; break; case SDRAM0_CFGDATA: - switch (sdram->addr) { + switch (s->addr) { case 0x00: /* SDRAM_BESR0 */ - sdram->besr0 &=3D ~val; + s->besr0 &=3D ~val; break; case 0x08: /* SDRAM_BESR1 */ - sdram->besr1 &=3D ~val; + s->besr1 &=3D ~val; break; case 0x10: /* SDRAM_BEAR */ - sdram->bear =3D val; + s->bear =3D val; break; case 0x20: /* SDRAM_CFG */ val &=3D 0xFFE00000; - if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { + if (!(s->cfg & 0x80000000) && (val & 0x80000000)) { trace_ppc4xx_sdram_enable("enable"); /* validate all RAM mappings */ - sdram_ddr_map_bcr(sdram); - sdram->status &=3D ~0x80000000; - } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { + sdram_ddr_map_bcr(s); + s->status &=3D ~0x80000000; + } else if ((s->cfg & 0x80000000) && !(val & 0x80000000)) { trace_ppc4xx_sdram_enable("disable"); /* invalidate all RAM mappings */ - sdram_ddr_unmap_bcr(sdram); - sdram->status |=3D 0x80000000; + sdram_ddr_unmap_bcr(s); + s->status |=3D 0x80000000; } - if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) { - sdram->status |=3D 0x40000000; - } else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) { - sdram->status &=3D ~0x40000000; + if (!(s->cfg & 0x40000000) && (val & 0x40000000)) { + s->status |=3D 0x40000000; + } else if ((s->cfg & 0x40000000) && !(val & 0x40000000)) { + s->status &=3D ~0x40000000; } - sdram->cfg =3D val; + s->cfg =3D val; break; case 0x24: /* SDRAM_STATUS */ /* Read-only register */ break; case 0x30: /* SDRAM_RTR */ - sdram->rtr =3D val & 0x3FF80000; + s->rtr =3D val & 0x3FF80000; break; case 0x34: /* SDRAM_PMIT */ - sdram->pmit =3D (val & 0xF8000000) | 0x07C00000; + s->pmit =3D (val & 0xF8000000) | 0x07C00000; break; case 0x40: /* SDRAM_B0CR */ - sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000); + sdram_ddr_set_bcr(s, 0, val, s->cfg & 0x80000000); break; case 0x44: /* SDRAM_B1CR */ - sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000); + sdram_ddr_set_bcr(s, 1, val, s->cfg & 0x80000000); break; case 0x48: /* SDRAM_B2CR */ - sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000); + sdram_ddr_set_bcr(s, 2, val, s->cfg & 0x80000000); break; case 0x4C: /* SDRAM_B3CR */ - sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000); + sdram_ddr_set_bcr(s, 3, val, s->cfg & 0x80000000); break; case 0x80: /* SDRAM_TR */ - sdram->tr =3D val & 0x018FC01F; + s->tr =3D val & 0x018FC01F; break; case 0x94: /* SDRAM_ECCCFG */ - sdram->ecccfg =3D val & 0x00F00000; + s->ecccfg =3D val & 0x00F00000; break; case 0x98: /* SDRAM_ECCESR */ val &=3D 0xFFF0F000; - if (sdram->eccesr =3D=3D 0 && val !=3D 0) { - qemu_irq_raise(sdram->irq); - } else if (sdram->eccesr !=3D 0 && val =3D=3D 0) { - qemu_irq_lower(sdram->irq); + if (s->eccesr =3D=3D 0 && val !=3D 0) { + qemu_irq_raise(s->irq); + } else if (s->eccesr !=3D 0 && val =3D=3D 0) { + qemu_irq_lower(s->irq); } - sdram->eccesr =3D val; + s->eccesr =3D val; break; default: /* Error */ break; @@ -382,21 +382,21 @@ static void sdram_ddr_dcr_write(void *opaque, int dcr= n, uint32_t val) =20 static void ppc4xx_sdram_ddr_reset(DeviceState *dev) { - Ppc4xxSdramDdrState *sdram =3D PPC4xx_SDRAM_DDR(dev); - - sdram->addr =3D 0; - sdram->bear =3D 0; - sdram->besr0 =3D 0; /* No error */ - sdram->besr1 =3D 0; /* No error */ - sdram->cfg =3D 0; - sdram->ecccfg =3D 0; /* No ECC */ - sdram->eccesr =3D 0; /* No error */ - sdram->pmit =3D 0x07C00000; - sdram->rtr =3D 0x05F00000; - sdram->tr =3D 0x00854009; + Ppc4xxSdramDdrState *s =3D PPC4xx_SDRAM_DDR(dev); + + s->addr =3D 0; + s->bear =3D 0; + s->besr0 =3D 0; /* No error */ + s->besr1 =3D 0; /* No error */ + s->cfg =3D 0; + s->ecccfg =3D 0; /* No ECC */ + s->eccesr =3D 0; /* No error */ + s->pmit =3D 0x07C00000; + s->rtr =3D 0x05F00000; + s->tr =3D 0x00854009; /* We pre-initialize RAM banks */ - sdram->status =3D 0; - sdram->cfg =3D 0x00800000; + s->status =3D 0; + s->cfg =3D 0x00800000; } =20 static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp) @@ -564,7 +564,7 @@ static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *= sdram) =20 static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn) { - Ppc4xxSdramDdr2State *sdram =3D opaque; + Ppc4xxSdramDdr2State *s =3D opaque; uint32_t ret =3D 0; =20 switch (dcrn) { @@ -572,9 +572,9 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int d= crn) case SDRAM_R1BAS: case SDRAM_R2BAS: case SDRAM_R3BAS: - if (sdram->bank[dcrn - SDRAM_R0BAS].size) { - ret =3D sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base, - sdram->bank[dcrn - SDRAM_R0BAS].size); + if (s->bank[dcrn - SDRAM_R0BAS].size) { + ret =3D sdram_ddr2_bcr(s->bank[dcrn - SDRAM_R0BAS].base, + s->bank[dcrn - SDRAM_R0BAS].size); } break; case SDRAM_CONF1HB: @@ -584,16 +584,16 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int= dcrn) case SDRAM_PLBADDUHB: break; case SDRAM0_CFGADDR: - ret =3D sdram->addr; + ret =3D s->addr; break; case SDRAM0_CFGDATA: - switch (sdram->addr) { + switch (s->addr) { case 0x14: /* SDRAM_MCSTAT (405EX) */ case 0x1F: ret =3D 0x80000000; break; case 0x21: /* SDRAM_MCOPT2 */ - ret =3D sdram->mcopt2; + ret =3D s->mcopt2; break; case 0x40: /* SDRAM_MB0CF */ ret =3D 0x00008001; @@ -617,7 +617,7 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int d= crn) =20 static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val) { - Ppc4xxSdramDdr2State *sdram =3D opaque; + Ppc4xxSdramDdr2State *s =3D opaque; =20 switch (dcrn) { case SDRAM_R0BAS: @@ -631,23 +631,23 @@ static void sdram_ddr2_dcr_write(void *opaque, int dc= rn, uint32_t val) case SDRAM_PLBADDUHB: break; case SDRAM0_CFGADDR: - sdram->addr =3D val; + s->addr =3D val; break; case SDRAM0_CFGDATA: - switch (sdram->addr) { + switch (s->addr) { case 0x00: /* B0CR */ break; case 0x21: /* SDRAM_MCOPT2 */ - if (!(sdram->mcopt2 & BIT(27)) && (val & BIT(27))) { + if (!(s->mcopt2 & BIT(27)) && (val & BIT(27))) { trace_ppc4xx_sdram_enable("enable"); /* validate all RAM mappings */ - sdram_ddr2_map_bcr(sdram); - sdram->mcopt2 |=3D BIT(27); - } else if ((sdram->mcopt2 & BIT(27)) && !(val & BIT(27))) { + sdram_ddr2_map_bcr(s); + s->mcopt2 |=3D BIT(27); + } else if ((s->mcopt2 & BIT(27)) && !(val & BIT(27))) { trace_ppc4xx_sdram_enable("disable"); /* invalidate all RAM mappings */ - sdram_ddr2_unmap_bcr(sdram); - sdram->mcopt2 &=3D ~BIT(27); + sdram_ddr2_unmap_bcr(s); + s->mcopt2 &=3D ~BIT(27); } break; default: @@ -661,10 +661,10 @@ static void sdram_ddr2_dcr_write(void *opaque, int dc= rn, uint32_t val) =20 static void ppc4xx_sdram_ddr2_reset(DeviceState *dev) { - Ppc4xxSdramDdr2State *sdram =3D PPC4xx_SDRAM_DDR2(dev); + Ppc4xxSdramDdr2State *s =3D PPC4xx_SDRAM_DDR2(dev); =20 - sdram->addr =3D 0; - sdram->mcopt2 =3D 0; + s->addr =3D 0; + s->mcopt2 =3D 0; } =20 static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp) --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663094908962288.08985826169794; Tue, 13 Sep 2022 11:48:28 -0700 (PDT) Received: from localhost ([::1]:36190 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYAxP-00041W-Lu for importer@patchew.org; Tue, 13 Sep 2022 14:48:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43964) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ8-0006dP-7G; Tue, 13 Sep 2022 14:23:23 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:15247) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZ6-0007fW-77; Tue, 13 Sep 2022 14:23:21 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id B5EC8747F1D; Tue, 13 Sep 2022 20:23:18 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 7BE5C747644; Tue, 13 Sep 2022 20:23:18 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 17/18] ppc4xx_sdram: Generalise bank setup MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:18 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663094910224100001 Content-Type: text/plain; charset="utf-8" Currently only base and size are set on initial bank creation and bcr value is computed on mapping the region. Set bcr at init so the bcr encoding method becomes local to the controller model and mapping and unmapping can operate on the bank so it can be shared between different controller models. This patch converts the DDR2 controller. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc4xx_sdram.c | 93 ++++++++++++++++++++++--------------------- hw/ppc/trace-events | 1 + 2 files changed, 48 insertions(+), 46 deletions(-) diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c index e36898a906..79a9efce4b 100644 --- a/hw/ppc/ppc4xx_sdram.c +++ b/hw/ppc/ppc4xx_sdram.c @@ -106,6 +106,7 @@ static void ppc4xx_sdram_banks(MemoryRegion *ram, int n= r_banks, =20 static void sdram_bank_map(Ppc4xxSdramBank *bank) { + trace_ppc4xx_sdram_map(bank->base, bank->size); memory_region_init(&bank->container, NULL, "sdram-container", bank->si= ze); memory_region_add_subregion(&bank->container, 0, &bank->ram); memory_region_add_subregion(get_system_memory(), bank->base, @@ -114,11 +115,26 @@ static void sdram_bank_map(Ppc4xxSdramBank *bank) =20 static void sdram_bank_unmap(Ppc4xxSdramBank *bank) { + trace_ppc4xx_sdram_unmap(bank->base, bank->size); memory_region_del_subregion(get_system_memory(), &bank->container); memory_region_del_subregion(&bank->container, &bank->ram); object_unparent(OBJECT(&bank->container)); } =20 +static void sdram_bank_set_bcr(Ppc4xxSdramBank *bank, uint32_t bcr, + hwaddr base, hwaddr size, int enabled) +{ + if (memory_region_is_mapped(&bank->container)) { + sdram_bank_unmap(bank); + } + bank->bcr =3D bcr; + bank->base =3D base; + bank->size =3D size; + if (enabled && (bcr & 1)) { + sdram_bank_map(bank); + } +} + /*************************************************************************= ****/ /* DDR SDRAM controller */ static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size) @@ -445,6 +461,8 @@ static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc= , void *data) =20 /*************************************************************************= ****/ /* DDR2 SDRAM controller */ +#define SDRAM_DDR2_BCR_MASK 0xffe0ffc1 + enum { SDRAM_R0BAS =3D 0x40, SDRAM_R1BAS, @@ -518,50 +536,6 @@ static hwaddr sdram_ddr2_size(uint32_t bcr) return size; } =20 -static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i, - uint32_t bcr, int enabled) -{ - if (sdram->bank[i].bcr & 1) { - /* First unmap RAM if enabled */ - trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr), - sdram_ddr2_size(sdram->bank[i].bcr)); - sdram_bank_unmap(&sdram->bank[i]); - } - sdram->bank[i].bcr =3D bcr & 0xffe0ffc1; - sdram->bank[i].base =3D sdram_ddr2_base(bcr); - sdram->bank[i].size =3D sdram_ddr2_size(bcr); - if (enabled && (bcr & 1)) { - trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr)); - sdram_bank_map(&sdram->bank[i]); - } -} - -static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram) -{ - int i; - - for (i =3D 0; i < sdram->nbanks; i++) { - if (sdram->bank[i].size) { - sdram_ddr2_set_bcr(sdram, i, - sdram_ddr2_bcr(sdram->bank[i].base, - sdram->bank[i].size), 1); - } else { - sdram_ddr2_set_bcr(sdram, i, 0, 0); - } - } -} - -static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram) -{ - int i; - - for (i =3D 0; i < sdram->nbanks; i++) { - if (sdram->bank[i].size) { - sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0); - } - } -} - static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn) { Ppc4xxSdramDdr2State *s =3D opaque; @@ -618,6 +592,7 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int d= crn) static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val) { Ppc4xxSdramDdr2State *s =3D opaque; + int i; =20 switch (dcrn) { case SDRAM_R0BAS: @@ -641,12 +616,24 @@ static void sdram_ddr2_dcr_write(void *opaque, int dc= rn, uint32_t val) if (!(s->mcopt2 & BIT(27)) && (val & BIT(27))) { trace_ppc4xx_sdram_enable("enable"); /* validate all RAM mappings */ - sdram_ddr2_map_bcr(s); + for (i =3D 0; i < s->nbanks; i++) { + if (s->bank[i].size) { + sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr, + s->bank[i].base, s->bank[i].siz= e, + 1); + } + } s->mcopt2 |=3D BIT(27); } else if ((s->mcopt2 & BIT(27)) && !(val & BIT(27))) { trace_ppc4xx_sdram_enable("disable"); /* invalidate all RAM mappings */ - sdram_ddr2_unmap_bcr(s); + for (i =3D 0; i < s->nbanks; i++) { + if (s->bank[i].size) { + sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr, + s->bank[i].base, s->bank[i].siz= e, + 0); + } + } s->mcopt2 &=3D ~BIT(27); } break; @@ -675,6 +662,7 @@ static void ppc4xx_sdram_ddr2_realize(DeviceState *dev,= Error **errp) 4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * M= iB, 32 * MiB, 16 * MiB, 8 * MiB, 0 }; + int i; =20 if (s->nbanks < 1 || s->nbanks > 4) { error_setg(errp, "Invalid number of RAM banks"); @@ -685,6 +673,19 @@ static void ppc4xx_sdram_ddr2_realize(DeviceState *dev= , Error **errp) return; } ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes); + for (i =3D 0; i < s->nbanks; i++) { + if (s->bank[i].size) { + s->bank[i].bcr =3D sdram_ddr2_bcr(s->bank[i].base, s->bank[i].= size); + s->bank[i].bcr &=3D SDRAM_DDR2_BCR_MASK; + sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr, + s->bank[i].base, s->bank[i].size, 0); + } else { + sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0); + } + trace_ppc4xx_sdram_init(sdram_ddr2_base(s->bank[i].bcr), + sdram_ddr2_size(s->bank[i].bcr), + s->bank[i].bcr); + } =20 ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR, s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index a07d5aca0f..3b3e4211d4 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -179,3 +179,4 @@ ppc405ep_clocks_setup(const char *trace) "%s" ppc4xx_sdram_enable(const char *trace) "%s SDRAM controller" ppc4xx_sdram_unmap(uint64_t addr, uint64_t size) "Unmap RAM area 0x%" PRIx= 64 " size 0x%" PRIx64 ppc4xx_sdram_map(uint64_t addr, uint64_t size) "Map RAM area 0x%" PRIx64 "= size 0x%" PRIx64 +ppc4xx_sdram_init(uint64_t base, uint64_t size, uint32_t bcr) "Init RAM ar= ea 0x%" PRIx64 " size 0x%" PRIx64 " bcr 0x%x" --=20 2.30.4 From nobody Sun Feb 8 10:48:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663095487381747.9066916387491; Tue, 13 Sep 2022 11:58:07 -0700 (PDT) Received: from localhost ([::1]:41980 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYB6k-0002Go-D3 for importer@patchew.org; Tue, 13 Sep 2022 14:58:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55332) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZV-00076Q-4C; Tue, 13 Sep 2022 14:23:45 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:15252) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYAZR-0007ff-HE; Tue, 13 Sep 2022 14:23:44 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id C1489747F1E; Tue, 13 Sep 2022 20:23:19 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 89599747644; Tue, 13 Sep 2022 20:23:19 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 18/18] ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 20:23:19 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663095488003100001 Content-Type: text/plain; charset="utf-8" Use the generic bank handling introduced in previous patch in the DDR SDRAM controller too. This also fixes previously broken region unmap due to sdram_ddr_unmap_bcr() ignoring container region so it crashed with an assert when the guest tried to disable the controller. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc4xx_sdram.c | 98 ++++++++++++++++--------------------------- 1 file changed, 37 insertions(+), 61 deletions(-) diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c index 79a9efce4b..c731012940 100644 --- a/hw/ppc/ppc4xx_sdram.c +++ b/hw/ppc/ppc4xx_sdram.c @@ -137,6 +137,8 @@ static void sdram_bank_set_bcr(Ppc4xxSdramBank *bank, u= int32_t bcr, =20 /*************************************************************************= ****/ /* DDR SDRAM controller */ +#define SDRAM_DDR_BCR_MASK 0xFFDEE001 + static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size) { uint32_t bcr; @@ -195,58 +197,6 @@ static hwaddr sdram_ddr_size(uint32_t bcr) return size; } =20 -static void sdram_ddr_set_bcr(Ppc4xxSdramDdrState *sdram, int i, - uint32_t bcr, int enabled) -{ - if (sdram->bank[i].bcr & 1) { - /* Unmap RAM */ - trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr), - sdram_ddr_size(sdram->bank[i].bcr)); - memory_region_del_subregion(get_system_memory(), - &sdram->bank[i].container); - memory_region_del_subregion(&sdram->bank[i].container, - &sdram->bank[i].ram); - object_unparent(OBJECT(&sdram->bank[i].container)); - } - sdram->bank[i].bcr =3D bcr & 0xFFDEE001; - if (enabled && (bcr & 1)) { - trace_ppc4xx_sdram_map(sdram_ddr_base(bcr), sdram_ddr_size(bcr)); - memory_region_init(&sdram->bank[i].container, NULL, "sdram-contain= er", - sdram_ddr_size(bcr)); - memory_region_add_subregion(&sdram->bank[i].container, 0, - &sdram->bank[i].ram); - memory_region_add_subregion(get_system_memory(), - sdram_ddr_base(bcr), - &sdram->bank[i].container); - } -} - -static void sdram_ddr_map_bcr(Ppc4xxSdramDdrState *sdram) -{ - int i; - - for (i =3D 0; i < sdram->nbanks; i++) { - if (sdram->bank[i].size !=3D 0) { - sdram_ddr_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base, - sdram->bank[i].size)= , 1); - } else { - sdram_ddr_set_bcr(sdram, i, 0, 0); - } - } -} - -static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram) -{ - int i; - - for (i =3D 0; i < sdram->nbanks; i++) { - trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr), - sdram_ddr_size(sdram->bank[i].bcr)); - memory_region_del_subregion(get_system_memory(), - &sdram->bank[i].ram); - } -} - static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn) { Ppc4xxSdramDdrState *s =3D opaque; @@ -317,6 +267,7 @@ static uint32_t sdram_ddr_dcr_read(void *opaque, int dc= rn) static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val) { Ppc4xxSdramDdrState *s =3D opaque; + int i; =20 switch (dcrn) { case SDRAM0_CFGADDR: @@ -338,12 +289,24 @@ static void sdram_ddr_dcr_write(void *opaque, int dcr= n, uint32_t val) if (!(s->cfg & 0x80000000) && (val & 0x80000000)) { trace_ppc4xx_sdram_enable("enable"); /* validate all RAM mappings */ - sdram_ddr_map_bcr(s); + for (i =3D 0; i < s->nbanks; i++) { + if (s->bank[i].size) { + sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr, + s->bank[i].base, s->bank[i].siz= e, + 1); + } + } s->status &=3D ~0x80000000; } else if ((s->cfg & 0x80000000) && !(val & 0x80000000)) { trace_ppc4xx_sdram_enable("disable"); /* invalidate all RAM mappings */ - sdram_ddr_unmap_bcr(s); + for (i =3D 0; i < s->nbanks; i++) { + if (s->bank[i].size) { + sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr, + s->bank[i].base, s->bank[i].siz= e, + 0); + } + } s->status |=3D 0x80000000; } if (!(s->cfg & 0x40000000) && (val & 0x40000000)) { @@ -363,16 +326,16 @@ static void sdram_ddr_dcr_write(void *opaque, int dcr= n, uint32_t val) s->pmit =3D (val & 0xF8000000) | 0x07C00000; break; case 0x40: /* SDRAM_B0CR */ - sdram_ddr_set_bcr(s, 0, val, s->cfg & 0x80000000); - break; case 0x44: /* SDRAM_B1CR */ - sdram_ddr_set_bcr(s, 1, val, s->cfg & 0x80000000); - break; case 0x48: /* SDRAM_B2CR */ - sdram_ddr_set_bcr(s, 2, val, s->cfg & 0x80000000); - break; case 0x4C: /* SDRAM_B3CR */ - sdram_ddr_set_bcr(s, 3, val, s->cfg & 0x80000000); + i =3D (s->addr - 0x40) / 4; + val &=3D SDRAM_DDR_BCR_MASK; + if (s->bank[i].size) { + sdram_bank_set_bcr(&s->bank[i], val, + sdram_ddr_base(val), sdram_ddr_size(val= ), + s->cfg & 0x80000000); + } break; case 0x80: /* SDRAM_TR */ s->tr =3D val & 0x018FC01F; @@ -422,6 +385,7 @@ static void ppc4xx_sdram_ddr_realize(DeviceState *dev, = Error **errp) const ram_addr_t valid_bank_sizes[] =3D { 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * M= iB, 0 }; + int i; =20 if (s->nbanks < 1 || s->nbanks > 4) { error_setg(errp, "Invalid number of RAM banks"); @@ -432,6 +396,18 @@ static void ppc4xx_sdram_ddr_realize(DeviceState *dev,= Error **errp) return; } ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes); + for (i =3D 0; i < s->nbanks; i++) { + if (s->bank[i].size) { + s->bank[i].bcr =3D sdram_ddr_bcr(s->bank[i].base, s->bank[i].s= ize); + sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr, + s->bank[i].base, s->bank[i].size, 0); + } else { + sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0); + } + trace_ppc4xx_sdram_init(sdram_ddr_base(s->bank[i].bcr), + sdram_ddr_size(s->bank[i].bcr), + s->bank[i].bcr); + } =20 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); =20 --=20 2.30.4