From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660405049656475.7127127135599; Sat, 13 Aug 2022 08:37:29 -0700 (PDT) Received: from localhost ([::1]:60208 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtCZ-00033z-Al for importer@patchew.org; Sat, 13 Aug 2022 11:37:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52558) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9n-0008SI-Ko; Sat, 13 Aug 2022 11:34:35 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:28277) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9l-0006IK-5R; Sat, 13 Aug 2022 11:34:35 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 4310574818E; Sat, 13 Aug 2022 17:34:28 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 05E98746397; Sat, 13 Aug 2022 17:34:28 +0200 (CEST) Message-Id: <50e79b2c5f2c17e2b6b7920dd6526b5c091ac8bb.1660402839.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 01/22] ppc/ppc4xx: Introduce a DCR device model MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:28 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660405051909100001 From: C=C3=A9dric Le Goater The Device Control Registers (DCR) of on-SoC devices are accessed by software through the use of the mtdcr and mfdcr instructions. These are converted in transactions on a side band bus, the DCR bus, which connects the on-SoC devices to the CPU. Ideally, we should model these accesses with a DCR namespace and DCR memory regions but today the DCR handlers are installed in a DCR table under the CPU. Instead, introduce a little device model wrapper to hold a CPU link and handle registration of DCR handlers. The DCR device inherits from SysBus because most of these devices also have MMIO regions and/or IRQs. Being a SysBusDevice makes things easier to install the device model in the overall SoC. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc4xx_devs.c | 41 +++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/ppc4xx.h | 17 +++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 069b511951..f4d7ae9567 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -664,3 +664,44 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum,= uint8_t rxcnum, mal, &dcr_read_mal, &dcr_write_mal); } } + +/* PPC4xx_DCR_DEVICE */ + +void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, + dcr_read_cb dcr_read, dcr_write_cb dcr_write) +{ + assert(dev->cpu); + ppc_dcr_register(&dev->cpu->env, dcrn, opaque, dcr_read, dcr_write); +} + +bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, + Error **errp) +{ + object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort= ); + return sysbus_realize(SYS_BUS_DEVICE(dev), errp); +} + +static Property ppc4xx_dcr_properties[] =3D { + DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU, + PowerPCCPU *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + device_class_set_props(dc, ppc4xx_dcr_properties); +} + +static const TypeInfo ppc4xx_types[] =3D { + { + .name =3D TYPE_PPC4xx_DCR_DEVICE, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Ppc4xxDcrDeviceState), + .class_init =3D ppc4xx_dcr_class_init, + .abstract =3D true, + } +}; + +DEFINE_TYPES(ppc4xx_types) diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 591e2421a3..a537a5567b 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -27,6 +27,7 @@ =20 #include "hw/ppc/ppc.h" #include "exec/memory.h" +#include "hw/sysbus.h" =20 void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, MemoryRegion ram_memories[], @@ -44,4 +45,20 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, u= int8_t rxcnum, =20 #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" =20 +/* + * Generic DCR device + */ +#define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE); +struct Ppc4xxDcrDeviceState { + SysBusDevice parent_obj; + + PowerPCCPU *cpu; +}; + +void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, + dcr_read_cb dcr_read, dcr_write_cb dcr_write); +bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, + Error **errp); + #endif /* PPC4XX_H */ --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660405080641782.7095459721759; Sat, 13 Aug 2022 08:38:00 -0700 (PDT) Received: from localhost ([::1]:60590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtD4-0003Ji-09 for importer@patchew.org; Sat, 13 Aug 2022 11:37:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52622) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9q-00005h-3K; Sat, 13 Aug 2022 11:34:38 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:28282) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9l-0006IN-3l; Sat, 13 Aug 2022 11:34:37 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 46E91748191; Sat, 13 Aug 2022 17:34:29 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 127CE748190; Sat, 13 Aug 2022 17:34:29 +0200 (CEST) Message-Id: <155df7531214db48c3fd4da5dc866d842f332b7c.1660402839.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 02/22] ppc/ppc405: QOM'ify CPC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:29 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660405082075100001 From: C=C3=A9dric Le Goater The CPC controller is currently modeled as a DCR device. Now that all clock settings are handled at the CPC level, change the SoC "sys-clk" property to be an alias on the same property in the CPC model. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 35 ++++++++++- hw/ppc/ppc405_uc.c | 141 ++++++++++++++++++++------------------------- 2 files changed, 95 insertions(+), 81 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 8cc76cc8b3..2ba829988d 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,6 +63,39 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; =20 +#define TYPE_PPC405_CPC "ppc405-cpc" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC); + +enum { + PPC405EP_CPU_CLK =3D 0, + PPC405EP_PLB_CLK =3D 1, + PPC405EP_OPB_CLK =3D 2, + PPC405EP_EBC_CLK =3D 3, + PPC405EP_MAL_CLK =3D 4, + PPC405EP_PCI_CLK =3D 5, + PPC405EP_UART0_CLK =3D 6, + PPC405EP_UART1_CLK =3D 7, + PPC405EP_CLK_NB =3D 8, +}; + +struct Ppc405CpcState { + Ppc4xxDcrDeviceState parent_obj; + + uint32_t sysclk; + clk_setup_t clk_setup[PPC405EP_CLK_NB]; + uint32_t boot; + uint32_t epctl; + uint32_t pllmr[2]; + uint32_t ucr; + uint32_t srr; + uint32_t jtagid; + uint32_t pci; + /* Clock and power management */ + uint32_t er; + uint32_t fr; + uint32_t sr; +}; + #define TYPE_PPC405_SOC "ppc405-soc" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC); =20 @@ -78,9 +111,9 @@ struct Ppc405SoCState { MemoryRegion *dram_mr; hwaddr ram_size; =20 - uint32_t sysclk; PowerPCCPU cpu; DeviceState *uic; + Ppc405CpcState cpc; }; =20 /* PowerPC 405 core */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 14a525b2eb..ec83c292a5 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1178,36 +1178,7 @@ enum { #endif }; =20 -enum { - PPC405EP_CPU_CLK =3D 0, - PPC405EP_PLB_CLK =3D 1, - PPC405EP_OPB_CLK =3D 2, - PPC405EP_EBC_CLK =3D 3, - PPC405EP_MAL_CLK =3D 4, - PPC405EP_PCI_CLK =3D 5, - PPC405EP_UART0_CLK =3D 6, - PPC405EP_UART1_CLK =3D 7, - PPC405EP_CLK_NB =3D 8, -}; - -typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; -struct ppc405ep_cpc_t { - uint32_t sysclk; - clk_setup_t clk_setup[PPC405EP_CLK_NB]; - uint32_t boot; - uint32_t epctl; - uint32_t pllmr[2]; - uint32_t ucr; - uint32_t srr; - uint32_t jtagid; - uint32_t pci; - /* Clock and power management */ - uint32_t er; - uint32_t fr; - uint32_t sr; -}; - -static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) +static void ppc405ep_compute_clocks(Ppc405CpcState *cpc) { uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; uint32_t UART0_clk, UART1_clk; @@ -1300,12 +1271,11 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t= *cpc) clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); } =20 -static uint32_t dcr_read_epcpc (void *opaque, int dcrn) +static uint32_t dcr_read_epcpc(void *opaque, int dcrn) { - ppc405ep_cpc_t *cpc; + Ppc405CpcState *cpc =3D opaque; uint32_t ret; =20 - cpc =3D opaque; switch (dcrn) { case PPC405EP_CPC0_BOOT: ret =3D cpc->boot; @@ -1340,11 +1310,10 @@ static uint32_t dcr_read_epcpc (void *opaque, int d= crn) return ret; } =20 -static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val) +static void dcr_write_epcpc(void *opaque, int dcrn, uint32_t val) { - ppc405ep_cpc_t *cpc; + Ppc405CpcState *cpc =3D opaque; =20 - cpc =3D opaque; switch (dcrn) { case PPC405EP_CPC0_BOOT: /* Read-only register */ @@ -1377,9 +1346,9 @@ static void dcr_write_epcpc (void *opaque, int dcrn, = uint32_t val) } } =20 -static void ppc405ep_cpc_reset (void *opaque) +static void ppc405_cpc_reset(DeviceState *dev) { - ppc405ep_cpc_t *cpc =3D opaque; + Ppc405CpcState *cpc =3D PPC405_CPC(dev); =20 cpc->boot =3D 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ cpc->epctl =3D 0x00000000; @@ -1391,53 +1360,66 @@ static void ppc405ep_cpc_reset (void *opaque) cpc->er =3D 0x00000000; cpc->fr =3D 0x00000000; cpc->sr =3D 0x00000000; + cpc->jtagid =3D 0x20267049; ppc405ep_compute_clocks(cpc); } =20 /* XXX: sysclk should be between 25 and 100 MHz */ -static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], - uint32_t sysclk) +static void ppc405_cpc_realize(DeviceState *dev, Error **errp) { - ppc405ep_cpc_t *cpc; + Ppc405CpcState *cpc =3D PPC405_CPC(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); + + assert(dcr->cpu); + cpc->clk_setup[PPC405EP_CPU_CLK].cb =3D + ppc_40x_timers_init(&dcr->cpu->env, cpc->sysclk, PPC_INTERRUPT_PIT= ); + cpc->clk_setup[PPC405EP_CPU_CLK].opaque =3D &dcr->cpu->env; + + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_BOOT, cpc, + &dcr_read_epcpc, &dcr_write_epcpc); + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_EPCTL, cpc, + &dcr_read_epcpc, &dcr_write_epcpc); + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR0, cpc, + &dcr_read_epcpc, &dcr_write_epcpc); + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR1, cpc, + &dcr_read_epcpc, &dcr_write_epcpc); + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_UCR, cpc, + &dcr_read_epcpc, &dcr_write_epcpc); + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_SRR, cpc, + &dcr_read_epcpc, &dcr_write_epcpc); + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_JTAGID, cpc, + &dcr_read_epcpc, &dcr_write_epcpc); + ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PCI, cpc, + &dcr_read_epcpc, &dcr_write_epcpc); +} =20 - cpc =3D g_new0(ppc405ep_cpc_t, 1); - memcpy(cpc->clk_setup, clk_setup, - PPC405EP_CLK_NB * sizeof(clk_setup_t)); - cpc->jtagid =3D 0x20267049; - cpc->sysclk =3D sysclk; - qemu_register_reset(&ppc405ep_cpc_reset, cpc); - ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, - &dcr_read_epcpc, &dcr_write_epcpc); - ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, - &dcr_read_epcpc, &dcr_write_epcpc); - ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, - &dcr_read_epcpc, &dcr_write_epcpc); - ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, - &dcr_read_epcpc, &dcr_write_epcpc); - ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, - &dcr_read_epcpc, &dcr_write_epcpc); - ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, - &dcr_read_epcpc, &dcr_write_epcpc); - ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, - &dcr_read_epcpc, &dcr_write_epcpc); - ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, - &dcr_read_epcpc, &dcr_write_epcpc); -#if 0 - ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc, - &dcr_read_epcpc, &dcr_write_epcpc); - ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc, - &dcr_read_epcpc, &dcr_write_epcpc); - ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc, - &dcr_read_epcpc, &dcr_write_epcpc); -#endif +static Property ppc405_cpc_properties[] =3D { + DEFINE_PROP_UINT32("sys-clk", Ppc405CpcState, sysclk, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ppc405_cpc_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc405_cpc_realize; + dc->reset =3D ppc405_cpc_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; + device_class_set_props(dc, ppc405_cpc_properties); } =20 +/* PPC405_SOC */ + static void ppc405_soc_instance_init(Object *obj) { Ppc405SoCState *s =3D PPC405_SOC(obj); =20 object_initialize_child(obj, "cpu", &s->cpu, POWERPC_CPU_TYPE_NAME("405ep")); + + object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC); + object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk"); } =20 static void ppc405_reset(void *opaque) @@ -1448,12 +1430,9 @@ static void ppc405_reset(void *opaque) static void ppc405_soc_realize(DeviceState *dev, Error **errp) { Ppc405SoCState *s =3D PPC405_SOC(dev); - clk_setup_t clk_setup[PPC405EP_CLK_NB]; qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; CPUPPCState *env; =20 - memset(clk_setup, 0, sizeof(clk_setup)); - /* init CPUs */ if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { return; @@ -1462,14 +1441,12 @@ static void ppc405_soc_realize(DeviceState *dev, Er= ror **errp) =20 env =3D &s->cpu.env; =20 - clk_setup[PPC405EP_CPU_CLK].cb =3D - ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT); - clk_setup[PPC405EP_CPU_CLK].opaque =3D env; - ppc_dcr_init(env, NULL, NULL); =20 /* CPU control */ - ppc405ep_cpc_init(env, clk_setup, s->sysclk); + if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->cpc), &s->cpu, errp)) { + return; + } =20 /* PLB arbitrer */ ppc4xx_plb_init(env); @@ -1561,7 +1538,6 @@ static void ppc405_soc_realize(DeviceState *dev, Erro= r **errp) static Property ppc405_soc_properties[] =3D { DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_UINT32("sys-clk", Ppc405SoCState, sysclk, 0), DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0), DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0), DEFINE_PROP_END_OF_LIST(), @@ -1579,6 +1555,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { + .name =3D TYPE_PPC405_CPC, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc405CpcState), + .class_init =3D ppc405_cpc_class_init, + }, { .name =3D TYPE_PPC405_SOC, .parent =3D TYPE_DEVICE, .instance_size =3D sizeof(Ppc405SoCState), --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660405499428597.5653068270188; Sat, 13 Aug 2022 08:44:59 -0700 (PDT) Received: from localhost ([::1]:50096 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtJq-0007C4-Bx for importer@patchew.org; Sat, 13 Aug 2022 11:44:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52618) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9q-00005Q-AC; Sat, 13 Aug 2022 11:34:38 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:28287) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9l-0006IT-Gy; Sat, 13 Aug 2022 11:34:37 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 501A1748194; Sat, 13 Aug 2022 17:34:30 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 1E660748190; Sat, 13 Aug 2022 17:34:30 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 03/22] ppc/ppc405: QOM'ify GPT MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:30 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660405500902100001 From: C=C3=A9dric Le Goater The GPT controller is currently modeled as a SysBus device with a unique memory region, a couple of IRQs and a timer. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 22 ++++++++++ hw/ppc/ppc405_uc.c | 99 ++++++++++++++++++++++++--------------------- hw/ppc/trace-events | 1 - 3 files changed, 75 insertions(+), 47 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 2ba829988d..bcf55e4f6b 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,6 +63,27 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; =20 +/* General purpose timers */ +#define TYPE_PPC405_GPT "ppc405-gpt" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT); +struct Ppc405GptState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + int64_t tb_offset; + uint32_t tb_freq; + QEMUTimer *timer; + qemu_irq irqs[5]; + uint32_t oe; + uint32_t ol; + uint32_t im; + uint32_t is; + uint32_t ie; + uint32_t comp[5]; + uint32_t mask[5]; +}; + #define TYPE_PPC405_CPC "ppc405-cpc" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC); =20 @@ -114,6 +135,7 @@ struct Ppc405SoCState { PowerPCCPU cpu; DeviceState *uic; Ppc405CpcState cpc; + Ppc405GptState gpt; }; =20 /* PowerPC 405 core */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index ec83c292a5..bf95fabdc0 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -926,34 +926,18 @@ static void ppc405_ocm_init(CPUPPCState *env) =20 /*************************************************************************= ****/ /* General purpose timers */ -typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; -struct ppc4xx_gpt_t { - MemoryRegion iomem; - int64_t tb_offset; - uint32_t tb_freq; - QEMUTimer *timer; - qemu_irq irqs[5]; - uint32_t oe; - uint32_t ol; - uint32_t im; - uint32_t is; - uint32_t ie; - uint32_t comp[5]; - uint32_t mask[5]; -}; - -static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) +static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n) { /* XXX: TODO */ return 0; } =20 -static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) +static void ppc4xx_gpt_set_output(Ppc405GptState *gpt, int n, int level) { /* XXX: TODO */ } =20 -static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) +static void ppc4xx_gpt_set_outputs(Ppc405GptState *gpt) { uint32_t mask; int i; @@ -974,7 +958,7 @@ static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) } } =20 -static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) +static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt) { uint32_t mask; int i; @@ -989,14 +973,14 @@ static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) } } =20 -static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) +static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt) { /* XXX: TODO */ } =20 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) { - ppc4xx_gpt_t *gpt =3D opaque; + Ppc405GptState *gpt =3D opaque; uint32_t ret; int idx; =20 @@ -1050,7 +1034,7 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr = addr, unsigned size) static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - ppc4xx_gpt_t *gpt =3D opaque; + Ppc405GptState *gpt =3D opaque; int idx; =20 trace_ppc4xx_gpt_write(addr, size, value); @@ -1114,22 +1098,20 @@ static const MemoryRegionOps gpt_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -static void ppc4xx_gpt_cb (void *opaque) +static void ppc4xx_gpt_cb(void *opaque) { - ppc4xx_gpt_t *gpt; + Ppc405GptState *gpt =3D opaque; =20 - gpt =3D opaque; ppc4xx_gpt_set_irqs(gpt); ppc4xx_gpt_set_outputs(gpt); ppc4xx_gpt_compute_timer(gpt); } =20 -static void ppc4xx_gpt_reset (void *opaque) +static void ppc405_gpt_reset(DeviceState *dev) { - ppc4xx_gpt_t *gpt; + Ppc405GptState *gpt =3D PPC405_GPT(dev); int i; =20 - gpt =3D opaque; timer_del(gpt->timer); gpt->oe =3D 0x00000000; gpt->ol =3D 0x00000000; @@ -1142,21 +1124,34 @@ static void ppc4xx_gpt_reset (void *opaque) } } =20 -static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) +static void ppc405_gpt_realize(DeviceState *dev, Error **errp) { - ppc4xx_gpt_t *gpt; + Ppc405GptState *s =3D PPC405_GPT(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); int i; =20 - trace_ppc4xx_gpt_init(base); + s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, s); + memory_region_init_io(&s->iomem, OBJECT(s), &gpt_ops, s, "gpt", 0xd4); + sysbus_init_mmio(sbd, &s->iomem); =20 - gpt =3D g_new0(ppc4xx_gpt_t, 1); - for (i =3D 0; i < 5; i++) { - gpt->irqs[i] =3D irqs[i]; + for (i =3D 0; i < ARRAY_SIZE(s->irqs); i++) { + sysbus_init_irq(sbd, &s->irqs[i]); } - gpt->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); - memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); - memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); - qemu_register_reset(ppc4xx_gpt_reset, gpt); +} + +static void ppc405_gpt_finalize(Object *obj) +{ + timer_del(PPC405_GPT(obj)->timer); +} + +static void ppc405_gpt_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc405_gpt_realize; + dc->reset =3D ppc405_gpt_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; } =20 /*************************************************************************= ****/ @@ -1420,6 +1415,8 @@ static void ppc405_soc_instance_init(Object *obj) =20 object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC); object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk"); + + object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT); } =20 static void ppc405_reset(void *opaque) @@ -1430,8 +1427,10 @@ static void ppc405_reset(void *opaque) static void ppc405_soc_realize(DeviceState *dev, Error **errp) { Ppc405SoCState *s =3D PPC405_SOC(dev); - qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; + qemu_irq dma_irqs[4], mal_irqs[4]; CPUPPCState *env; + SysBusDevice *sbd; + int i; =20 /* init CPUs */ if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { @@ -1517,12 +1516,14 @@ static void ppc405_soc_realize(DeviceState *dev, Er= ror **errp) ppc405_ocm_init(env); =20 /* GPT */ - gpt_irqs[0] =3D qdev_get_gpio_in(s->uic, 19); - gpt_irqs[1] =3D qdev_get_gpio_in(s->uic, 20); - gpt_irqs[2] =3D qdev_get_gpio_in(s->uic, 21); - gpt_irqs[3] =3D qdev_get_gpio_in(s->uic, 22); - gpt_irqs[4] =3D qdev_get_gpio_in(s->uic, 23); - ppc4xx_gpt_init(0xef600000, gpt_irqs); + sbd =3D SYS_BUS_DEVICE(&s->gpt); + if (!sysbus_realize(sbd, errp)) { + return; + } + sysbus_mmio_map(sbd, 0, 0xef600000); + for (i =3D 0; i < ARRAY_SIZE(s->gpt.irqs); i++) { + sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 19 + i)); + } =20 /* MAL */ mal_irqs[0] =3D qdev_get_gpio_in(s->uic, 11); @@ -1555,6 +1556,12 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { + .name =3D TYPE_PPC405_GPT, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Ppc405GptState), + .instance_finalize =3D ppc405_gpt_finalize, + .class_init =3D ppc405_gpt_class_init, + }, { .name =3D TYPE_PPC405_CPC, .parent =3D TYPE_PPC4xx_DCR_DEVICE, .instance_size =3D sizeof(Ppc405CpcState), diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index 5c0a215cad..adb4500888 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -162,7 +162,6 @@ ocm_unmap(const char* prefix, uint32_t isarc) "OCM unma= p %s 0x%08" PRIx32 =20 ppc4xx_gpt_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d" ppc4xx_gpt_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PR= Ix64 " size %d =3D 0x%" PRIx64 -ppc4xx_gpt_init(uint64_t addr) "offet 0x%" PRIx64 =20 ppc405ep_clocks_compute(const char *param, uint32_t param2, uint32_t val) = "%s 0x%1" PRIx32 " %d" ppc405ep_clocks_setup(const char *trace) "%s" --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660405335890578.6434926854073; Sat, 13 Aug 2022 08:42:15 -0700 (PDT) Received: from localhost ([::1]:41394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtHB-0001Gm-NI for importer@patchew.org; Sat, 13 Aug 2022 11:42:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52620) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9q-00005T-0b; Sat, 13 Aug 2022 11:34:38 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:28292) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9l-0006Ib-TT; Sat, 13 Aug 2022 11:34:37 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 6666A748195; Sat, 13 Aug 2022 17:34:31 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 30873748190; Sat, 13 Aug 2022 17:34:31 +0200 (CEST) Message-Id: <945147317f98dd64e0dfa7a91a9786f3c111e903.1660402839.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 04/22] ppc/ppc405: QOM'ify OCM MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:31 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660405336220100001 From: C=C3=A9dric Le Goater The OCM controller is currently modeled as a simple DCR device with a couple of memory regions. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 16 ++++++++++ hw/ppc/ppc405_uc.c | 77 +++++++++++++++++++++++----------------------- 2 files changed, 55 insertions(+), 38 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index bcf55e4f6b..a5b493d3e7 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,6 +63,21 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; =20 +/* On Chip Memory */ +#define TYPE_PPC405_OCM "ppc405-ocm" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM); +struct Ppc405OcmState { + Ppc4xxDcrDeviceState parent_obj; + + MemoryRegion ram; + MemoryRegion isarc_ram; + MemoryRegion dsarc_ram; + uint32_t isarc; + uint32_t isacntl; + uint32_t dsarc; + uint32_t dsacntl; +}; + /* General purpose timers */ #define TYPE_PPC405_GPT "ppc405-gpt" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT); @@ -136,6 +151,7 @@ struct Ppc405SoCState { DeviceState *uic; Ppc405CpcState cpc; Ppc405GptState gpt; + Ppc405OcmState ocm; }; =20 /* PowerPC 405 core */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index bf95fabdc0..2282cfcd18 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -773,20 +773,9 @@ enum { OCM0_DSACNTL =3D 0x01B, }; =20 -typedef struct ppc405_ocm_t ppc405_ocm_t; -struct ppc405_ocm_t { - MemoryRegion ram; - MemoryRegion isarc_ram; - MemoryRegion dsarc_ram; - uint32_t isarc; - uint32_t isacntl; - uint32_t dsarc; - uint32_t dsacntl; -}; - -static void ocm_update_mappings (ppc405_ocm_t *ocm, - uint32_t isarc, uint32_t isacntl, - uint32_t dsarc, uint32_t dsacntl) +static void ocm_update_mappings(Ppc405OcmState *ocm, + uint32_t isarc, uint32_t isacntl, + uint32_t dsarc, uint32_t dsacntl) { trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); @@ -828,12 +817,11 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, } } =20 -static uint32_t dcr_read_ocm (void *opaque, int dcrn) +static uint32_t dcr_read_ocm(void *opaque, int dcrn) { - ppc405_ocm_t *ocm; + Ppc405OcmState *ocm =3D opaque; uint32_t ret; =20 - ocm =3D opaque; switch (dcrn) { case OCM0_ISARC: ret =3D ocm->isarc; @@ -855,12 +843,11 @@ static uint32_t dcr_read_ocm (void *opaque, int dcrn) return ret; } =20 -static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val) +static void dcr_write_ocm(void *opaque, int dcrn, uint32_t val) { - ppc405_ocm_t *ocm; + Ppc405OcmState *ocm =3D opaque; uint32_t isarc, dsarc, isacntl, dsacntl; =20 - ocm =3D opaque; isarc =3D ocm->isarc; dsarc =3D ocm->dsarc; isacntl =3D ocm->isacntl; @@ -886,12 +873,11 @@ static void dcr_write_ocm (void *opaque, int dcrn, ui= nt32_t val) ocm->dsacntl =3D dsacntl; } =20 -static void ocm_reset (void *opaque) +static void ppc405_ocm_reset(DeviceState *dev) { - ppc405_ocm_t *ocm; + Ppc405OcmState *ocm =3D PPC405_OCM(dev); uint32_t isarc, dsarc, isacntl, dsacntl; =20 - ocm =3D opaque; isarc =3D 0x00000000; isacntl =3D 0x00000000; dsarc =3D 0x00000000; @@ -903,25 +889,31 @@ static void ocm_reset (void *opaque) ocm->dsacntl =3D dsacntl; } =20 -static void ppc405_ocm_init(CPUPPCState *env) +static void ppc405_ocm_realize(DeviceState *dev, Error **errp) { - ppc405_ocm_t *ocm; + Ppc405OcmState *ocm =3D PPC405_OCM(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); =20 - ocm =3D g_new0(ppc405_ocm_t, 1); /* XXX: Size is 4096 or 0x04000000 */ - memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB, + memory_region_init_ram(&ocm->isarc_ram, OBJECT(ocm), "ppc405.ocm", 4 *= KiB, &error_fatal); - memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", + memory_region_init_alias(&ocm->dsarc_ram, OBJECT(ocm), "ppc405.dsarc", &ocm->isarc_ram, 0, 4 * KiB); - qemu_register_reset(&ocm_reset, ocm); - ppc_dcr_register(env, OCM0_ISARC, - ocm, &dcr_read_ocm, &dcr_write_ocm); - ppc_dcr_register(env, OCM0_ISACNTL, - ocm, &dcr_read_ocm, &dcr_write_ocm); - ppc_dcr_register(env, OCM0_DSARC, - ocm, &dcr_read_ocm, &dcr_write_ocm); - ppc_dcr_register(env, OCM0_DSACNTL, - ocm, &dcr_read_ocm, &dcr_write_ocm); + + ppc4xx_dcr_register(dcr, OCM0_ISARC, ocm, &dcr_read_ocm, &dcr_write_oc= m); + ppc4xx_dcr_register(dcr, OCM0_ISACNTL, ocm, &dcr_read_ocm, &dcr_write_= ocm); + ppc4xx_dcr_register(dcr, OCM0_DSARC, ocm, &dcr_read_ocm, &dcr_write_oc= m); + ppc4xx_dcr_register(dcr, OCM0_DSACNTL, ocm, &dcr_read_ocm, &dcr_write_= ocm); +} + +static void ppc405_ocm_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc405_ocm_realize; + dc->reset =3D ppc405_ocm_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; } =20 /*************************************************************************= ****/ @@ -1417,6 +1409,8 @@ static void ppc405_soc_instance_init(Object *obj) object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk"); =20 object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT); + + object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM); } =20 static void ppc405_reset(void *opaque) @@ -1513,7 +1507,9 @@ static void ppc405_soc_realize(DeviceState *dev, Erro= r **errp) } =20 /* OCM */ - ppc405_ocm_init(env); + if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ocm), &s->cpu, errp)) { + return; + } =20 /* GPT */ sbd =3D SYS_BUS_DEVICE(&s->gpt); @@ -1556,6 +1552,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { + .name =3D TYPE_PPC405_OCM, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc405OcmState), + .class_init =3D ppc405_ocm_class_init, + }, { .name =3D TYPE_PPC405_GPT, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(Ppc405GptState), --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660405528897350.2190103421906; Sat, 13 Aug 2022 08:45:28 -0700 (PDT) Received: from localhost ([::1]:50680 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtKJ-0007bj-Pw for importer@patchew.org; Sat, 13 Aug 2022 11:45:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9r-0000D2-Om; Sat, 13 Aug 2022 11:34:40 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:28308) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9p-0006JE-HA; Sat, 13 Aug 2022 11:34:39 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 64716748196; Sat, 13 Aug 2022 17:34:32 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 3B12D748190; Sat, 13 Aug 2022 17:34:32 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 05/22] ppc/ppc405: QOM'ify GPIO MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:32 +0200 (CEST) X-Spam-Probability: 11% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660405529076100001 From: C=C3=A9dric Le Goater The GPIO controller is currently modeled as a simple SysBus device with a unique memory region. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 21 +++++++++++++++++++ hw/ppc/ppc405_uc.c | 50 ++++++++++++++++++++++----------------------- hw/ppc/trace-events | 1 - 3 files changed, 45 insertions(+), 27 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index a5b493d3e7..21f6cb3585 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,6 +63,26 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; =20 +/* GPIO */ +#define TYPE_PPC405_GPIO "ppc405-gpio" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO); +struct Ppc405GpioState { + SysBusDevice parent_obj; + + MemoryRegion io; + uint32_t or; + uint32_t tcr; + uint32_t osrh; + uint32_t osrl; + uint32_t tsrh; + uint32_t tsrl; + uint32_t odr; + uint32_t ir; + uint32_t rr1; + uint32_t isr1h; + uint32_t isr1l; +}; + /* On Chip Memory */ #define TYPE_PPC405_OCM "ppc405-ocm" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM); @@ -152,6 +172,7 @@ struct Ppc405SoCState { Ppc405CpcState cpc; Ppc405GptState gpt; Ppc405OcmState ocm; + Ppc405GpioState gpio; }; =20 /* PowerPC 405 core */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 2282cfcd18..7ed3cf7149 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -714,22 +714,6 @@ static void ppc405_dma_init(CPUPPCState *env, qemu_irq= irqs[4]) =20 /*************************************************************************= ****/ /* GPIO */ -typedef struct ppc405_gpio_t ppc405_gpio_t; -struct ppc405_gpio_t { - MemoryRegion io; - uint32_t or; - uint32_t tcr; - uint32_t osrh; - uint32_t osrl; - uint32_t tsrh; - uint32_t tsrl; - uint32_t odr; - uint32_t ir; - uint32_t rr1; - uint32_t isr1h; - uint32_t isr1l; -}; - static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) { trace_ppc405_gpio_read(addr, size); @@ -748,20 +732,22 @@ static const MemoryRegionOps ppc405_gpio_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -static void ppc405_gpio_reset (void *opaque) +static void ppc405_gpio_realize(DeviceState *dev, Error **errp) { + Ppc405GpioState *s =3D PPC405_GPIO(dev); + + memory_region_init_io(&s->io, OBJECT(s), &ppc405_gpio_ops, s, "gpio", + 0x38); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io); } =20 -static void ppc405_gpio_init(hwaddr base) +static void ppc405_gpio_class_init(ObjectClass *oc, void *data) { - ppc405_gpio_t *gpio; - - trace_ppc405_gpio_init(base); + DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - gpio =3D g_new0(ppc405_gpio_t, 1); - memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio",= 0x038); - memory_region_add_subregion(get_system_memory(), base, &gpio->io); - qemu_register_reset(&ppc405_gpio_reset, gpio); + dc->realize =3D ppc405_gpio_realize; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; } =20 /*************************************************************************= ****/ @@ -1411,6 +1397,8 @@ static void ppc405_soc_instance_init(Object *obj) object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT); =20 object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM); + + object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO); } =20 static void ppc405_reset(void *opaque) @@ -1489,8 +1477,13 @@ static void ppc405_soc_realize(DeviceState *dev, Err= or **errp) /* I2C controller */ sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, qdev_get_gpio_in(s->uic, 2)); + /* GPIO */ - ppc405_gpio_init(0xef600700); + sbd =3D SYS_BUS_DEVICE(&s->gpio); + if (!sysbus_realize(sbd, errp)) { + return; + } + sysbus_mmio_map(sbd, 0, 0xef600700); =20 /* Serial ports */ if (serial_hd(0) !=3D NULL) { @@ -1552,6 +1545,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { + .name =3D TYPE_PPC405_GPIO, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Ppc405GpioState), + .class_init =3D ppc405_gpio_class_init, + }, { .name =3D TYPE_PPC405_OCM, .parent =3D TYPE_PPC4xx_DCR_DEVICE, .instance_size =3D sizeof(Ppc405OcmState), diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index adb4500888..66fbf0e035 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -154,7 +154,6 @@ opba_init(uint64_t addr) "offet 0x%" PRIx64 =20 ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d" ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" P= RIx64 " size %d =3D 0x%" PRIx64 -ppc405_gpio_init(uint64_t addr) "offet 0x%" PRIx64 =20 ocm_update_mappings(uint32_t isarc, uint32_t isacntl, uint32_t dsarc, uint= 32_t dsacntl, uint32_t ocm_isarc, uint32_t ocm_isacntl, uint32_t ocm_dsarc,= uint32_t ocm_dsacntl) "OCM update ISA 0x%08" PRIx32 " 0x%08" PRIx32 " (0x%= 08" PRIx32" 0x%08" PRIx32 ") DSA 0x%08" PRIx32 " 0x%08" PRIx32" (0x%08" PRI= x32 " 0x%08" PRIx32 ")" ocm_map(const char* prefix, uint32_t isarc) "OCM map %s 0x%08" PRIx32 --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660405156507865.8560024616772; Sat, 13 Aug 2022 08:39:16 -0700 (PDT) Received: from localhost ([::1]:34804 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtEJ-00059a-Fu for importer@patchew.org; Sat, 13 Aug 2022 11:39:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52678) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9s-0000G1-Ol; Sat, 13 Aug 2022 11:34:40 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:28309) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9p-0006JG-Is; Sat, 13 Aug 2022 11:34:39 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 7CC14748198; Sat, 13 Aug 2022 17:34:33 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 46E6C748190; Sat, 13 Aug 2022 17:34:33 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 06/22] ppc/ppc405: QOM'ify DMA MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:33 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660405157555100001 From: C=C3=A9dric Le Goater The DMA controller is currently modeled as a DCR device with a couple of IRQs. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 19 ++++++ hw/ppc/ppc405_uc.c | 141 ++++++++++++++++++++------------------------- 2 files changed, 81 insertions(+), 79 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 21f6cb3585..c75e4c7cb5 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,6 +63,24 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; =20 +/* DMA controller */ +#define TYPE_PPC405_DMA "ppc405-dma" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA); +struct Ppc405DmaState { + Ppc4xxDcrDeviceState parent_obj; + + qemu_irq irqs[4]; + uint32_t cr[4]; + uint32_t ct[4]; + uint32_t da[4]; + uint32_t sa[4]; + uint32_t sg[4]; + uint32_t sr; + uint32_t sgc; + uint32_t slp; + uint32_t pol; +}; + /* GPIO */ #define TYPE_PPC405_GPIO "ppc405-gpio" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO); @@ -173,6 +191,7 @@ struct Ppc405SoCState { Ppc405GptState gpt; Ppc405OcmState ocm; Ppc405GpioState gpio; + Ppc405DmaState dma; }; =20 /* PowerPC 405 core */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 7ed3cf7149..40af07e321 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -613,35 +613,20 @@ enum { DMA0_POL =3D 0x126, }; =20 -typedef struct ppc405_dma_t ppc405_dma_t; -struct ppc405_dma_t { - qemu_irq irqs[4]; - uint32_t cr[4]; - uint32_t ct[4]; - uint32_t da[4]; - uint32_t sa[4]; - uint32_t sg[4]; - uint32_t sr; - uint32_t sgc; - uint32_t slp; - uint32_t pol; -}; - -static uint32_t dcr_read_dma (void *opaque, int dcrn) +static uint32_t dcr_read_dma(void *opaque, int dcrn) { return 0; } =20 -static void dcr_write_dma (void *opaque, int dcrn, uint32_t val) +static void dcr_write_dma(void *opaque, int dcrn, uint32_t val) { } =20 -static void ppc405_dma_reset (void *opaque) +static void ppc405_dma_reset(DeviceState *dev) { - ppc405_dma_t *dma; + Ppc405DmaState *dma =3D PPC405_DMA(dev); int i; =20 - dma =3D opaque; for (i =3D 0; i < 4; i++) { dma->cr[i] =3D 0x00000000; dma->ct[i] =3D 0x00000000; @@ -655,61 +640,50 @@ static void ppc405_dma_reset (void *opaque) dma->pol =3D 0x00000000; } =20 -static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4]) +static void ppc405_dma_realize(DeviceState *dev, Error **errp) +{ + Ppc405DmaState *dma =3D PPC405_DMA(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); + int i; + + for (i =3D 0; i < ARRAY_SIZE(dma->irqs); i++) { + sysbus_init_irq(SYS_BUS_DEVICE(dma), &dma->irqs[i]); + } + + ppc4xx_dcr_register(dcr, DMA0_CR0, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_CT0, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_DA0, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_SA0, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_SG0, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_CR1, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_CT1, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_DA1, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_SA1, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_SG1, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_CR2, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_CT2, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_DA2, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_SA2, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_SG2, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_CR3, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_CT3, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_DA3, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_SA3, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_SG3, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_SR, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_SGC, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_SLP, dma, &dcr_read_dma, &dcr_write_dma); + ppc4xx_dcr_register(dcr, DMA0_POL, dma, &dcr_read_dma, &dcr_write_dma); +} + +static void ppc405_dma_class_init(ObjectClass *oc, void *data) { - ppc405_dma_t *dma; - - dma =3D g_new0(ppc405_dma_t, 1); - memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); - qemu_register_reset(&ppc405_dma_reset, dma); - ppc_dcr_register(env, DMA0_CR0, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_CT0, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_DA0, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_SA0, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_SG0, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_CR1, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_CT1, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_DA1, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_SA1, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_SG1, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_CR2, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_CT2, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_DA2, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_SA2, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_SG2, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_CR3, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_CT3, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_DA3, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_SA3, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_SG3, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_SR, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_SGC, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_SLP, - dma, &dcr_read_dma, &dcr_write_dma); - ppc_dcr_register(env, DMA0_POL, - dma, &dcr_read_dma, &dcr_write_dma); + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc405_dma_realize; + dc->reset =3D ppc405_dma_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; } =20 /*************************************************************************= ****/ @@ -1399,6 +1373,8 @@ static void ppc405_soc_instance_init(Object *obj) object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM); =20 object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO); + + object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA); } =20 static void ppc405_reset(void *opaque) @@ -1409,7 +1385,7 @@ static void ppc405_reset(void *opaque) static void ppc405_soc_realize(DeviceState *dev, Error **errp) { Ppc405SoCState *s =3D PPC405_SOC(dev); - qemu_irq dma_irqs[4], mal_irqs[4]; + qemu_irq mal_irqs[4]; CPUPPCState *env; SysBusDevice *sbd; int i; @@ -1468,11 +1444,13 @@ static void ppc405_soc_realize(DeviceState *dev, Er= ror **errp) ppc405_ebc_init(env); =20 /* DMA controller */ - dma_irqs[0] =3D qdev_get_gpio_in(s->uic, 5); - dma_irqs[1] =3D qdev_get_gpio_in(s->uic, 6); - dma_irqs[2] =3D qdev_get_gpio_in(s->uic, 7); - dma_irqs[3] =3D qdev_get_gpio_in(s->uic, 8); - ppc405_dma_init(env, dma_irqs); + if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->dma), &s->cpu, errp)) { + return; + } + sbd =3D SYS_BUS_DEVICE(&s->dma); + for (i =3D 0; i < ARRAY_SIZE(s->dma.irqs); i++) { + sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 5 + i)); + } =20 /* I2C controller */ sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, @@ -1545,6 +1523,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { + .name =3D TYPE_PPC405_DMA, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc405DmaState), + .class_init =3D ppc405_dma_class_init, + }, { .name =3D TYPE_PPC405_GPIO, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(Ppc405GpioState), --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660405340857973.566140031275; Sat, 13 Aug 2022 08:42:20 -0700 (PDT) Received: from localhost ([::1]:41998 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtHH-0001gq-P0 for importer@patchew.org; Sat, 13 Aug 2022 11:42:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52642) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9q-00008U-Pj; Sat, 13 Aug 2022 11:34:38 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:28310) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9o-0006JM-OD; Sat, 13 Aug 2022 11:34:38 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 7FB68748199; Sat, 13 Aug 2022 17:34:34 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 518BB748190; Sat, 13 Aug 2022 17:34:34 +0200 (CEST) Message-Id: <07e940eebb2b6d8a42968c5162a19933ab3c5b40.1660402839.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 07/22] ppc/ppc405: QOM'ify EBC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:34 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660405342264100001 From: C=C3=A9dric Le Goater EBC is currently modeled as a DCR device. Also drop the ppc405_ebc_init() helper and adapt the sam460ex machine. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 17 ++++++++++++- hw/ppc/ppc405_uc.c | 62 ++++++++++++++++++++++++---------------------- hw/ppc/sam460ex.c | 4 ++- 3 files changed, 51 insertions(+), 32 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index c75e4c7cb5..82bf8dae93 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,6 +63,21 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; =20 +/* Peripheral controller */ +#define TYPE_PPC405_EBC "ppc405-ebc" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC); +struct Ppc405EbcState { + Ppc4xxDcrDeviceState parent_obj; + + uint32_t addr; + uint32_t bcr[8]; + uint32_t bap[8]; + uint32_t bear; + uint32_t besr0; + uint32_t besr1; + uint32_t cfg; +}; + /* DMA controller */ #define TYPE_PPC405_DMA "ppc405-dma" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA); @@ -192,12 +207,12 @@ struct Ppc405SoCState { Ppc405OcmState ocm; Ppc405GpioState gpio; Ppc405DmaState dma; + Ppc405EbcState ebc; }; =20 /* PowerPC 405 core */ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size); =20 void ppc4xx_plb_init(CPUPPCState *env); -void ppc405_ebc_init(CPUPPCState *env); =20 #endif /* PPC405_H */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 40af07e321..f259de07e2 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -393,28 +393,16 @@ static void ppc4xx_opba_init(hwaddr base) =20 /*************************************************************************= ****/ /* Peripheral controller */ -typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; -struct ppc4xx_ebc_t { - uint32_t addr; - uint32_t bcr[8]; - uint32_t bap[8]; - uint32_t bear; - uint32_t besr0; - uint32_t besr1; - uint32_t cfg; -}; - enum { EBC0_CFGADDR =3D 0x012, EBC0_CFGDATA =3D 0x013, }; =20 -static uint32_t dcr_read_ebc (void *opaque, int dcrn) +static uint32_t dcr_read_ebc(void *opaque, int dcrn) { - ppc4xx_ebc_t *ebc; + Ppc405EbcState *ebc =3D opaque; uint32_t ret; =20 - ebc =3D opaque; switch (dcrn) { case EBC0_CFGADDR: ret =3D ebc->addr; @@ -494,11 +482,10 @@ static uint32_t dcr_read_ebc (void *opaque, int dcrn) return ret; } =20 -static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val) +static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val) { - ppc4xx_ebc_t *ebc; + Ppc405EbcState *ebc =3D opaque; =20 - ebc =3D opaque; switch (dcrn) { case EBC0_CFGADDR: ebc->addr =3D val; @@ -554,12 +541,11 @@ static void dcr_write_ebc (void *opaque, int dcrn, ui= nt32_t val) } } =20 -static void ebc_reset (void *opaque) +static void ppc405_ebc_reset(DeviceState *dev) { - ppc4xx_ebc_t *ebc; + Ppc405EbcState *ebc =3D PPC405_EBC(dev); int i; =20 - ebc =3D opaque; ebc->addr =3D 0x00000000; ebc->bap[0] =3D 0x7F8FFE80; ebc->bcr[0] =3D 0xFFE28000; @@ -572,16 +558,23 @@ static void ebc_reset (void *opaque) ebc->cfg =3D 0x80400000; } =20 -void ppc405_ebc_init(CPUPPCState *env) +static void ppc405_ebc_realize(DeviceState *dev, Error **errp) { - ppc4xx_ebc_t *ebc; - - ebc =3D g_new0(ppc4xx_ebc_t, 1); - qemu_register_reset(&ebc_reset, ebc); - ppc_dcr_register(env, EBC0_CFGADDR, - ebc, &dcr_read_ebc, &dcr_write_ebc); - ppc_dcr_register(env, EBC0_CFGDATA, - ebc, &dcr_read_ebc, &dcr_write_ebc); + Ppc405EbcState *ebc =3D PPC405_EBC(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); + + ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_= ebc); + ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_= ebc); +} + +static void ppc405_ebc_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc405_ebc_realize; + dc->reset =3D ppc405_ebc_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; } =20 /*************************************************************************= ****/ @@ -1375,6 +1368,8 @@ static void ppc405_soc_instance_init(Object *obj) object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO); =20 object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA); + + object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC); } =20 static void ppc405_reset(void *opaque) @@ -1441,7 +1436,9 @@ static void ppc405_soc_realize(DeviceState *dev, Erro= r **errp) s->do_dram_init); =20 /* External bus controller */ - ppc405_ebc_init(env); + if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) { + return; + } =20 /* DMA controller */ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->dma), &s->cpu, errp)) { @@ -1523,6 +1520,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { + .name =3D TYPE_PPC405_EBC, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc405EbcState), + .class_init =3D ppc405_ebc_class_init, + }, { .name =3D TYPE_PPC405_DMA, .parent =3D TYPE_PPC4xx_DCR_DEVICE, .instance_size =3D sizeof(Ppc405DmaState), diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 0357ee077f..320c61a7f3 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -371,7 +371,9 @@ static void sam460ex_init(MachineState *machine) qdev_get_gpio_in(uic[0], 3)); =20 /* External bus controller */ - ppc405_ebc_init(env); + dev =3D qdev_new(TYPE_PPC405_EBC); + ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); + object_unref(OBJECT(dev)); =20 /* CPR */ ppc4xx_cpr_init(env); --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660405857844504.97093092044315; Sat, 13 Aug 2022 08:50:57 -0700 (PDT) Received: from localhost ([::1]:59540 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtPc-0005WR-R8 for importer@patchew.org; Sat, 13 Aug 2022 11:50:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52650) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9r-00009h-4N; Sat, 13 Aug 2022 11:34:39 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:28315) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9p-0006JS-0f; Sat, 13 Aug 2022 11:34:38 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 897A9748190; Sat, 13 Aug 2022 17:34:35 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 5FE8F74818E; Sat, 13 Aug 2022 17:34:35 +0200 (CEST) Message-Id: <26b4a16795147e820f3be480f6bb1456865755d5.1660402839.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 08/22] ppc/ppc405: QOM'ify OPBA MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:35 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660405858676100001 From: C=C3=A9dric Le Goater The OPB arbitrer is currently modeled as a simple SysBus device with a unique memory region. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 12 +++++++++++ hw/ppc/ppc405_uc.c | 49 +++++++++++++++++++++++++++------------------ hw/ppc/trace-events | 1 - 3 files changed, 41 insertions(+), 21 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 82bf8dae93..d63c2acdc7 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; =20 +/* OPB arbitrer */ +#define TYPE_PPC405_OPBA "ppc405-opba" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA); +struct Ppc405OpbaState { + SysBusDevice parent_obj; + + MemoryRegion io; + uint8_t cr; + uint8_t pr; +}; + /* Peripheral controller */ #define TYPE_PPC405_EBC "ppc405-ebc" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC); @@ -208,6 +219,7 @@ struct Ppc405SoCState { Ppc405GpioState gpio; Ppc405DmaState dma; Ppc405EbcState ebc; + Ppc405OpbaState opba; }; =20 /* PowerPC 405 core */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index f259de07e2..911ec958c6 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -310,16 +310,9 @@ static void ppc4xx_pob_init(CPUPPCState *env) =20 /*************************************************************************= ****/ /* OPB arbitrer */ -typedef struct ppc4xx_opba_t ppc4xx_opba_t; -struct ppc4xx_opba_t { - MemoryRegion io; - uint8_t cr; - uint8_t pr; -}; - static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) { - ppc4xx_opba_t *opba =3D opaque; + Ppc405OpbaState *opba =3D opaque; uint32_t ret; =20 switch (addr) { @@ -341,7 +334,7 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, u= nsigned size) static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - ppc4xx_opba_t *opba =3D opaque; + Ppc405OpbaState *opba =3D opaque; =20 trace_opba_writeb(addr, value); =20 @@ -366,25 +359,30 @@ static const MemoryRegionOps opba_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void ppc4xx_opba_reset (void *opaque) +static void ppc405_opba_reset(DeviceState *dev) { - ppc4xx_opba_t *opba; + Ppc405OpbaState *opba =3D PPC405_OPBA(dev); =20 - opba =3D opaque; opba->cr =3D 0x00; /* No dynamic priorities - park disabled */ opba->pr =3D 0x11; } =20 -static void ppc4xx_opba_init(hwaddr base) +static void ppc405_opba_realize(DeviceState *dev, Error **errp) { - ppc4xx_opba_t *opba; + Ppc405OpbaState *s =3D PPC405_OPBA(dev); + + memory_region_init_io(&s->io, OBJECT(s), &opba_ops, s, "opba", 2); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io); +} =20 - trace_opba_init(base); +static void ppc405_opba_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - opba =3D g_new0(ppc4xx_opba_t, 1); - memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002); - memory_region_add_subregion(get_system_memory(), base, &opba->io); - qemu_register_reset(ppc4xx_opba_reset, opba); + dc->realize =3D ppc405_opba_realize; + dc->reset =3D ppc405_opba_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; } =20 /*************************************************************************= ****/ @@ -1370,6 +1368,8 @@ static void ppc405_soc_instance_init(Object *obj) object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA); =20 object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC); + + object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA); } =20 static void ppc405_reset(void *opaque) @@ -1407,7 +1407,11 @@ static void ppc405_soc_realize(DeviceState *dev, Err= or **errp) ppc4xx_pob_init(env); =20 /* OBP arbitrer */ - ppc4xx_opba_init(0xef600600); + sbd =3D SYS_BUS_DEVICE(&s->opba); + if (!sysbus_realize(sbd, errp)) { + return; + } + sysbus_mmio_map(sbd, 0, 0xef600600); =20 /* Universal interrupt controller */ s->uic =3D qdev_new(TYPE_PPC_UIC); @@ -1520,6 +1524,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { + .name =3D TYPE_PPC405_OPBA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Ppc405OpbaState), + .class_init =3D ppc405_opba_class_init, + }, { .name =3D TYPE_PPC405_EBC, .parent =3D TYPE_PPC4xx_DCR_DEVICE, .instance_size =3D sizeof(Ppc405EbcState), diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index 66fbf0e035..38b62e9348 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -150,7 +150,6 @@ ppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint= 32_t size) "addr 0x%" PRI # ppc405_boards.c opba_readb(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " =3D 0x%" PRIx32 opba_writeb(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " =3D 0x%" PRIx= 64 -opba_init(uint64_t addr) "offet 0x%" PRIx64 =20 ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d" ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" P= RIx64 " size %d =3D 0x%" PRIx64 --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166040534738355.97050836961114; Sat, 13 Aug 2022 08:42:27 -0700 (PDT) Received: from localhost ([::1]:42556 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtHO-00024A-5p for importer@patchew.org; Sat, 13 Aug 2022 11:42:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52680) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9t-0000Gv-7A; Sat, 13 Aug 2022 11:34:41 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:28324) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9r-0006K4-6u; Sat, 13 Aug 2022 11:34:40 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 97075748197; Sat, 13 Aug 2022 17:34:36 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 6D9DC74818E; Sat, 13 Aug 2022 17:34:36 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 09/22] ppc/ppc405: QOM'ify POB MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:36 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660405348260100003 From: C=C3=A9dric Le Goater POB is currently modeled as a simple DCR device. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 12 ++++++++++ hw/ppc/ppc405_uc.c | 56 ++++++++++++++++++++++++++-------------------- 2 files changed, 44 insertions(+), 24 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index d63c2acdc7..4140e811d5 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; =20 +/* PLB to OPB bridge */ +#define TYPE_PPC405_POB "ppc405-pob" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB); +struct Ppc405PobState { + Ppc4xxDcrDeviceState parent_obj; + + uint32_t bear; + uint32_t besr0; + uint32_t besr1; +}; + /* OPB arbitrer */ #define TYPE_PPC405_OPBA "ppc405-opba" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA); @@ -220,6 +231,7 @@ struct Ppc405SoCState { Ppc405DmaState dma; Ppc405EbcState ebc; Ppc405OpbaState opba; + Ppc405PobState pob; }; =20 /* PowerPC 405 core */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 911ec958c6..0ad1cce790 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -234,19 +234,11 @@ enum { POB0_BEAR =3D 0x0A4, }; =20 -typedef struct ppc4xx_pob_t ppc4xx_pob_t; -struct ppc4xx_pob_t { - uint32_t bear; - uint32_t besr0; - uint32_t besr1; -}; - -static uint32_t dcr_read_pob (void *opaque, int dcrn) +static uint32_t dcr_read_pob(void *opaque, int dcrn) { - ppc4xx_pob_t *pob; + Ppc405PobState *pob =3D opaque; uint32_t ret; =20 - pob =3D opaque; switch (dcrn) { case POB0_BEAR: ret =3D pob->bear; @@ -266,11 +258,10 @@ static uint32_t dcr_read_pob (void *opaque, int dcrn) return ret; } =20 -static void dcr_write_pob (void *opaque, int dcrn, uint32_t val) +static void dcr_write_pob(void *opaque, int dcrn, uint32_t val) { - ppc4xx_pob_t *pob; + Ppc405PobState *pob =3D opaque; =20 - pob =3D opaque; switch (dcrn) { case POB0_BEAR: /* Read only */ @@ -286,26 +277,34 @@ static void dcr_write_pob (void *opaque, int dcrn, ui= nt32_t val) } } =20 -static void ppc4xx_pob_reset (void *opaque) +static void ppc405_pob_reset(DeviceState *dev) { - ppc4xx_pob_t *pob; + Ppc405PobState *pob =3D PPC405_POB(dev); =20 - pob =3D opaque; /* No error */ pob->bear =3D 0x00000000; pob->besr0 =3D 0x0000000; pob->besr1 =3D 0x0000000; } =20 -static void ppc4xx_pob_init(CPUPPCState *env) +static void ppc405_pob_realize(DeviceState *dev, Error **errp) +{ + Ppc405PobState *pob =3D PPC405_POB(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); + + ppc4xx_dcr_register(dcr, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob= ); + ppc4xx_dcr_register(dcr, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_po= b); + ppc4xx_dcr_register(dcr, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_po= b); +} + +static void ppc405_pob_class_init(ObjectClass *oc, void *data) { - ppc4xx_pob_t *pob; + DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - pob =3D g_new0(ppc4xx_pob_t, 1); - ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); - ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); - ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); - qemu_register_reset(ppc4xx_pob_reset, pob); + dc->realize =3D ppc405_pob_realize; + dc->reset =3D ppc405_pob_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; } =20 /*************************************************************************= ****/ @@ -1370,6 +1369,8 @@ static void ppc405_soc_instance_init(Object *obj) object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC); =20 object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA); + + object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB); } =20 static void ppc405_reset(void *opaque) @@ -1404,7 +1405,9 @@ static void ppc405_soc_realize(DeviceState *dev, Erro= r **errp) ppc4xx_plb_init(env); =20 /* PLB to OPB bridge */ - ppc4xx_pob_init(env); + if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->pob), &s->cpu, errp)) { + return; + } =20 /* OBP arbitrer */ sbd =3D SYS_BUS_DEVICE(&s->opba); @@ -1524,6 +1527,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { + .name =3D TYPE_PPC405_POB, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc405PobState), + .class_init =3D ppc405_pob_class_init, + }, { .name =3D TYPE_PPC405_OPBA, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(Ppc405OpbaState), --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166040601414993.5336401156842; Sat, 13 Aug 2022 08:53:34 -0700 (PDT) Received: from localhost ([::1]:38248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtS9-0001ya-5w for importer@patchew.org; Sat, 13 Aug 2022 11:53:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9t-0000HL-CI; Sat, 13 Aug 2022 11:34:41 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:28325) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9r-0006K6-BR; Sat, 13 Aug 2022 11:34:41 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id A42BE74819A; Sat, 13 Aug 2022 17:34:37 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 77B8E74818E; Sat, 13 Aug 2022 17:34:37 +0200 (CEST) Message-Id: <7da700adf02a625045f4d272d04872f943207635.1660402839.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 10/22] ppc/ppc405: QOM'ify PLB MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:37 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660406015372100001 From: C=C3=A9dric Le Goater PLB is currently modeled as a simple DCR device. Also drop the ppc4xx_plb_init() helper and adapt the sam460ex machine. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 14 ++++++++-- hw/ppc/ppc405_uc.c | 64 ++++++++++++++++++++++++++-------------------- hw/ppc/sam460ex.c | 4 ++- 3 files changed, 51 insertions(+), 31 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 4140e811d5..cb34792daf 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; =20 +/* Peripheral local bus arbitrer */ +#define TYPE_PPC405_PLB "ppc405-plb" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB); +struct Ppc405PlbState { + Ppc4xxDcrDeviceState parent_obj; + + uint32_t acr; + uint32_t bear; + uint32_t besr; +}; + /* PLB to OPB bridge */ #define TYPE_PPC405_POB "ppc405-pob" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB); @@ -232,11 +243,10 @@ struct Ppc405SoCState { Ppc405EbcState ebc; Ppc405OpbaState opba; Ppc405PobState pob; + Ppc405PlbState plb; }; =20 /* PowerPC 405 core */ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size); =20 -void ppc4xx_plb_init(CPUPPCState *env); - #endif /* PPC405_H */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 0ad1cce790..94ea6b5b70 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -148,19 +148,11 @@ enum { PLB4A1_ACR =3D 0x089, }; =20 -typedef struct ppc4xx_plb_t ppc4xx_plb_t; -struct ppc4xx_plb_t { - uint32_t acr; - uint32_t bear; - uint32_t besr; -}; - -static uint32_t dcr_read_plb (void *opaque, int dcrn) +static uint32_t dcr_read_plb(void *opaque, int dcrn) { - ppc4xx_plb_t *plb; + Ppc405PlbState *plb =3D opaque; uint32_t ret; =20 - plb =3D opaque; switch (dcrn) { case PLB0_ACR: ret =3D plb->acr; @@ -180,11 +172,10 @@ static uint32_t dcr_read_plb (void *opaque, int dcrn) return ret; } =20 -static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) +static void dcr_write_plb(void *opaque, int dcrn, uint32_t val) { - ppc4xx_plb_t *plb; + Ppc405PlbState *plb =3D opaque; =20 - plb =3D opaque; switch (dcrn) { case PLB0_ACR: /* We don't care about the actual parameters written as @@ -202,28 +193,36 @@ static void dcr_write_plb (void *opaque, int dcrn, ui= nt32_t val) } } =20 -static void ppc4xx_plb_reset (void *opaque) +static void ppc405_plb_reset(DeviceState *dev) { - ppc4xx_plb_t *plb; + Ppc405PlbState *plb =3D PPC405_PLB(dev); =20 - plb =3D opaque; plb->acr =3D 0x00000000; plb->bear =3D 0x00000000; plb->besr =3D 0x00000000; } =20 -void ppc4xx_plb_init(CPUPPCState *env) +static void ppc405_plb_realize(DeviceState *dev, Error **errp) +{ + Ppc405PlbState *plb =3D PPC405_PLB(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); + + ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_pl= b); + ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_pl= b); + ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); + ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb= ); + ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb= ); + ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_pl= b); +} + +static void ppc405_plb_class_init(ObjectClass *oc, void *data) { - ppc4xx_plb_t *plb; - - plb =3D g_new0(ppc4xx_plb_t, 1); - ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); - ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); - ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); - ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); - ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); - ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); - qemu_register_reset(ppc4xx_plb_reset, plb); + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc405_plb_realize; + dc->reset =3D ppc405_plb_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; } =20 /*************************************************************************= ****/ @@ -1371,6 +1370,8 @@ static void ppc405_soc_instance_init(Object *obj) object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA); =20 object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB); + + object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB); } =20 static void ppc405_reset(void *opaque) @@ -1402,7 +1403,9 @@ static void ppc405_soc_realize(DeviceState *dev, Erro= r **errp) } =20 /* PLB arbitrer */ - ppc4xx_plb_init(env); + if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->plb), &s->cpu, errp)) { + return; + } =20 /* PLB to OPB bridge */ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->pob), &s->cpu, errp)) { @@ -1527,6 +1530,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { + .name =3D TYPE_PPC405_PLB, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc405PlbState), + .class_init =3D ppc405_plb_class_init, + }, { .name =3D TYPE_PPC405_POB, .parent =3D TYPE_PPC4xx_DCR_DEVICE, .instance_size =3D sizeof(Ppc405PobState), diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 320c61a7f3..31139c1554 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -309,7 +309,9 @@ static void sam460ex_init(MachineState *machine) ppc_dcr_init(env, NULL, NULL); =20 /* PLB arbitrer */ - ppc4xx_plb_init(env); + dev =3D qdev_new(TYPE_PPC405_PLB); + ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); + object_unref(OBJECT(dev)); =20 /* interrupt controllers */ for (i =3D 0; i < ARRAY_SIZE(uic); i++) { --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660406316003608.497619650997; Sat, 13 Aug 2022 08:58:36 -0700 (PDT) Received: from localhost ([::1]:53006 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtX0-0003yx-Aa for importer@patchew.org; Sat, 13 Aug 2022 11:58:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52724) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9w-0000St-Ap; Sat, 13 Aug 2022 11:34:44 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:28327) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9t-0006KX-M8; Sat, 13 Aug 2022 11:34:44 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id D0ABB748191; Sat, 13 Aug 2022 17:34:38 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 835B274818E; Sat, 13 Aug 2022 17:34:38 +0200 (CEST) Message-Id: <61905349d9e9c07f37373e3a4d77f47b607dab19.1660402839.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 11/22] ppc/ppc405: QOM'ify MAL MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:38 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660406316975100001 From: C=C3=A9dric Le Goater The Memory Access Layer (MAL) controller is currently modeled as a DCR device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt the sam460ex machine. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 1 + hw/ppc/ppc405_uc.c | 17 +++-- hw/ppc/ppc4xx_devs.c | 145 ++++++++++++++++++++-------------------- hw/ppc/sam460ex.c | 12 ++-- include/hw/ppc/ppc4xx.h | 28 +++++++- 5 files changed, 117 insertions(+), 86 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index cb34792daf..31c94e4742 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -244,6 +244,7 @@ struct Ppc405SoCState { Ppc405OpbaState opba; Ppc405PobState pob; Ppc405PlbState plb; + Ppc4xxMalState mal; }; =20 /* PowerPC 405 core */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 94ea6b5b70..922c23346f 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1372,6 +1372,8 @@ static void ppc405_soc_instance_init(Object *obj) object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB); =20 object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB); + + object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL); } =20 static void ppc405_reset(void *opaque) @@ -1382,7 +1384,6 @@ static void ppc405_reset(void *opaque) static void ppc405_soc_realize(DeviceState *dev, Error **errp) { Ppc405SoCState *s =3D PPC405_SOC(dev); - qemu_irq mal_irqs[4]; CPUPPCState *env; SysBusDevice *sbd; int i; @@ -1500,11 +1501,15 @@ static void ppc405_soc_realize(DeviceState *dev, Er= ror **errp) } =20 /* MAL */ - mal_irqs[0] =3D qdev_get_gpio_in(s->uic, 11); - mal_irqs[1] =3D qdev_get_gpio_in(s->uic, 12); - mal_irqs[2] =3D qdev_get_gpio_in(s->uic, 13); - mal_irqs[3] =3D qdev_get_gpio_in(s->uic, 14); - ppc4xx_mal_init(env, 4, 2, mal_irqs); + object_property_set_int(OBJECT(&s->mal), "txc-num", 4, &error_abort); + object_property_set_int(OBJECT(&s->mal), "rxc-num", 2, &error_abort); + if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->mal), &s->cpu, errp)) { + return; + } + sbd =3D SYS_BUS_DEVICE(&s->mal); + for (i =3D 0; i < ARRAY_SIZE(s->mal.irqs); i++) { + sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 11 + i)); + } =20 /* Ethernet */ /* Uses UIC IRQs 9, 15, 17 */ diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index f4d7ae9567..7d40c1b68a 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -459,32 +459,10 @@ enum { MAL0_RCBS1 =3D 0x1E1, }; =20 -typedef struct ppc4xx_mal_t ppc4xx_mal_t; -struct ppc4xx_mal_t { - qemu_irq irqs[4]; - uint32_t cfg; - uint32_t esr; - uint32_t ier; - uint32_t txcasr; - uint32_t txcarr; - uint32_t txeobisr; - uint32_t txdeir; - uint32_t rxcasr; - uint32_t rxcarr; - uint32_t rxeobisr; - uint32_t rxdeir; - uint32_t *txctpr; - uint32_t *rxctpr; - uint32_t *rcbs; - uint8_t txcnum; - uint8_t rxcnum; -}; - -static void ppc4xx_mal_reset(void *opaque) +static void ppc4xx_mal_reset(DeviceState *dev) { - ppc4xx_mal_t *mal; + Ppc4xxMalState *mal =3D PPC4xx_MAL(dev); =20 - mal =3D opaque; mal->cfg =3D 0x0007C000; mal->esr =3D 0x00000000; mal->ier =3D 0x00000000; @@ -498,10 +476,9 @@ static void ppc4xx_mal_reset(void *opaque) =20 static uint32_t dcr_read_mal(void *opaque, int dcrn) { - ppc4xx_mal_t *mal; + Ppc4xxMalState *mal =3D opaque; uint32_t ret; =20 - mal =3D opaque; switch (dcrn) { case MAL0_CFG: ret =3D mal->cfg; @@ -555,13 +532,12 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn) =20 static void dcr_write_mal(void *opaque, int dcrn, uint32_t val) { - ppc4xx_mal_t *mal; + Ppc4xxMalState *mal =3D opaque; =20 - mal =3D opaque; switch (dcrn) { case MAL0_CFG: if (val & 0x80000000) { - ppc4xx_mal_reset(mal); + ppc4xx_mal_reset(DEVICE(mal)); } mal->cfg =3D val & 0x00FFC087; break; @@ -612,59 +588,76 @@ static void dcr_write_mal(void *opaque, int dcrn, uin= t32_t val) } } =20 -void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum, - qemu_irq irqs[4]) +static void ppc4xx_mal_realize(DeviceState *dev, Error **errp) { - ppc4xx_mal_t *mal; + Ppc4xxMalState *mal =3D PPC4xx_MAL(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); int i; =20 - assert(txcnum <=3D 32 && rxcnum <=3D 32); - mal =3D g_malloc0(sizeof(*mal)); - mal->txcnum =3D txcnum; - mal->rxcnum =3D rxcnum; - mal->txctpr =3D g_new0(uint32_t, txcnum); - mal->rxctpr =3D g_new0(uint32_t, rxcnum); - mal->rcbs =3D g_new0(uint32_t, rxcnum); - for (i =3D 0; i < 4; i++) { - mal->irqs[i] =3D irqs[i]; + if (mal->txcnum > 32 || mal->rxcnum > 32) { + error_setg(errp, "invalid TXC/RXC number"); + return; + } + + mal->txctpr =3D g_new0(uint32_t, mal->txcnum); + mal->rxctpr =3D g_new0(uint32_t, mal->rxcnum); + mal->rcbs =3D g_new0(uint32_t, mal->rxcnum); + + for (i =3D 0; i < ARRAY_SIZE(mal->irqs); i++) { + sysbus_init_irq(SYS_BUS_DEVICE(dev), &mal->irqs[i]); } - qemu_register_reset(&ppc4xx_mal_reset, mal); - ppc_dcr_register(env, MAL0_CFG, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_ESR, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_IER, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_TXCASR, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_TXCARR, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_TXEOBISR, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_TXDEIR, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_RXCASR, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_RXCARR, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_RXEOBISR, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_RXDEIR, - mal, &dcr_read_mal, &dcr_write_mal); - for (i =3D 0; i < txcnum; i++) { - ppc_dcr_register(env, MAL0_TXCTP0R + i, - mal, &dcr_read_mal, &dcr_write_mal); + + ppc4xx_dcr_register(dcr, MAL0_CFG, mal, &dcr_read_mal, &dcr_write_mal); + ppc4xx_dcr_register(dcr, MAL0_ESR, mal, &dcr_read_mal, &dcr_write_mal); + ppc4xx_dcr_register(dcr, MAL0_IER, mal, &dcr_read_mal, &dcr_write_mal); + ppc4xx_dcr_register(dcr, MAL0_TXCASR, mal, &dcr_read_mal, &dcr_write_m= al); + ppc4xx_dcr_register(dcr, MAL0_TXCARR, mal, &dcr_read_mal, &dcr_write_m= al); + ppc4xx_dcr_register(dcr, MAL0_TXEOBISR, mal, &dcr_read_mal, &dcr_write= _mal); + ppc4xx_dcr_register(dcr, MAL0_TXDEIR, mal, &dcr_read_mal, &dcr_write_m= al); + ppc4xx_dcr_register(dcr, MAL0_RXCASR, mal, &dcr_read_mal, &dcr_write_m= al); + ppc4xx_dcr_register(dcr, MAL0_RXCARR, mal, &dcr_read_mal, &dcr_write_m= al); + ppc4xx_dcr_register(dcr, MAL0_RXEOBISR, mal, &dcr_read_mal, &dcr_write= _mal); + ppc4xx_dcr_register(dcr, MAL0_RXDEIR, mal, &dcr_read_mal, &dcr_write_m= al); + for (i =3D 0; i < mal->txcnum; i++) { + ppc4xx_dcr_register(dcr, MAL0_TXCTP0R + i, + mal, &dcr_read_mal, &dcr_write_mal); } - for (i =3D 0; i < rxcnum; i++) { - ppc_dcr_register(env, MAL0_RXCTP0R + i, - mal, &dcr_read_mal, &dcr_write_mal); + for (i =3D 0; i < mal->rxcnum; i++) { + ppc4xx_dcr_register(dcr, MAL0_RXCTP0R + i, + mal, &dcr_read_mal, &dcr_write_mal); } - for (i =3D 0; i < rxcnum; i++) { - ppc_dcr_register(env, MAL0_RCBS0 + i, - mal, &dcr_read_mal, &dcr_write_mal); + for (i =3D 0; i < mal->rxcnum; i++) { + ppc4xx_dcr_register(dcr, MAL0_RCBS0 + i, + mal, &dcr_read_mal, &dcr_write_mal); } } =20 +static void ppc4xx_mal_finalize(Object *obj) +{ + Ppc4xxMalState *mal =3D PPC4xx_MAL(obj); + + g_free(mal->rcbs); + g_free(mal->rxctpr); + g_free(mal->txctpr); +} + +static Property ppc4xx_mal_properties[] =3D { + DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0), + DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ppc4xx_mal_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc4xx_mal_realize; + dc->reset =3D ppc4xx_mal_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; + device_class_set_props(dc, ppc4xx_mal_properties); +} + /* PPC4xx_DCR_DEVICE */ =20 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, @@ -696,6 +689,12 @@ static void ppc4xx_dcr_class_init(ObjectClass *oc, voi= d *data) =20 static const TypeInfo ppc4xx_types[] =3D { { + .name =3D TYPE_PPC4xx_MAL, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc4xxMalState), + .instance_finalize =3D ppc4xx_mal_finalize, + .class_init =3D ppc4xx_mal_class_init, + }, { .name =3D TYPE_PPC4xx_DCR_DEVICE, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(Ppc4xxDcrDeviceState), diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 31139c1554..c16303462d 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -280,7 +280,6 @@ static void sam460ex_init(MachineState *machine) hwaddr ram_sizes[SDRAM_NR_BANKS] =3D {0}; MemoryRegion *l2cache_ram =3D g_new(MemoryRegion, 1); DeviceState *uic[4]; - qemu_irq mal_irqs[4]; int i; PCIBus *pci_bus; PowerPCCPU *cpu; @@ -387,10 +386,15 @@ static void sam460ex_init(MachineState *machine) ppc4xx_sdr_init(env); =20 /* MAL */ - for (i =3D 0; i < ARRAY_SIZE(mal_irqs); i++) { - mal_irqs[i] =3D qdev_get_gpio_in(uic[2], 3 + i); + dev =3D qdev_new(TYPE_PPC4xx_MAL); + qdev_prop_set_uint32(dev, "txc-num", 4); + qdev_prop_set_uint32(dev, "rxc-num", 16); + ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); + object_unref(OBJECT(dev)); + sbdev =3D SYS_BUS_DEVICE(dev); + for (i =3D 0; i < ARRAY_SIZE(PPC4xx_MAL(dev)->irqs); i++) { + sysbus_connect_irq(sbdev, i, qdev_get_gpio_in(uic[2], 3 + i)); } - ppc4xx_mal_init(env, 4, 16, mal_irqs); =20 /* DMA */ ppc4xx_dma_init(env, 0x200); diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index a537a5567b..f40bd49bc7 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -40,9 +40,6 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, i= nt nbanks, hwaddr *ram_sizes, int do_init); =20 -void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum, - qemu_irq irqs[4]); - #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" =20 /* @@ -61,4 +58,29 @@ void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int = dcrn, void *opaque, bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, Error **errp); =20 +/* Memory Access Layer (MAL) */ +#define TYPE_PPC4xx_MAL "ppc4xx-mal" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL); +struct Ppc4xxMalState { + Ppc4xxDcrDeviceState parent_obj; + + qemu_irq irqs[4]; + uint32_t cfg; + uint32_t esr; + uint32_t ier; + uint32_t txcasr; + uint32_t txcarr; + uint32_t txeobisr; + uint32_t txdeir; + uint32_t rxcasr; + uint32_t rxcarr; + uint32_t rxeobisr; + uint32_t rxdeir; + uint32_t *txctpr; + uint32_t *rxctpr; + uint32_t *rcbs; + uint8_t txcnum; + uint8_t rxcnum; +}; + #endif /* PPC4XX_H */ --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660406146724876.6064814416937; Sat, 13 Aug 2022 08:55:46 -0700 (PDT) Received: from localhost ([::1]:45730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtUH-0007Au-KQ for importer@patchew.org; Sat, 13 Aug 2022 11:55:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9v-0000PE-A4; Sat, 13 Aug 2022 11:34:43 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:28332) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9t-0006Ko-7I; Sat, 13 Aug 2022 11:34:43 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id BFD87748194; Sat, 13 Aug 2022 17:34:39 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 8ED1574818E; Sat, 13 Aug 2022 17:34:39 +0200 (CEST) Message-Id: <3f182ba0e89eeea855516cf3651fb8cc4cf9b546.1660402839.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 12/22] ppc4xx: Move PLB model to ppc4xx_devs.c MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:39 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660406148051100001 Content-Type: text/plain; charset="utf-8" The PLB is shared between 405 and 440 so move it to the shared file. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 11 ----- hw/ppc/ppc405_uc.c | 93 ---------------------------------------- hw/ppc/ppc4xx_devs.c | 94 +++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/ppc4xx.h | 11 +++++ 4 files changed, 105 insertions(+), 104 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 31c94e4742..d85c595f9d 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,17 +63,6 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; =20 -/* Peripheral local bus arbitrer */ -#define TYPE_PPC405_PLB "ppc405-plb" -OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB); -struct Ppc405PlbState { - Ppc4xxDcrDeviceState parent_obj; - - uint32_t acr; - uint32_t bear; - uint32_t besr; -}; - /* PLB to OPB bridge */ #define TYPE_PPC405_POB "ppc405-pob" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB); diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 922c23346f..3de6c77631 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -137,94 +137,6 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_a= ddr_t ram_size) /*************************************************************************= ****/ /* Shared peripherals */ =20 -/*************************************************************************= ****/ -/* Peripheral local bus arbitrer */ -enum { - PLB3A0_ACR =3D 0x077, - PLB4A0_ACR =3D 0x081, - PLB0_BESR =3D 0x084, - PLB0_BEAR =3D 0x086, - PLB0_ACR =3D 0x087, - PLB4A1_ACR =3D 0x089, -}; - -static uint32_t dcr_read_plb(void *opaque, int dcrn) -{ - Ppc405PlbState *plb =3D opaque; - uint32_t ret; - - switch (dcrn) { - case PLB0_ACR: - ret =3D plb->acr; - break; - case PLB0_BEAR: - ret =3D plb->bear; - break; - case PLB0_BESR: - ret =3D plb->besr; - break; - default: - /* Avoid gcc warning */ - ret =3D 0; - break; - } - - return ret; -} - -static void dcr_write_plb(void *opaque, int dcrn, uint32_t val) -{ - Ppc405PlbState *plb =3D opaque; - - switch (dcrn) { - case PLB0_ACR: - /* We don't care about the actual parameters written as - * we don't manage any priorities on the bus - */ - plb->acr =3D val & 0xF8000000; - break; - case PLB0_BEAR: - /* Read only */ - break; - case PLB0_BESR: - /* Write-clear */ - plb->besr &=3D ~val; - break; - } -} - -static void ppc405_plb_reset(DeviceState *dev) -{ - Ppc405PlbState *plb =3D PPC405_PLB(dev); - - plb->acr =3D 0x00000000; - plb->bear =3D 0x00000000; - plb->besr =3D 0x00000000; -} - -static void ppc405_plb_realize(DeviceState *dev, Error **errp) -{ - Ppc405PlbState *plb =3D PPC405_PLB(dev); - Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); - - ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_pl= b); - ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_pl= b); - ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); - ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb= ); - ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb= ); - ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_pl= b); -} - -static void ppc405_plb_class_init(ObjectClass *oc, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(oc); - - dc->realize =3D ppc405_plb_realize; - dc->reset =3D ppc405_plb_reset; - /* Reason: only works as function of a ppc4xx SoC */ - dc->user_creatable =3D false; -} - /*************************************************************************= ****/ /* PLB to OPB bridge */ enum { @@ -1535,11 +1447,6 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { - .name =3D TYPE_PPC405_PLB, - .parent =3D TYPE_PPC4xx_DCR_DEVICE, - .instance_size =3D sizeof(Ppc405PlbState), - .class_init =3D ppc405_plb_class_init, - }, { .name =3D TYPE_PPC405_POB, .parent =3D TYPE_PPC4xx_DCR_DEVICE, .instance_size =3D sizeof(Ppc405PobState), diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 7d40c1b68a..843d759b1b 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -658,6 +658,95 @@ static void ppc4xx_mal_class_init(ObjectClass *oc, voi= d *data) device_class_set_props(dc, ppc4xx_mal_properties); } =20 +/*************************************************************************= ****/ +/* Peripheral local bus arbitrer */ +enum { + PLB3A0_ACR =3D 0x077, + PLB4A0_ACR =3D 0x081, + PLB0_BESR =3D 0x084, + PLB0_BEAR =3D 0x086, + PLB0_ACR =3D 0x087, + PLB4A1_ACR =3D 0x089, +}; + +static uint32_t dcr_read_plb(void *opaque, int dcrn) +{ + Ppc405PlbState *plb =3D opaque; + uint32_t ret; + + switch (dcrn) { + case PLB0_ACR: + ret =3D plb->acr; + break; + case PLB0_BEAR: + ret =3D plb->bear; + break; + case PLB0_BESR: + ret =3D plb->besr; + break; + default: + /* Avoid gcc warning */ + ret =3D 0; + break; + } + + return ret; +} + +static void dcr_write_plb(void *opaque, int dcrn, uint32_t val) +{ + Ppc405PlbState *plb =3D opaque; + + switch (dcrn) { + case PLB0_ACR: + /* + * We don't care about the actual parameters written as + * we don't manage any priorities on the bus + */ + plb->acr =3D val & 0xF8000000; + break; + case PLB0_BEAR: + /* Read only */ + break; + case PLB0_BESR: + /* Write-clear */ + plb->besr &=3D ~val; + break; + } +} + +static void ppc405_plb_reset(DeviceState *dev) +{ + Ppc405PlbState *plb =3D PPC405_PLB(dev); + + plb->acr =3D 0x00000000; + plb->bear =3D 0x00000000; + plb->besr =3D 0x00000000; +} + +static void ppc405_plb_realize(DeviceState *dev, Error **errp) +{ + Ppc405PlbState *plb =3D PPC405_PLB(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); + + ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_pl= b); + ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_pl= b); + ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); + ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb= ); + ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb= ); + ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_pl= b); +} + +static void ppc405_plb_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc405_plb_realize; + dc->reset =3D ppc405_plb_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; +} + /* PPC4xx_DCR_DEVICE */ =20 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, @@ -694,6 +783,11 @@ static const TypeInfo ppc4xx_types[] =3D { .instance_size =3D sizeof(Ppc4xxMalState), .instance_finalize =3D ppc4xx_mal_finalize, .class_init =3D ppc4xx_mal_class_init, + }, { + .name =3D TYPE_PPC405_PLB, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc405PlbState), + .class_init =3D ppc405_plb_class_init, }, { .name =3D TYPE_PPC4xx_DCR_DEVICE, .parent =3D TYPE_SYS_BUS_DEVICE, diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index f40bd49bc7..e696e159f3 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -83,4 +83,15 @@ struct Ppc4xxMalState { uint8_t rxcnum; }; =20 +/* Peripheral local bus arbitrer */ +#define TYPE_PPC405_PLB "ppc405-plb" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB); +struct Ppc405PlbState { + Ppc4xxDcrDeviceState parent_obj; + + uint32_t acr; + uint32_t bear; + uint32_t besr; +}; + #endif /* PPC4XX_H */ --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660405852173720.2853236690528; Sat, 13 Aug 2022 08:50:52 -0700 (PDT) Received: from localhost ([::1]:59106 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtPV-0005Bd-VL for importer@patchew.org; Sat, 13 Aug 2022 11:50:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9x-0000Vx-46; Sat, 13 Aug 2022 11:34:45 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:28337) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9u-0006L5-Ax; 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charset="utf-8" The EBC is shared between 405 and 440 so move it to shared file. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 15 ---- hw/ppc/ppc405_uc.c | 191 ---------------------------------------- hw/ppc/ppc4xx_devs.c | 191 ++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/ppc4xx.h | 15 ++++ 4 files changed, 206 insertions(+), 206 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index d85c595f9d..c0251f0894 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -85,21 +85,6 @@ struct Ppc405OpbaState { uint8_t pr; }; =20 -/* Peripheral controller */ -#define TYPE_PPC405_EBC "ppc405-ebc" -OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC); -struct Ppc405EbcState { - Ppc4xxDcrDeviceState parent_obj; - - uint32_t addr; - uint32_t bcr[8]; - uint32_t bap[8]; - uint32_t bear; - uint32_t besr0; - uint32_t besr1; - uint32_t cfg; -}; - /* DMA controller */ #define TYPE_PPC405_DMA "ppc405-dma" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA); diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 3de6c77631..01625e3237 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -299,192 +299,6 @@ static void ppc405_opba_class_init(ObjectClass *oc, v= oid *data) /* Code decompression controller */ /* XXX: TODO */ =20 -/*************************************************************************= ****/ -/* Peripheral controller */ -enum { - EBC0_CFGADDR =3D 0x012, - EBC0_CFGDATA =3D 0x013, -}; - -static uint32_t dcr_read_ebc(void *opaque, int dcrn) -{ - Ppc405EbcState *ebc =3D opaque; - uint32_t ret; - - switch (dcrn) { - case EBC0_CFGADDR: - ret =3D ebc->addr; - break; - case EBC0_CFGDATA: - switch (ebc->addr) { - case 0x00: /* B0CR */ - ret =3D ebc->bcr[0]; - break; - case 0x01: /* B1CR */ - ret =3D ebc->bcr[1]; - break; - case 0x02: /* B2CR */ - ret =3D ebc->bcr[2]; - break; - case 0x03: /* B3CR */ - ret =3D ebc->bcr[3]; - break; - case 0x04: /* B4CR */ - ret =3D ebc->bcr[4]; - break; - case 0x05: /* B5CR */ - ret =3D ebc->bcr[5]; - break; - case 0x06: /* B6CR */ - ret =3D ebc->bcr[6]; - break; - case 0x07: /* B7CR */ - ret =3D ebc->bcr[7]; - break; - case 0x10: /* B0AP */ - ret =3D ebc->bap[0]; - break; - case 0x11: /* B1AP */ - ret =3D ebc->bap[1]; - break; - case 0x12: /* B2AP */ - ret =3D ebc->bap[2]; - break; - case 0x13: /* B3AP */ - ret =3D ebc->bap[3]; - break; - case 0x14: /* B4AP */ - ret =3D ebc->bap[4]; - break; - case 0x15: /* B5AP */ - ret =3D ebc->bap[5]; - break; - case 0x16: /* B6AP */ - ret =3D ebc->bap[6]; - break; - case 0x17: /* B7AP */ - ret =3D ebc->bap[7]; - break; - case 0x20: /* BEAR */ - ret =3D ebc->bear; - break; - case 0x21: /* BESR0 */ - ret =3D ebc->besr0; - break; - case 0x22: /* BESR1 */ - ret =3D ebc->besr1; - break; - case 0x23: /* CFG */ - ret =3D ebc->cfg; - break; - default: - ret =3D 0x00000000; - break; - } - break; - default: - ret =3D 0x00000000; - break; - } - - return ret; -} - -static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val) -{ - Ppc405EbcState *ebc =3D opaque; - - switch (dcrn) { - case EBC0_CFGADDR: - ebc->addr =3D val; - break; - case EBC0_CFGDATA: - switch (ebc->addr) { - case 0x00: /* B0CR */ - break; - case 0x01: /* B1CR */ - break; - case 0x02: /* B2CR */ - break; - case 0x03: /* B3CR */ - break; - case 0x04: /* B4CR */ - break; - case 0x05: /* B5CR */ - break; - case 0x06: /* B6CR */ - break; - case 0x07: /* B7CR */ - break; - case 0x10: /* B0AP */ - break; - case 0x11: /* B1AP */ - break; - case 0x12: /* B2AP */ - break; - case 0x13: /* B3AP */ - break; - case 0x14: /* B4AP */ - break; - case 0x15: /* B5AP */ - break; - case 0x16: /* B6AP */ - break; - case 0x17: /* B7AP */ - break; - case 0x20: /* BEAR */ - break; - case 0x21: /* BESR0 */ - break; - case 0x22: /* BESR1 */ - break; - case 0x23: /* CFG */ - break; - default: - break; - } - break; - default: - break; - } -} - -static void ppc405_ebc_reset(DeviceState *dev) -{ - Ppc405EbcState *ebc =3D PPC405_EBC(dev); - int i; - - ebc->addr =3D 0x00000000; - ebc->bap[0] =3D 0x7F8FFE80; - ebc->bcr[0] =3D 0xFFE28000; - for (i =3D 0; i < 8; i++) { - ebc->bap[i] =3D 0x00000000; - ebc->bcr[i] =3D 0x00000000; - } - ebc->besr0 =3D 0x00000000; - ebc->besr1 =3D 0x00000000; - ebc->cfg =3D 0x80400000; -} - -static void ppc405_ebc_realize(DeviceState *dev, Error **errp) -{ - Ppc405EbcState *ebc =3D PPC405_EBC(dev); - Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); - - ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_= ebc); - ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_= ebc); -} - -static void ppc405_ebc_class_init(ObjectClass *oc, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(oc); - - dc->realize =3D ppc405_ebc_realize; - dc->reset =3D ppc405_ebc_reset; - /* Reason: only works as function of a ppc4xx SoC */ - dc->user_creatable =3D false; -} - /*************************************************************************= ****/ /* DMA controller */ enum { @@ -1456,11 +1270,6 @@ static const TypeInfo ppc405_types[] =3D { .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(Ppc405OpbaState), .class_init =3D ppc405_opba_class_init, - }, { - .name =3D TYPE_PPC405_EBC, - .parent =3D TYPE_PPC4xx_DCR_DEVICE, - .instance_size =3D sizeof(Ppc405EbcState), - .class_init =3D ppc405_ebc_class_init, }, { .name =3D TYPE_PPC405_DMA, .parent =3D TYPE_PPC4xx_DCR_DEVICE, diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 843d759b1b..96941ae040 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -747,6 +747,192 @@ static void ppc405_plb_class_init(ObjectClass *oc, vo= id *data) dc->user_creatable =3D false; } =20 +/*************************************************************************= ****/ +/* Peripheral controller */ +enum { + EBC0_CFGADDR =3D 0x012, + EBC0_CFGDATA =3D 0x013, +}; + +static uint32_t dcr_read_ebc(void *opaque, int dcrn) +{ + Ppc405EbcState *ebc =3D opaque; + uint32_t ret; + + switch (dcrn) { + case EBC0_CFGADDR: + ret =3D ebc->addr; + break; + case EBC0_CFGDATA: + switch (ebc->addr) { + case 0x00: /* B0CR */ + ret =3D ebc->bcr[0]; + break; + case 0x01: /* B1CR */ + ret =3D ebc->bcr[1]; + break; + case 0x02: /* B2CR */ + ret =3D ebc->bcr[2]; + break; + case 0x03: /* B3CR */ + ret =3D ebc->bcr[3]; + break; + case 0x04: /* B4CR */ + ret =3D ebc->bcr[4]; + break; + case 0x05: /* B5CR */ + ret =3D ebc->bcr[5]; + break; + case 0x06: /* B6CR */ + ret =3D ebc->bcr[6]; + break; + case 0x07: /* B7CR */ + ret =3D ebc->bcr[7]; + break; + case 0x10: /* B0AP */ + ret =3D ebc->bap[0]; + break; + case 0x11: /* B1AP */ + ret =3D ebc->bap[1]; + break; + case 0x12: /* B2AP */ + ret =3D ebc->bap[2]; + break; + case 0x13: /* B3AP */ + ret =3D ebc->bap[3]; + break; + case 0x14: /* B4AP */ + ret =3D ebc->bap[4]; + break; + case 0x15: /* B5AP */ + ret =3D ebc->bap[5]; + break; + case 0x16: /* B6AP */ + ret =3D ebc->bap[6]; + break; + case 0x17: /* B7AP */ + ret =3D ebc->bap[7]; + break; + case 0x20: /* BEAR */ + ret =3D ebc->bear; + break; + case 0x21: /* BESR0 */ + ret =3D ebc->besr0; + break; + case 0x22: /* BESR1 */ + ret =3D ebc->besr1; + break; + case 0x23: /* CFG */ + ret =3D ebc->cfg; + break; + default: + ret =3D 0x00000000; + break; + } + break; + default: + ret =3D 0x00000000; + break; + } + + return ret; +} + +static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val) +{ + Ppc405EbcState *ebc =3D opaque; + + switch (dcrn) { + case EBC0_CFGADDR: + ebc->addr =3D val; + break; + case EBC0_CFGDATA: + switch (ebc->addr) { + case 0x00: /* B0CR */ + break; + case 0x01: /* B1CR */ + break; + case 0x02: /* B2CR */ + break; + case 0x03: /* B3CR */ + break; + case 0x04: /* B4CR */ + break; + case 0x05: /* B5CR */ + break; + case 0x06: /* B6CR */ + break; + case 0x07: /* B7CR */ + break; + case 0x10: /* B0AP */ + break; + case 0x11: /* B1AP */ + break; + case 0x12: /* B2AP */ + break; + case 0x13: /* B3AP */ + break; + case 0x14: /* B4AP */ + break; + case 0x15: /* B5AP */ + break; + case 0x16: /* B6AP */ + break; + case 0x17: /* B7AP */ + break; + case 0x20: /* BEAR */ + break; + case 0x21: /* BESR0 */ + break; + case 0x22: /* BESR1 */ + break; + case 0x23: /* CFG */ + break; + default: + break; + } + break; + default: + break; + } +} + +static void ppc405_ebc_reset(DeviceState *dev) +{ + Ppc405EbcState *ebc =3D PPC405_EBC(dev); + int i; + + ebc->addr =3D 0x00000000; + ebc->bap[0] =3D 0x7F8FFE80; + ebc->bcr[0] =3D 0xFFE28000; + for (i =3D 0; i < 8; i++) { + ebc->bap[i] =3D 0x00000000; + ebc->bcr[i] =3D 0x00000000; + } + ebc->besr0 =3D 0x00000000; + ebc->besr1 =3D 0x00000000; + ebc->cfg =3D 0x80400000; +} + +static void ppc405_ebc_realize(DeviceState *dev, Error **errp) +{ + Ppc405EbcState *ebc =3D PPC405_EBC(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); + + ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_= ebc); + ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_= ebc); +} + +static void ppc405_ebc_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc405_ebc_realize; + dc->reset =3D ppc405_ebc_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; +} + /* PPC4xx_DCR_DEVICE */ =20 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, @@ -788,6 +974,11 @@ static const TypeInfo ppc4xx_types[] =3D { .parent =3D TYPE_PPC4xx_DCR_DEVICE, .instance_size =3D sizeof(Ppc405PlbState), .class_init =3D ppc405_plb_class_init, + }, { + .name =3D TYPE_PPC405_EBC, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc405EbcState), + .class_init =3D ppc405_ebc_class_init, }, { .name =3D TYPE_PPC4xx_DCR_DEVICE, .parent =3D TYPE_SYS_BUS_DEVICE, diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index e696e159f3..6e361cf254 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -94,4 +94,19 @@ struct Ppc405PlbState { uint32_t besr; }; =20 +/* Peripheral controller */ +#define TYPE_PPC405_EBC "ppc405-ebc" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC); +struct Ppc405EbcState { + Ppc4xxDcrDeviceState parent_obj; + + uint32_t addr; + uint32_t bcr[8]; + uint32_t bap[8]; + uint32_t bear; + uint32_t besr0; + uint32_t besr1; + uint32_t cfg; +}; + #endif /* PPC4XX_H */ --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660406008487247.88771118247314; Sat, 13 Aug 2022 08:53:28 -0700 (PDT) Received: from localhost ([::1]:37922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtS3-0001kn-Gk for importer@patchew.org; Sat, 13 Aug 2022 11:53:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52742) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9x-0000XN-IN; Sat, 13 Aug 2022 11:34:45 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:28342) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9v-0006LN-Fd; Sat, 13 Aug 2022 11:34:45 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id DD44174819C; Sat, 13 Aug 2022 17:34:41 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id B0E8674818E; Sat, 13 Aug 2022 17:34:41 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 14/22] ppc/ppc405: Use an embedded PPCUIC model in SoC state MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:41 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660406009365100001 From: C=C3=A9dric Le Goater Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 3 ++- hw/ppc/ppc405_uc.c | 28 ++++++++++++++-------------- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index c0251f0894..5bcbce2893 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -27,6 +27,7 @@ =20 #include "qom/object.h" #include "hw/ppc/ppc4xx.h" +#include "hw/intc/ppc-uic.h" =20 #define PPC405EP_SDRAM_BASE 0x00000000 #define PPC405EP_NVRAM_BASE 0xF0000000 @@ -208,7 +209,7 @@ struct Ppc405SoCState { hwaddr ram_size; =20 PowerPCCPU cpu; - DeviceState *uic; + PPCUIC uic; Ppc405CpcState cpc; Ppc405GptState gpt; Ppc405OcmState ocm; diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 01625e3237..82830f52bf 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1080,6 +1080,8 @@ static void ppc405_soc_instance_init(Object *obj) object_initialize_child(obj, "cpu", &s->cpu, POWERPC_CPU_TYPE_NAME("405ep")); =20 + object_initialize_child(obj, "uic", &s->uic, TYPE_PPC_UIC); + object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC); object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk"); =20 @@ -1147,17 +1149,15 @@ static void ppc405_soc_realize(DeviceState *dev, Er= ror **errp) sysbus_mmio_map(sbd, 0, 0xef600600); =20 /* Universal interrupt controller */ - s->uic =3D qdev_new(TYPE_PPC_UIC); - - object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu), + object_property_set_link(OBJECT(&s->uic), "cpu", OBJECT(&s->cpu), &error_fatal); - if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) { + sbd =3D SYS_BUS_DEVICE(&s->uic); + if (!sysbus_realize(sbd, errp)) { return; } - - sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT, + sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT)= ); - sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT, + sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT, qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT= )); =20 /* SDRAM controller */ @@ -1168,7 +1168,7 @@ static void ppc405_soc_realize(DeviceState *dev, Erro= r **errp) "ppc405.sdram0", s->dram_mr, s->ram_bases[0], s->ram_sizes[0]); =20 - ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 1, + ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1, s->ram_banks, s->ram_bases, s->ram_sizes, s->do_dram_init); =20 @@ -1183,12 +1183,12 @@ static void ppc405_soc_realize(DeviceState *dev, Er= ror **errp) } sbd =3D SYS_BUS_DEVICE(&s->dma); for (i =3D 0; i < ARRAY_SIZE(s->dma.irqs); i++) { - sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 5 + i)); + sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 5 + i= )); } =20 /* I2C controller */ sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, - qdev_get_gpio_in(s->uic, 2)); + qdev_get_gpio_in(DEVICE(&s->uic), 2)); =20 /* GPIO */ sbd =3D SYS_BUS_DEVICE(&s->gpio); @@ -1200,13 +1200,13 @@ static void ppc405_soc_realize(DeviceState *dev, Er= ror **errp) /* Serial ports */ if (serial_hd(0) !=3D NULL) { serial_mm_init(get_system_memory(), 0xef600300, 0, - qdev_get_gpio_in(s->uic, 0), + qdev_get_gpio_in(DEVICE(&s->uic), 0), PPC_SERIAL_MM_BAUDBASE, serial_hd(0), DEVICE_BIG_ENDIAN); } if (serial_hd(1) !=3D NULL) { serial_mm_init(get_system_memory(), 0xef600400, 0, - qdev_get_gpio_in(s->uic, 1), + qdev_get_gpio_in(DEVICE(&s->uic), 1), PPC_SERIAL_MM_BAUDBASE, serial_hd(1), DEVICE_BIG_ENDIAN); } @@ -1223,7 +1223,7 @@ static void ppc405_soc_realize(DeviceState *dev, Erro= r **errp) } sysbus_mmio_map(sbd, 0, 0xef600000); for (i =3D 0; i < ARRAY_SIZE(s->gpt.irqs); i++) { - sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 19 + i)); + sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 19 + = i)); } =20 /* MAL */ @@ -1234,7 +1234,7 @@ static void ppc405_soc_realize(DeviceState *dev, Erro= r **errp) } sbd =3D SYS_BUS_DEVICE(&s->mal); for (i =3D 0; i < ARRAY_SIZE(s->mal.irqs); i++) { - sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 11 + i)); + sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 11 + = i)); } =20 /* Ethernet */ --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660406600532938.3596623715196; Sat, 13 Aug 2022 09:03:20 -0700 (PDT) Received: from localhost ([::1]:59070 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtba-0008Kh-SR for importer@patchew.org; Sat, 13 Aug 2022 12:03:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52778) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9z-0000dK-Ps; Sat, 13 Aug 2022 11:34:47 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:28347) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9w-0006Lb-FR; Sat, 13 Aug 2022 11:34:47 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 09F5074819D; Sat, 13 Aug 2022 17:34:43 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id C95A874818E; Sat, 13 Aug 2022 17:34:42 +0200 (CEST) Message-Id: <221c889d9c783397dce54390cf6fcc3f3b194d22.1660402839.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 15/22] hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:42 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660406602823100001 Content-Type: text/plain; charset="utf-8" Make ppc-uic a subclass of ppc4xx-dcr-device which will handle the cpu link and make it uniform with the other PPC4xx devices. Signed-off-by: BALATON Zoltan Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/ppc-uic.c | 26 ++++++-------------------- hw/ppc/ppc405_uc.c | 6 ++---- hw/ppc/ppc440_bamboo.c | 7 ++----- hw/ppc/ppc4xx_devs.c | 1 - hw/ppc/sam460ex.c | 17 +++++++---------- hw/ppc/virtex_ml507.c | 7 ++----- include/hw/intc/ppc-uic.h | 6 ++---- 7 files changed, 21 insertions(+), 49 deletions(-) diff --git a/hw/intc/ppc-uic.c b/hw/intc/ppc-uic.c index 60013f2dde..dcf5de5d43 100644 --- a/hw/intc/ppc-uic.c +++ b/hw/intc/ppc-uic.c @@ -25,11 +25,8 @@ #include "qemu/osdep.h" #include "hw/intc/ppc-uic.h" #include "hw/irq.h" -#include "cpu.h" -#include "hw/ppc/ppc.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" -#include "qapi/error.h" =20 enum { DCR_UICSR =3D 0x000, @@ -105,10 +102,9 @@ static void ppcuic_trigger_irq(PPCUIC *uic) =20 static void ppcuic_set_irq(void *opaque, int irq_num, int level) { - PPCUIC *uic; + PPCUIC *uic =3D opaque; uint32_t mask, sr; =20 - uic =3D opaque; mask =3D 1U << (31 - irq_num); LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32 " mask %08" PRIx32 " =3D> %08" PRIx32 " %08" PRIx32 "\n", @@ -144,10 +140,9 @@ static void ppcuic_set_irq(void *opaque, int irq_num, = int level) =20 static uint32_t dcr_read_uic(void *opaque, int dcrn) { - PPCUIC *uic; + PPCUIC *uic =3D opaque; uint32_t ret; =20 - uic =3D opaque; dcrn -=3D uic->dcr_base; switch (dcrn) { case DCR_UICSR: @@ -192,9 +187,8 @@ static uint32_t dcr_read_uic(void *opaque, int dcrn) =20 static void dcr_write_uic(void *opaque, int dcrn, uint32_t val) { - PPCUIC *uic; + PPCUIC *uic =3D opaque; =20 - uic =3D opaque; dcrn -=3D uic->dcr_base; LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val); switch (dcrn) { @@ -251,19 +245,12 @@ static void ppc_uic_reset(DeviceState *dev) static void ppc_uic_realize(DeviceState *dev, Error **errp) { PPCUIC *uic =3D PPC_UIC(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); - PowerPCCPU *cpu; int i; =20 - if (!uic->cpu) { - /* This is a programming error in the code using this device */ - error_setg(errp, "ppc-uic 'cpu' link property was not set"); - return; - } - - cpu =3D POWERPC_CPU(uic->cpu); for (i =3D 0; i < DCR_UICMAX; i++) { - ppc_dcr_register(&cpu->env, uic->dcr_base + i, uic, + ppc4xx_dcr_register(dcr, uic->dcr_base + i, uic, &dcr_read_uic, &dcr_write_uic); } =20 @@ -273,7 +260,6 @@ static void ppc_uic_realize(DeviceState *dev, Error **e= rrp) } =20 static Property ppc_uic_properties[] =3D { - DEFINE_PROP_LINK("cpu", PPCUIC, cpu, TYPE_CPU, CPUState *), DEFINE_PROP_UINT32("dcr-base", PPCUIC, dcr_base, 0xc0), DEFINE_PROP_BOOL("use-vectors", PPCUIC, use_vectors, true), DEFINE_PROP_END_OF_LIST() @@ -308,7 +294,7 @@ static void ppc_uic_class_init(ObjectClass *klass, void= *data) =20 static const TypeInfo ppc_uic_info =3D { .name =3D TYPE_PPC_UIC, - .parent =3D TYPE_SYS_BUS_DEVICE, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, .instance_size =3D sizeof(PPCUIC), .class_init =3D ppc_uic_class_init, }; diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 82830f52bf..aa3617f876 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1149,12 +1149,10 @@ static void ppc405_soc_realize(DeviceState *dev, Er= ror **errp) sysbus_mmio_map(sbd, 0, 0xef600600); =20 /* Universal interrupt controller */ - object_property_set_link(OBJECT(&s->uic), "cpu", OBJECT(&s->cpu), - &error_fatal); - sbd =3D SYS_BUS_DEVICE(&s->uic); - if (!sysbus_realize(sbd, errp)) { + if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->uic), &s->cpu, errp)) { return; } + sbd =3D SYS_BUS_DEVICE(&s->uic); sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT)= ); sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT, diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 873f930c77..b14a9ef776 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -193,12 +193,9 @@ static void bamboo_init(MachineState *machine) =20 /* interrupt controller */ uicdev =3D qdev_new(TYPE_PPC_UIC); + ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uicdev), cpu, &error_fatal); + object_unref(OBJECT(uicdev)); uicsbd =3D SYS_BUS_DEVICE(uicdev); - - object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), - &error_fatal); - sysbus_realize_and_unref(uicsbd, &error_fatal); - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT)); sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 96941ae040..49793b56cd 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -29,7 +29,6 @@ #include "hw/irq.h" #include "hw/ppc/ppc.h" #include "hw/ppc/ppc4xx.h" -#include "hw/intc/ppc-uic.h" #include "hw/qdev-properties.h" #include "qemu/log.h" #include "exec/address-spaces.h" diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index c16303462d..c96de98690 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -314,7 +314,6 @@ static void sam460ex_init(MachineState *machine) =20 /* interrupt controllers */ for (i =3D 0; i < ARRAY_SIZE(uic); i++) { - SysBusDevice *sbd; /* * UICs 1, 2 and 3 are cascaded through UIC 0. * input_ints[n] is the interrupt number on UIC 0 which @@ -326,22 +325,20 @@ static void sam460ex_init(MachineState *machine) const int input_ints[] =3D { -1, 30, 10, 16 }; =20 uic[i] =3D qdev_new(TYPE_PPC_UIC); - sbd =3D SYS_BUS_DEVICE(uic[i]); - qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10); - object_property_set_link(OBJECT(uic[i]), "cpu", OBJECT(cpu), - &error_fatal); - sysbus_realize_and_unref(sbd, &error_fatal); + ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uic[i]), cpu, &error_fatal); + object_unref(OBJECT(uic[i])); =20 + sbdev =3D SYS_BUS_DEVICE(uic[i]); if (i =3D=3D 0) { - sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, + sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT, qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_IN= T)); - sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT, + sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT, qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CI= NT)); } else { - sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, + sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT, qdev_get_gpio_in(uic[0], input_ints[i])); - sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT, + sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT, qdev_get_gpio_in(uic[0], input_ints[i] + 1)= ); } } diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index 53b126ff48..493ea0c19f 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -104,12 +104,9 @@ static PowerPCCPU *ppc440_init_xilinx(const char *cpu_= type, uint32_t sysclk) =20 /* interrupt controller */ uicdev =3D qdev_new(TYPE_PPC_UIC); + ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uicdev), cpu, &error_fatal); + object_unref(OBJECT(uicdev)); uicsbd =3D SYS_BUS_DEVICE(uicdev); - - object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), - &error_fatal); - sysbus_realize_and_unref(uicsbd, &error_fatal); - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT)); sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, diff --git a/include/hw/intc/ppc-uic.h b/include/hw/intc/ppc-uic.h index 22dd5e5ac2..4d82e9a3c6 100644 --- a/include/hw/intc/ppc-uic.h +++ b/include/hw/intc/ppc-uic.h @@ -25,8 +25,7 @@ #ifndef HW_INTC_PPC_UIC_H #define HW_INTC_PPC_UIC_H =20 -#include "hw/sysbus.h" -#include "qom/object.h" +#include "hw/ppc/ppc4xx.h" =20 #define TYPE_PPC_UIC "ppc-uic" OBJECT_DECLARE_SIMPLE_TYPE(PPCUIC, PPC_UIC) @@ -56,14 +55,13 @@ enum { =20 struct PPCUIC { /*< private >*/ - SysBusDevice parent_obj; + Ppc4xxDcrDeviceState parent_obj; =20 /*< public >*/ qemu_irq output_int; qemu_irq output_cint; =20 /* properties */ - CPUState *cpu; uint32_t dcr_base; bool use_vectors; =20 --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660405755676950.0375519851219; Sat, 13 Aug 2022 08:49:15 -0700 (PDT) Received: from localhost ([::1]:55264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtNw-0002SD-LI for importer@patchew.org; Sat, 13 Aug 2022 11:49:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52784) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMtA0-0000fH-7H; Sat, 13 Aug 2022 11:34:48 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:28352) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9x-0006Lo-GZ; Sat, 13 Aug 2022 11:34:47 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id F273374819A; Sat, 13 Aug 2022 17:34:43 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id D3EC474818E; Sat, 13 Aug 2022 17:34:43 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 16/22] ppc/ppc405: Use an explicit I2C object MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:43 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660405756239100001 From: C=C3=A9dric Le Goater Having an explicit I2C model object will help if one day we want to add I2C devices on the bus from the machine init routine. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 2 ++ hw/ppc/ppc405_uc.c | 10 ++++++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 5bcbce2893..12eee97169 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -28,6 +28,7 @@ #include "qom/object.h" #include "hw/ppc/ppc4xx.h" #include "hw/intc/ppc-uic.h" +#include "hw/i2c/ppc4xx_i2c.h" =20 #define PPC405EP_SDRAM_BASE 0x00000000 #define PPC405EP_NVRAM_BASE 0xF0000000 @@ -215,6 +216,7 @@ struct Ppc405SoCState { Ppc405OcmState ocm; Ppc405GpioState gpio; Ppc405DmaState dma; + PPC4xxI2CState i2c; Ppc405EbcState ebc; Ppc405OpbaState opba; Ppc405PobState pob; diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index aa3617f876..a7a7d7e65b 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1093,6 +1093,8 @@ static void ppc405_soc_instance_init(Object *obj) =20 object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA); =20 + object_initialize_child(obj, "i2c", &s->i2c, TYPE_PPC4xx_I2C); + object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC); =20 object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA); @@ -1185,8 +1187,12 @@ static void ppc405_soc_realize(DeviceState *dev, Err= or **errp) } =20 /* I2C controller */ - sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, - qdev_get_gpio_in(DEVICE(&s->uic), 2)); + sbd =3D SYS_BUS_DEVICE(&s->i2c); + if (!sysbus_realize(sbd, errp)) { + return; + } + sysbus_mmio_map(sbd, 0, 0xef600500); + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(DEVICE(&s->uic), 2)); =20 /* GPIO */ sbd =3D SYS_BUS_DEVICE(&s->gpio); --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660406117003731.6769145396363; Sat, 13 Aug 2022 08:55:17 -0700 (PDT) Received: from localhost ([::1]:44642 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtTn-0006R1-1N for importer@patchew.org; Sat, 13 Aug 2022 11:55:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52796) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMtA1-0000iC-Bp; Sat, 13 Aug 2022 11:34:49 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:28359) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9y-0006M4-IZ; Sat, 13 Aug 2022 11:34:49 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 1138A748191; Sat, 13 Aug 2022 17:34:45 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id E1E3174818E; Sat, 13 Aug 2022 17:34:44 +0200 (CEST) Message-Id: <092ec66e749939f9c7ab3d1252012461366719ac.1660402839.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 17/22] ppc/ppc405: QOM'ify FPGA MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:44 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660406118026100001 From: C=C3=A9dric Le Goater Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405_boards.c | 56 +++++++++++++++++++++++++++++------------- 1 file changed, 39 insertions(+), 17 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 3677793adc..7af0d7feef 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -71,18 +71,23 @@ struct Ppc405MachineState { * - NVRAM (0xF0000000) * - FPGA (0xF0300000) */ -typedef struct ref405ep_fpga_t ref405ep_fpga_t; -struct ref405ep_fpga_t { + +#define TYPE_REF405EP_FPGA "ref405ep-fpga" +OBJECT_DECLARE_SIMPLE_TYPE(Ref405epFpgaState, REF405EP_FPGA); +struct Ref405epFpgaState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + uint8_t reg0; uint8_t reg1; }; =20 static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned si= ze) { - ref405ep_fpga_t *fpga; + Ref405epFpgaState *fpga =3D opaque; uint32_t ret; =20 - fpga =3D opaque; switch (addr) { case 0x0: ret =3D fpga->reg0; @@ -101,9 +106,8 @@ static uint64_t ref405ep_fpga_readb(void *opaque, hwadd= r addr, unsigned size) static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - ref405ep_fpga_t *fpga; + Ref405epFpgaState *fpga =3D opaque; =20 - fpga =3D opaque; switch (addr) { case 0x0: /* Read only */ @@ -126,27 +130,40 @@ static const MemoryRegionOps ref405ep_fpga_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void ref405ep_fpga_reset (void *opaque) +static void ref405ep_fpga_reset(DeviceState *dev) { - ref405ep_fpga_t *fpga; + Ref405epFpgaState *fpga =3D REF405EP_FPGA(dev); =20 - fpga =3D opaque; fpga->reg0 =3D 0x00; fpga->reg1 =3D 0x0F; } =20 -static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) +static void ref405ep_fpga_realize(DeviceState *dev, Error **errp) { - ref405ep_fpga_t *fpga; - MemoryRegion *fpga_memory =3D g_new(MemoryRegion, 1); + Ref405epFpgaState *s =3D REF405EP_FPGA(dev); =20 - fpga =3D g_new0(ref405ep_fpga_t, 1); - memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga, + memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s, "fpga", 0x00000100); - memory_region_add_subregion(sysmem, base, fpga_memory); - qemu_register_reset(&ref405ep_fpga_reset, fpga); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); +} + +static void ref405ep_fpga_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ref405ep_fpga_realize; + dc->reset =3D ref405ep_fpga_reset; + /* Reason: only works as part of a ppc405 board */ + dc->user_creatable =3D false; } =20 +static const TypeInfo ref405ep_fpga_type =3D { + .name =3D TYPE_REF405EP_FPGA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Ref405epFpgaState), + .class_init =3D ref405ep_fpga_class_init, +}; + /* * CPU reset handler when booting directly from a loaded kernel */ @@ -331,7 +348,11 @@ static void ref405ep_init(MachineState *machine) memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE, s= ram); =20 /* Register FPGA */ - ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE); + dev =3D qdev_new(TYPE_REF405EP_FPGA); + object_property_add_child(OBJECT(machine), "fpga", OBJECT(dev)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PPC405EP_FPGA_BASE); + /* Register NVRAM */ dev =3D qdev_new("sysbus-m48t08"); qdev_prop_set_int32(dev, "base-year", 1968); @@ -376,6 +397,7 @@ static void ppc405_machine_init(void) { type_register_static(&ppc405_machine_type); type_register_static(&ref405ep_type); + type_register_static(&ref405ep_fpga_type); } =20 type_init(ppc405_machine_init) --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660406303039389.4560817502605; Sat, 13 Aug 2022 08:58:23 -0700 (PDT) Received: from localhost ([::1]:52908 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtWn-0003uf-Uk for importer@patchew.org; Sat, 13 Aug 2022 11:58:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52814) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMtA2-0000lo-FS; Sat, 13 Aug 2022 11:34:50 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:28364) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9z-0006MI-Kp; Sat, 13 Aug 2022 11:34:50 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 33EA5748193; Sat, 13 Aug 2022 17:34:46 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id F0BC974818E; Sat, 13 Aug 2022 17:34:45 +0200 (CEST) Message-Id: <40e17a00dbfa6aadb1643a6362e415fa9f6daced.1660402839.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 18/22] ppc405: Move machine specific code to ppc405_boards.c MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:45 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660406305025100001 Content-Type: text/plain; charset="utf-8" These are only used by tha board code so move out from the shared SoC model and put it in the boards file. Signed-off-by: BALATON Zoltan Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/ppc405.h | 38 ----- hw/ppc/ppc405_boards.c | 375 +++++++++++++++++++++++++++-------------- hw/ppc/ppc405_uc.c | 92 ---------- 3 files changed, 251 insertions(+), 254 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 12eee97169..6b26fc6d17 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -30,41 +30,6 @@ #include "hw/intc/ppc-uic.h" #include "hw/i2c/ppc4xx_i2c.h" =20 -#define PPC405EP_SDRAM_BASE 0x00000000 -#define PPC405EP_NVRAM_BASE 0xF0000000 -#define PPC405EP_FPGA_BASE 0xF0300000 -#define PPC405EP_SRAM_BASE 0xFFF00000 -#define PPC405EP_SRAM_SIZE (512 * KiB) -#define PPC405EP_FLASH_BASE 0xFFF80000 - -/* Bootinfo as set-up by u-boot */ -typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t; -struct ppc4xx_bd_info_t { - uint32_t bi_memstart; - uint32_t bi_memsize; - uint32_t bi_flashstart; - uint32_t bi_flashsize; - uint32_t bi_flashoffset; /* 0x10 */ - uint32_t bi_sramstart; - uint32_t bi_sramsize; - uint32_t bi_bootflags; - uint32_t bi_ipaddr; /* 0x20 */ - uint8_t bi_enetaddr[6]; - uint16_t bi_ethspeed; - uint32_t bi_intfreq; - uint32_t bi_busfreq; /* 0x30 */ - uint32_t bi_baudrate; - uint8_t bi_s_version[4]; - uint8_t bi_r_version[32]; - uint32_t bi_procfreq; - uint32_t bi_plb_busfreq; - uint32_t bi_pci_busfreq; - uint8_t bi_pci_enetaddr[6]; - uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */ - uint32_t bi_opbfreq; - uint32_t bi_iic_fast[2]; -}; - /* PLB to OPB bridge */ #define TYPE_PPC405_POB "ppc405-pob" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB); @@ -224,7 +189,4 @@ struct Ppc405SoCState { Ppc4xxMalState mal; }; =20 -/* PowerPC 405 core */ -ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size); - #endif /* PPC405_H */ diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 7af0d7feef..083f12b23e 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -48,6 +48,10 @@ #define KERNEL_LOAD_ADDR 0x01000000 #define INITRD_LOAD_ADDR 0x01800000 =20 +#define PPC405EP_SDRAM_BASE 0x00000000 +#define PPC405EP_SRAM_BASE 0xFFF00000 +#define PPC405EP_SRAM_SIZE (512 * KiB) + #define USE_FLASH_BIOS =20 #define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405") @@ -61,112 +65,7 @@ struct Ppc405MachineState { Ppc405SoCState soc; }; =20 -/*************************************************************************= ****/ -/* PPC405EP reference board (IBM) */ -/* Standalone board with: - * - PowerPC 405EP CPU - * - SDRAM (0x00000000) - * - Flash (0xFFF80000) - * - SRAM (0xFFF00000) - * - NVRAM (0xF0000000) - * - FPGA (0xF0300000) - */ - -#define TYPE_REF405EP_FPGA "ref405ep-fpga" -OBJECT_DECLARE_SIMPLE_TYPE(Ref405epFpgaState, REF405EP_FPGA); -struct Ref405epFpgaState { - SysBusDevice parent_obj; - - MemoryRegion iomem; - - uint8_t reg0; - uint8_t reg1; -}; - -static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned si= ze) -{ - Ref405epFpgaState *fpga =3D opaque; - uint32_t ret; - - switch (addr) { - case 0x0: - ret =3D fpga->reg0; - break; - case 0x1: - ret =3D fpga->reg1; - break; - default: - ret =3D 0; - break; - } - - return ret; -} - -static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, - unsigned size) -{ - Ref405epFpgaState *fpga =3D opaque; - - switch (addr) { - case 0x0: - /* Read only */ - break; - case 0x1: - fpga->reg1 =3D value; - break; - default: - break; - } -} - -static const MemoryRegionOps ref405ep_fpga_ops =3D { - .read =3D ref405ep_fpga_readb, - .write =3D ref405ep_fpga_writeb, - .impl.min_access_size =3D 1, - .impl.max_access_size =3D 1, - .valid.min_access_size =3D 1, - .valid.max_access_size =3D 4, - .endianness =3D DEVICE_BIG_ENDIAN, -}; - -static void ref405ep_fpga_reset(DeviceState *dev) -{ - Ref405epFpgaState *fpga =3D REF405EP_FPGA(dev); - - fpga->reg0 =3D 0x00; - fpga->reg1 =3D 0x0F; -} - -static void ref405ep_fpga_realize(DeviceState *dev, Error **errp) -{ - Ref405epFpgaState *s =3D REF405EP_FPGA(dev); - - memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s, - "fpga", 0x00000100); - sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); -} - -static void ref405ep_fpga_class_init(ObjectClass *oc, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(oc); - - dc->realize =3D ref405ep_fpga_realize; - dc->reset =3D ref405ep_fpga_reset; - /* Reason: only works as part of a ppc405 board */ - dc->user_creatable =3D false; -} - -static const TypeInfo ref405ep_fpga_type =3D { - .name =3D TYPE_REF405EP_FPGA, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(Ref405epFpgaState), - .class_init =3D ref405ep_fpga_class_init, -}; - -/* - * CPU reset handler when booting directly from a loaded kernel - */ +/* CPU reset handler when booting directly from a loaded kernel */ static struct boot_info { uint32_t entry; uint32_t bdloc; @@ -197,6 +96,126 @@ static void main_cpu_reset(void *opaque) env->nip =3D bi->entry; } =20 +/* Bootinfo as set-up by u-boot */ +typedef struct { + uint32_t bi_memstart; + uint32_t bi_memsize; + uint32_t bi_flashstart; + uint32_t bi_flashsize; + uint32_t bi_flashoffset; /* 0x10 */ + uint32_t bi_sramstart; + uint32_t bi_sramsize; + uint32_t bi_bootflags; + uint32_t bi_ipaddr; /* 0x20 */ + uint8_t bi_enetaddr[6]; + uint16_t bi_ethspeed; + uint32_t bi_intfreq; + uint32_t bi_busfreq; /* 0x30 */ + uint32_t bi_baudrate; + uint8_t bi_s_version[4]; + uint8_t bi_r_version[32]; + uint32_t bi_procfreq; + uint32_t bi_plb_busfreq; + uint32_t bi_pci_busfreq; + uint8_t bi_pci_enetaddr[6]; + uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */ + uint32_t bi_opbfreq; + uint32_t bi_iic_fast[2]; +} ppc4xx_bd_info_t; + +static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd, + ram_addr_t ram_size) +{ + memset(bd, 0, sizeof(*bd)); + + bd->bi_memstart =3D PPC405EP_SDRAM_BASE; + bd->bi_memsize =3D ram_size; + bd->bi_sramstart =3D PPC405EP_SRAM_BASE; + bd->bi_sramsize =3D PPC405EP_SRAM_SIZE; + bd->bi_bootflags =3D 0; + bd->bi_intfreq =3D 133333333; + bd->bi_busfreq =3D 33333333; + bd->bi_baudrate =3D 115200; + bd->bi_s_version[0] =3D 'Q'; + bd->bi_s_version[1] =3D 'M'; + bd->bi_s_version[2] =3D 'U'; + bd->bi_s_version[3] =3D '\0'; + bd->bi_r_version[0] =3D 'Q'; + bd->bi_r_version[1] =3D 'E'; + bd->bi_r_version[2] =3D 'M'; + bd->bi_r_version[3] =3D 'U'; + bd->bi_r_version[4] =3D '\0'; + bd->bi_procfreq =3D 133333333; + bd->bi_plb_busfreq =3D 33333333; + bd->bi_pci_busfreq =3D 33333333; + bd->bi_opbfreq =3D 33333333; +} + +static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t= *bd) +{ + CPUState *cs =3D env_cpu(env); + ram_addr_t bdloc; + int i, n; + + /* We put the bd structure at the top of memory */ + if (bd->bi_memsize >=3D 0x01000000UL) { + bdloc =3D 0x01000000UL - sizeof(ppc4xx_bd_info_t); + } else { + bdloc =3D bd->bi_memsize - sizeof(ppc4xx_bd_info_t); + } + stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); + stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); + stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); + stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); + stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); + stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); + stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); + stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); + stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); + for (i =3D 0; i < 6; i++) { + stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); + } + stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); + stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); + stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); + stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); + for (i =3D 0; i < 4; i++) { + stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); + } + for (i =3D 0; i < 32; i++) { + stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); + } + stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq); + stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq); + stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq); + for (i =3D 0; i < 6; i++) { + stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]); + } + n =3D 0x70; /* includes 2 bytes hole */ + for (i =3D 0; i < 6; i++) { + stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); + } + stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); + n +=3D 4; + for (i =3D 0; i < 2; i++) { + stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); + n +=3D 4; + } + + return bdloc; +} + +static ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_siz= e) +{ + ppc4xx_bd_info_t bd; + + memset(&bd, 0, sizeof(bd)); + + ppc405_set_default_bootinfo(&bd, ram_size); + + return __ppc405_set_bootinfo(env, &bd); +} + static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; @@ -334,6 +353,132 @@ static void ppc405_init(MachineState *machine) } } =20 +static void ppc405_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "PPC405 generic machine"; + mc->init =3D ppc405_init; + mc->default_ram_size =3D 128 * MiB; + mc->default_ram_id =3D "ppc405.ram"; +} + +static const TypeInfo ppc405_machine_type =3D { + .name =3D TYPE_PPC405_MACHINE, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(Ppc405MachineState), + .class_init =3D ppc405_machine_class_init, + .abstract =3D true, +}; + +/*************************************************************************= ****/ +/* PPC405EP reference board (IBM) */ +/* + * Standalone board with: + * - PowerPC 405EP CPU + * - SDRAM (0x00000000) + * - Flash (0xFFF80000) + * - SRAM (0xFFF00000) + * - NVRAM (0xF0000000) + * - FPGA (0xF0300000) + */ + +#define PPC405EP_NVRAM_BASE 0xF0000000 +#define PPC405EP_FPGA_BASE 0xF0300000 +#define PPC405EP_FLASH_BASE 0xFFF80000 + +#define TYPE_REF405EP_FPGA "ref405ep-fpga" +OBJECT_DECLARE_SIMPLE_TYPE(Ref405epFpgaState, REF405EP_FPGA); +struct Ref405epFpgaState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + uint8_t reg0; + uint8_t reg1; +}; + +static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned si= ze) +{ + Ref405epFpgaState *fpga =3D opaque; + uint32_t ret; + + switch (addr) { + case 0x0: + ret =3D fpga->reg0; + break; + case 0x1: + ret =3D fpga->reg1; + break; + default: + ret =3D 0; + break; + } + + return ret; +} + +static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + Ref405epFpgaState *fpga =3D opaque; + + switch (addr) { + case 0x0: + /* Read only */ + break; + case 0x1: + fpga->reg1 =3D value; + break; + default: + break; + } +} + +static const MemoryRegionOps ref405ep_fpga_ops =3D { + .read =3D ref405ep_fpga_readb, + .write =3D ref405ep_fpga_writeb, + .impl.min_access_size =3D 1, + .impl.max_access_size =3D 1, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static void ref405ep_fpga_reset(DeviceState *dev) +{ + Ref405epFpgaState *fpga =3D REF405EP_FPGA(dev); + + fpga->reg0 =3D 0x00; + fpga->reg1 =3D 0x0F; +} + +static void ref405ep_fpga_realize(DeviceState *dev, Error **errp) +{ + Ref405epFpgaState *s =3D REF405EP_FPGA(dev); + + memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s, + "fpga", 0x00000100); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); +} + +static void ref405ep_fpga_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ref405ep_fpga_realize; + dc->reset =3D ref405ep_fpga_reset; + /* Reason: only works as part of a ppc405 board */ + dc->user_creatable =3D false; +} + +static const TypeInfo ref405ep_fpga_type =3D { + .name =3D TYPE_REF405EP_FPGA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Ref405epFpgaState), + .class_init =3D ref405ep_fpga_class_init, +}; + static void ref405ep_init(MachineState *machine) { DeviceState *dev; @@ -375,24 +520,6 @@ static const TypeInfo ref405ep_type =3D { .class_init =3D ref405ep_class_init, }; =20 -static void ppc405_machine_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - - mc->desc =3D "PPC405 generic machine"; - mc->init =3D ppc405_init; - mc->default_ram_size =3D 128 * MiB; - mc->default_ram_id =3D "ppc405.ram"; -} - -static const TypeInfo ppc405_machine_type =3D { - .name =3D TYPE_PPC405_MACHINE, - .parent =3D TYPE_MACHINE, - .instance_size =3D sizeof(Ppc405MachineState), - .class_init =3D ppc405_machine_class_init, - .abstract =3D true, -}; - static void ppc405_machine_init(void) { type_register_static(&ppc405_machine_type); diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index a7a7d7e65b..b13026200f 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -42,98 +42,6 @@ #include "qapi/error.h" #include "trace.h" =20 -static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd, - ram_addr_t ram_size) -{ - memset(bd, 0, sizeof(*bd)); - - bd->bi_memstart =3D PPC405EP_SDRAM_BASE; - bd->bi_memsize =3D ram_size; - bd->bi_sramstart =3D PPC405EP_SRAM_BASE; - bd->bi_sramsize =3D PPC405EP_SRAM_SIZE; - bd->bi_bootflags =3D 0; - bd->bi_intfreq =3D 133333333; - bd->bi_busfreq =3D 33333333; - bd->bi_baudrate =3D 115200; - bd->bi_s_version[0] =3D 'Q'; - bd->bi_s_version[1] =3D 'M'; - bd->bi_s_version[2] =3D 'U'; - bd->bi_s_version[3] =3D '\0'; - bd->bi_r_version[0] =3D 'Q'; - bd->bi_r_version[1] =3D 'E'; - bd->bi_r_version[2] =3D 'M'; - bd->bi_r_version[3] =3D 'U'; - bd->bi_r_version[4] =3D '\0'; - bd->bi_procfreq =3D 133333333; - bd->bi_plb_busfreq =3D 33333333; - bd->bi_pci_busfreq =3D 33333333; - bd->bi_opbfreq =3D 33333333; -} - -static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t= *bd) -{ - CPUState *cs =3D env_cpu(env); - ram_addr_t bdloc; - int i, n; - - /* We put the bd structure at the top of memory */ - if (bd->bi_memsize >=3D 0x01000000UL) - bdloc =3D 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); - else - bdloc =3D bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); - stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); - stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); - stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); - stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); - stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); - stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); - stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); - stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); - stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); - for (i =3D 0; i < 6; i++) { - stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); - } - stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); - stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); - stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); - stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); - for (i =3D 0; i < 4; i++) { - stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); - } - for (i =3D 0; i < 32; i++) { - stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); - } - stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq); - stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq); - stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq); - for (i =3D 0; i < 6; i++) { - stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]); - } - n =3D 0x70; /* includes 2 bytes hole */ - for (i =3D 0; i < 6; i++) { - stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); - } - stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); - n +=3D 4; - for (i =3D 0; i < 2; i++) { - stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); - n +=3D 4; - } - - return bdloc; -} - -ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size) -{ - ppc4xx_bd_info_t bd; - - memset(&bd, 0, sizeof(bd)); - - ppc405_set_default_bootinfo(&bd, ram_size); - - return __ppc405_set_bootinfo(env, &bd); -} - /*************************************************************************= ****/ /* Shared peripherals */ =20 --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660406997735508.1756597250427; Sat, 13 Aug 2022 09:09:57 -0700 (PDT) Received: from localhost ([::1]:39206 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMthy-00067R-7i for importer@patchew.org; Sat, 13 Aug 2022 12:09:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMtA2-0000kM-62; Sat, 13 Aug 2022 11:34:50 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:28369) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMtA0-0006MU-M4; Sat, 13 Aug 2022 11:34:49 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 28DE7748194; Sat, 13 Aug 2022 17:34:47 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 0D87A74818E; Sat, 13 Aug 2022 17:34:47 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 19/22] hw/ppc/Kconfig: Remove PPC405 dependency from sam460ex MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:47 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660406998960100001 Content-Type: text/plain; charset="utf-8" Now that shared PPC4xx devices are separated from PPC405 ones we can drop this depencency. Signed-off-by: BALATON Zoltan Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index 400511c6b7..205f9f98d7 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -58,7 +58,6 @@ config PPC4XX =20 config SAM460EX bool - select PPC405 select PFLASH_CFI01 select IDE_SII3112 select M41T80 --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16604054299695.931749395903012; Sat, 13 Aug 2022 08:43:49 -0700 (PDT) Received: from localhost ([::1]:47590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtIi-0005WA-Uf for importer@patchew.org; Sat, 13 Aug 2022 11:43:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52828) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMtA3-0000ph-Hf; Sat, 13 Aug 2022 11:34:51 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:28374) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMtA1-0006Mp-Tl; Sat, 13 Aug 2022 11:34:51 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 4744574819B; Sat, 13 Aug 2022 17:34:48 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 1772F74818E; Sat, 13 Aug 2022 17:34:48 +0200 (CEST) Message-Id: <4bd1f2f953fac2c70091446ec5805f41857c44fd.1660402839.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 20/22] hw/ppc/Kconfig: Move imply before select MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:48 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660405430607100001 Content-Type: text/plain; charset="utf-8" In pegasos2 section move imply before select to match other sections. Signed-off-by: BALATON Zoltan Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index 205f9f98d7..3a4418a69e 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -71,6 +71,7 @@ config SAM460EX =20 config PEGASOS2 bool + imply ATI_VGA select MV64361 select VT82C686 select IDE_VIA @@ -78,7 +79,6 @@ config PEGASOS2 select VOF # This should come with VT82C686 select ACPI_X86 - imply ATI_VGA =20 config PREP bool --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660407220661353.4008480678981; Sat, 13 Aug 2022 09:13:40 -0700 (PDT) Received: from localhost ([::1]:45844 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtlb-0002YR-KX for importer@patchew.org; Sat, 13 Aug 2022 12:13:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52862) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMtA4-0000vg-VN; Sat, 13 Aug 2022 11:34:52 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:28379) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMtA2-0006Mz-RH; Sat, 13 Aug 2022 11:34:52 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 5743F74819C; Sat, 13 Aug 2022 17:34:49 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 2353C74818E; Sat, 13 Aug 2022 17:34:49 +0200 (CEST) Message-Id: <011b7081d56ae856c1862bbfe92207ea8fe52399.1660402839.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 21/22] ppc4xx: Drop empty default cases MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:49 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660407222775100001 Content-Type: text/plain; charset="utf-8" Remove default case labels that do nothing or only there to set a default value that could easily be done at the variable definition instead. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405_boards.c | 7 +------ hw/ppc/ppc405_uc.c | 29 +++++------------------------ hw/ppc/ppc440_uc.c | 27 --------------------------- hw/ppc/ppc4xx_devs.c | 31 ++++--------------------------- 4 files changed, 10 insertions(+), 84 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 083f12b23e..a876b4af85 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -401,7 +401,7 @@ struct Ref405epFpgaState { static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned si= ze) { Ref405epFpgaState *fpga =3D opaque; - uint32_t ret; + uint32_t ret =3D 0; =20 switch (addr) { case 0x0: @@ -410,9 +410,6 @@ static uint64_t ref405ep_fpga_readb(void *opaque, hwadd= r addr, unsigned size) case 0x1: ret =3D fpga->reg1; break; - default: - ret =3D 0; - break; } =20 return ret; @@ -430,8 +427,6 @@ static void ref405ep_fpga_writeb(void *opaque, hwaddr a= ddr, uint64_t value, case 0x1: fpga->reg1 =3D value; break; - default: - break; } } =20 diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index b13026200f..6c84d87330 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -56,7 +56,7 @@ enum { static uint32_t dcr_read_pob(void *opaque, int dcrn) { Ppc405PobState *pob =3D opaque; - uint32_t ret; + uint32_t ret =3D 0; =20 switch (dcrn) { case POB0_BEAR: @@ -68,10 +68,6 @@ static uint32_t dcr_read_pob(void *opaque, int dcrn) case POB0_BESR1: ret =3D pob->besr1; break; - default: - /* Avoid gcc warning */ - ret =3D 0; - break; } =20 return ret; @@ -131,7 +127,7 @@ static void ppc405_pob_class_init(ObjectClass *oc, void= *data) static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) { Ppc405OpbaState *opba =3D opaque; - uint32_t ret; + uint32_t ret =3D 0; =20 switch (addr) { case 0x00: @@ -140,9 +136,6 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, u= nsigned size) case 0x01: ret =3D opba->pr; break; - default: - ret =3D 0x00; - break; } =20 trace_opba_readb(addr, ret); @@ -163,8 +156,6 @@ static void opba_writeb(void *opaque, hwaddr addr, uint= 64_t value, case 0x01: opba->pr =3D value & 0xFF; break; - default: - break; } } static const MemoryRegionOps opba_ops =3D { @@ -403,7 +394,7 @@ static void ocm_update_mappings(Ppc405OcmState *ocm, static uint32_t dcr_read_ocm(void *opaque, int dcrn) { Ppc405OcmState *ocm =3D opaque; - uint32_t ret; + uint32_t ret =3D 0; =20 switch (dcrn) { case OCM0_ISARC: @@ -418,9 +409,6 @@ static uint32_t dcr_read_ocm(void *opaque, int dcrn) case OCM0_DSACNTL: ret =3D ocm->dsacntl; break; - default: - ret =3D 0; - break; } =20 return ret; @@ -556,7 +544,7 @@ static void ppc4xx_gpt_compute_timer(Ppc405GptState *gp= t) static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) { Ppc405GptState *gpt =3D opaque; - uint32_t ret; + uint32_t ret =3D -1; int idx; =20 trace_ppc4xx_gpt_read(addr, size); @@ -598,9 +586,6 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr ad= dr, unsigned size) idx =3D (addr - 0xC0) >> 2; ret =3D gpt->mask[idx]; break; - default: - ret =3D -1; - break; } =20 return ret; @@ -844,7 +829,7 @@ static void ppc405ep_compute_clocks(Ppc405CpcState *cpc) static uint32_t dcr_read_epcpc(void *opaque, int dcrn) { Ppc405CpcState *cpc =3D opaque; - uint32_t ret; + uint32_t ret =3D 0; =20 switch (dcrn) { case PPC405EP_CPC0_BOOT: @@ -871,10 +856,6 @@ static uint32_t dcr_read_epcpc(void *opaque, int dcrn) case PPC405EP_CPC0_PCI: ret =3D cpc->pci; break; - default: - /* Avoid gcc warning */ - ret =3D 0; - break; } =20 return ret; diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 11fdb88c22..b390672bce 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -147,9 +147,6 @@ static uint32_t dcr_read_l2sram(void *opaque, int dcrn) case DCR_ISRAM0_DPC: ret =3D l2sram->isram0[dcrn - DCR_ISRAM0_BASE]; break; - - default: - break; } =20 return ret; @@ -304,12 +301,8 @@ static uint32_t dcr_read_cpr(void *opaque, int dcrn) case CPR0_AHBD: ret =3D (1 << 24); break; - default: - break; } break; - default: - break; } =20 return ret; @@ -325,8 +318,6 @@ static void dcr_write_cpr(void *opaque, int dcrn, uint3= 2_t val) break; case CPR0_CFGDATA: break; - default: - break; } } =20 @@ -421,12 +412,8 @@ static uint32_t dcr_read_sdr(void *opaque, int dcrn) case PESDR1_LOOP: ret =3D 1 << 12; break; - default: - break; } break; - default: - break; } =20 return ret; @@ -444,12 +431,8 @@ static void dcr_write_sdr(void *opaque, int dcrn, uint= 32_t val) switch (sdr->addr) { case 0x00: /* B0CR */ break; - default: - break; } break; - default: - break; } } =20 @@ -646,12 +629,8 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn) case 0xE1: /* SDR0_DDR0 */ ret =3D SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; break; - default: - break; } break; - default: - break; } =20 return ret; @@ -679,12 +658,8 @@ static void dcr_write_sdram(void *opaque, int dcrn, ui= nt32_t val) switch (sdram->addr) { case 0x00: /* B0CR */ break; - default: - break; } break; - default: - break; } } =20 @@ -760,8 +735,6 @@ static uint32_t dcr_read_ahb(void *opaque, int dcrn) case AHB_BOT: ret =3D ahb->bot; break; - default: - break; } =20 return ret; diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 49793b56cd..f5806f06e7 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -182,7 +182,7 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) static uint32_t dcr_read_sdram (void *opaque, int dcrn) { ppc4xx_sdram_t *sdram; - uint32_t ret; + uint32_t ret =3D 0; =20 sdram =3D opaque; switch (dcrn) { @@ -238,10 +238,6 @@ static uint32_t dcr_read_sdram (void *opaque, int dcrn) break; } break; - default: - /* Avoid gcc warning */ - ret =3D 0x00000000; - break; } =20 return ret; @@ -321,8 +317,6 @@ static void dcr_write_sdram (void *opaque, int dcrn, ui= nt32_t val) qemu_irq_lower(sdram->irq); sdram->eccesr =3D val; break; - default: /* Error */ - break; } break; } @@ -476,7 +470,7 @@ static void ppc4xx_mal_reset(DeviceState *dev) static uint32_t dcr_read_mal(void *opaque, int dcrn) { Ppc4xxMalState *mal =3D opaque; - uint32_t ret; + uint32_t ret =3D 0; =20 switch (dcrn) { case MAL0_CFG: @@ -512,9 +506,6 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn) case MAL0_RXDEIR: ret =3D mal->rxdeir; break; - default: - ret =3D 0; - break; } if (dcrn >=3D MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { ret =3D mal->txctpr[dcrn - MAL0_TXCTP0R]; @@ -671,7 +662,7 @@ enum { static uint32_t dcr_read_plb(void *opaque, int dcrn) { Ppc405PlbState *plb =3D opaque; - uint32_t ret; + uint32_t ret =3D 0; =20 switch (dcrn) { case PLB0_ACR: @@ -683,10 +674,6 @@ static uint32_t dcr_read_plb(void *opaque, int dcrn) case PLB0_BESR: ret =3D plb->besr; break; - default: - /* Avoid gcc warning */ - ret =3D 0; - break; } =20 return ret; @@ -756,7 +743,7 @@ enum { static uint32_t dcr_read_ebc(void *opaque, int dcrn) { Ppc405EbcState *ebc =3D opaque; - uint32_t ret; + uint32_t ret =3D 0; =20 switch (dcrn) { case EBC0_CFGADDR: @@ -824,14 +811,8 @@ static uint32_t dcr_read_ebc(void *opaque, int dcrn) case 0x23: /* CFG */ ret =3D ebc->cfg; break; - default: - ret =3D 0x00000000; - break; } break; - default: - ret =3D 0x00000000; - break; } =20 return ret; @@ -887,12 +868,8 @@ static void dcr_write_ebc(void *opaque, int dcrn, uint= 32_t val) break; case 0x23: /* CFG */ break; - default: - break; } break; - default: - break; } } =20 --=20 2.30.4 From nobody Thu May 2 02:36:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Sat, 13 Aug 2022 17:34:50 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 22/22] ppc/ppc4xx: Fix sdram trace events MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:50 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660406612577100001 From: C=C3=A9dric Le Goater Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc4xx_devs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index f5806f06e7..3311b30a81 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -142,7 +142,7 @@ static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i, } sdram->bcr[i] =3D bcr & 0xFFDEE001; if (enabled && (bcr & 0x00000001)) { - trace_ppc4xx_sdram_unmap(sdram_base(bcr), sdram_size(bcr)); + trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr)); memory_region_init(&sdram->containers[i], NULL, "sdram-containers", sdram_size(bcr)); memory_region_add_subregion(&sdram->containers[i], 0, --=20 2.30.4