From nobody Sun May 19 16:27:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=siemens.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641140753863272.22367945783196; Sun, 2 Jan 2022 08:25:53 -0800 (PST) Received: from localhost ([::1]:34316 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n43g8-0004SQ-Bi for importer@patchew.org; Sun, 02 Jan 2022 11:25:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57484) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n43PM-0006z1-2p for qemu-devel@nongnu.org; Sun, 02 Jan 2022 11:08:32 -0500 Received: from goliath.siemens.de ([192.35.17.28]:42543) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n43PJ-0004Di-Rm for qemu-devel@nongnu.org; Sun, 02 Jan 2022 11:08:31 -0500 Received: from mail1.sbs.de (mail1.sbs.de [192.129.41.35]) by goliath.siemens.de (8.15.2/8.15.2) with ESMTPS id 202G8Qwu028211 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sun, 2 Jan 2022 17:08:26 +0100 Received: from fedora.vmnet8.md1wgtfc ([144.145.220.57]) by mail1.sbs.de (8.15.2/8.15.2) with ESMTP id 202G82UT030977; Sun, 2 Jan 2022 17:08:26 +0100 From: Konrad Schwarz To: qemu-devel@nongnu.org Subject: [PATCH v1 1/5] RISC-V: larger and more consistent register set for 'info registers' Date: Sun, 2 Jan 2022 17:06:08 +0100 Message-Id: <85d02ac883c7cf40fbd54e8747783937e0370eaa.1641137349.git.konrad.schwarz@siemens.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.35.17.28; envelope-from=konrad.schwarz@siemens.com; helo=goliath.siemens.de X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 02 Jan 2022 11:21:56 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Schwarz , Alistair Francis , Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1641140754885100002 Content-Type: text/plain; charset="utf-8" Display more CSRs in the 'info registers' command and group them according to function. The number of CSRs in RISC-V is so large to make it impractical for all CSRs to be displayed by 'info registers'. The code uses conditional compilation directives around register groups; advanced users can enable/disable register groups as required. Signed-off-by: Konrad Schwarz --- target/riscv/cpu.c | 327 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 303 insertions(+), 24 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f812998123..eb9518fc16 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3,6 +3,7 @@ * * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu * Copyright (c) 2017-2018 SiFive, Inc. + * Copyright (c) 2021 Siemens AG, konrad.schwarz@siemens.com * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -244,40 +245,318 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE = *f, int flags) #ifndef CONFIG_USER_ONLY { static const int dump_csrs[] =3D { + +# if 0 + CSR_USTATUS, + CSR_UIE, + CSR_UTVEC, + +/* User Trap Handling */ + CSR_USCRATCH, + CSR_UEPC, + CSR_UCAUSE, + CSR_UTVAL, + CSR_UIP, +# endif + +/* User Floating-Point CSRs */ + CSR_FFLAGS, + CSR_FRM, + CSR_FCSR, + +/* User Vector CSRs */ + CSR_VSTART, + CSR_VXSAT, + CSR_VXRM, + CSR_VL, + CSR_VTYPE, + +# if 0 +/* User Timers and Counters */ + CSR_CYCLE, + CSR_TIME, + CSR_INSTRET, + CSR_HPMCOUNTER3, + CSR_HPMCOUNTER4, + CSR_HPMCOUNTER5, + CSR_HPMCOUNTER6, + CSR_HPMCOUNTER7, + CSR_HPMCOUNTER8, + CSR_HPMCOUNTER9, + CSR_HPMCOUNTER10, + CSR_HPMCOUNTER11, + CSR_HPMCOUNTER12, + CSR_HPMCOUNTER13, + CSR_HPMCOUNTER14, + CSR_HPMCOUNTER15, + CSR_HPMCOUNTER16, + CSR_HPMCOUNTER17, + CSR_HPMCOUNTER18, + CSR_HPMCOUNTER19, + CSR_HPMCOUNTER20, + CSR_HPMCOUNTER21, + CSR_HPMCOUNTER22, + CSR_HPMCOUNTER23, + CSR_HPMCOUNTER24, + CSR_HPMCOUNTER25, + CSR_HPMCOUNTER26, + CSR_HPMCOUNTER27, + CSR_HPMCOUNTER28, + CSR_HPMCOUNTER29, + CSR_HPMCOUNTER30, + CSR_HPMCOUNTER31, + CSR_CYCLEH, + CSR_TIMEH, + CSR_INSTRETH, + CSR_HPMCOUNTER3H, + CSR_HPMCOUNTER4H, + CSR_HPMCOUNTER5H, + CSR_HPMCOUNTER6H, + CSR_HPMCOUNTER7H, + CSR_HPMCOUNTER8H, + CSR_HPMCOUNTER9H, + CSR_HPMCOUNTER10H, + CSR_HPMCOUNTER11H, + CSR_HPMCOUNTER12H, + CSR_HPMCOUNTER13H, + CSR_HPMCOUNTER14H, + CSR_HPMCOUNTER15H, + CSR_HPMCOUNTER16H, + CSR_HPMCOUNTER17H, + CSR_HPMCOUNTER18H, + CSR_HPMCOUNTER19H, + CSR_HPMCOUNTER20H, + CSR_HPMCOUNTER21H, + CSR_HPMCOUNTER22H, + CSR_HPMCOUNTER23H, + CSR_HPMCOUNTER24H, + CSR_HPMCOUNTER25H, + CSR_HPMCOUNTER26H, + CSR_HPMCOUNTER27H, + CSR_HPMCOUNTER28H, + CSR_HPMCOUNTER29H, + CSR_HPMCOUNTER30H, + CSR_HPMCOUNTER31H, +# endif + +# if 0 +/* Machine Timers and Counters */ + CSR_MCYCLE, + CSR_MINSTRET, + CSR_MCYCLEH, + CSR_MINSTRETH, +# endif + +/* Machine Information Registers */ + CSR_MVENDORID, + CSR_MARCHID, + CSR_MIMPID, CSR_MHARTID, + +/* Machine Trap Setup */ CSR_MSTATUS, - CSR_MSTATUSH, - CSR_HSTATUS, - CSR_VSSTATUS, - CSR_MIP, - CSR_MIE, - CSR_MIDELEG, - CSR_HIDELEG, + CSR_MISA, CSR_MEDELEG, - CSR_HEDELEG, + CSR_MIDELEG, + CSR_MIE, CSR_MTVEC, - CSR_STVEC, - CSR_VSTVEC, + CSR_MCOUNTEREN, + +# if defined TARGET_RISCV32 +/* 32-bit only */ + CSR_MSTATUSH, +# endif + +/* Machine Trap Handling */ + CSR_MSCRATCH, CSR_MEPC, - CSR_SEPC, - CSR_VSEPC, CSR_MCAUSE, - CSR_SCAUSE, - CSR_VSCAUSE, CSR_MTVAL, + CSR_MIP, + +/* Supervisor Trap Setup */ + CSR_SSTATUS, + CSR_SEDELEG, + CSR_SIDELEG, + CSR_SIE, + CSR_STVEC, + CSR_SCOUNTEREN, + +/* Supervisor Trap Handling */ + CSR_SSCRATCH, + CSR_SEPC, + CSR_SCAUSE, CSR_STVAL, + CSR_SIP, + +/* Supervisor Protection and Translation */ + CSR_SPTBR, + CSR_SATP, + +/* Hpervisor CSRs */ + CSR_HSTATUS, + CSR_HEDELEG, + CSR_HIDELEG, + CSR_HIE, + CSR_HCOUNTEREN, + CSR_HGEIE, CSR_HTVAL, + CSR_HVIP, + CSR_HIP, + CSR_HTINST, + CSR_HGEIP, + CSR_HGATP, + CSR_HTIMEDELTA, + CSR_HTIMEDELTAH, + +/* Virtual CSRs */ + CSR_VSSTATUS, + CSR_VSIE, + CSR_VSTVEC, + CSR_VSSCRATCH, + CSR_VSEPC, + CSR_VSCAUSE, + CSR_VSTVAL, + CSR_VSIP, + CSR_VSATP, + + CSR_MTINST, CSR_MTVAL2, - CSR_MSCRATCH, - CSR_SSCRATCH, - CSR_SATP, - CSR_MMTE, - CSR_UPMBASE, - CSR_UPMMASK, - CSR_SPMBASE, - CSR_SPMMASK, - CSR_MPMBASE, - CSR_MPMMASK, + +# if 0 +/* Enhanced Physical Memory Protection (ePMP) */ + CSR_MSECCFG, + CSR_MSECCFGH, +# endif +# if 0 +/* Physical Memory Protection */ + CSR_PMPCFG0, + CSR_PMPCFG1, + CSR_PMPCFG2, + CSR_PMPCFG3, + CSR_PMPADDR0, + CSR_PMPADDR1, + CSR_PMPADDR2, + CSR_PMPADDR3, + CSR_PMPADDR4, + CSR_PMPADDR5, + CSR_PMPADDR6, + CSR_PMPADDR7, + CSR_PMPADDR8, + CSR_PMPADDR9, + CSR_PMPADDR10, + CSR_PMPADDR11, + CSR_PMPADDR12, + CSR_PMPADDR13, + CSR_PMPADDR14, + CSR_PMPADDR15, +# endif + +# if 0 +/* Debug/Trace Registers (shared with Debug Mode) */ + CSR_TSELECT, + CSR_TDATA1, + CSR_TDATA2, + CSR_TDATA3, +# endif + +# if 0 +/* Debug Mode Registers */ + CSR_DCSR, + CSR_DPC, + CSR_DSCRATCH, +# endif + +# if 0 +/* Performance Counters */ + CSR_MHPMCOUNTER3, + CSR_MHPMCOUNTER4, + CSR_MHPMCOUNTER5, + CSR_MHPMCOUNTER6, + CSR_MHPMCOUNTER7, + CSR_MHPMCOUNTER8, + CSR_MHPMCOUNTER9, + CSR_MHPMCOUNTER10, + CSR_MHPMCOUNTER11, + CSR_MHPMCOUNTER12, + CSR_MHPMCOUNTER13, + CSR_MHPMCOUNTER14, + CSR_MHPMCOUNTER15, + CSR_MHPMCOUNTER16, + CSR_MHPMCOUNTER17, + CSR_MHPMCOUNTER18, + CSR_MHPMCOUNTER19, + CSR_MHPMCOUNTER20, + CSR_MHPMCOUNTER21, + CSR_MHPMCOUNTER22, + CSR_MHPMCOUNTER23, + CSR_MHPMCOUNTER24, + CSR_MHPMCOUNTER25, + CSR_MHPMCOUNTER26, + CSR_MHPMCOUNTER27, + CSR_MHPMCOUNTER28, + CSR_MHPMCOUNTER29, + CSR_MHPMCOUNTER30, + CSR_MHPMCOUNTER31, + CSR_MHPMEVENT3, + CSR_MHPMEVENT4, + CSR_MHPMEVENT5, + CSR_MHPMEVENT6, + CSR_MHPMEVENT7, + CSR_MHPMEVENT8, + CSR_MHPMEVENT9, + CSR_MHPMEVENT10, + CSR_MHPMEVENT11, + CSR_MHPMEVENT12, + CSR_MHPMEVENT13, + CSR_MHPMEVENT14, + CSR_MHPMEVENT15, + CSR_MHPMEVENT16, + CSR_MHPMEVENT17, + CSR_MHPMEVENT18, + CSR_MHPMEVENT19, + CSR_MHPMEVENT20, + CSR_MHPMEVENT21, + CSR_MHPMEVENT22, + CSR_MHPMEVENT23, + CSR_MHPMEVENT24, + CSR_MHPMEVENT25, + CSR_MHPMEVENT26, + CSR_MHPMEVENT27, + CSR_MHPMEVENT28, + CSR_MHPMEVENT29, + CSR_MHPMEVENT30, + CSR_MHPMEVENT31, + CSR_MHPMCOUNTER3H, + CSR_MHPMCOUNTER4H, + CSR_MHPMCOUNTER5H, + CSR_MHPMCOUNTER6H, + CSR_MHPMCOUNTER7H, + CSR_MHPMCOUNTER8H, + CSR_MHPMCOUNTER9H, + CSR_MHPMCOUNTER10H, + CSR_MHPMCOUNTER11H, + CSR_MHPMCOUNTER12H, + CSR_MHPMCOUNTER13H, + CSR_MHPMCOUNTER14H, + CSR_MHPMCOUNTER15H, + CSR_MHPMCOUNTER16H, + CSR_MHPMCOUNTER17H, + CSR_MHPMCOUNTER18H, + CSR_MHPMCOUNTER19H, + CSR_MHPMCOUNTER20H, + CSR_MHPMCOUNTER21H, + CSR_MHPMCOUNTER22H, + CSR_MHPMCOUNTER23H, + CSR_MHPMCOUNTER24H, + CSR_MHPMCOUNTER25H, + CSR_MHPMCOUNTER26H, + CSR_MHPMCOUNTER27H, + CSR_MHPMCOUNTER28H, + CSR_MHPMCOUNTER29H, + CSR_MHPMCOUNTER30H, + CSR_MHPMCOUNTER31H, +# endif }; =20 for (int i =3D 0; i < ARRAY_SIZE(dump_csrs); ++i) { --=20 Konrad Schwarz From nobody Sun May 19 16:27:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=siemens.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 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([144.145.220.57]) by mail1.sbs.de (8.15.2/8.15.2) with ESMTP id 202G82UU030977; Sun, 2 Jan 2022 17:08:26 +0100 From: Konrad Schwarz To: qemu-devel@nongnu.org Subject: [PATCH v1 2/5] RISC-V: monitor's print register functionality Date: Sun, 2 Jan 2022 17:06:09 +0100 Message-Id: <21df652bd597a70406cdd59fdf50c5c65b30a572.1641137349.git.konrad.schwarz@siemens.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.35.17.14; envelope-from=konrad.schwarz@siemens.com; helo=david.siemens.de X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 02 Jan 2022 11:21:56 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Schwarz , Alistair Francis , Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1641140754856100001 Content-Type: text/plain; charset="utf-8" Enable the print (p) command to display both general-purpose and Contral and Status (CSR) registers. General purpose registers can be named using the xN form or their ABI names (zero, ra, sp, a0, s1, t2). Signed-off-by: Konrad Schwarz --- target/riscv/monitor.c | 69 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 7efb4b62c1..3f74ea9934 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -2,6 +2,7 @@ * QEMU monitor for RISC-V * * Copyright (c) 2019 Bin Meng + * Copyright (c) 2021 Siemens AG, konrad.schwarz@siemens.com * * RISC-V specific monitor commands implementation * @@ -234,3 +235,71 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) =20 mem_info_svxx(mon, env); } + +static const MonitorDef monitor_defs[] =3D { +# define MONITORDEF_RISCV_GPR(NO, ALIAS)\ + { "x" #NO #ALIAS, offsetof(CPURISCVState, gpr[NO]) }, + + MONITORDEF_RISCV_GPR(0, |zero) + MONITORDEF_RISCV_GPR(1, |ra) + MONITORDEF_RISCV_GPR(2, |sp) + MONITORDEF_RISCV_GPR(3, |gp) + MONITORDEF_RISCV_GPR(4, |tp) + MONITORDEF_RISCV_GPR(5, |t0) + MONITORDEF_RISCV_GPR(6, |t1) + MONITORDEF_RISCV_GPR(7, |t2) + MONITORDEF_RISCV_GPR(8, |s0|fp) + MONITORDEF_RISCV_GPR(9, |s1) + MONITORDEF_RISCV_GPR(10, |a0) + MONITORDEF_RISCV_GPR(11, |a1) + MONITORDEF_RISCV_GPR(12, |a2) + MONITORDEF_RISCV_GPR(13, |a3) + MONITORDEF_RISCV_GPR(14, |a4) + MONITORDEF_RISCV_GPR(15, |a5) + MONITORDEF_RISCV_GPR(16, |a6) + MONITORDEF_RISCV_GPR(17, |a7) + MONITORDEF_RISCV_GPR(18, |s2) + MONITORDEF_RISCV_GPR(19, |s3) + MONITORDEF_RISCV_GPR(20, |s4) + MONITORDEF_RISCV_GPR(21, |s5) + MONITORDEF_RISCV_GPR(22, |s6) + MONITORDEF_RISCV_GPR(23, |s7) + MONITORDEF_RISCV_GPR(24, |s8) + MONITORDEF_RISCV_GPR(25, |s9) + MONITORDEF_RISCV_GPR(26, |s10) + MONITORDEF_RISCV_GPR(27, |s11) + MONITORDEF_RISCV_GPR(28, |t3) + MONITORDEF_RISCV_GPR(29, |t4) + MONITORDEF_RISCV_GPR(30, |t5) + MONITORDEF_RISCV_GPR(31, |t6) + + { }, +}; + +const MonitorDef *target_monitor_defs(void) +{ + return monitor_defs; +} + +int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval) +{ + + target_ulong ret_value; + CPURISCVState *const env =3D &RISCV_CPU (cs)->env; + riscv_csr_operations *op; + for (op =3D csr_ops; 1[&csr_ops] > op; ++op) { + if (!op->name) { + continue; + } + if (!strcmp(name, op->name)) { + if (RISCV_EXCP_NONE !=3D riscv_csrrw_debug(env, op - csr_ops, + &ret_value, + 0 /* new_value */, + 0 /* write_mask */)) + return -1; + *pval =3D ret_value; + return 0; + } + } + return -1; +} --=20 Konrad Schwarz From nobody Sun May 19 16:27:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=siemens.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641140952263137.6845233528552; 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Sun, 2 Jan 2022 17:08:27 +0100 From: Konrad Schwarz To: qemu-devel@nongnu.org Subject: [PATCH v1 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations Date: Sun, 2 Jan 2022 17:06:10 +0100 Message-Id: <03cb38fdfab89a6725fa0c7cadad2055d6be48a4.1641137349.git.konrad.schwarz@siemens.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.35.17.28; envelope-from=konrad.schwarz@siemens.com; helo=goliath.siemens.de X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 02 Jan 2022 11:21:56 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Schwarz , Alistair Francis , Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1641140954667100003 Content-Type: text/plain; charset="utf-8" This is analog to the existing 'info mem' command and is implemented using the same machinery. Signed-off-by: Konrad Schwarz --- hmp-commands-info.hx | 16 +++++ include/monitor/hmp-target.h | 2 + target/riscv/monitor.c | 135 +++++++++++++++++++++++++---------- 3 files changed, 117 insertions(+), 36 deletions(-) diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx index 407a1da800..fa519f0129 100644 --- a/hmp-commands-info.hx +++ b/hmp-commands-info.hx @@ -237,6 +237,22 @@ SRST Show the active virtual memory mappings. ERST =20 +#if defined TARGET_RISCV + { + .name =3D "gmem", + .args_type =3D "", + .params =3D "", + .help =3D "show the hypervisor guest's physical address" + " translation", + .cmd =3D hmp_info_gmem, + }, +#endif + +SRST + ``info gmem`` + Show the hypervisor guest's physical address translation. +ERST + { .name =3D "mtree", .args_type =3D "flatview:-f,dispatch_tree:-d,owner:-o,disabled:-D= ", diff --git a/include/monitor/hmp-target.h b/include/monitor/hmp-target.h index ffdc15a34b..9f2dd976f6 100644 --- a/include/monitor/hmp-target.h +++ b/include/monitor/hmp-target.h @@ -2,6 +2,7 @@ * QEMU monitor * * Copyright (c) 2003-2004 Fabrice Bellard + * Copyright (c) 2021 Siemens AG, konrad.schwarz@siemens.com * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -45,6 +46,7 @@ CPUArchState *mon_get_cpu_env(Monitor *mon); CPUState *mon_get_cpu(Monitor *mon); =20 void hmp_info_mem(Monitor *mon, const QDict *qdict); +void hmp_info_gmem(Monitor *mon, const QDict *qdict); void hmp_info_tlb(Monitor *mon, const QDict *qdict); void hmp_mce(Monitor *mon, const QDict *qdict); void hmp_info_local_apic(Monitor *mon, const QDict *qdict); diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 3f74ea9934..ad58bdf9ca 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -25,16 +25,6 @@ #include "monitor/monitor.h" #include "monitor/hmp-target.h" =20 -#ifdef TARGET_RISCV64 -#define PTE_HEADER_FIELDS "vaddr paddr "\ - "size attr\n" -#define PTE_HEADER_DELIMITER "---------------- ---------------- "\ - "---------------- -------\n" -#else -#define PTE_HEADER_FIELDS "vaddr paddr size attr\n" -#define PTE_HEADER_DELIMITER "-------- ---------------- -------- ------= -\n" -#endif - /* Perform linear address sign extension */ static target_ulong addr_canonical(int va_bits, target_ulong addr) { @@ -47,10 +37,34 @@ static target_ulong addr_canonical(int va_bits, target_= ulong addr) return addr; } =20 -static void print_pte_header(Monitor *mon) +static void print_pte_header(Monitor *mon, + char const vaddr_char, char const paddr_char) { - monitor_printf(mon, PTE_HEADER_FIELDS); - monitor_printf(mon, PTE_HEADER_DELIMITER); + +# define VIRTUAL_WIDTH\ + ((int) ((sizeof "ff" - sizeof "") * sizeof(target_ulong))) +# define PHYSICAL_WIDTH\ + ((int) ((sizeof "ff" - sizeof "") * sizeof(hwaddr))) +# define ATTRIBUTE_WIDTH ((int) (sizeof "rwxugad" - sizeof "")) + +# define VIRTUAL_COLUMN_WIDTH (1 + VIRTUAL_WIDTH) +# define PHYSICAL_COLUMN_WIDTH (1 + PHYSICAL_WIDTH) + + static char const dashes[PHYSICAL_WIDTH] =3D "----------------"; + + monitor_printf(mon, + "%c%-*s%c%-*s%-*s%-*s\n" + "%-*.*s%-*.*s%-*.*s%-*.*s\n", + + vaddr_char, VIRTUAL_COLUMN_WIDTH - 1, "addr", + paddr_char, PHYSICAL_COLUMN_WIDTH - 1, "addr", + VIRTUAL_COLUMN_WIDTH, "size", + ATTRIBUTE_WIDTH, "attr", + + VIRTUAL_COLUMN_WIDTH, VIRTUAL_WIDTH, dashes, + PHYSICAL_COLUMN_WIDTH, PHYSICAL_WIDTH, dashes, + VIRTUAL_COLUMN_WIDTH, VIRTUAL_WIDTH, dashes, + ATTRIBUTE_WIDTH, ATTRIBUTE_WIDTH, dashes); } =20 static void print_pte(Monitor *mon, int va_bits, target_ulong vaddr, @@ -65,21 +79,36 @@ static void print_pte(Monitor *mon, int va_bits, target= _ulong vaddr, return; } =20 - monitor_printf(mon, TARGET_FMT_lx " " TARGET_FMT_plx " " TARGET_FMT_lx - " %c%c%c%c%c%c%c\n", - addr_canonical(va_bits, vaddr), - paddr, size, - attr & PTE_R ? 'r' : '-', - attr & PTE_W ? 'w' : '-', - attr & PTE_X ? 'x' : '-', - attr & PTE_U ? 'u' : '-', - attr & PTE_G ? 'g' : '-', - attr & PTE_A ? 'a' : '-', - attr & PTE_D ? 'd' : '-'); +# if 4 =3D=3D TARGET_LONG_SIZE +# define TARGET_xFMT PRIx32 +# elif 8 =3D=3D TARGET_LONG_SIZE +# define TARGET_xFMT PRIx64 +# else +# error TARGET_LONG_SIZE not handled +# endif + + /* note: RISC-V physical addresses are actually xlen + 2 bits long + OTHO, QEMU wil probably never support addresses longer than 64 bits */ + monitor_printf(mon, + "%-*.*" TARGET_xFMT + "%-*.*" PRIx64 + "%-*.*" TARGET_xFMT + "%c%c%c%c%c%c%c\n", + VIRTUAL_COLUMN_WIDTH, VIRTUAL_WIDTH, addr_canonical(va_bits, v= addr), + PHYSICAL_COLUMN_WIDTH, PHYSICAL_WIDTH, paddr, + VIRTUAL_COLUMN_WIDTH, VIRTUAL_WIDTH, size, + attr & PTE_R ? 'r' : '-', + attr & PTE_W ? 'w' : '-', + attr & PTE_X ? 'x' : '-', + attr & PTE_U ? 'u' : '-', + attr & PTE_G ? 'g' : '-', + attr & PTE_A ? 'a' : '-', + attr & PTE_D ? 'd' : '-'); } =20 static void walk_pte(Monitor *mon, hwaddr base, target_ulong start, int level, int ptidxbits, int ptesize, int va_bits, + int guest, target_ulong *vbase, hwaddr *pbase, hwaddr *last_padd= r, target_ulong *last_size, int *last_attr) { @@ -89,7 +118,7 @@ static void walk_pte(Monitor *mon, hwaddr base, target_u= long start, target_ulong pte; int ptshift; int attr; - int idx; + int idx, idx_end; =20 if (level < 0) { return; @@ -98,7 +127,8 @@ static void walk_pte(Monitor *mon, hwaddr base, target_u= long start, ptshift =3D level * ptidxbits; pgsize =3D 1UL << (PGSHIFT + ptshift); =20 - for (idx =3D 0; idx < (1UL << ptidxbits); idx++) { + for (idx =3D 0, idx_end =3D 1 << (ptidxbits + (guest ? 2 : 0)); + idx_end > idx; idx++) { pte_addr =3D base + idx * ptesize; cpu_physical_memory_read(pte_addr, &pte, ptesize); =20 @@ -131,7 +161,9 @@ static void walk_pte(Monitor *mon, hwaddr base, target_= ulong start, } else { /* pointer to the next level of the page table */ walk_pte(mon, paddr, start, level - 1, ptidxbits, ptesize, - va_bits, vbase, pbase, last_paddr, + va_bits, + 0 /* guest */, + vbase, pbase, last_paddr, last_size, last_attr); } } @@ -141,7 +173,9 @@ static void walk_pte(Monitor *mon, hwaddr base, target_= ulong start, =20 } =20 -static void mem_info_svxx(Monitor *mon, CPUArchState *env) +static void mem_info_svxx(Monitor *mon, CPUArchState *env, + target_ulong const atp, + int guest, char const vaddr_char, char const paddr_char) { int levels, ptidxbits, ptesize, vm, va_bits; hwaddr base; @@ -152,11 +186,11 @@ static void mem_info_svxx(Monitor *mon, CPUArchState = *env) int last_attr; =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - base =3D (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; - vm =3D get_field(env->satp, SATP32_MODE); + base =3D (hwaddr)get_field(atp, SATP32_PPN) << PGSHIFT; + vm =3D get_field(atp, SATP32_MODE); } else { - base =3D (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; - vm =3D get_field(env->satp, SATP64_MODE); + base =3D (hwaddr)get_field(atp, SATP64_PPN) << PGSHIFT; + vm =3D get_field(atp, SATP64_MODE); } =20 switch (vm) { @@ -189,7 +223,7 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *e= nv) va_bits =3D PGSHIFT + levels * ptidxbits; =20 /* print header */ - print_pte_header(mon); + print_pte_header(mon, vaddr_char, paddr_char); =20 vbase =3D -1; pbase =3D -1; @@ -199,6 +233,7 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *e= nv) =20 /* walk page tables, starting from address 0 */ walk_pte(mon, base, 0, levels - 1, ptidxbits, ptesize, va_bits, + guest, &vbase, &pbase, &last_paddr, &last_size, &last_attr); =20 /* don't forget the last one */ @@ -209,6 +244,7 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *e= nv) void hmp_info_mem(Monitor *mon, const QDict *qdict) { CPUArchState *env; + target_ulong atp; =20 env =3D mon_get_cpu_env(mon); if (!env) { @@ -221,19 +257,46 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) return; } =20 + atp =3D env->satp; if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - if (!(env->satp & SATP32_MODE)) { + if (!(atp & SATP32_MODE)) { monitor_printf(mon, "No translation or protection\n"); return; } } else { - if (!(env->satp & SATP64_MODE)) { + if (!(atp & SATP64_MODE)) { monitor_printf(mon, "No translation or protection\n"); return; } } =20 - mem_info_svxx(mon, env); + mem_info_svxx(mon, env, atp, 0, 'v', 'p'); +} + +void hmp_info_gmem(Monitor *mon, const QDict *qdict) +{ + CPUArchState *env; + target_ulong atp; + + env =3D mon_get_cpu_env(mon); + if (!env) { + monitor_printf(mon, "No CPU available\n"); + return; + } + + if (!riscv_has_ext(env, RVH)) { + monitor_printf(mon, "hypervisor extension not available\n"); + return; + } + + atp =3D env->hgatp; + if (!((MXL_RV32 =3D=3D riscv_cpu_mxl(env) ? SATP32_MODE : SATP64_MODE) + & atp)) { + monitor_printf(mon, "No translation or protection\n"); + return; + } + + mem_info_svxx(mon, env, atp, 1, 'g', 'p'); } =20 static const MonitorDef monitor_defs[] =3D { --=20 Konrad Schwarz From nobody Sun May 19 16:27:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=siemens.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641140964181950.5669024020597; Sun, 2 Jan 2022 08:29:24 -0800 (PST) Received: from localhost ([::1]:41610 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n43jX-00012A-5P for importer@patchew.org; Sun, 02 Jan 2022 11:29:23 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57498) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n43PO-00071T-NJ for qemu-devel@nongnu.org; Sun, 02 Jan 2022 11:08:34 -0500 Received: from goliath.siemens.de ([192.35.17.28]:42545) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n43PJ-0004Dm-Vn for qemu-devel@nongnu.org; Sun, 02 Jan 2022 11:08:33 -0500 Received: from mail1.sbs.de (mail1.sbs.de [192.129.41.35]) by goliath.siemens.de (8.15.2/8.15.2) with ESMTPS id 202G8RIQ028221 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sun, 2 Jan 2022 17:08:28 +0100 Received: from fedora.vmnet8.md1wgtfc ([144.145.220.57]) by mail1.sbs.de (8.15.2/8.15.2) with ESMTP id 202G82UW030977; Sun, 2 Jan 2022 17:08:27 +0100 From: Konrad Schwarz To: qemu-devel@nongnu.org Subject: [PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver Date: Sun, 2 Jan 2022 17:06:11 +0100 Message-Id: <4d994cf0ee4cc31c9173db6b73f4ae05272016ac.1641137349.git.konrad.schwarz@siemens.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.35.17.28; envelope-from=konrad.schwarz@siemens.com; helo=goliath.siemens.de X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 02 Jan 2022 11:21:56 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Schwarz , Alistair Francis , Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1641140965468100001 Content-Type: text/plain; charset="utf-8" GDB target descriptions support typed registers; such that `info register X' displays not only the hex value of register `X', but also the individual bitfields the register comprises (if any), using textual labels if possible. This patch includes type information for GDB for a large subset of the RISC-V Control and Status Registers (CSRs). Signed-off-by: Konrad Schwarz --- target/riscv/csr.c | 2 + target/riscv/csr32-op-gdbserver.h | 109 ++++++++++ target/riscv/csr64-op-gdbserver.h | 76 +++++++ target/riscv/gdb_csr_types.c | 333 ++++++++++++++++++++++++++++++ target/riscv/gdb_csr_types.h | 3 + target/riscv/gdbstub.c | 26 ++- target/riscv/meson.build | 4 +- 7 files changed, 547 insertions(+), 6 deletions(-) create mode 100644 target/riscv/csr32-op-gdbserver.h create mode 100644 target/riscv/csr64-op-gdbserver.h create mode 100644 target/riscv/gdb_csr_types.c create mode 100644 target/riscv/gdb_csr_types.h diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9f41954894..557b4afe0e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3,6 +3,7 @@ * * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu * Copyright (c) 2017-2018 SiFive, Inc. + * Copyright (c) 2021 Siemens AG, konrad.schwarz@siemens.com * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -2094,5 +2095,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHPMCOUNTER29H] =3D { "mhpmcounter29h", any32, read_zero }, [CSR_MHPMCOUNTER30H] =3D { "mhpmcounter30h", any32, read_zero }, [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", any32, read_zero }, + #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/riscv/csr32-op-gdbserver.h b/target/riscv/csr32-op-gdbs= erver.h new file mode 100644 index 0000000000..e8ec527f23 --- /dev/null +++ b/target/riscv/csr32-op-gdbserver.h @@ -0,0 +1,109 @@ +/* Copyright (c) 2021 Siemens AG, konrad.schwarz@siemens.com */ + + [CSR_USTATUS] { .gdb_type =3D "sstatus-fields", .gdb_group =3D "user" }, + [CSR_UIE] { .gdb_type =3D "sie-fields", .gdb_group =3D "user" }, + [CSR_UTVEC] { .gdb_type =3D "code_ptr", .gdb_group =3D "user" }, + [CSR_USCRATCH] { .gdb_type =3D "data_ptr", .gdb_group =3D "user" }, + [CSR_UEPC] { .gdb_type =3D "code_ptr", .gdb_group =3D "user" }, + [CSR_UCAUSE] { .gdb_type =3D "scause-fields", .gdb_group =3D "user" }, + [CSR_UTVAL] { .gdb_type =3D "data_ptr", .gdb_group =3D "user" }, + [CSR_UIP] { .gdb_type =3D "code_ptr", .gdb_group =3D "user" }, + [CSR_CYCLE] { .gdb_type =3D "uint32", .gdb_group =3D "user" }, + [CSR_TIME] { .gdb_type =3D "uint32", .gdb_group =3D "user" }, + [CSR_INSTRET] { .gdb_type =3D "uint32", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER3] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER4] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER5] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER6] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER7] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER8] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER9] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER10] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER11] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER12] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER13] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER14] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER15] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER16] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER17] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER18] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER19] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER20] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER21] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER22] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER23] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER24] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER25] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER26] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER27] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER28] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER29] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER30] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER31] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_CYCLEH] { .gdb_type =3D "uint32", .gdb_group =3D "user" }, + [CSR_TIMEH] { .gdb_type =3D "uint32", .gdb_group =3D "user" }, + [CSR_INSTRETH] { .gdb_type =3D "uint32", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER3H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER4H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER5H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER6H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER7H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER8H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER9H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER10H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER11H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER12H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER13H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER14H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER15H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER16H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER17H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER18H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER19H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER20H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER21H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER22H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER23H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER24H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER25H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER26H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER27H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER28H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER29H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER30H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER31H] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_SSTATUS] { .gdb_type =3D "sstatus-fields", .gdb_group =3D "supervis= or" }, + [CSR_SEDELEG] { .gdb_type =3D "uint32", .gdb_group =3D "supervisor" }, + [CSR_SIDELEG] { .gdb_type =3D "sie-fields", .gdb_group =3D "supervisor" = }, + [CSR_SIE] { .gdb_type =3D "sie-fields", .gdb_group =3D "supervisor" }, + [CSR_STVEC] { .gdb_type =3D "stvec-fields", .gdb_group =3D "supervisor" = }, + [CSR_SCOUNTEREN] { .gdb_type =3D "scounteren-fields", .gdb_group =3D "su= pervisor" }, + [CSR_SSCRATCH] { .gdb_type =3D "data_ptr", .gdb_group =3D "supervisor" }, + [CSR_SEPC] { .gdb_type =3D "code_ptr", .gdb_group =3D "supervisor" }, + [CSR_SCAUSE] { .gdb_type =3D "scause-fields", .gdb_group =3D "supervisor= " }, + [CSR_STVAL] { .gdb_type =3D "data_ptr", .gdb_group =3D "supervisor" }, + [CSR_SIP] { .gdb_type =3D "sip-fields", .gdb_group =3D "supervisor" }, + [CSR_SATP] { .gdb_type =3D "satp-fields", .gdb_group =3D "supervisor" }, + [CSR_HSTATUS] { .gdb_type =3D "hstatus-fields", .gdb_group =3D "hypervis= or" }, + [CSR_HEDELEG] { .gdb_type =3D "hedeleg-fields", .gdb_group =3D "hypervis= or" }, + [CSR_HIDELEG] { .gdb_type =3D "hie-fields", .gdb_group =3D "hypervisor" = }, + [CSR_HIE] { .gdb_type =3D "hie-fields", .gdb_group =3D "hypervisor" }, + [CSR_HCOUNTEREN] { .gdb_type =3D "int", .gdb_group =3D "hypervisor" }, + [CSR_HGEIE] { .gdb_type =3D "uint32", .gdb_group =3D "hypervisor" }, + [CSR_HGEIP] { .gdb_type =3D "uint32", .gdb_group =3D "hypervisor" }, + [CSR_HTVAL] { .gdb_type =3D "data_ptr", .gdb_group =3D "hypervisor" }, + [CSR_HIP] { .gdb_type =3D "hip-fields", .gdb_group =3D "hypervisor" }, + [CSR_HVIP] { .gdb_type =3D "hvip-fields", .gdb_group =3D "hypervisor" }, + [CSR_HGATP] { .gdb_type =3D "hgatp-fields", .gdb_group =3D "hypervisor" = }, + [CSR_HTIMEDELTA] { .gdb_type =3D "int", .gdb_group =3D "hypervisor" }, + [CSR_HTIMEDELTAH] { .gdb_type =3D "int", .gdb_group =3D "hypervisor" }, + [CSR_HTINST] { .gdb_type =3D "uint32", .gdb_group =3D "hypervisor" }, + [CSR_VSSTATUS] { .gdb_type =3D "sstatus-fields", .gdb_group =3D "virtual= -supervisor" }, + [CSR_VSIE] { .gdb_type =3D "sie-fields", .gdb_group =3D "virtual-supervi= sor" }, + [CSR_VSTVEC] { .gdb_type =3D "stvec-fields", .gdb_group =3D "virtual-sup= ervisor" }, + [CSR_VSSCRATCH] { .gdb_type =3D "data_ptr", .gdb_group =3D "virtual-supe= rvisor" }, + [CSR_VSEPC] { .gdb_type =3D "code_ptr", .gdb_group =3D "virtual-supervis= or" }, + [CSR_VSCAUSE] { .gdb_type =3D "scause-fields", .gdb_group =3D "virtual-s= upervisor" }, + [CSR_VSTVAL] { .gdb_type =3D "data_ptr", .gdb_group =3D "virtual-supervi= sor" }, + [CSR_VSIP] { .gdb_type =3D "sip-fields", .gdb_group =3D "virtual-supervi= sor" }, + [CSR_VSATP] { .gdb_type =3D "satp-fields", .gdb_group =3D "virtual-super= visor" }, diff --git a/target/riscv/csr64-op-gdbserver.h b/target/riscv/csr64-op-gdbs= erver.h new file mode 100644 index 0000000000..fc4bc62d9e --- /dev/null +++ b/target/riscv/csr64-op-gdbserver.h @@ -0,0 +1,76 @@ +/* Copyright (c) 2021 Siemens AG, konrad.schwarz@siemens.com */ + + [CSR_USTATUS] { .gdb_type =3D "sstatus-fields", .gdb_group =3D "user" }, + [CSR_UIE] { .gdb_type =3D "sie-fields", .gdb_group =3D "user" }, + [CSR_UTVEC] { .gdb_type =3D "code_ptr", .gdb_group =3D "user" }, + [CSR_USCRATCH] { .gdb_type =3D "data_ptr", .gdb_group =3D "user" }, + [CSR_UEPC] { .gdb_type =3D "code_ptr", .gdb_group =3D "user" }, + [CSR_UCAUSE] { .gdb_type =3D "scause-fields", .gdb_group =3D "user" }, + [CSR_UTVAL] { .gdb_type =3D "data_ptr", .gdb_group =3D "user" }, + [CSR_UIP] { .gdb_type =3D "code_ptr", .gdb_group =3D "user" }, + [CSR_CYCLE] { .gdb_type =3D "uint64", .gdb_group =3D "user" }, + [CSR_TIME] { .gdb_type =3D "uint64", .gdb_group =3D "user" }, + [CSR_INSTRET] { .gdb_type =3D "uint64", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER3] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER4] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER5] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER6] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER7] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER8] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER9] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER10] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER11] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER12] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER13] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER14] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER15] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER16] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER17] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER18] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER19] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER20] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER21] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER22] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER23] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER24] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER25] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER26] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER27] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER28] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER29] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER30] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_HPMCOUNTER31] { .gdb_type =3D "int", .gdb_group =3D "user" }, + [CSR_SSTATUS] { .gdb_type =3D "sstatus-fields", .gdb_group =3D "supervis= or" }, + [CSR_SEDELEG] { .gdb_type =3D "uint64", .gdb_group =3D "supervisor" }, + [CSR_SIDELEG] { .gdb_type =3D "sie-fields", .gdb_group =3D "supervisor" = }, + [CSR_SIE] { .gdb_type =3D "sie-fields", .gdb_group =3D "supervisor" }, + [CSR_STVEC] { .gdb_type =3D "stvec-fields", .gdb_group =3D "supervisor" = }, + [CSR_SCOUNTEREN] { .gdb_type =3D "scounteren-fields", .gdb_group =3D "su= pervisor" }, + [CSR_SSCRATCH] { .gdb_type =3D "data_ptr", .gdb_group =3D "supervisor" }, + [CSR_SEPC] { .gdb_type =3D "code_ptr", .gdb_group =3D "supervisor" }, + [CSR_SCAUSE] { .gdb_type =3D "scause-fields", .gdb_group =3D "supervisor= " }, + [CSR_STVAL] { .gdb_type =3D "data_ptr", .gdb_group =3D "supervisor" }, + [CSR_SIP] { .gdb_type =3D "sip-fields", .gdb_group =3D "supervisor" }, + [CSR_SATP] { .gdb_type =3D "satp-fields", .gdb_group =3D "supervisor" }, + [CSR_HSTATUS] { .gdb_type =3D "hstatus-fields", .gdb_group =3D "hypervis= or" }, + [CSR_HEDELEG] { .gdb_type =3D "hedeleg-fields", .gdb_group =3D "hypervis= or" }, + [CSR_HIDELEG] { .gdb_type =3D "hie-fields", .gdb_group =3D "hypervisor" = }, + [CSR_HIE] { .gdb_type =3D "hie-fields", .gdb_group =3D "hypervisor" }, + [CSR_HCOUNTEREN] { .gdb_type =3D "int", .gdb_group =3D "hypervisor" }, + [CSR_HGEIE] { .gdb_type =3D "uint64", .gdb_group =3D "hypervisor" }, + [CSR_HGEIP] { .gdb_type =3D "uint64", .gdb_group =3D "hypervisor" }, + [CSR_HTVAL] { .gdb_type =3D "data_ptr", .gdb_group =3D "hypervisor" }, + [CSR_HIP] { .gdb_type =3D "hip-fields", .gdb_group =3D "hypervisor" }, + [CSR_HVIP] { .gdb_type =3D "hvip-fields", .gdb_group =3D "hypervisor" }, + [CSR_HGATP] { .gdb_type =3D "hgatp-fields", .gdb_group =3D "hypervisor" = }, + [CSR_HTIMEDELTA] { .gdb_type =3D "int", .gdb_group =3D "hypervisor" }, + [CSR_HTINST] { .gdb_type =3D "uint64", .gdb_group =3D "hypervisor" }, + [CSR_VSSTATUS] { .gdb_type =3D "sstatus-fields", .gdb_group =3D "virtual= -supervisor" }, + [CSR_VSIE] { .gdb_type =3D "sie-fields", .gdb_group =3D "virtual-supervi= sor" }, + [CSR_VSTVEC] { .gdb_type =3D "stvec-fields", .gdb_group =3D "virtual-sup= ervisor" }, + [CSR_VSSCRATCH] { .gdb_type =3D "data_ptr", .gdb_group =3D "virtual-supe= rvisor" }, + [CSR_VSEPC] { .gdb_type =3D "code_ptr", .gdb_group =3D "virtual-supervis= or" }, + [CSR_VSCAUSE] { .gdb_type =3D "scause-fields", .gdb_group =3D "virtual-s= upervisor" }, + [CSR_VSTVAL] { .gdb_type =3D "data_ptr", .gdb_group =3D "virtual-supervi= sor" }, + [CSR_VSIP] { .gdb_type =3D "sip-fields", .gdb_group =3D "virtual-supervi= sor" }, + [CSR_VSATP] { .gdb_type =3D "satp-fields", .gdb_group =3D "virtual-super= visor" }, diff --git a/target/riscv/gdb_csr_types.c b/target/riscv/gdb_csr_types.c new file mode 100644 index 0000000000..48b1db2b88 --- /dev/null +++ b/target/riscv/gdb_csr_types.c @@ -0,0 +1,333 @@ +/* Copyright (c) 2021 Siemens AG, konrad.schwarz@siemens.com */ + +#include "qemu/osdep.h" +#include "gdb_csr_types.h" +#define STR(X) #X + +char const riscv_gdb_csr_types[] =3D +#ifdef TARGET_RISCV32 + STR( + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +) +#elif defined TARGET_RISCV64 + STR( + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +) +# endif +; diff --git a/target/riscv/gdb_csr_types.h b/target/riscv/gdb_csr_types.h new file mode 100644 index 0000000000..e55c978ac8 --- /dev/null +++ b/target/riscv/gdb_csr_types.h @@ -0,0 +1,3 @@ +/* Copyright (c) 2021 Siemens AG, konrad.schwarz@siemens.com */ + +extern char const riscv_gdb_csr_types[]; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 23429179e2..9c3f68eeaf 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -2,6 +2,7 @@ * RISC-V GDB Server Stub * * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2021 Siemens AG, konrad.schwarz@siemens.com * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -155,6 +156,9 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uin= t8_t *mem_buf, int n) return 0; } =20 +#include "gdb_csr_types.h" +#include "gdb_csr_type_group.h" + static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) { RISCVCPU *cpu =3D RISCV_CPU(cs); @@ -163,21 +167,33 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, in= t base_reg) riscv_csr_predicate_fn predicate; int bitsize =3D 16 << env->misa_mxl_max; int i; + riscv_csr_operations *csr_op; + struct riscv_gdb_csr_tg const *csr_tg; =20 g_string_printf(s, ""); g_string_append_printf(s, ""); g_string_append_printf(s, ""= ); =20 - for (i =3D 0; i < CSR_TABLE_SIZE; i++) { - predicate =3D csr_ops[i].predicate; + g_string_append(s, riscv_gdb_csr_types); + + for (i =3D 0, csr_op =3D csr_ops, csr_tg =3D riscv_gdb_csr_type_group; + i < CSR_TABLE_SIZE; ++csr_op, ++csr_tg, ++i) { + predicate =3D csr_op->predicate; if (predicate && (predicate(env, i) =3D=3D RISCV_EXCP_NONE)) { - if (csr_ops[i].name) { - g_string_append_printf(s, "name) { + g_string_append_printf(s, "na= me); } else { g_string_append_printf(s, "", base_reg + i); + g_string_append_printf(s, " regnum=3D\"%d\"", base_reg + i); + if (csr_tg->gdb_type) { + g_string_append_printf(s, " type=3D\"%s\"", csr_tg->gdb_ty= pe); + } + if (csr_tg->gdb_group) { + g_string_append_printf(s, " group=3D\"%s\"", csr_tg->gdb_g= roup); + } + g_string_append(s, " />\n"); } } =20 diff --git a/target/riscv/meson.build b/target/riscv/meson.build index d5e0bc93ea..e1945e54c4 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -25,7 +25,9 @@ riscv_softmmu_ss.add(files( 'arch_dump.c', 'pmp.c', 'monitor.c', - 'machine.c' + 'machine.c', + 'gdb_csr_types.c', + 'gdb_csr_type_group.c' )) =20 target_arch +=3D {'riscv': riscv_ss} --=20 Konrad Schwarz From nobody Sun May 19 16:27:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=siemens.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641140754663164.6272305621269; Sun, 2 Jan 2022 08:25:54 -0800 (PST) Received: from localhost ([::1]:34454 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n43g9-0004Y3-JB for importer@patchew.org; Sun, 02 Jan 2022 11:25:53 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57494) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n43PM-00070M-R3 for qemu-devel@nongnu.org; Sun, 02 Jan 2022 11:08:32 -0500 Received: from thoth.sbs.de ([192.35.17.2]:49056) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n43PK-0004Dq-Md for qemu-devel@nongnu.org; Sun, 02 Jan 2022 11:08:32 -0500 Received: from mail1.sbs.de (mail1.sbs.de [192.129.41.35]) by thoth.sbs.de (8.15.2/8.15.2) with ESMTPS id 202G8Sct013940 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sun, 2 Jan 2022 17:08:28 +0100 Received: from fedora.vmnet8.md1wgtfc ([144.145.220.57]) by mail1.sbs.de (8.15.2/8.15.2) with ESMTP id 202G82UX030977; Sun, 2 Jan 2022 17:08:28 +0100 From: Konrad Schwarz To: qemu-devel@nongnu.org Subject: [PATCH v1 5/5] RISC-V: Add `v' (virtualization mode) bit to the `priv' virtual debug register Date: Sun, 2 Jan 2022 17:06:12 +0100 Message-Id: <77b569e2920dc9b6aeeb9df9d81023cd86027206.1641137349.git.konrad.schwarz@siemens.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.35.17.2; envelope-from=konrad.schwarz@siemens.com; helo=thoth.sbs.de X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 02 Jan 2022 11:21:56 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Schwarz , Alistair Francis , Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1641140756409100005 Content-Type: text/plain; charset="utf-8" The RISC-V Debug Support specification suggests debuggers provide "virtual debug registers" to show state not directly visible in the ISA, and defines one such register, `priv', which encodes the processor's current operating mode in the two least significant bits. GDB represents virtual debug registers in the `org.gnu.gdb.riscv.virtual' feature of RISC-V target descriptions. This patch adds the `v' (hypervisor virtualization mode) bit to `priv' as specified by section 4.9.1 of version 1.0 of the RISC-V Debug Support specification. Signed-off-by: Konrad Schwarz --- gdb-xml/riscv-32bit-virtual.xml | 30 ++++++++++++++++++++++++++++-- gdb-xml/riscv-64bit-virtual.xml | 30 ++++++++++++++++++++++++++++-- target/riscv/gdbstub.c | 5 ++++- 3 files changed, 60 insertions(+), 5 deletions(-) diff --git a/gdb-xml/riscv-32bit-virtual.xml b/gdb-xml/riscv-32bit-virtual.= xml index 905f1c555d..7dad42cd67 100644 --- a/gdb-xml/riscv-32bit-virtual.xml +++ b/gdb-xml/riscv-32bit-virtual.xml @@ -5,7 +5,33 @@ are permitted in any medium without royalty provided the copyright notice and this notice are preserved. --> =20 + + - - + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-64bit-virtual.xml b/gdb-xml/riscv-64bit-virtual.= xml index 62d86c237b..02c234670d 100644 --- a/gdb-xml/riscv-64bit-virtual.xml +++ b/gdb-xml/riscv-64bit-virtual.xml @@ -5,7 +5,33 @@ are permitted in any medium without royalty provided the copyright notice and this notice are preserved. --> =20 + + - - + + + + + + + + + + + + + + + + + + + diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 9c3f68eeaf..b3fa9f864e 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -136,7 +136,10 @@ static int riscv_gdb_get_virtual(CPURISCVState *cs, GB= yteArray *buf, int n) #ifdef CONFIG_USER_ONLY return gdb_get_regl(buf, 0); #else - return gdb_get_regl(buf, cs->priv); + RISCVCPU *const cpu =3D RISCV_CPU(cs); + CPURISCVState *const env =3D &cpu->env; + return gdb_get_regl(buf, riscv_cpu_virt_enabled(env) << 2 | cs->pr= iv); + /* per RISCV Debug Spec 1.0, 4.9.1 */ #endif } return 0; --=20 Konrad Schwarz