From nobody Sun Feb 8 02:21:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163529920766248.237772648285954; Tue, 26 Oct 2021 18:46:47 -0700 (PDT) Received: from localhost ([::1]:33758 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mfY1e-0000nU-L9 for importer@patchew.org; Tue, 26 Oct 2021 21:46:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfXwP-0001WU-3l for qemu-devel@nongnu.org; Tue, 26 Oct 2021 21:41:21 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:62139) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfXwI-0003G8-An for qemu-devel@nongnu.org; Tue, 26 Oct 2021 21:41:20 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 16DB0756078; Wed, 27 Oct 2021 03:41:09 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 96C0F7463B7; Wed, 27 Oct 2021 03:41:08 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 1/6] hw/sh4: Fix a typo in a comment Date: Wed, 27 Oct 2021 03:32:21 +0200 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Magnus Damm , Yoshinori Sato Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1635299208215100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: BALATON Zoltan Reviewed-by: Richard Henderson --- hw/timer/sh_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 02eb865908..0a18ac8276 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -107,7 +107,7 @@ static void sh_timer_write(void *opaque, hwaddr offset, if (s->enabled) { /* * Pause the timer if it is running. This may cause some inacc= uracy - * dure to rounding, but avoids a whole lot of other messyness + * due to rounding, but avoids a whole lot of other messyness */ ptimer_stop(s->timer); } --=20 2.21.4 From nobody Sun Feb 8 02:21:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635299014702435.7984363212237; Tue, 26 Oct 2021 18:43:34 -0700 (PDT) Received: from localhost ([::1]:54604 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mfXyX-0004GQ-5w for importer@patchew.org; Tue, 26 Oct 2021 21:43:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47008) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfXwP-0001XL-Bs for qemu-devel@nongnu.org; Tue, 26 Oct 2021 21:41:21 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:62157) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfXwM-0003J4-BX for qemu-devel@nongnu.org; Tue, 26 Oct 2021 21:41:21 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 25C2575619C; Wed, 27 Oct 2021 03:41:16 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 9D867748F58; Wed, 27 Oct 2021 03:41:08 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 2/6] hw//sh4: Use qemu_log instead of fprintf to stderr Date: Wed, 27 Oct 2021 03:32:21 +0200 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Magnus Damm , Yoshinori Sato Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1635299017004100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: BALATON Zoltan Reviewed-by: Richard Henderson --- hw/char/sh_serial.c | 7 ++++--- hw/sh4/sh7750.c | 13 ++++++------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 1b1e6a6a04..c4231975c7 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -30,6 +30,7 @@ #include "hw/sh4/sh.h" #include "chardev/char-fe.h" #include "qapi/error.h" +#include "qemu/log.h" #include "qemu/timer.h" =20 //#define DEBUG_SERIAL @@ -200,8 +201,8 @@ static void sh_serial_write(void *opaque, hwaddr offs, } } =20 - fprintf(stderr, "sh_serial: unsupported write to 0x%02" - HWADDR_PRIx "\n", offs); + qemu_log_mask(LOG_UNIMP, "sh_serial: unsupported write to 0x%02" + HWADDR_PRIx "\n", offs); abort(); } =20 @@ -307,7 +308,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr off= s, #endif =20 if (ret & ~((1 << 16) - 1)) { - fprintf(stderr, "sh_serial: unsupported read from 0x%02" + qemu_log_mask(LOG_UNIMP, "sh_serial: unsupported read from 0x%02" HWADDR_PRIx "\n", offs); abort(); } diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index ca7e261aba..f2f251f165 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -24,6 +24,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" #include "hw/irq.h" #include "hw/sh4/sh.h" #include "sysemu/sysemu.h" @@ -205,13 +206,13 @@ static void portb_changed(SH7750State *s, uint16_t pr= ev) =20 static void error_access(const char *kind, hwaddr addr) { - fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n", - kind, regname(addr), addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s to %s (0x" TARGET_FMT_plx + ") not supported\n", kind, regname(addr), addr); } =20 static void ignore_access(const char *kind, hwaddr addr) { - fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n", + qemu_log_mask(LOG_UNIMP, "%s to %s (0x" TARGET_FMT_plx ") ignored\n", kind, regname(addr), addr); } =20 @@ -241,8 +242,7 @@ static uint32_t sh7750_mem_readw(void *opaque, hwaddr a= ddr) case SH7750_PCR_A7: return s->pcr; case SH7750_RFCR_A7: - fprintf(stderr, - "Read access to refresh count register, incrementing\n"); + /* Read access to refresh count register, incrementing */ return s->rfcr++; case SH7750_PDTRA_A7: return porta_lines(s); @@ -363,13 +363,12 @@ static void sh7750_mem_writew(void *opaque, hwaddr ad= dr, portb_changed(s, temp); return; case SH7750_RFCR_A7: - fprintf(stderr, "Write access to refresh count register\n"); s->rfcr =3D mem_value; return; case SH7750_GPIOIC_A7: s->gpioic =3D mem_value; if (mem_value !=3D 0) { - fprintf(stderr, "I/O interrupts not implemented\n"); + qemu_log_mask(LOG_UNIMP, "I/O interrupts not implemented\n"); abort(); } return; --=20 2.21.4 From nobody Sun Feb 8 02:21:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163529929796625.511327946878623; Tue, 26 Oct 2021 18:48:17 -0700 (PDT) Received: from localhost ([::1]:36836 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mfY36-0002uc-Vw for importer@patchew.org; Tue, 26 Oct 2021 21:48:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46984) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfXwO-0001UV-0r for qemu-devel@nongnu.org; Tue, 26 Oct 2021 21:41:20 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:62158) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfXwL-0003J5-Hx for qemu-devel@nongnu.org; Tue, 26 Oct 2021 21:41:19 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 5ADD475619D; Wed, 27 Oct 2021 03:41:16 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id A35B6756030; Wed, 27 Oct 2021 03:41:08 +0200 (CEST) Message-Id: <031a5111bb1ef1e66fd8f05fbe4a5ecbbcb25396.1635298341.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 3/6] hw/sh4: Change debug printfs to traces Date: Wed, 27 Oct 2021 03:32:21 +0200 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Magnus Damm , Yoshinori Sato Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1635299300202100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: BALATON Zoltan --- hw/char/sh_serial.c | 13 ++----- hw/char/trace-events | 3 ++ hw/intc/sh_intc.c | 79 +++++++++++-------------------------------- hw/intc/trace-events | 8 +++++ hw/sh4/sh7750.c | 8 ++--- hw/sh4/trace-events | 3 ++ hw/sh4/trace.h | 1 + hw/timer/sh_timer.c | 12 ++----- hw/timer/trace-events | 3 ++ meson.build | 1 + 10 files changed, 47 insertions(+), 84 deletions(-) create mode 100644 hw/sh4/trace-events create mode 100644 hw/sh4/trace.h diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index c4231975c7..ccfd570d29 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -32,8 +32,7 @@ #include "qapi/error.h" #include "qemu/log.h" #include "qemu/timer.h" - -//#define DEBUG_SERIAL +#include "trace.h" =20 #define SH_SERIAL_FLAG_TEND (1 << 0) #define SH_SERIAL_FLAG_TDE (1 << 1) @@ -90,10 +89,7 @@ static void sh_serial_write(void *opaque, hwaddr offs, sh_serial_state *s =3D opaque; unsigned char ch; =20 -#ifdef DEBUG_SERIAL - printf("sh_serial: write offs=3D0x%02x val=3D0x%02x\n", - offs, val); -#endif + trace_sh_serial("write", size, offs, val); switch (offs) { case 0x00: /* SMR */ s->smr =3D val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); @@ -302,10 +298,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr of= fs, break; } } -#ifdef DEBUG_SERIAL - printf("sh_serial: read offs=3D0x%02x val=3D0x%x\n", - offs, ret); -#endif + trace_sh_serial("read ", size, offs, ret); =20 if (ret & ~((1 << 16) - 1)) { qemu_log_mask(LOG_UNIMP, "sh_serial: unsupported read from 0x%02" diff --git a/hw/char/trace-events b/hw/char/trace-events index b774832af4..3e49860e7b 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -101,3 +101,6 @@ exynos_uart_rx_timeout(uint32_t channel, uint32_t stat,= uint32_t intsp) "UART%d: =20 # cadence_uart.c cadence_uart_baudrate(unsigned baudrate) "baudrate %u" + +# sh_serial.c +sh_serial(const char *op, unsigned size, uint64_t offs, uint64_t val) "%s = size %d offs 0x%02" PRIx64 " val 0x%02" PRIx64 diff --git a/hw/intc/sh_intc.c b/hw/intc/sh_intc.c index e7c9964dba..c1058d97c0 100644 --- a/hw/intc/sh_intc.c +++ b/hw/intc/sh_intc.c @@ -9,13 +9,12 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" #include "cpu.h" #include "hw/sh4/sh_intc.h" #include "hw/irq.h" #include "hw/sh4/sh.h" - -//#define DEBUG_INTC -//#define DEBUG_INTC_SOURCES +#include "trace.h" =20 #define INTC_A7(x) ((x) & 0x1fffffff) =20 @@ -57,20 +56,14 @@ void sh_intc_toggle_source(struct intc_source *source, } } =20 - if (enable_changed || assert_adj || pending_changed) { -#ifdef DEBUG_INTC_SOURCES - printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n", - source->parent->pending, - source->asserted, - source->enable_count, - source->enable_max, - source->vect, - source->asserted ? "asserted " : - assert_adj ? "deasserted" : "", - enable_changed =3D=3D 1 ? "enabled " : - enable_changed =3D=3D -1 ? "disabled " : "", - source->pending ? "pending" : ""); -#endif + if (enable_changed || assert_adj || pending_changed) { + trace_sh_intc_sources(source->parent->pending, source->asserted, + source->enable_count, source->enable_max, + source->vect, source->asserted ? "asserted "= : + assert_adj ? "deasserted" : "", + enable_changed =3D=3D 1 ? "enabled " : + enable_changed =3D=3D -1 ? "disabled " : "", + source->pending ? "pending" : ""); } } =20 @@ -101,10 +94,7 @@ int sh_intc_get_pending_vector(struct intc_desc *desc, = int imask) struct intc_source *source =3D desc->sources + i; =20 if (source->pending) { -#ifdef DEBUG_INTC_SOURCES - printf("sh_intc: (%d) returning interrupt source 0x%x\n", - desc->pending, source->vect); -#endif + trace_sh_intc_pending(desc->pending, source->vect); return source->vect; } } @@ -199,30 +189,22 @@ static void sh_intc_toggle_mask(struct intc_desc *des= c, intc_enum id, return; } if (!source->next_enum_id && (!source->enable_max || !source->vect)) { -#ifdef DEBUG_INTC_SOURCES - printf("sh_intc: reserved interrupt source %d modified\n", id); -#endif + qemu_log_mask(LOG_UNIMP, + "sh_intc: reserved interrupt source %d modified\n", = id); return; } =20 if (source->vect) { sh_intc_toggle_source(source, enable ? 1 : -1, 0); } -#ifdef DEBUG_INTC - else { - printf("setting interrupt group %d to %d\n", id, !!enable); - } -#endif =20 if ((is_group || !source->vect) && source->next_enum_id) { sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1); } =20 -#ifdef DEBUG_INTC if (!source->vect) { - printf("setting interrupt group %d to %d - done\n", id, !!enable); + trace_sh_intc_set(id, !!enable); } -#endif } =20 static uint64_t sh_intc_read(void *opaque, hwaddr offset, @@ -235,12 +217,9 @@ static uint64_t sh_intc_read(void *opaque, hwaddr offs= et, unsigned int mode =3D 0; unsigned long *valuep; =20 -#ifdef DEBUG_INTC - printf("sh_intc_read 0x%lx\n", (unsigned long) offset); -#endif - sh_intc_locate(desc, (unsigned long)offset, &valuep, &enum_ids, &first, &width, &mode); + trace_sh_intc_read(size, offset, *valuep); return *valuep; } =20 @@ -256,13 +235,9 @@ static void sh_intc_write(void *opaque, hwaddr offset, unsigned long *valuep; unsigned long mask; =20 -#ifdef DEBUG_INTC - printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value); -#endif - + trace_sh_intc_write(size, offset, value); sh_intc_locate(desc, (unsigned long)offset, &valuep, &enum_ids, &first, &width, &mode); - switch (mode) { case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break; @@ -282,18 +257,10 @@ static void sh_intc_write(void *opaque, hwaddr offset, if ((*valuep & mask) =3D=3D (value & mask)) { continue; } -#if 0 - printf("k =3D %d, first =3D %d, enum =3D %d, mask =3D 0x%08x\n", - k, first, enum_ids[k], (unsigned int)mask); -#endif sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0); } =20 *valuep =3D value; - -#ifdef DEBUG_INTC - printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, valu= e); -#endif } =20 static const MemoryRegionOps sh_intc_ops =3D { @@ -416,11 +383,8 @@ void sh_intc_register_sources(struct intc_desc *desc, s =3D sh_intc_source(desc, vect->enum_id); if (s) { s->vect =3D vect->vect; - -#ifdef DEBUG_INTC_SOURCES - printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n", - vect->enum_id, s->vect, s->enable_count, s->enable_max); -#endif + trace_sh_intc_register("source", vect->enum_id, s->vect, + s->enable_count, s->enable_max); } } =20 @@ -438,11 +402,8 @@ void sh_intc_register_sources(struct intc_desc *desc, s =3D sh_intc_source(desc, gr->enum_ids[k - 1]); s->next_enum_id =3D gr->enum_ids[k]; } - -#ifdef DEBUG_INTC_SOURCES - printf("sh_intc: registered group %d (%d/%d)\n", - gr->enum_id, s->enable_count, s->enable_max); -#endif + trace_sh_intc_register("group", gr->enum_id, 0xffff, + s->enable_count, s->enable_max); } } } diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 6a17d38998..9c7e41f41c 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -238,3 +238,11 @@ goldfish_pic_write(void *dev, int idx, unsigned int ad= dr, unsigned int size, uin goldfish_pic_reset(void *dev, int idx) "pic: %p goldfish-irq.%d" goldfish_pic_realize(void *dev, int idx) "pic: %p goldfish-irq.%d" goldfish_pic_instance_init(void *dev) "pic: %p goldfish-irq" + +# sh_intc.c +sh_intc_sources(int p, int a, int c, int m, unsigned short v, const char *= s1, const char *s2, const char *s3) "(%d/%d/%d/%d) interrupt source 0x%x %s= %s%s" +sh_intc_pending(int p, unsigned short v) "(%d) returning interrupt source = 0x%x" +sh_intc_register(const char *s, int id, unsigned short v, int c, int m) "%= s %d -> 0x%04x (%d/%d)" +sh_intc_read(unsigned size, uint64_t offset, unsigned long val) "size %d 0= x%" PRIx64 " -> 0x%" PRIx64 +sh_intc_write(unsigned size, uint64_t offset, unsigned long val) "size %d = 0x%" PRIx64 " <- 0x%" PRIx64 +sh_intc_set(int id, int enable) "setting interrupt group %d to %d" diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index f2f251f165..c3c3caf952 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -33,6 +33,7 @@ #include "hw/sh4/sh_intc.h" #include "hw/timer/tmu012.h" #include "exec/exec-all.h" +#include "trace.h" =20 #define NB_DEVICES 4 =20 @@ -148,15 +149,11 @@ static void porta_changed(SH7750State *s, uint16_t pr= ev) uint16_t currenta, changes; int i, r =3D 0; =20 -#if 0 - fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n", - prev, porta_lines(s)); - fprintf(stderr, "pdtra=3D0x%04x, pctra=3D0x%08x\n", s->pdtra, s->pctra= ); -#endif currenta =3D porta_lines(s); if (currenta =3D=3D prev) { return; } + trace_sh7750_porta(prev, currenta, s->pdtra, s->pctra); changes =3D currenta ^ prev; =20 for (i =3D 0; i < NB_DEVICES; i++) { @@ -183,6 +180,7 @@ static void portb_changed(SH7750State *s, uint16_t prev) if (currentb =3D=3D prev) { return; } + trace_sh7750_portb(prev, currentb, s->pdtrb, s->pctrb); changes =3D currentb ^ prev; =20 for (i =3D 0; i < NB_DEVICES; i++) { diff --git a/hw/sh4/trace-events b/hw/sh4/trace-events new file mode 100644 index 0000000000..4b61cd56c8 --- /dev/null +++ b/hw/sh4/trace-events @@ -0,0 +1,3 @@ +# sh7750.c +sh7750_porta(uint16_t prev, uint16_t cur, uint16_t pdtr, uint16_t pctr) "p= orta changed from 0x%04x to 0x%04x\npdtra=3D0x%04x, pctra=3D0x%08x" +sh7750_portb(uint16_t prev, uint16_t cur, uint16_t pdtr, uint16_t pctr) "p= ortb changed from 0x%04x to 0x%04x\npdtrb=3D0x%04x, pctrb=3D0x%08x" diff --git a/hw/sh4/trace.h b/hw/sh4/trace.h new file mode 100644 index 0000000000..e2c13323b7 --- /dev/null +++ b/hw/sh4/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_sh4.h" diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 0a18ac8276..1f29f4a650 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -15,8 +15,7 @@ #include "hw/sh4/sh.h" #include "hw/timer/tmu012.h" #include "hw/ptimer.h" - -//#define DEBUG_TIMER +#include "trace.h" =20 #define TIMER_TCR_TPSC (7 << 0) #define TIMER_TCR_CKEG (3 << 3) @@ -203,10 +202,7 @@ static void sh_timer_start_stop(void *opaque, int enab= le) { sh_timer_state *s =3D (sh_timer_state *)opaque; =20 -#ifdef DEBUG_TIMER - printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled); -#endif - + trace_sh_timer_start_stop(enable, s->enabled); ptimer_transaction_begin(s->timer); if (s->enabled && !enable) { ptimer_stop(s->timer); @@ -216,10 +212,6 @@ static void sh_timer_start_stop(void *opaque, int enab= le) } ptimer_transaction_commit(s->timer); s->enabled =3D !!enable; - -#ifdef DEBUG_TIMER - printf("sh_timer_start_stop done %d\n", s->enabled); -#endif } =20 static void sh_timer_tick(void *opaque) diff --git a/hw/timer/trace-events b/hw/timer/trace-events index d0edcd2a80..653025817b 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -94,3 +94,6 @@ sifive_pwm_set_alarm(uint64_t alarm, uint64_t now) "Setti= ng alarm to: 0x%" PRIx6 sifive_pwm_interrupt(int num) "Interrupt %d" sifive_pwm_read(uint64_t offset) "Read at address: 0x%" PRIx64 sifive_pwm_write(uint64_t data, uint64_t offset) "Write 0x%" PRIx64 " at a= ddress: 0x%" PRIx64 + +# sh_timer.c +sh_timer_start_stop(int enable, int current) "%d (%d)" diff --git a/meson.build b/meson.build index 2c5b53cbe2..b092728397 100644 --- a/meson.build +++ b/meson.build @@ -2459,6 +2459,7 @@ if have_system 'hw/s390x', 'hw/scsi', 'hw/sd', + 'hw/sh4', 'hw/sparc', 'hw/sparc64', 'hw/ssi', --=20 2.21.4 From nobody Sun Feb 8 02:21:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635299028451673.6420920781466; Tue, 26 Oct 2021 18:43:48 -0700 (PDT) Received: from localhost ([::1]:54760 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mfXyl-0004Mi-FC for importer@patchew.org; Tue, 26 Oct 2021 21:43:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47004) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfXwP-0001WB-0A for qemu-devel@nongnu.org; Tue, 26 Oct 2021 21:41:21 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:62135) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfXwI-0003G7-Ao for qemu-devel@nongnu.org; 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charset="utf-8" Signed-off-by: BALATON Zoltan Reviewed-by: Richard Henderson --- hw/sh4/r2d.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 57ccae7249..72759413f3 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -26,6 +26,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "cpu.h" #include "hw/sysbus.h" #include "hw/sh4/sh.h" @@ -324,7 +325,7 @@ static void r2d_init(MachineState *machine) SDRAM_BASE + LINUX_LOAD_OFFSET, INITRD_LOAD_OFFSET - LINUX_LOAD_= OFFSET); if (kernel_size < 0) { - fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_f= ilename); + error_report("qemu: could not load kernel '%s'", kernel_filena= me); exit(1); } =20 @@ -345,7 +346,7 @@ static void r2d_init(MachineState *machine) SDRAM_SIZE - INITRD_LOAD_OFFSET); =20 if (initrd_size < 0) { - fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_f= ilename); + error_report("qemu: could not load initrd '%s'", initrd_filena= me); exit(1); } =20 --=20 2.21.4 From nobody Sun Feb 8 02:21:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635299189033212.3377813611437; Tue, 26 Oct 2021 18:46:29 -0700 (PDT) Received: from localhost ([::1]:33338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mfY1M-0000V5-0X for importer@patchew.org; Tue, 26 Oct 2021 21:46:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46948) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfXwM-0001Tl-9L for qemu-devel@nongnu.org; Tue, 26 Oct 2021 21:41:18 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:62142) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfXwI-0003G9-BM for qemu-devel@nongnu.org; Tue, 26 Oct 2021 21:41:18 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 2412F756194; Wed, 27 Oct 2021 03:41:09 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id AC01975602D; Wed, 27 Oct 2021 03:41:08 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 5/6] hw/char/sh_serial: QOM-ify Date: Wed, 27 Oct 2021 03:32:21 +0200 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Magnus Damm , Yoshinori Sato Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1635299189738100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: BALATON Zoltan --- hw/char/sh_serial.c | 127 ++++++++++++++++++++++++++------------------ hw/sh4/sh7750.c | 62 +++++++++++++++------ include/hw/sh4/sh.h | 9 +--- 3 files changed, 123 insertions(+), 75 deletions(-) diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index ccfd570d29..91973affb5 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -26,7 +26,11 @@ */ =20 #include "qemu/osdep.h" +#include "hw/sysbus.h" #include "hw/irq.h" +#include "hw/qdev-core.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" #include "hw/sh4/sh.h" #include "chardev/char-fe.h" #include "qapi/error.h" @@ -42,10 +46,10 @@ =20 #define SH_RX_FIFO_LENGTH (16) =20 -typedef struct { - MemoryRegion iomem; - MemoryRegion iomem_p4; - MemoryRegion iomem_a7; +OBJECT_DECLARE_SIMPLE_TYPE(SHSerialState, SH_SERIAL) + +struct SHSerialState { + SysBusDevice parent; uint8_t smr; uint8_t brr; uint8_t scr; @@ -59,13 +63,12 @@ typedef struct { uint8_t rx_tail; uint8_t rx_head; =20 - int freq; - int feat; + uint8_t feat; int flags; int rtrg; =20 CharBackend chr; - QEMUTimer *fifo_timeout_timer; + QEMUTimer fifo_timeout_timer; uint64_t etu; /* Elementary Time Unit (ns) */ =20 qemu_irq eri; @@ -73,9 +76,13 @@ typedef struct { qemu_irq txi; qemu_irq tei; qemu_irq bri; -} sh_serial_state; +}; + +typedef struct {} SHSerialStateClass; =20 -static void sh_serial_clear_fifo(sh_serial_state *s) +OBJECT_DEFINE_TYPE(SHSerialState, sh_serial, SH_SERIAL, SYS_BUS_DEVICE) + +static void sh_serial_clear_fifo(SHSerialState *s) { memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH); s->rx_cnt =3D 0; @@ -86,7 +93,7 @@ static void sh_serial_clear_fifo(sh_serial_state *s) static void sh_serial_write(void *opaque, hwaddr offs, uint64_t val, unsigned size) { - sh_serial_state *s =3D opaque; + SHSerialState *s =3D opaque; unsigned char ch; =20 trace_sh_serial("write", size, offs, val); @@ -205,7 +212,7 @@ static void sh_serial_write(void *opaque, hwaddr offs, static uint64_t sh_serial_read(void *opaque, hwaddr offs, unsigned size) { - sh_serial_state *s =3D opaque; + SHSerialState *s =3D opaque; uint32_t ret =3D ~0; =20 #if 0 @@ -309,12 +316,12 @@ static uint64_t sh_serial_read(void *opaque, hwaddr o= ffs, return ret; } =20 -static int sh_serial_can_receive(sh_serial_state *s) +static int sh_serial_can_receive(SHSerialState *s) { return s->scr & (1 << 4); } =20 -static void sh_serial_receive_break(sh_serial_state *s) +static void sh_serial_receive_break(SHSerialState *s) { if (s->feat & SH_SERIAL_FEAT_SCIF) { s->sr |=3D (1 << 4); @@ -323,13 +330,13 @@ static void sh_serial_receive_break(sh_serial_state *= s) =20 static int sh_serial_can_receive1(void *opaque) { - sh_serial_state *s =3D opaque; + SHSerialState *s =3D opaque; return sh_serial_can_receive(s); } =20 static void sh_serial_timeout_int(void *opaque) { - sh_serial_state *s =3D opaque; + SHSerialState *s =3D opaque; =20 s->flags |=3D SH_SERIAL_FLAG_RDF; if (s->scr & (1 << 6) && s->rxi) { @@ -339,7 +346,7 @@ static void sh_serial_timeout_int(void *opaque) =20 static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) { - sh_serial_state *s =3D opaque; + SHSerialState *s =3D opaque; =20 if (s->feat & SH_SERIAL_FEAT_SCIF) { int i; @@ -353,11 +360,11 @@ static void sh_serial_receive1(void *opaque, const ui= nt8_t *buf, int size) if (s->rx_cnt >=3D s->rtrg) { s->flags |=3D SH_SERIAL_FLAG_RDF; if (s->scr & (1 << 6) && s->rxi) { - timer_del(s->fifo_timeout_timer); + timer_del(&s->fifo_timeout_timer); qemu_set_irq(s->rxi, 1); } } else { - timer_mod(s->fifo_timeout_timer, + timer_mod(&s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->et= u); } } @@ -369,7 +376,7 @@ static void sh_serial_receive1(void *opaque, const uint= 8_t *buf, int size) =20 static void sh_serial_event(void *opaque, QEMUChrEvent event) { - sh_serial_state *s =3D opaque; + SHSerialState *s =3D opaque; if (event =3D=3D CHR_EVENT_BREAK) { sh_serial_receive_break(s); } @@ -381,20 +388,10 @@ static const MemoryRegionOps sh_serial_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -void sh_serial_init(MemoryRegion *sysmem, - hwaddr base, int feat, - uint32_t freq, Chardev *chr, - qemu_irq eri_source, - qemu_irq rxi_source, - qemu_irq txi_source, - qemu_irq tei_source, - qemu_irq bri_source) +static void sh_serial_reset(DeviceState *dev) { - sh_serial_state *s; - - s =3D g_malloc0(sizeof(sh_serial_state)); + SHSerialState *s =3D SH_SERIAL(dev); =20 - s->feat =3D feat; s->flags =3D SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE; s->rtrg =3D 1; =20 @@ -403,38 +400,64 @@ void sh_serial_init(MemoryRegion *sysmem, s->scr =3D 1 << 5; /* pretend that TX is enabled so early printk works= */ s->sptr =3D 0; =20 - if (feat & SH_SERIAL_FEAT_SCIF) { + if (s->feat & SH_SERIAL_FEAT_SCIF) { s->fcr =3D 0; } else { s->dr =3D 0xff; } =20 sh_serial_clear_fifo(s); +} =20 - memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s, - "serial", 0x100000000ULL); - - memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem, - 0, 0x28); - memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4); - - memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem, - 0, 0x28); - memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7); - - if (chr) { - qemu_chr_fe_init(&s->chr, chr, &error_abort); +static void sh_serial_realize(DeviceState *d, Error **errp) +{ + SHSerialState *s =3D SH_SERIAL(d); + MemoryRegion *iomem =3D g_malloc(sizeof(*iomem)); + + assert(d->id); + memory_region_init_io(iomem, OBJECT(d), &sh_serial_ops, s, d->id, 0x28= ); + sysbus_init_mmio(SYS_BUS_DEVICE(d), iomem); + qdev_init_gpio_out_named(d, &s->eri, "eri", 1); + qdev_init_gpio_out_named(d, &s->rxi, "rxi", 1); + qdev_init_gpio_out_named(d, &s->txi, "txi", 1); + qdev_init_gpio_out_named(d, &s->tei, "tei", 1); + qdev_init_gpio_out_named(d, &s->bri, "bri", 1); + + if (qemu_chr_fe_backend_connected(&s->chr)) { qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1, sh_serial_receive1, sh_serial_event, NULL, s, NULL, true); } =20 - s->fifo_timeout_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, - sh_serial_timeout_int, s); + timer_init_ns(&s->fifo_timeout_timer, QEMU_CLOCK_VIRTUAL, + sh_serial_timeout_int, s); s->etu =3D NANOSECONDS_PER_SECOND / 9600; - s->eri =3D eri_source; - s->rxi =3D rxi_source; - s->txi =3D txi_source; - s->tei =3D tei_source; - s->bri =3D bri_source; +} + +static void sh_serial_finalize(Object *obj) +{ + SHSerialState *s =3D SH_SERIAL(obj); + + timer_del(&s->fifo_timeout_timer); +} + +static void sh_serial_init(Object *obj) +{ +} + +static Property sh_serial_properties[] =3D { + DEFINE_PROP_CHR("chardev", SHSerialState, chr), + DEFINE_PROP_UINT8("features", SHSerialState, feat, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void sh_serial_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + device_class_set_props(dc, sh_serial_properties); + dc->realize =3D sh_serial_realize; + dc->reset =3D sh_serial_reset; + /* Reason: part of SuperH CPU/SoC, needs to be wired up */ + dc->user_creatable =3D false; } diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index c3c3caf952..dba40a6fb4 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -24,10 +24,14 @@ */ =20 #include "qemu/osdep.h" +#include "qapi/error.h" #include "qemu/log.h" +#include "hw/sysbus.h" #include "hw/irq.h" #include "hw/sh4/sh.h" #include "sysemu/sysemu.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" #include "sh7750_regs.h" #include "sh7750_regnames.h" #include "hw/sh4/sh_intc.h" @@ -761,6 +765,9 @@ static const MemoryRegionOps sh7750_mmct_ops =3D { SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) { SH7750State *s; + DeviceState *dev; + SysBusDevice *sb; + MemoryRegion *mr, *alias; =20 s =3D g_malloc0(sizeof(SH7750State)); s->cpu =3D cpu; @@ -806,21 +813,46 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion= *sysmem) =20 cpu->env.intc_handle =3D &s->intc; =20 - sh_serial_init(sysmem, 0x1fe00000, - 0, s->periph_freq, serial_hd(0), - s->intc.irqs[SCI1_ERI], - s->intc.irqs[SCI1_RXI], - s->intc.irqs[SCI1_TXI], - s->intc.irqs[SCI1_TEI], - NULL); - sh_serial_init(sysmem, 0x1fe80000, - SH_SERIAL_FEAT_SCIF, - s->periph_freq, serial_hd(1), - s->intc.irqs[SCIF_ERI], - s->intc.irqs[SCIF_RXI], - s->intc.irqs[SCIF_TXI], - NULL, - s->intc.irqs[SCIF_BRI]); + /* SCI */ + dev =3D qdev_new(TYPE_SH_SERIAL); + dev->id =3D (char *)"sci"; + qdev_prop_set_chr(dev, "chardev", serial_hd(0)); + sb =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(sb, &error_fatal); + mr =3D sysbus_mmio_get_region(sb, 0); + alias =3D g_malloc(sizeof(*alias)); + memory_region_init_alias(alias, OBJECT(dev), "sci-p4", mr, + 0, memory_region_size(mr)); + memory_region_add_subregion(sysmem, P4ADDR(0x1fe00000), alias); + alias =3D g_malloc(sizeof(*alias)); + memory_region_init_alias(alias, OBJECT(dev), "sci-a7", mr, + 0, memory_region_size(mr)); + memory_region_add_subregion(sysmem, A7ADDR(0x1fe00000), alias); + qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCI1_ERI]); + qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCI1_RXI]); + qdev_connect_gpio_out_named(dev, "txi", 0, s->intc.irqs[SCI1_TXI]); + qdev_connect_gpio_out_named(dev, "tei", 0, s->intc.irqs[SCI1_TEI]); + + /* SCIF */ + dev =3D qdev_new(TYPE_SH_SERIAL); + dev->id =3D (char *)"scif"; + qdev_prop_set_chr(dev, "chardev", serial_hd(1)); + qdev_prop_set_uint8(dev, "features", SH_SERIAL_FEAT_SCIF); + sb =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(sb, &error_fatal); + mr =3D sysbus_mmio_get_region(sb, 0); + alias =3D g_malloc(sizeof(*alias)); + memory_region_init_alias(alias, OBJECT(dev), "scif-p4", mr, + 0, memory_region_size(mr)); + memory_region_add_subregion(sysmem, P4ADDR(0x1fe80000), alias); + alias =3D g_malloc(sizeof(*alias)); + memory_region_init_alias(alias, OBJECT(dev), "scif-a7", mr, + 0, memory_region_size(mr)); + memory_region_add_subregion(sysmem, A7ADDR(0x1fe80000), alias); + qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCIF_ERI]); + qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCIF_RXI]); + qdev_connect_gpio_out_named(dev, "txi", 0, s->intc.irqs[SCIF_TXI]); + qdev_connect_gpio_out_named(dev, "bri", 0, s->intc.irqs[SCIF_BRI]); =20 tmu012_init(sysmem, 0x1fd80000, TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h index 366cedcda0..ec716cdd45 100644 --- a/include/hw/sh4/sh.h +++ b/include/hw/sh4/sh.h @@ -54,15 +54,8 @@ int sh7750_register_io_device(struct SH7750State *s, sh7750_io_device *device); =20 /* sh_serial.c */ +#define TYPE_SH_SERIAL "sh-serial" #define SH_SERIAL_FEAT_SCIF (1 << 0) -void sh_serial_init(MemoryRegion *sysmem, - hwaddr base, int feat, - uint32_t freq, Chardev *chr, - qemu_irq eri_source, - qemu_irq rxi_source, - qemu_irq txi_source, - qemu_irq tei_source, - qemu_irq bri_source); =20 /* sh7750.c */ qemu_irq sh7750_irl(struct SH7750State *s); --=20 2.21.4 From nobody Sun Feb 8 02:21:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1635299007223630.360357289483; Tue, 26 Oct 2021 18:43:27 -0700 (PDT) Received: from localhost ([::1]:54236 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mfXyP-000423-Qj for importer@patchew.org; Tue, 26 Oct 2021 21:43:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfXwL-0001TW-4j for qemu-devel@nongnu.org; Tue, 26 Oct 2021 21:41:17 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:62145) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfXwI-0003GB-AY for qemu-devel@nongnu.org; Tue, 26 Oct 2021 21:41:16 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 3F038756197; Wed, 27 Oct 2021 03:41:09 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id B4D4375603A; Wed, 27 Oct 2021 03:41:08 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 6/6] hw/char/sh_serial: Add device id to trace output Date: Wed, 27 Oct 2021 03:32:21 +0200 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Magnus Damm , Yoshinori Sato Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1635299009236100002 Content-Type: text/plain; charset="utf-8" Normally there are at least two sh_serial instances. Add device id to trace messages to make it clear which instance they belong to otherwise its not possible to tell which serial device is accessed. Signed-off-by: BALATON Zoltan --- hw/char/sh_serial.c | 6 ++++-- hw/char/trace-events | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 91973affb5..c2dc51f7f0 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -94,9 +94,10 @@ static void sh_serial_write(void *opaque, hwaddr offs, uint64_t val, unsigned size) { SHSerialState *s =3D opaque; + DeviceState *d =3D DEVICE(s); unsigned char ch; =20 - trace_sh_serial("write", size, offs, val); + trace_sh_serial(d->id, "write", size, offs, val); switch (offs) { case 0x00: /* SMR */ s->smr =3D val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); @@ -213,6 +214,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr off= s, unsigned size) { SHSerialState *s =3D opaque; + DeviceState *d =3D DEVICE(s); uint32_t ret =3D ~0; =20 #if 0 @@ -305,7 +307,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr off= s, break; } } - trace_sh_serial("read ", size, offs, ret); + trace_sh_serial(d->id, "read ", size, offs, ret); =20 if (ret & ~((1 << 16) - 1)) { qemu_log_mask(LOG_UNIMP, "sh_serial: unsupported read from 0x%02" diff --git a/hw/char/trace-events b/hw/char/trace-events index 3e49860e7b..2f799c57ae 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -103,4 +103,4 @@ exynos_uart_rx_timeout(uint32_t channel, uint32_t stat,= uint32_t intsp) "UART%d: cadence_uart_baudrate(unsigned baudrate) "baudrate %u" =20 # sh_serial.c -sh_serial(const char *op, unsigned size, uint64_t offs, uint64_t val) "%s = size %d offs 0x%02" PRIx64 " val 0x%02" PRIx64 +sh_serial(char *id, const char *op, unsigned size, uint64_t offs, uint64_t= val) "%s %s size %d offs 0x%02" PRIx64 " val 0x%02" PRIx64 --=20 2.21.4