From nobody Sun May 19 05:22:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1619235028; cv=none; d=zohomail.com; s=zohoarc; b=VGvlWqyS1HrI1L99xnEQK+NpqeCUcCtyZdgM5Cm3/MyAMuraGTZPRLs/04BcTTQMUiWhHzSk20zZWPmQCD0ebwMsTMbegS5rTIfxXuPJML4oiEhB8Z0DPwiW93AUoUN/I0m/phq+BsNVAyOIGq3uBrbewmgSO39e+J4WjErc9Mg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619235028; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Zqc4Bu846oH4Zng50ePts3zfvy2oRsPCEL4rE0JJWqM=; b=XXjnXCxgSAMO/E4lU6C6YaBzTUaR3zSuR3CE6LfdgtXDgaZacFBi8o1lxB+JkEdhzL78TbIYvP288sAcSRqoADXgEUyzxs9AtjJFmOYwoRt/qvPiQsbbwuXDvSAZ47DsQ4ep4kaehq7HLlWamjl1uEg/jqP/aUbmtXiyTEPFUbI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619235028342283.1416863764614; Fri, 23 Apr 2021 20:30:28 -0700 (PDT) Received: from localhost ([::1]:47948 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1la8zy-0005Dw-AY for importer@patchew.org; Fri, 23 Apr 2021 23:30:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52272) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la8z0-0004bY-4F; Fri, 23 Apr 2021 23:29:26 -0400 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:65372) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la8yv-0000Iv-Mn; Fri, 23 Apr 2021 23:29:25 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 24 Apr 2021 11:29:19 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 20:09:52 -0700 Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.34]) by uls-op-cesaip02.wdc.com with ESMTP; 23 Apr 2021 20:28:45 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1619234961; x=1650770961; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0JibYDDe0G2kjwlZigzacAGKcZc6HxILmbRL3QjmnOY=; b=LgIszeRGKpiUlyHW0RO1XZNppsuCiZtQLBOVUxh0vXwoy0uvnhF4ui0f 2E670MrNGeoqGJfpFV697yPQ0mJ1fazfXaLbUXDGcS0km4TE8VL4ur2xn 2HkNDZF1EuNlSEBCWwi7oTDYYTR/UI0KU2vwZ7NxHy4hpUGNZzz+bFqsm xnVSabUR1phGlotQAEA1RwlCjH2qzWd1gt0rNmv0D31fWuxi6Gg/SJjE8 E+axvozT/R1Yn37We22wnoCOu8NR/5Ezfm9ylAMqlnIi1eKXFow9sHbWr Rgm0xBUMWmvxcP6xKBpxxVYVyQAvYgMZN/czALkYpX9Xwutw1aN/K3b6y g==; IronPort-SDR: S+2zHoJQsJ4pt1A1hMrXnC7/w8de/gzdlLr2GYk+u/VIfoBvqk/31Rr8uzeZFTmuPMINWbQ37i v35AEmh6Zfq9if0kmC5YUXY/CovOtmVkfcWSx8ANUvRHgECdAIX3AluDBP5P+Q+QnshzE9rYFj T2HFainAcUyvk07V/fILfhFsPPwUk//bc0/XfmtUZdAIoBE3B2Pw439TTZDAxBUxutHUf79Qh5 XHIJltiTz0fxB+OVbjTPQMyKu1jyHEpqlcthUcyzw+hLzs1FOYFz7+kCrNSNUEsT8jujD3tpAt GLk= X-IronPort-AV: E=Sophos;i="5.82,247,1613404800"; d="scan'208";a="170655470" IronPort-SDR: tyxImuyYe837SX+QbuaS5JqFyxuXs7GXE3+oKvBm99iLj8N6YiuvbDUQpTMnxSYitlPJtlRQg5 2No698yzNwOsi3WZWDy69xRkW3Xc5gFY7zqib1/ul2Pf+AozUSUEzLarayBS3hkoiydyaLGHwK AfHLkDyCt2R6TWuyHshqF4dfDB1YlAQQcmKmOls/jt8pX22Dcm3i/wkv58Ysflul5exxg5muRZ qNqdrfB3Hi2N86HR/3COGMKWHEgnHOTyavIIwppzDfp+qeQVHy0wZ4kRltxbKuYDHUbynq/PWL DKo7hbxjtno12cletgDTdg9J IronPort-SDR: Mq3wK20DuYw9+nbGbzd9McGFDYx+q2AOKbfvR9DpBHHNvfCjMe9F5Sv2Zj5htQGRMeVZAZMz79 pGAglkLGjBR1qdHkLCFnxWyccXwvwHFiyqhAA0JksENQrlx4wbMfQo3p27rygm/vq0GhmMxY5d +v0iG4qEBVhIAL1Xa3ePQeW5Q/zcmfQpaQF3uJwLmqdimU1h3yrDWusaAmpm7CSm7gO0Pzxsjr wtrXnGTrJY2Ehm7uMr2EGtSpa6DLOhEE18bJdUlMNUKfwfg8+RZ0NA9/+O9ZpaE9DmTxXCMUPe 5As= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 01/10] target/riscv: Remove the hardcoded RVXLEN macro Date: Sat, 24 Apr 2021 13:28:33 +1000 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=7413b051c=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng --- target/riscv/cpu.h | 6 ------ target/riscv/cpu.c | 6 +++++- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index add734bbbd..7e879fb9ca 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -54,12 +54,6 @@ #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) =20 -#if defined(TARGET_RISCV32) -#define RVXLEN RV32 -#elif defined(TARGET_RISCV64) -#define RVXLEN RV64 -#endif - #define RV(x) ((target_ulong)1 << (x - 'A')) =20 #define RVI RV('I') diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 04ac03f8c9..3191fd0082 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -147,7 +147,11 @@ static void set_resetvec(CPURISCVState *env, target_ul= ong resetvec) static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#if defined(TARGET_RISCV32) + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#elif defined(TARGET_RISCV64) + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#endif set_priv_version(env, PRIV_VERSION_1_11_0); } =20 --=20 2.31.1 From nobody Sun May 19 05:22:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1619235148; cv=none; d=zohomail.com; s=zohoarc; b=FhLyCt1FtIcUc9cfRBk2sVc2NXjX3x8OQNHlijKYmQ8vaishFPu9kE5yEqlrNL+ZdFn1t6PQGw9cE2QrMIj+XjCNNHeSxzfH2+BxXyUEgmQ+OQA+62/kloP0g1CiXbhd+OmYzUiS4IWg6DOZq/f91L2ifsGXvGkPP8exe7h3arI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619235148; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gWJefcGxWFyv/HUF3MyeqFjqyc2erkpMW7RcJQatYqw=; b=i1dMqpbnoCY3jwIp6kCv2jgLZlYs3B3RdbN3plf1FFw2tNA0LPI+cG+6K/qFd8T2GG9I16lB99SK7aavLVQN6HYHsDgIJ6TtBP09qI5vfOnaaQSc/sJiF8YVNPaSGXFYNQ2+2fqfd7A+W/l0eM4m4SPjFpKax+Sh/Nkq88Lpyjw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619235148859283.8480445109084; Fri, 23 Apr 2021 20:32:28 -0700 (PDT) Received: from localhost ([::1]:50840 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1la91v-0006WD-LJ for importer@patchew.org; Fri, 23 Apr 2021 23:32:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52500) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la91H-00062M-L7; Fri, 23 Apr 2021 23:31:47 -0400 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:7218) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la91F-0002D8-En; Fri, 23 Apr 2021 23:31:47 -0400 Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 24 Apr 2021 11:31:42 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 20:10:45 -0700 Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.34]) by uls-op-cesaip02.wdc.com with ESMTP; 23 Apr 2021 20:30:07 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1619235105; x=1650771105; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=d2vyhak+ZI8u5OwIFhEy1tLDEU1teHlg0/kZ5Vj4J2E=; b=Cb3ZA7bUiV6I+qKLgG4+8CW831/kT55cRDZb+L2ACa8PgUNgxSUoiY6S d4EovJ7B6O2/PtoPmSR1mzTJygQcfwWvxlvXPGu47dm1r5po6bMbLKAow vaNursdTenhsBerKLwMDI+RI2CwmrLdfbRrs0vy2TcSmBOo7p6GyD2Tqb +HTIXo3MxmP/+1k24uclAbbf68V3+HxoI3vRcheaZ9Dy3tXYiB0RGbCea 8HDpSUAOyZM15c3HyXJTPwwJ+NN3hbKUko6rOL3HcHGqoCZrrlzLhQ8d6 ZRPpgf5jyw4tr53UcaUN7Rk92D4nOfdm+/3+cDRobzZ3swcbNimfaaQDP g==; IronPort-SDR: 6e/06d+STkY3x2nuI6c/QiH1qk/gHSw9rvckN4YpwLvCRZ1CaMXxAazIIXsxgV2/ViNgcv32E4 bFSqyrTw6W3LIxGDDyPeFDTXLeu4P6R+6rE2Hgu2qh+QfMAcrazI/ehM17J2sPQeWE0oCnx/qk hXTjCvRl7SFoEM202W4ywgn+l4jkKiIsd+OLcvxmrbivPeJxFtyi/wJS1AgAN+HgmYVMpcbzEm mrHOwnA7D8rK37cCS9TGqv/KwmX62TW+IiZb17MQTa2LGtFF2+oUSVqtmCUjhbsotUoeFmCI0J q7g= X-IronPort-AV: E=Sophos;i="5.82,247,1613404800"; d="scan'208";a="166115745" IronPort-SDR: sX+1QbYVO1ag2FRaHtcaUpyAJolR85zs7e5jLARnpZTdZkS2wh/mH6LLcT0hqVjWiaHno1F/uo dJbO3Co7IY2IOLbJkyD0vl9ymH3KXfTYLrT0vV73KaytES9c8sITxkIL8YH/p3rTa43FmK1sZB 8g6hvTDBiW6fVR33G6aEohSDzWt5dtSsH662QRx7ushUkRrxniEKuMM8qexZ1N1kcJqQgl8JLO re6NOAmu/vNImiMUJCHSkI1JTqJgIZ7Jk5a87d2XpC+qYbXacxt62g9wnuFkm49Y5JKjDA5dq7 k3KTH2nqaGU/t2pa9XUNmnJJ IronPort-SDR: NJlgn4fFiq4sF1BmmGw1IFl+g8yyx1D/+Q+CQB4s+r3C1GkTNm4b4Oe+VOUfRH1XhGAJf94cau L9N71+XvSo0AYDHGHQNozhB+2VR4/GOF/UyhuvMQLC0B/jkuBAPU80vh7pg4/Kt2TlTShvBqPQ DeoTrmukg4xTbOnds9hjK9mk7Ac4l1gWO6N7WMy5IRF5gFZBVOuynZfHvXKw+po022bEgGQJwL 8vjpJZFqSzIi9M+qCel4T1ov68rTJs8B1QcjInYlUCOCROGrnU9dGOlgyp2E7UdMzetNbeGyfk HYg= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 02/10] target/riscv: Remove the hardcoded SSTATUS_SD macro Date: Sat, 24 Apr 2021 13:29:50 +1000 Message-Id: <9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=7413b051c=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This also ensures that the SD bit is not writable. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 6 ------ target/riscv/csr.c | 9 ++++++++- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 24d89939a0..3a0e79e545 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -403,12 +403,6 @@ #define SSTATUS32_SD 0x80000000 #define SSTATUS64_SD 0x8000000000000000ULL =20 -#if defined(TARGET_RISCV32) -#define SSTATUS_SD SSTATUS32_SD -#elif defined(TARGET_RISCV64) -#define SSTATUS_SD SSTATUS64_SD -#endif - /* hstatus CSR bits */ #define HSTATUS_VSBE 0x00000020 #define HSTATUS_GVA 0x00000040 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 97ceff718f..41951a0a84 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -459,7 +459,7 @@ static const target_ulong delegable_excps =3D (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | - SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; + SSTATUS_SUM | SSTATUS_MXR; static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP; static const target_ulong hip_writable_mask =3D MIP_VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | M= IP_VSEIP; @@ -788,6 +788,13 @@ static RISCVException read_sstatus(CPURISCVState *env,= int csrno, target_ulong *val) { target_ulong mask =3D (sstatus_v1_10_mask); + + if (riscv_cpu_is_32bit(env)) { + mask |=3D SSTATUS32_SD; + } else { + mask |=3D SSTATUS64_SD; + } + *val =3D env->mstatus & mask; return RISCV_EXCP_NONE; } --=20 2.31.1 From nobody Sun May 19 05:22:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1619235291; cv=none; d=zohomail.com; s=zohoarc; b=TenekVA9ZmbAX2P+ib1cMgNjq89v2oQdTNfDUCCOyAXU0wB+S2gdPyhI2/8WRDxtcu/Kf9M2fLOL4uKHkNWzPeEZ8eXoqmTuWHTOHgJ+ETKgbCZCCGV9tm8YdsAE+ctNLC9EGlBt/Q439mly6XgOXauuqjrX41N1Io6VpygTH2c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619235291; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NeSU15/TBJizq/ka/w1pzehkrc9HsbvLov6D5RsZ2RA=; b=LYvUO8qkttbHm+NiK2TZsIH3sw0ijnEIoUgJ2ERW36gtR0YGYqqWFCDlnnN1hJpHdYhCpw54DsdkRuhBRkhyzu6x4YqkAwQ+RDBhcU6JSYMFPMMNgtmQXyqThJ4XSZGdUlLe0mJCRZxn6pvNWefH0tIotty7RU06KJiQaFcUySg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619235291794870.5831229000739; Fri, 23 Apr 2021 20:34:51 -0700 (PDT) Received: from localhost ([::1]:53808 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1la94E-0007je-Jo for importer@patchew.org; Fri, 23 Apr 2021 23:34:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la92o-000703-JD; Fri, 23 Apr 2021 23:33:22 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:13296) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la92j-0003OF-N9; Fri, 23 Apr 2021 23:33:21 -0400 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 24 Apr 2021 11:33:15 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 20:12:17 -0700 Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.34]) by uls-op-cesaip02.wdc.com with ESMTP; 23 Apr 2021 20:32:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1619235197; x=1650771197; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D6P6yUd5iDfYHgJdxhkkY5EVlfJB3ZVeD4QbkrzJvH0=; b=Rjqx9p5YvSyQrY1YahzKeKnSPwSarXcy8wlvtR6c46y2tqzUJHj7/2xa eZDJfrJLM1+yODSJOUZOIHyEJLBOnVexk0QlI2VgxIDpZ3PzvAogGAp6e 8vjlcqGldbs9v7BnmkMdDI33oqPmZ/iA3Mf+VdhrCxekVfbpOX+AYEVqH 4NqUOcsYtf5UgbIg0SpxDKudWO6KC9BZYBRBYOmGh0LrXMsnm/ucOgdOW besEBx9uGEtGtSAi5DBCIUGTZPyjOwiYHFQMOwo2DIrwk7c3Wc3pQC2ut a7/VPT3JbYs/hs4S7pkCxTPWbjK8gu1SweXoKU/BsFf5H4fZc40cmRbMc g==; IronPort-SDR: ps7y//ayHEMI37HEwza56OqudFrQ6G6UVyefo8O3r2JBRllL/lxf+bb/YBk+6ziQYxHDKYg+rG jR4mdyPbeLGbboBU7b6D2YppX8HgMmiFrxZGFyqyqXdGWV3vvF6hupTtkGZL5xBqvz3vErk4KR pUhgAqYEfk1xgka/BVRdZAf6m4QS+gqmxw0qrLc1WdzirGdMdhx+CQRwCdC9xptBZgBGjZ61vK fPHSQBunBc65NS1Zuw9CXrqy2A1aZW9jMlr84oKnfR7ehtPusRv/z77XQO5adHQripqlstOY0l jes= X-IronPort-AV: E=Sophos;i="5.82,247,1613404800"; d="scan'208";a="277100802" IronPort-SDR: C02DEEu3E77DuxMX8+8rxojepO77hE6Tf2T6LJjx4pIzNckSewrD0H/BUXqNOAkmbcxWSB3ISw iSqQJJkjMyNSG0SwwwZAeqMm0d82xnSXnGfK+kBksHGuN9d9MwnfTZYzg1IGm41+HE70Zs3NLB cCwSgp97x/BrXzsxQfiMjAO8loFHTfijgaoqg/iZaA38qAlnx5sfX92pC/+t2UXl8CzNrvGYcE SpZKTFQfppJFOytRSEqfPc6IJMQaIw/0m/FOi6FNOqooBTxfvpz/3RKbhSZYt9HjgaXTFEAYew UC2crOa78zNmTGk4Ro8iI1zq IronPort-SDR: B4kU5D9/kLRZe6uuHV7fcGEJ2PH2y/AtQ2MkX9F/0LDQUIbKJsVsNojM8014ioVIouNkFD7P3U VtAd85+iGMdr5ZXfq+RgmKYwZCU1gLb2zzYv2+7qaiomBRj5torWjwPSbWbg/Qpp+BnwgYjRXw x5JeqFIl7EnJcZuJ3CUnVpyMShkyKMastGDkGG048Zhcn8UNMa94i4CmI6JpVNWP/ktBS6+EeT KZQ+lzT+6xeIGrUvazBcSww+abyWh6x6lCutoGgsEIx73kF5v4hCaas0uToz2OoCqBToFYHvET I1s= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 03/10] target/riscv: Remove the hardcoded HGATP_MODE macro Date: Sat, 24 Apr 2021 13:31:55 +1000 Message-Id: <665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=7413b051c=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 11 ----------- target/riscv/cpu_helper.c | 24 +++++++++++++++--------- 2 files changed, 15 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 3a0e79e545..d738e2fdbd 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -195,17 +195,6 @@ #define CSR_HTIMEDELTA 0x605 #define CSR_HTIMEDELTAH 0x615 =20 -#if defined(TARGET_RISCV32) -#define HGATP_MODE SATP32_MODE -#define HGATP_VMID SATP32_ASID -#define HGATP_PPN SATP32_PPN -#endif -#if defined(TARGET_RISCV64) -#define HGATP_MODE SATP64_MODE -#define HGATP_VMID SATP64_ASID -#define HGATP_PPN SATP64_PPN -#endif - /* Virtual CSRs */ #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1018c0036d..d9defbdd34 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -413,8 +413,13 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, } widened =3D 0; } else { - base =3D (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT; - vm =3D get_field(env->hgatp, HGATP_MODE); + if (riscv_cpu_is_32bit(env)) { + base =3D (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; + vm =3D get_field(env->hgatp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; + vm =3D get_field(env->hgatp, SATP64_MODE); + } widened =3D 2; } /* status.SUM will be ignored if execute on background */ @@ -618,16 +623,17 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, bool first_stage, bool two_stage) { CPUState *cs =3D env_cpu(env); - int page_fault_exceptions; + int page_fault_exceptions, vm; + if (first_stage) { - page_fault_exceptions =3D - get_field(env->satp, SATP_MODE) !=3D VM_1_10_MBARE && - !pmp_violation; + vm =3D get_field(env->satp, SATP_MODE); + } else if (riscv_cpu_is_32bit(env)) { + vm =3D get_field(env->hgatp, SATP32_MODE); } else { - page_fault_exceptions =3D - get_field(env->hgatp, HGATP_MODE) !=3D VM_1_10_MBARE && - !pmp_violation; + vm =3D get_field(env->hgatp, SATP64_MODE); } + page_fault_exceptions =3D vm !=3D VM_1_10_MBARE && !pmp_violation; + switch (access_type) { case MMU_INST_FETCH: if (riscv_cpu_virt_enabled(env) && !first_stage) { --=20 2.31.1 From nobody Sun May 19 05:22:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1619235312; cv=none; d=zohomail.com; s=zohoarc; b=i9f77YUjZ1NFT2KcphPFnCEjIMzFhAkpjf0WsN4irS80xDpTGdMOnknw83rkEScuSAcNpRGhvIFqkaH+pqNYyM8v5YvBLHIm5nmWIiIYn48Xff+udvE0HyxleM16qU+wX0DLXzEy0kFWHKBU5y8VVWky+kfSb9NAijNBBzNy/mk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619235312; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sAOS4Lrr+9f3snEXo3rCNmxvo20xutm4swgQIBfFzQY=; b=ctJQ5UEd1z9Bdua85NYAoAUWGk03bfl0en/KnS07DTAhrbric8jTsS0KLb4BwhwxQBBEpSdxdVIxMNUK7Jr/8nVgq9mIZ0MHiDrCa3MwLtHIbmwy4Cw6hxVMV83tHUKf03EXIMQ7iRa9QRDgvBod3bVjL9BsPKd1KWe0hcxIbsE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619235312179973.4309854280689; Fri, 23 Apr 2021 20:35:12 -0700 (PDT) Received: from localhost ([::1]:55640 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1la94Z-0008WN-31 for importer@patchew.org; Fri, 23 Apr 2021 23:35:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52868) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la931-0007Eg-Nw; Fri, 23 Apr 2021 23:33:35 -0400 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:30729) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la92z-0003ZF-Ul; Fri, 23 Apr 2021 23:33:35 -0400 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 24 Apr 2021 11:33:27 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 20:12:29 -0700 Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.34]) by uls-op-cesaip02.wdc.com with ESMTP; 23 Apr 2021 20:33:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1619235213; x=1650771213; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5qpLFkZI8ARu9VDdsKVtYaczs0XvC0KW+StVQqe5e3M=; b=UwUBdg+EuBeuKDku5VU8Po+KFL3etzrGBMTgIbQLx2qQRjjWD+99Rbca z3MP9N9iehYFKFigvuMZBICU8EXCeI5+qolVN0SzCt9v+4hhmepzDtLVh lq77Rao6xxtLo0So/sQ48TgJXQ5OBh/qIBOSB6/pOK9I4QWfZnQB5/6LB ImspeeGJCo2XFMsrmaSf9Y5HYFR0NI0n2LWWsE7W2Xyzzen8aLffoz3Wv XxOGJI7xi33Y7P5Sr0zhhNLW3pWndl8eOu8hEQKTnviYtAqTztmgKnPcf F9J3rdmH1TkiQU74WwjuPFrMTWvKka8ysoGSMzJJ710sIVtxVrtbpVBHn A==; IronPort-SDR: +Zvy6vmNbKwER8i6R1xpv3CIYTeYw3c+I9A2kqzNJLW/oa9+ZXSz+o8897pbaG0oZlythCeFkK LTCpUFKlllmhoo5wPSxzM/7N0HiPiqteZyymWQssNNZGsBfxhYgCYsxHrf/if7V2nq+fS+x6Cs A8TRcg6LtG1eSZ5SGWfu0+VMhzPOOTROHz6IwT2pLue7ECtP/rc7wlSMXudgNEVbFi8rM1kH++ CwZVIVWY3xpuxieXcz9tiHaJgg9WZ6G6T2qSIVeJjoUYzKJgno8uMQTxSgiTRdg5XwfzEgn8v3 YYg= X-IronPort-AV: E=Sophos;i="5.82,247,1613404800"; d="scan'208";a="165465285" IronPort-SDR: 7iHm7ipA7myjr8q7rIP++yo3fiqJqvKz5lpgiGZeD01VXOjXhqDESDeOw7/ASjYCvdhmQ4mahD Cho6Fzq8+nHHyqd++FL4QRr91JDgh3WXdEVL7o+DZIkdxWtYZXGPE+mDcO7AChgtStbtlNmQ+s n+yFXJ/xM3z4XeyrS+9RE3dEl6qRcRB8wyyV11IR2VIqnqBhN2mvebt4Xoib5+p3+Qxz1W9s1S noVPkcUmNDRtv1LWIDuIvaWPLiCJfMYZNFA/Ji+CucfMlNRlMTY7yzQILlk2MDIrDfmXocKTBP bKOQFdKxSPa9ezaR2K9RZ5Wu IronPort-SDR: Hn15hJXKu79Kmg+ncUOHTjMRYY2d1mbsSnzxNwTwaD3STEzRW9HGI9iM8sCalWt4Mjfzooz3yF RZApS13ZVbqqX1g5aiOzmXkMseX7LQTUiR0bsXVntOkJ12UOL5e8SSuK06nw5mJ1n+7DWOCgAm d0CL+2e9rcJPUp2ypdIzwU05xgrHAFNqb6zLj/qk7zi5pb1TMoyttkhfr+O3238/yobXVIypRP iVjrokswe3MiwpLMhPzl0Qm+R6y9PisxqVPYt49is74uBuhJmzEQF63fV0/UU6qNmCwREPUGAm 9B4= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 04/10] target/riscv: Remove the hardcoded MSTATUS_SD macro Date: Sat, 24 Apr 2021 13:33:18 +1000 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=7413b051c=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 10 ---------- target/riscv/csr.c | 12 ++++++++++-- target/riscv/translate.c | 19 +++++++++++++++++-- 3 files changed, 27 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index d738e2fdbd..6e30b312f0 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -368,16 +368,6 @@ #define MXL_RV64 2 #define MXL_RV128 3 =20 -#if defined(TARGET_RISCV32) -#define MSTATUS_SD MSTATUS32_SD -#define MISA_MXL MISA32_MXL -#define MXL_VAL MXL_RV32 -#elif defined(TARGET_RISCV64) -#define MSTATUS_SD MSTATUS64_SD -#define MISA_MXL MISA64_MXL -#define MXL_VAL MXL_RV64 -#endif - /* sstatus CSR bits */ #define SSTATUS_UIE 0x00000001 #define SSTATUS_SIE 0x00000002 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 41951a0a84..e955753441 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -538,7 +538,11 @@ static RISCVException write_mstatus(CPURISCVState *env= , int csrno, =20 dirty =3D ((mstatus & MSTATUS_FS) =3D=3D MSTATUS_FS) | ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); - mstatus =3D set_field(mstatus, MSTATUS_SD, dirty); + if (riscv_cpu_is_32bit(env)) { + mstatus =3D set_field(mstatus, MSTATUS32_SD, dirty); + } else { + mstatus =3D set_field(mstatus, MSTATUS64_SD, dirty); + } env->mstatus =3D mstatus; =20 return RISCV_EXCP_NONE; @@ -614,7 +618,11 @@ static RISCVException write_misa(CPURISCVState *env, i= nt csrno, } =20 /* misa.MXL writes are not supported by QEMU */ - val =3D (env->misa & MISA_MXL) | (val & ~MISA_MXL); + if (riscv_cpu_is_32bit(env)) { + val =3D (env->misa & MISA32_MXL) | (val & ~MISA32_MXL); + } else { + val =3D (env->misa & MISA64_MXL) | (val & ~MISA64_MXL); + } =20 /* flush translation cache */ if (val !=3D env->misa) { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 26eccc5eb1..a596f80f20 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -78,6 +78,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t e= xt) return ctx->misa & ext; } =20 +#ifdef TARGET_RISCV32 +# define is_32bit(ctx) true +#elif defined(CONFIG_USER_ONLY) +# define is_32bit(ctx) false +#else +static inline bool is_32bit(DisasContext *ctx) +{ + return (ctx->misa & RV32) =3D=3D RV32; +} +#endif + /* * RISC-V requires NaN-boxing of narrower width floating point values. * This applies when a 32-bit value is assigned to a 64-bit FP register. @@ -369,6 +380,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_u= long imm) static void mark_fs_dirty(DisasContext *ctx) { TCGv tmp; + target_ulong sd; + if (ctx->mstatus_fs =3D=3D MSTATUS_FS) { return; } @@ -376,13 +389,15 @@ static void mark_fs_dirty(DisasContext *ctx) ctx->mstatus_fs =3D MSTATUS_FS; =20 tmp =3D tcg_temp_new(); + sd =3D is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD; + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); =20 if (ctx->virt_enabled) { tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); } tcg_temp_free(tmp); --=20 2.31.1 From nobody Sun May 19 05:22:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1619235334; cv=none; d=zohomail.com; s=zohoarc; b=QtFVDX5XcF/D5jxVnQ4f+fu2BX0eSM3QcdhbDn4nwKj2cQcax6hr2uD6j0WOD2BODVqxr5ezWFwObeEYy6KYzQlL4TCfdIAWZus809sl95ygBmBkg8HgdO+D8m6H+Q/r1DFdSF5D7AIacS+6V4EHbXUrUu3M7lGBczqL0G41sb4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619235334; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=viyUTBj8iRleBZrIeCTacKr/Oaw1cHJm975axNOjBR8=; b=kooHQohV27bLb9VYHwvnBaD6hUYBR2dd00FvPh8MacDY47EAsjIW74VCxFMjVLPrhk6yVhzPjPJo7Me+y9R+fRn9OJ+3YI5TA2Ey9XO6PMfSZ0NKzER74QqNFN8+wC8v+jwXz/Hlf6mRnO274YIM+ryr0Gsiu2sDpptl/d2aEvs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619235334044480.8630940417419; Fri, 23 Apr 2021 20:35:34 -0700 (PDT) Received: from localhost ([::1]:57390 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1la94v-0000on-2D for importer@patchew.org; Fri, 23 Apr 2021 23:35:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52908) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la93F-0007bC-Bh; Fri, 23 Apr 2021 23:33:49 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:34829) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la93D-0003jo-ER; Fri, 23 Apr 2021 23:33:49 -0400 Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 24 Apr 2021 11:33:47 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 20:12:47 -0700 Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.34]) by uls-op-cesaip01.wdc.com with ESMTP; 23 Apr 2021 20:33:41 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1619235229; x=1650771229; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ygg6H2+uFVvvKu0RbWmEUqUImpa0lHaDJjsFKROC69M=; b=DKtfZESEQYjXbUWrQbMvMlxSt7xFrK5SyAfL/asEwuCf3/HaVgTMcFpl OzpDIS4fbdWvlycBI4EdIAtGvWiWl0YzOkn5Tw2bPJPinsWUMawfWstQQ vJjQpUrDC0QFHWrhktDad6spQMFDQ1flJArtq06i8zb0+SIQuDPvvpnU3 j3BcQQXoRtsAPxn1DWkjyLE8gxMELCzWedDJrFzrY8qw+D7rYyHcHYgim ZxCixqqKGKSr6mBlbkC7mY65L8s3D0S8c0aybGaa4IgVYLFpJj43DP0++ Tg8IbjyaAgZC7xxlKSrGUgz7+dbT6qsC6zi2xSH6hZK8Tm2r/4oqxRsOU w==; IronPort-SDR: I1G8/it1wA2RHdJioHKhZFHSYX3h5u5kTsbdzDtldCPqDlupuNo2HyJS/GPvKriNlp89Rh0lUy UguUVFGwCENgbUFXThNAw5X6ObAUfqRKzuMx12bS6jya5Z6035fs1pr6jgOc/2dPbgTYbe2awM VyOdLAUYeoOdKWRjN/G66s0W4vTOFeHGbcJFX8Zr5DYEnU88E3QAC6MkYPoFTa5r0vD33MbfXv 51NWnLWyDJDJTQrkr0nYhgrkxZeo9w/HCKq0iDDRxQSNFpyNmuXMSxm4RFvv3WRkU16Arl2/9V rQg= X-IronPort-AV: E=Sophos;i="5.82,247,1613404800"; d="scan'208";a="270020526" IronPort-SDR: hedmdaGOucElb0kde708lBALBuwZrL+FjEONYpJqvXJbR4WJbwOH8DwmF6sqb0Q635x1+0dePX b9T5kwcgQaDUrOhKuCio7RhIhQ6nBNXu5u6K2JwjrXv/lID6XU/RbCoQR2phWSGY66RMm162Xz BoAWucw91v327SufvTsgb8QEth5vCzXxNzc+W2OYKP4GCmIifxefRGTLxJSsPyagTRtHX02FVo uolvYstvygX3ZfhcFIIGqcRiJsE9b1s53fXtEgSiKYKQfjIC55LP2Rk3aBsH4PYhcjgfMb8lt2 +FY9lLTC+kU0FcXXwODXEEVt IronPort-SDR: 0fVAORnQlp9vvwVzWrHYvcR55vh8ykVTALy12C3iMJ3/1PYo1Cs0P2vErwPXGVo9jQeqkVfWfu sxDn7+0j3vPosSNaL3xLOdXMhbe+haeGtaj2GpbkredoaFhDvRC/UFrpEkQ/5Siu/zC7YnQOcS SoMhXiwF1hUKq3kfQVpJ+PSATEevY5EQOsMpIb+Fi54hWeFrmb9w7UnMCrn0dRws3vltDSNz73 /cQP8Io79milfituixXPPwj8Hv7SwoS9rBUiCjRQN3m9BvN5LJxd9th4N7VYRW5Slisdp5ljDO bcI= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 05/10] target/riscv: Remove the hardcoded SATP_MODE macro Date: Sat, 24 Apr 2021 13:33:31 +1000 Message-Id: <6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=7413b051c=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 11 ----------- target/riscv/cpu_helper.c | 32 ++++++++++++++++++++++++-------- target/riscv/csr.c | 19 +++++++++++++++---- target/riscv/monitor.c | 22 +++++++++++++++++----- 4 files changed, 56 insertions(+), 28 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6e30b312f0..d98f3bc8bc 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -432,17 +432,6 @@ #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL =20 -#if defined(TARGET_RISCV32) -#define SATP_MODE SATP32_MODE -#define SATP_ASID SATP32_ASID -#define SATP_PPN SATP32_PPN -#endif -#if defined(TARGET_RISCV64) -#define SATP_MODE SATP64_MODE -#define SATP_ASID SATP64_ASID -#define SATP_PPN SATP64_PPN -#endif - /* VM modes (mstatus.vm) privileged ISA 1.9.1 */ #define VM_1_09_MBARE 0 #define VM_1_09_MBB 1 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d9defbdd34..968cb8046f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -405,11 +405,21 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, =20 if (first_stage =3D=3D true) { if (use_background) { - base =3D (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT; - vm =3D get_field(env->vsatp, SATP_MODE); + if (riscv_cpu_is_32bit(env)) { + base =3D (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSH= IFT; + vm =3D get_field(env->vsatp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSH= IFT; + vm =3D get_field(env->vsatp, SATP64_MODE); + } } else { - base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; - vm =3D get_field(env->satp, SATP_MODE); + if (riscv_cpu_is_32bit(env)) { + base =3D (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHI= FT; + vm =3D get_field(env->satp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHI= FT; + vm =3D get_field(env->satp, SATP64_MODE); + } } widened =3D 0; } else { @@ -624,14 +634,20 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, { CPUState *cs =3D env_cpu(env); int page_fault_exceptions, vm; + uint64_t stap_mode; + + if (riscv_cpu_is_32bit(env)) { + stap_mode =3D SATP32_MODE; + } else { + stap_mode =3D SATP64_MODE; + } =20 if (first_stage) { - vm =3D get_field(env->satp, SATP_MODE); - } else if (riscv_cpu_is_32bit(env)) { - vm =3D get_field(env->hgatp, SATP32_MODE); + vm =3D get_field(env->satp, stap_mode); } else { - vm =3D get_field(env->hgatp, SATP64_MODE); + vm =3D get_field(env->hgatp, stap_mode); } + page_fault_exceptions =3D vm !=3D VM_1_10_MBARE && !pmp_violation; =20 switch (access_type) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e955753441..fe5628fea6 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -997,16 +997,27 @@ static RISCVException read_satp(CPURISCVState *env, i= nt csrno, static RISCVException write_satp(CPURISCVState *env, int csrno, target_ulong val) { + int vm, mask, asid; + if (!riscv_feature(env, RISCV_FEATURE_MMU)) { return RISCV_EXCP_NONE; } - if (validate_vm(env, get_field(val, SATP_MODE)) && - ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) - { + + if (riscv_cpu_is_32bit(env)) { + vm =3D validate_vm(env, get_field(val, SATP32_MODE)); + mask =3D (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_P= PN); + asid =3D (val ^ env->satp) & SATP32_ASID; + } else { + vm =3D validate_vm(env, get_field(val, SATP64_MODE)); + mask =3D (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_P= PN); + asid =3D (val ^ env->satp) & SATP64_ASID; + } + + if (vm && mask) { if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { return RISCV_EXCP_ILLEGAL_INST; } else { - if ((val ^ env->satp) & SATP_ASID) { + if (asid) { tlb_flush(env_cpu(env)); } env->satp =3D val; diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index e51188f919..f7e6ea72b3 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -150,9 +150,14 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *= env) target_ulong last_size; int last_attr; =20 - base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; + if (riscv_cpu_is_32bit(env)) { + base =3D (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; + vm =3D get_field(env->satp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; + vm =3D get_field(env->satp, SATP64_MODE); + } =20 - vm =3D get_field(env->satp, SATP_MODE); switch (vm) { case VM_1_10_SV32: levels =3D 2; @@ -215,9 +220,16 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) return; } =20 - if (!(env->satp & SATP_MODE)) { - monitor_printf(mon, "No translation or protection\n"); - return; + if (riscv_cpu_is_32bit(env)) { + if (!(env->satp & SATP32_MODE)) { + monitor_printf(mon, "No translation or protection\n"); + return; + } + } else { + if (!(env->satp & SATP64_MODE)) { + monitor_printf(mon, "No translation or protection\n"); + return; + } } =20 mem_info_svxx(mon, env); --=20 2.31.1 From nobody Sun May 19 05:22:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1619235342; cv=none; d=zohomail.com; s=zohoarc; b=R2QWUKsJgkDykHzugk6/83u/tcC4PLGwqAQ5DTd88+3GafRB1ytglqAzJdtcdTVcli7f3OZnvJVsaqvbZfiAsObOQBqK236G+zEDU499i2BIBL0vXqTDJBsTBv/NCCgMGGIPp+d8gx1fWB7FWIJzaTOsI7/HinpYv4rfAlQJb20= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619235342; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kPZf5jbWDf5QHua11mKAEU4y7XEm/ueQvy6uxe/kRE0=; b=E0bKiWblMLVUy3gYCgvSOfJYYWa7x8/+03FJv0vtzB8vRTMxtVIQWKdZHSsDNIV+hEkmObfhrwnP6o4ndg+nY+iAQRle1Sh4eE4gU9ZiC98Wz222Bjqe5gvDo05LNi3Ek3jh76fbvuT/nFzwl5mAn3U7cqniCQnPI78sDMTcVK4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619235342493536.0470786290796; Fri, 23 Apr 2021 20:35:42 -0700 (PDT) Received: from localhost ([::1]:58156 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1la953-00017I-FH for importer@patchew.org; Fri, 23 Apr 2021 23:35:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52994) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la93S-0007rI-4X; Fri, 23 Apr 2021 23:34:02 -0400 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:4877) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la93P-0003tc-Mf; Fri, 23 Apr 2021 23:34:01 -0400 Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 24 Apr 2021 11:33:57 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 20:12:59 -0700 Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.34]) by uls-op-cesaip02.wdc.com with ESMTP; 23 Apr 2021 20:33:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1619235239; x=1650771239; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yp6F0Q+Swib2+GJbDoLfYqYlTDrfVWqPKtiCYQ7+Cww=; b=LnQfjKGQ0I7Qjx6itPvM3sZODvOZl8aKB1u2maCOu2HX2cStdl9kdlT5 CXmWyBXCIdkCLw6tpoIRNWs+Chn7dNuTw13qgucixGPDKn+t5cBNEAtpm elr3ycA0T1NEpvbMnB6Ck7eiJSKoELclCGYTVHOSxL9+TjdmAXmEm54PN 7dUEpdjxoPKbT0Kzs1wnrX1xeQR3J+Qjdg+VVQqH8awZw3hD8Z/i3yPY3 Dq/tR0hBggietXSXyp5sRye1JrImjzq9I/KYP7gWFtcxYvRV8FcJ1S13S YemgSEvP8MsMmz+a/A6ywfYlGlBBR58OlrUphIno304y4uAQz0XcmjMlG Q==; IronPort-SDR: 5nPqheNVlKC24PQ47pAXSwz2krMYys0hrc7aZoFxuHk3+ZonLROzdhFea95leyKarlZPQV9fxg 2mDAdGYUZJUuQMLNZzaK6Rdr9iRvzQjDfd0WV6kC++AP9j9EDb7XskFX2cBEbwYe3XfejxyHBT F6GBvyvBF9jVY8rB2k0uow7TAr3szmAliEM8sFF/pW40+XAow1zUKvw9Nc6cvjOm3OJaUP4eR4 ZH0wzsk54ubVMMr+KvIthK3Pe6p7UfiZu6zozLpUp/rpakO480xwgtRaBhRRrZC90VX4b2vpun G+Y= X-IronPort-AV: E=Sophos;i="5.82,247,1613404800"; d="scan'208";a="170655709" IronPort-SDR: CiSB7jx8U/XRKf70YZQ95mPvlSlz51r1zgG5HL4AJNki+4EmxqpN0OTah827e0cz8vEDMRN7Gr nGxrjECx/NvSspEiKlaDhGLAAywDz3OUWBkdcv7hPoD66XeV/4smCcCxEm0Zq2obqVufUFqXdt BHy5PGIaBwBxtFZyIh1kqtf919X4Ay5UbU0RNbA5/YRmBGMpRIb/+Y9ocHuAmpkBsFNPR0F1eE smquiOm1gZuDCJ0gWafMC7cNOJr1QURfRMg1LXM5g0zDPbZnlOTrYvM8HdEupsl+nxClTcQCjY 15Jx3UT4udSzROh5aKZxYo7Y IronPort-SDR: pbKqK1lvm2f91sgfUHrFmwApT/ynhnHmZ7JaDkZlOTZnSONE6kSXg3yLv/+Hh4L+V1/85XpfEJ IP+pOo5f1kdWKl+0+q6mHXPizg+YYKU3+tSP4JUeQ/jmYGUfOSQdJ+mmAovi/ShjgqvojPS/L1 ejPFLXkkOvfptMFL/4U58E1SsvOD1LySX+O7qY+8NHB2etOb2SBcVw/cU51NMvwZXFdNF6LMjo luVFpDte0mhuGU/5dO2jcC4lufjAxRQRw7l8AtLw+YoHrIfIfBub3F88AoBLm2ll6Gy9g4M0ks 2GA= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 06/10] target/riscv: Remove the unused HSTATUS_WPRI macro Date: Sat, 24 Apr 2021 13:33:48 +1000 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=7413b051c=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index d98f3bc8bc..52640e6856 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -396,12 +396,6 @@ #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL =20 -#if defined(TARGET_RISCV32) -#define HSTATUS_WPRI HSTATUS32_WPRI -#elif defined(TARGET_RISCV64) -#define HSTATUS_WPRI HSTATUS64_WPRI -#endif - #define HCOUNTEREN_CY (1 << 0) #define HCOUNTEREN_TM (1 << 1) #define HCOUNTEREN_IR (1 << 2) --=20 2.31.1 From nobody Sun May 19 05:22:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1619235484; cv=none; d=zohomail.com; s=zohoarc; b=Tu1Bip36xcKFJh6hU5U1CCR7gTQCkezfIXJ7nFxhiCjIkebqyhqW7MgSTKEQ2buy0P0EdhQ6ZEsB8yEl1YioyJ9kono61QbU+p6rUgXuxVf4zfe5lCgOS7zLRtsVy+sMQah+ND9MjmrCGaJFWkMO1Ihha4d3xsOytwRoIxt0o/E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619235484; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RHA83ElrMbO1X+NWcIOEUZehfB+QXJc8icg4rkg9IQ8=; b=dlj3oxrckwd6preOEYFnMjf7M6ZY4/seWGtkJ9L54NCdM/W7HB3tGs/KKeAGehBM7A6W/esOntz+faJHF+8sgmBKCI7MBC56I6/q9aSwMbuQ1cMKoSs0NpIE7cPNGJpa91sES9K36VP7Rb0PSYKpcU3QJLmwxqZV+Xr/mat1Jk0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619235484747576.4749391217844; Fri, 23 Apr 2021 20:38:04 -0700 (PDT) Received: from localhost ([::1]:36446 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1la97L-0003qG-Lw for importer@patchew.org; Fri, 23 Apr 2021 23:38:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53102) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la93e-00082p-Sz; Fri, 23 Apr 2021 23:34:14 -0400 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:7403) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la93b-00043T-Hm; Fri, 23 Apr 2021 23:34:14 -0400 Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 24 Apr 2021 11:34:09 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 20:13:11 -0700 Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.34]) by uls-op-cesaip01.wdc.com with ESMTP; 23 Apr 2021 20:34:07 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1619235251; x=1650771251; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RQcILOF1kLcOwUcABbfqKxgfDlarpcavDVVrkqxubPw=; b=Yvq+TMHt+VmJne0n5HGIeHjLCI0vmgHmcvmzwCmv7GK9Y6t+EL1XvzwF pirz8+cKEFbLopUWhl2rqaXyrs/udcUCnYoc7JwnNIfnTeV6+f1dXYCsy YGPRH4Rs+4CQn0Xad9rH2HGYCdMhmDr97h/oPTSSTtIvQRN9wB707zFbs gBxTn6x6KlX8O3t2PT7Wrt0XA8h+xXui1PbqXZITO8bc0tpBLyy76iCFw S8E/aM5HqJqZ/G87G1LxEs7oHh95dMJtYk7nhSTpjUZkYcGaavIGWOPrt 90Blqba9csXmGPcWfF13klp6XyjBt5hsJ2br9GEBBHVcTvbajmsfvFxzu g==; IronPort-SDR: yMTfLXwGy2qLtThoViO4kmyZyD+sY4c0IZZVns77az82ubUms+hE+ZUCa2eVu4JQw+XiaH67RC OOy1tnWyszQbyKuTUAPK6jqhpLru3OymKnZ7OCm1a9jf7XE5QBh0Psbi84UoUFan4EjSK+3Bgz 7b7NSIGtdx2ShCzZBxh1wEh3+QgH+WUZUxLW3EiPicVT2rJkZ9/VUsmlDRJtVmLoq5chir5UDA YRS71q/DTn4UEpxsIqqeWZ3LOuMzB4ChbhVh5rKBnRNXvVPg8p4FrNdkMC7sTfKFGm+SoB5eSm 86U= X-IronPort-AV: E=Sophos;i="5.82,247,1613404800"; d="scan'208";a="166115875" IronPort-SDR: ceJgXuJEKT5hAEmwtkP7zrlTNPrONgZY74SZbfigdHH3x7QcKrZ9rkb4p2pUFZ2FZrmwO/XxHx 4elsHCZZ80g7MTjZXwUF/3O6lqpNPG0RrYxv1bbopIqiA8hBICxrO8AAYH1zQoWCR+Ca61cF2y XnNI3b7S84hGP2L+susdBhtcxkgoz12YnqVjkI75ORVgy1uI+C/WVDEBVPO+3itCUBTRoHRcIG WJfVG9+SL+t14ha2kb5FjrMzn6RfTA1rSz7CBGZNH2sJI1trVqzOeRyCbs8An67gtMw6KaGXRd l3NhSjfRTw6zuyIfA5s2/chs IronPort-SDR: 7eBFnDyrzQahbXy99DLTDO2FmPZaAtoEbzntW+w5rrSDz/Sb8CYxPUJhIPHKwITa0isJe0NJGc fOykx9+r1vUNbSoLXRYlA6IaF5QPbx3pln+0BXgexnksORuXI5uR61dYaSxAc08KskvUHI++GO Uta1gIQX9yKs2CRNV7s4aNpyJ8ls1K9KUPcY3FmmEkMlt0K3i5IgSXP1aY+gXbKsQ4DSaNYfbS VPcicqHtUQEpXrGkc+L2LB5W/fAUkJkdf+QYBpqnDuzgQ2jWZgoTZFQGB9BlD+S9YBkSlN+vF4 8wg= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 07/10] target/riscv: Remove an unused CASE_OP_32_64 macro Date: Sat, 24 Apr 2021 13:34:00 +1000 Message-Id: <4853459564af35a6690120c74ad892f60cec35ff.1619234854.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=7413b051c=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng --- target/riscv/translate.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a596f80f20..a1f794ffda 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -67,12 +67,6 @@ typedef struct DisasContext { CPUState *cs; } DisasContext; =20 -#ifdef TARGET_RISCV64 -#define CASE_OP_32_64(X) case X: case glue(X, W) -#else -#define CASE_OP_32_64(X) case X -#endif - static inline bool has_ext(DisasContext *ctx, uint32_t ext) { return ctx->misa & ext; --=20 2.31.1 From nobody Sun May 19 05:22:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1619235450; cv=none; d=zohomail.com; s=zohoarc; b=NxUzQT8xJMiuc/TX2BCpON3+7LuOqIT3/B6IB/RFRaWKtQ8RrOLfWMtmrZBx2p/Cyxy6XKExtRCny6S1GdA1cARyQRaIsAWqLm2NCWoTahKaNMxVbhMEfipafGAMkempIki3raZw+u5gm8PxSCAx1Icbi58J7n7fapCoeEYEeOw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619235450; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BJiltYSKSYfRkPj291xX0LgV240YtLnCz19wjTe8IEI=; b=SVrIE2iZXj5So/k1EYQI9aMD7+n6PebTH96WCK7P/qKfmf9uc5Dl8heGUxw6x7sKvqrJtVR6K1Sxzos2gXMRCMk0QSOthYiaUckmVxm0q8eAtL72OpIKxraPPxOsQwFEOZEK+iFmXnO6n8ntvTu1wGOlsctUVHfgMrlOzUtdH/w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619235450981413.3027912667675; Fri, 23 Apr 2021 20:37:30 -0700 (PDT) Received: from localhost ([::1]:34288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1la96n-0002x9-DF for importer@patchew.org; Fri, 23 Apr 2021 23:37:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la93w-0008JO-0f; Fri, 23 Apr 2021 23:34:33 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:53336) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la93q-0004BP-88; Fri, 23 Apr 2021 23:34:31 -0400 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 24 Apr 2021 11:34:22 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 20:13:24 -0700 Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.34]) by uls-op-cesaip02.wdc.com with ESMTP; 23 Apr 2021 20:34:19 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1619235266; x=1650771266; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MqpIQlJ0i0/m9BcItdGzu0HlsENrUUSOxhFdL6n/qMI=; b=gJzqmj7rRN2B8c9x87clZE17AvKYcw67MUSdUv8J+8CROu/HzuMXpYpb 17V0VTexEwf+lenViKpfZLZlwjvhlq4tnbW5fNI99hzlS8NdZJEnLYj6F seBa0b1lc4DVAnCXPlPnY8pv/R4btl0xrglzq+NCCjH89hLcyyt8wV/HW 3UdmRVK6f/eBEPLztXn2qGjLTsdZRE20u8DKTXwSdLUjO4XxAf8lWgyMT IHm8Utp3moKyqxjhUHMMqzb+wov5u5IWcPg5OVJunYRGAqvsYJlk6DAsv OEUpu/7YpdAGgTYgHMbDzniDMwKtGsMsPvDH1C1fRo8N7Whh3ZZGNRGSA A==; IronPort-SDR: gAXKVq4a/85E2h/zggjlLZj+o9ynD/aq77ZNIZdmIeNh0CzFsr1/NtC/07pwE7cQkdZ2K2+bio xOAwyu8Bg0kqXZCIMsw9Lkn2GikzRNChA88Ik44zDKY2qrG587b3Qjy2ylGCk51isPPsjZh8u7 yiaXrd+ORiq4yycVqtUiWnAbw9fw0osw1/IKzeW9Fd2V4NAwB5kIvPioO8qr6WXXGmAWK3cImT T26NLDn/z4A7AKww3IbvQ2xrIZkcNjXjO1y4D22/SbvhryveDuJ4QeDilqJ4vPm5j0AGTVtx3p oPI= X-IronPort-AV: E=Sophos;i="5.82,247,1613404800"; d="scan'208";a="277100852" IronPort-SDR: P7ml4IgWXISYJi3Efxi47nlr4gLUXBdVuh4h1bfF9YLgaUM4h489wqDESGwB2+BhM2f3arBO0C 9mFx5NdxQBD5A4gaeKf2ZsGRUxVcvGphJ3/PcoP6Q8UmlWmGpI1pnu77CgMWbjNpcPLTkmQzcM /0wyExoy034bmEiaZJ8i/nrakn3Iag5mLBTpQkYn3xz0rG4Ra2sVG5y4NIMdDW3tpCW1ieJVZp krEYXM2/0UQwYTueAruecZSC9XCKwo/5JrYebETcqsaKpQyGf7+oERd5tfM+3IBFp8az2l4mBa Ev/NwzyanaAX9uWHPtracn47 IronPort-SDR: +cas80iTj7bUQ6W+9K02H3T+OigscBU+u/xtbVzIPiVBgUDuq+XAJflmkCrIrmk/BfTHjE3y0G BdFTpck9t5voXLhP6/KdydBgdscjRlB31djKesYUcB/Bl4OP+3ZdrTQDA/fpAXUt0U19V7+ktj IXcunR3+11mWmD1AaG6C6zExL/C4OvChD5XtTpRuyGD0KSd5zAXnvfme7KyKDTTxhF7fE8goew wHuvxdlWvhiO84ogzPJuAKKImAuxVAnMCuEYhB4pAlBe2pFV0Nj+OPd9I2Gb4N9KNd7kDL6ajb 0VU= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions Date: Sat, 24 Apr 2021 13:34:12 +1000 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=7413b051c=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 18 +++-- target/riscv/insn32-64.decode | 88 ------------------------- target/riscv/insn32.decode | 67 ++++++++++++++++++- target/riscv/fpu_helper.c | 16 ++--- target/riscv/translate.c | 11 ++-- target/riscv/vector_helper.c | 4 -- target/riscv/insn_trans/trans_rva.c.inc | 14 +++- target/riscv/insn_trans/trans_rvd.c.inc | 17 ++++- target/riscv/insn_trans/trans_rvf.c.inc | 6 +- target/riscv/insn_trans/trans_rvh.c.inc | 8 ++- target/riscv/insn_trans/trans_rvi.c.inc | 16 +++-- target/riscv/insn_trans/trans_rvm.c.inc | 12 +++- target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++------ target/riscv/meson.build | 2 +- 14 files changed, 166 insertions(+), 152 deletions(-) delete mode 100644 target/riscv/insn32-64.decode diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e3f3f41e89..c7267593c3 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -27,12 +27,12 @@ DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64= , i64) DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64) DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64) DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64) -DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64) DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl) DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl) -DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl) DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64) =20 /* Floating Point - Double Precision */ @@ -50,12 +50,12 @@ DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64= , i64) DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64) DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64) DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64) -DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64) DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl) DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl) -DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl) DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64) =20 /* Special functions */ @@ -241,7 +241,6 @@ DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32) -#ifdef TARGET_RISCV64 DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoaddw_v_d, void, ptr, ptr, tl, ptr, env, i32) @@ -260,7 +259,6 @@ DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, en= v, i32) DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32) -#endif DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoaddw_v_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoxorw_v_w, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode deleted file mode 100644 index 8157dee8b7..0000000000 --- a/target/riscv/insn32-64.decode +++ /dev/null @@ -1,88 +0,0 @@ -# -# RISC-V translation routines for the RV Instruction Set. -# -# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de -# Bastian Koppelmann, kbastian@mail.uni-paderborn.de -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2 or later, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License along = with -# this program. If not, see . - -# This is concatenated with insn32.decode for risc64 targets. -# Most of the fields and formats are there. - -%sh5 20:5 - -@sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5 = %rs1 %rd - -# *** RV64I Base Instruction Set (in addition to RV32I) *** -lwu ............ ..... 110 ..... 0000011 @i -ld ............ ..... 011 ..... 0000011 @i -sd ....... ..... ..... 011 ..... 0100011 @s -addiw ............ ..... 000 ..... 0011011 @i -slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 -srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 -sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 -addw 0000000 ..... ..... 000 ..... 0111011 @r -subw 0100000 ..... ..... 000 ..... 0111011 @r -sllw 0000000 ..... ..... 001 ..... 0111011 @r -srlw 0000000 ..... ..... 101 ..... 0111011 @r -sraw 0100000 ..... ..... 101 ..... 0111011 @r - -# *** RV64M Standard Extension (in addition to RV32M) *** -mulw 0000001 ..... ..... 000 ..... 0111011 @r -divw 0000001 ..... ..... 100 ..... 0111011 @r -divuw 0000001 ..... ..... 101 ..... 0111011 @r -remw 0000001 ..... ..... 110 ..... 0111011 @r -remuw 0000001 ..... ..... 111 ..... 0111011 @r - -# *** RV64A Standard Extension (in addition to RV32A) *** -lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld -sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st -amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st -amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st -amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st -amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st -amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st -amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st -amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st -amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st -amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st - -#*** Vector AMO operations (in addition to Zvamo) *** -vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm - -# *** RV64F Standard Extension (in addition to RV32F) *** -fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm -fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm -fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm -fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm - -# *** RV64D Standard Extension (in addition to RV32D) *** -fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm -fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm -fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 -fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm -fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm -fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 - -# *** RV32H Base Instruction Set *** -hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 -hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 -hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 84080dd18c..fecf0f15d5 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -21,6 +21,7 @@ %rs2 20:5 %rs1 15:5 %rd 7:5 +%sh5 20:5 =20 %sh10 20:10 %csr 20:12 @@ -86,6 +87,8 @@ @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 @sfence_vm ....... ..... ..... ... ..... ....... %rs1 =20 +# Formats 64: +@sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5 = %rs1 %rd =20 # *** Privileged Instructions *** ecall 000000000000 00000 000 00000 1110011 @@ -144,6 +147,20 @@ csrrwi ............ ..... 101 ..... 1110011 @csr csrrsi ............ ..... 110 ..... 1110011 @csr csrrci ............ ..... 111 ..... 1110011 @csr =20 +# *** RV64I Base Instruction Set (in addition to RV32I) *** +lwu ............ ..... 110 ..... 0000011 @i +ld ............ ..... 011 ..... 0000011 @i +sd ....... ..... ..... 011 ..... 0100011 @s +addiw ............ ..... 000 ..... 0011011 @i +slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 +srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 +sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 +addw 0000000 ..... ..... 000 ..... 0111011 @r +subw 0100000 ..... ..... 000 ..... 0111011 @r +sllw 0000000 ..... ..... 001 ..... 0111011 @r +srlw 0000000 ..... ..... 101 ..... 0111011 @r +sraw 0100000 ..... ..... 101 ..... 0111011 @r + # *** RV32M Standard Extension *** mul 0000001 ..... ..... 000 ..... 0110011 @r mulh 0000001 ..... ..... 001 ..... 0110011 @r @@ -154,6 +171,13 @@ divu 0000001 ..... ..... 101 ..... 0110011 @r rem 0000001 ..... ..... 110 ..... 0110011 @r remu 0000001 ..... ..... 111 ..... 0110011 @r =20 +# *** RV64M Standard Extension (in addition to RV32M) *** +mulw 0000001 ..... ..... 000 ..... 0111011 @r +divw 0000001 ..... ..... 100 ..... 0111011 @r +divuw 0000001 ..... ..... 101 ..... 0111011 @r +remw 0000001 ..... ..... 110 ..... 0111011 @r +remuw 0000001 ..... ..... 111 ..... 0111011 @r + # *** RV32A Standard Extension *** lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st @@ -167,6 +191,19 @@ amomax_w 10100 . . ..... ..... 010 ..... 0101111 @at= om_st amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st =20 +# *** RV64A Standard Extension (in addition to RV32A) *** +lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld +sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st +amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st +amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st +amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st +amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st +amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st +amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st +amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st +amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st +amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st + # *** RV32F Standard Extension *** flw ............ ..... 010 ..... 0000111 @i fsw ....... ..... ..... 010 ..... 0100111 @s @@ -195,6 +232,12 @@ fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_= rm fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 =20 +# *** RV64F Standard Extension (in addition to RV32F) *** +fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm +fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm + # *** RV32D Standard Extension *** fld ............ ..... 011 ..... 0000111 @i fsd ....... ..... ..... 011 ..... 0100111 @s @@ -223,6 +266,14 @@ fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_= rm fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm =20 +# *** RV64D Standard Extension (in addition to RV32D) *** +fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm +fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm +fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 +fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm +fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm +fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 + # *** RV32H Base Instruction Set *** hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2 hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2 @@ -237,7 +288,10 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r= 2_s hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma =20 -# *** RV32V Extension *** +# *** RV32H Base Instruction Set *** +hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 +hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 +hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s =20 # *** Vector loads and stores are encoded within LOADFP/STORE-FP *** vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm @@ -592,3 +646,14 @@ vcompress_vm 010111 - ..... ..... 010 ..... 1010111= @r =20 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r + +#*** Vector AMO operations (in addition to Zvamo) *** +vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 7c4ab92ecb..8700516a14 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -223,13 +223,13 @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env, uin= t64_t rs1) return (int32_t)float32_to_uint32(frs1, &env->fp_status); } =20 -uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1) +target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1) { float32 frs1 =3D check_nanbox_s(rs1); return float32_to_int64(frs1, &env->fp_status); } =20 -uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1) +target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1) { float32 frs1 =3D check_nanbox_s(rs1); return float32_to_uint64(frs1, &env->fp_status); @@ -245,12 +245,12 @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_= ulong rs1) return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status)); } =20 -uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1) +uint64_t helper_fcvt_s_l(CPURISCVState *env, target_ulong rs1) { return nanbox_s(int64_to_float32(rs1, &env->fp_status)); } =20 -uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1) +uint64_t helper_fcvt_s_lu(CPURISCVState *env, target_ulong rs1) { return nanbox_s(uint64_to_float32(rs1, &env->fp_status)); } @@ -332,12 +332,12 @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env, uin= t64_t frs1) return (int32_t)float64_to_uint32(frs1, &env->fp_status); } =20 -uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1) +target_ulong helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1) { return float64_to_int64(frs1, &env->fp_status); } =20 -uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1) +target_ulong helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1) { return float64_to_uint64(frs1, &env->fp_status); } @@ -352,12 +352,12 @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_= ulong rs1) return uint32_to_float64((uint32_t)rs1, &env->fp_status); } =20 -uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1) +uint64_t helper_fcvt_d_l(CPURISCVState *env, target_ulong rs1) { return int64_to_float64(rs1, &env->fp_status); } =20 -uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1) +uint64_t helper_fcvt_d_lu(CPURISCVState *env, target_ulong rs1) { return uint64_to_float64(rs1, &env->fp_status); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a1f794ffda..669fd0d525 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -74,8 +74,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ex= t) =20 #ifdef TARGET_RISCV32 # define is_32bit(ctx) true -#elif defined(CONFIG_USER_ONLY) -# define is_32bit(ctx) false #else static inline bool is_32bit(DisasContext *ctx) { @@ -435,6 +433,12 @@ EX_SH(12) } \ } while (0) =20 +#define REQUIRE_64BIT(ctx) do { \ + if (is_32bit(ctx)) { \ + return false; \ + } \ +} while (0) + static int ex_rvc_register(DisasContext *ctx, int reg) { return 8 + reg; @@ -482,7 +486,6 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *= a, return true; } =20 -#ifdef TARGET_RISCV64 static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) { tcg_gen_add_tl(ret, arg1, arg2); @@ -543,8 +546,6 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *= a, return true; } =20 -#endif - static bool gen_arith(DisasContext *ctx, arg_r *a, void(*func)(TCGv, TCGv, TCGv)) { diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 4651a1e224..12c31aa4b4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -751,7 +751,6 @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_= MIN, l) GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l) GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l) GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l) -#ifdef TARGET_RISCV64 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l) GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q) GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l) @@ -770,7 +769,6 @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_= MINU, l) GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q) GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l) GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q) -#endif =20 static inline void vext_amo_noatomic(void *vs3, void *v0, target_ulong base, @@ -814,7 +812,6 @@ void HELPER(NAME)(void *vs3, void *v0, target_ulong bas= e, \ GETPC()); \ } =20 -#ifdef TARGET_RISCV64 GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq) GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq) GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq) @@ -833,7 +830,6 @@ GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, = clearq) GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq) GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq) GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq) -#endif GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl) GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl) GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index be8a9f06dd..ab2ec4f0a5 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -165,60 +165,68 @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_am= omaxu_w *a) return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_T= ESL)); } =20 -#ifdef TARGET_RISCV64 - static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a) { + REQUIRE_64BIT(ctx); return gen_lr(ctx, a, MO_ALIGN | MO_TEQ); } =20 static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a) { + REQUIRE_64BIT(ctx); return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ)); } =20 static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ)); } =20 static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TE= Q)); } =20 static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TE= Q)); } =20 static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TE= Q)); } =20 static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ= )); } =20 static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_T= EQ)); } =20 static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_T= EQ)); } =20 static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_T= EQ)); } =20 static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_T= EQ)); } -#endif diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 4f832637fa..7e45538ae0 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -358,10 +358,9 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcv= t_d_wu *a) return true; } =20 -#ifdef TARGET_RISCV64 - static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 @@ -375,6 +374,7 @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_= l_d *a) =20 static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 @@ -388,15 +388,21 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fc= vt_lu_d *a) =20 static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 +#ifdef TARGET_RISCV64 gen_set_gpr(a->rd, cpu_fpr[a->rs1]); return true; +#else + qemu_build_not_reached(); +#endif } =20 static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 @@ -412,6 +418,7 @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_= d_l *a) =20 static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 @@ -427,9 +434,11 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcv= t_d_lu *a) =20 static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 +#ifdef TARGET_RISCV64 TCGv t0 =3D tcg_temp_new(); gen_get_gpr(t0, a->rs1); =20 @@ -437,5 +446,7 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_= x *a) tcg_temp_free(t0); mark_fs_dirty(ctx); return true; -} +#else + qemu_build_not_reached(); #endif +} diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index 3dfec8211d..db1c0c9974 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -415,9 +415,9 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_= x *a) return true; } =20 -#ifdef TARGET_RISCV64 static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 @@ -431,6 +431,7 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_= l_s *a) =20 static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 @@ -444,6 +445,7 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt= _lu_s *a) =20 static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 @@ -460,6 +462,7 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_= s_l *a) =20 static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a) { + REQUIRE_64BIT(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 @@ -473,4 +476,3 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt= _s_lu *a) tcg_temp_free(t0); return true; } -#endif diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index ce7ed5affb..6b5edf82b7 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -203,10 +203,11 @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w = *a) #endif } =20 -#ifdef TARGET_RISCV64 static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); + #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -228,7 +229,9 @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu = *a) =20 static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); + #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -250,7 +253,9 @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) =20 static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); + #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); @@ -269,7 +274,6 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) return false; #endif } -#endif =20 static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a) { diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index d04ca0394c..1340676209 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -204,22 +204,23 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a) return gen_store(ctx, a, MO_TESL); } =20 -#ifdef TARGET_RISCV64 static bool trans_lwu(DisasContext *ctx, arg_lwu *a) { + REQUIRE_64BIT(ctx); return gen_load(ctx, a, MO_TEUL); } =20 static bool trans_ld(DisasContext *ctx, arg_ld *a) { + REQUIRE_64BIT(ctx); return gen_load(ctx, a, MO_TEQ); } =20 static bool trans_sd(DisasContext *ctx, arg_sd *a) { + REQUIRE_64BIT(ctx); return gen_store(ctx, a, MO_TEQ); } -#endif =20 static bool trans_addi(DisasContext *ctx, arg_addi *a) { @@ -361,14 +362,15 @@ static bool trans_and(DisasContext *ctx, arg_and *a) return gen_arith(ctx, a, &tcg_gen_and_tl); } =20 -#ifdef TARGET_RISCV64 static bool trans_addiw(DisasContext *ctx, arg_addiw *a) { + REQUIRE_64BIT(ctx); return gen_arith_imm_tl(ctx, a, &gen_addw); } =20 static bool trans_slliw(DisasContext *ctx, arg_slliw *a) { + REQUIRE_64BIT(ctx); TCGv source1; source1 =3D tcg_temp_new(); gen_get_gpr(source1, a->rs1); @@ -383,6 +385,7 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a) =20 static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { + REQUIRE_64BIT(ctx); TCGv t =3D tcg_temp_new(); gen_get_gpr(t, a->rs1); tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt); @@ -395,6 +398,7 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a) =20 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { + REQUIRE_64BIT(ctx); TCGv t =3D tcg_temp_new(); gen_get_gpr(t, a->rs1); tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt); @@ -405,16 +409,19 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw = *a) =20 static bool trans_addw(DisasContext *ctx, arg_addw *a) { + REQUIRE_64BIT(ctx); return gen_arith(ctx, a, &gen_addw); } =20 static bool trans_subw(DisasContext *ctx, arg_subw *a) { + REQUIRE_64BIT(ctx); return gen_arith(ctx, a, &gen_subw); } =20 static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { + REQUIRE_64BIT(ctx); TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 @@ -433,6 +440,7 @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a) =20 static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { + REQUIRE_64BIT(ctx); TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 @@ -453,6 +461,7 @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a) =20 static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { + REQUIRE_64BIT(ctx); TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 @@ -473,7 +482,6 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a) =20 return true; } -#endif =20 static bool trans_fence(DisasContext *ctx, arg_fence *a) { diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_tr= ans/trans_rvm.c.inc index 47cd6edc72..10ecc456fc 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -87,34 +87,42 @@ static bool trans_remu(DisasContext *ctx, arg_remu *a) return gen_arith(ctx, a, &gen_remu); } =20 -#ifdef TARGET_RISCV64 static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); + return gen_arith(ctx, a, &gen_mulw); } =20 static bool trans_divw(DisasContext *ctx, arg_divw *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); + return gen_arith_div_w(ctx, a, &gen_div); } =20 static bool trans_divuw(DisasContext *ctx, arg_divuw *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); + return gen_arith_div_uw(ctx, a, &gen_divu); } =20 static bool trans_remw(DisasContext *ctx, arg_remw *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); + return gen_arith_div_w(ctx, a, &gen_rem); } =20 static bool trans_remuw(DisasContext *ctx, arg_remuw *a) { + REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); + return gen_arith_div_uw(ctx, a, &gen_remu); } -#endif diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 887c6b8883..47914a3b69 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -705,7 +705,6 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8= _t seq) gen_helper_vamominuw_v_w, gen_helper_vamomaxuw_v_w }; -#ifdef TARGET_RISCV64 static gen_helper_amo *const fnsd[18] =3D { gen_helper_vamoswapw_v_d, gen_helper_vamoaddw_v_d, @@ -726,7 +725,6 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8= _t seq) gen_helper_vamominud_v_d, gen_helper_vamomaxud_v_d }; -#endif =20 if (tb_cflags(s->base.tb) & CF_PARALLEL) { gen_helper_exit_atomic(cpu_env); @@ -734,12 +732,12 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uin= t8_t seq) return true; } else { if (s->sew =3D=3D 3) { -#ifdef TARGET_RISCV64 - fn =3D fnsd[seq]; -#else - /* Check done in amo_check(). */ - g_assert_not_reached(); -#endif + if (!is_32bit(s)) { + fn =3D fnsd[seq]; + } else { + /* Check done in amo_check(). */ + g_assert_not_reached(); + } } else { assert(seq < ARRAY_SIZE(fnsw)); fn =3D fnsw[seq]; @@ -769,6 +767,11 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a) ((1 << s->sew) >=3D 4)); } =20 +static bool amo_check64(DisasContext *s, arg_rwdvm* a) +{ + return !is_32bit(s) && amo_check(s, a); +} + GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check) GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check) GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check) @@ -778,17 +781,15 @@ GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_chec= k) GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check) GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check) GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check) -#ifdef TARGET_RISCV64 -GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check) -#endif +GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check64) =20 /* *** Vector Integer Arithmetic Instructions diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 88ab850682..24bf049164 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -7,7 +7,7 @@ gen32 =3D [ =20 gen64 =3D [ decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode= ', '--static-decode=3Ddecode_insn16', '--insnwidth=3D16']), - decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode= ', '--static-decode=3Ddecode_insn32']), + decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), ] =20 riscv_ss =3D ss.source_set() --=20 2.31.1 From nobody Sun May 19 05:22:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1619235545; cv=none; d=zohomail.com; s=zohoarc; b=bRjZ4EFCUb+rxh5F7YLVv+Iuoa4Qbam/6UQDXREek4xhfxxdE16wiHZavZn1T6tTSsZP7PVcT+rT67Jrg2zu7Bc7Hbs801V9mlyx3sgieC9X13BNzBogvF+0SeIyRajZxWxsOOQEaz3OkMTzBk+1QE0G18iR0HTk3zQslaup9gI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619235545; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=N1ZgTER+txXZjDGX034+EJFt5tA1etmR2V0pM1M3kVk=; b=FtI4dHWp+QSQv+YQIAwmyEp2GxVYk/9YM3GRkPsQHkIr11pFmqp9YZZHBwWwwyNVuTVh4Wb5Lg4FQ9rsHWr0/3BXBV7cJmWgW7lyOcBy8RPEAjmEornC1CVB6qAutXgfAdWp/uFwex8+KVoDs0PPfeUbaNe5UYKkMo8zLQityUY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619235545912842.1936750234053; Fri, 23 Apr 2021 20:39:05 -0700 (PDT) Received: from localhost ([::1]:40718 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1la98K-0005YP-S3 for importer@patchew.org; Fri, 23 Apr 2021 23:39:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53190) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la945-0008Mg-M0; Fri, 23 Apr 2021 23:34:42 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:53336) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la941-0004BP-0L; Fri, 23 Apr 2021 23:34:40 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 24 Apr 2021 11:34:34 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 20:15:07 -0700 Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.34]) by uls-op-cesaip01.wdc.com with ESMTP; 23 Apr 2021 20:34:32 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1619235277; x=1650771277; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lGDTyAhY8hezdUtJCTKLTSQi2mnrxTyltB8vZ0V1nks=; b=GAFABxgiIqd7kgqIgSyPTG5cQZkfIw2eqz83ytOzOkN5AmnSIlNNw2hj loMHPufqYiDhGnHDNrIg3vRZdiaHk+cCsKf1SKgejEEGBZufX13FtOWtd n9cG8/4iL7OP9CbmpgZkoO2atWZcS4bCoiFu9fuszB8BAb54pAlee6fn5 lHPYEFfkBy5vTjt0u+VAAZylW8Xsm1KgumSujY7h9ASX78itVOqEQxMTV CYRY8TdMlPygCvp/3rdx8sKQJh6PFkS2kkeY/ismvO1OZgGStXv3OkoQ0 dUU9ZmbENP6HBQZoe6iGU4MhPrewkxQvf3k0hblSM6NmS/dWcdYyxdTYi A==; IronPort-SDR: GNk1WYHAWDa1pSzCBySloJ4w/+KhYopEV2PpXvytKVQdoYqPM5abFNb09jkVegfvWDSlfMi+80 18Je/ok4TIyb4avOXD+Oq1BYdCf7uGctV6AwZcieZ1aRIi6hzMJVZADyFC2WrrNb48gtCjJ8wl Sib69bVDFTRlQ14rzW85JIP9DSlA6nR/EMqpD9wxmRxEYNxgFqhiWJ3YeAjiLH+kYMFHBJxkyr r86ZXfqddLi6yvApY8pOZUE5etgFfwoTvBsCvXCD5fecbicIeUWMKu9OaMLBh5NfJ2CvAMp1tZ tXM= X-IronPort-AV: E=Sophos;i="5.82,247,1613404800"; d="scan'208";a="277100858" IronPort-SDR: jFG45jphT9e1ojCzBg1mRN21WFCGSYdf2UQbPmXxEcSgXg7IU1fsfSTdTCXcmROJhfd5QM6Eor rpq89OFrMgb1dvDLvhG39i0kryQfsowuQXJsDw/uH2ap6XPkuz1v7i0iujaCK2xSjDZXcBdMzs 26OX0OS8OHbGTxnYF3s37vOzEH3xZklll/ym7O7EgOhJ08HdmnxjNfOReZm9txnIPm5/ikuriw 7hae9ngSNeTAkHq1ToHf5PKNL2Upi4BjWXy5nwYvl9W1wyZ+7CpwOiRwELN05a25N4ecE9pfId D+LO1ueHFa5GG/lWixVEAdU4 IronPort-SDR: 6c3Zz/8h1Vxo2QnKC1YjtXjKK824KHy23oX4Ts4NxcppxvApi2EJefZmKhssOLISsH6h3Q2toW /XC6inQYl8ScISabKI4DYXCjd9u4OZRZruLfUgRsq0cBQPjCrA7sODyQiVuhiZswOjMnhSrSh0 UXOES5yHxI0aQqzROr9a8jvzJbToHt0hs1iaOM+MkZfFL1dv4UrKN+8++8bMVh2WLwX3xxheRT HXCw7l1hXYjEr9B4Qg5vSMP7S/sfZ4lPJ0NHkWobKM244bSe7OTeCvb6vZEPYqiqtGzKBd5jdz sas= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 09/10] target/riscv: Consolidate RV32/64 16-bit instructions Date: Sat, 24 Apr 2021 13:34:25 +1000 Message-Id: <01e2b0efeae311adc7ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=7413b051c=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This patch removes the insn16-32.decode and insn16-64.decode decode files and consolidates the instructions into the general RISC-V insn16.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn16-32.decode | 28 ------------------- target/riscv/insn16-64.decode | 36 ------------------------- target/riscv/insn16.decode | 30 +++++++++++++++++++++ target/riscv/insn_trans/trans_rvi.c.inc | 6 +++++ target/riscv/meson.build | 11 +++----- 5 files changed, 39 insertions(+), 72 deletions(-) delete mode 100644 target/riscv/insn16-32.decode delete mode 100644 target/riscv/insn16-64.decode diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode deleted file mode 100644 index 0819b17028..0000000000 --- a/target/riscv/insn16-32.decode +++ /dev/null @@ -1,28 +0,0 @@ -# -# RISC-V translation routines for the RVXI Base Integer Instruction Set. -# -# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de -# Bastian Koppelmann, kbastian@mail.uni-paderborn.de -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2 or later, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License along = with -# this program. If not, see . - -# *** RV32C Standard Extension (Quadrant 0) *** -flw 011 ... ... .. ... 00 @cl_w -fsw 111 ... ... .. ... 00 @cs_w - -# *** RV32C Standard Extension (Quadrant 1) *** -jal 001 ........... 01 @cj rd=3D1 # C.JAL - -# *** RV32C Standard Extension (Quadrant 2) *** -flw 011 . ..... ..... 10 @c_lwsp -fsw 111 . ..... ..... 10 @c_swsp diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode deleted file mode 100644 index 672e1e916f..0000000000 --- a/target/riscv/insn16-64.decode +++ /dev/null @@ -1,36 +0,0 @@ -# -# RISC-V translation routines for the RVXI Base Integer Instruction Set. -# -# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de -# Bastian Koppelmann, kbastian@mail.uni-paderborn.de -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2 or later, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License along = with -# this program. If not, see . - -# *** RV64C Standard Extension (Quadrant 0) *** -ld 011 ... ... .. ... 00 @cl_d -sd 111 ... ... .. ... 00 @cs_d - -# *** RV64C Standard Extension (Quadrant 1) *** -{ - illegal 001 - 00000 ----- 01 # c.addiw, RES rd=3D0 - addiw 001 . ..... ..... 01 @ci -} -subw 100 1 11 ... 00 ... 01 @cs_2 -addw 100 1 11 ... 01 ... 01 @cs_2 - -# *** RV64C Standard Extension (Quadrant 2) *** -{ - illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=3D0 - ld 011 . ..... ..... 10 @c_ldsp -} -sd 111 . ..... ..... 10 @c_sdsp diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 1cb93876fe..2e9212663c 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -92,6 +92,16 @@ lw 010 ... ... .. ... 00 @cl_w fsd 101 ... ... .. ... 00 @cs_d sw 110 ... ... .. ... 00 @cs_w =20 +# *** RV32C and RV64C specific Standard Extension (Quadrant 0) *** +{ + ld 011 ... ... .. ... 00 @cl_d + flw 011 ... ... .. ... 00 @cl_w +} +{ + sd 111 ... ... .. ... 00 @cs_d + fsw 111 ... ... .. ... 00 @cs_w +} + # *** RV32/64C Standard Extension (Quadrant 1) *** addi 000 . ..... ..... 01 @ci addi 010 . ..... ..... 01 @c_li @@ -111,6 +121,15 @@ jal 101 ........... 01 @cj rd=3D0= # C.J beq 110 ... ... ..... 01 @cb_z bne 111 ... ... ..... 01 @cb_z =20 +# *** RV64C and RV32C specific Standard Extension (Quadrant 1) *** +{ + c64_illegal 001 - 00000 ----- 01 # c.addiw, RES rd=3D0 + addiw 001 . ..... ..... 01 @ci + jal 001 ........... 01 @cj rd=3D1 # C.JAL +} +subw 100 1 11 ... 00 ... 01 @cs_2 +addw 100 1 11 ... 01 ... 01 @cs_2 + # *** RV32/64C Standard Extension (Quadrant 2) *** slli 000 . ..... ..... 10 @c_shift2 fld 001 . ..... ..... 10 @c_ldsp @@ -130,3 +149,14 @@ fld 001 . ..... ..... 10 @c_ldsp } fsd 101 ...... ..... 10 @c_sdsp sw 110 . ..... ..... 10 @c_swsp + +# *** RV32C and RV64C specific Standard Extension (Quadrant 2) *** +{ + c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=3D0 + ld 011 . ..... ..... 10 @c_ldsp + flw 011 . ..... ..... 10 @c_lwsp +} +{ + sd 111 . ..... ..... 10 @c_sdsp + fsw 111 . ..... ..... 10 @c_swsp +} diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 1340676209..bd93f634cf 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -24,6 +24,12 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *= a) return true; } =20 +static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a) +{ + REQUIRE_64BIT(ctx); + return trans_illegal(ctx, a); +} + static bool trans_lui(DisasContext *ctx, arg_lui *a) { if (a->rd !=3D 0) { diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 24bf049164..af6c3416b7 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -1,18 +1,13 @@ # FIXME extra_args should accept files() dir =3D meson.current_source_dir() -gen32 =3D [ - decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode= ', '--static-decode=3Ddecode_insn16', '--insnwidth=3D16']), - decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), -] =20 -gen64 =3D [ - decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode= ', '--static-decode=3Ddecode_insn16', '--insnwidth=3D16']), +gen =3D [ + decodetree.process('insn16.decode', extra_args: ['--static-decode=3Ddeco= de_insn16', '--insnwidth=3D16']), decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), ] =20 riscv_ss =3D ss.source_set() -riscv_ss.add(when: 'TARGET_RISCV32', if_true: gen32) -riscv_ss.add(when: 'TARGET_RISCV64', if_true: gen64) +riscv_ss.add(gen) riscv_ss.add(files( 'cpu.c', 'cpu_helper.c', --=20 2.31.1 From nobody Sun May 19 05:22:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1619235644; cv=none; d=zohomail.com; s=zohoarc; b=Ttrs+JocrzG0ylAN+Tz7scPhJ+sjB66Efz5WqaiwB4Hg/Outlp3wEdDWSgjoO4frGEVDt+enLEnqvmwctcBv/fJEgc2br3sGPXcbPdAMvIv98Bu6NtvMlmGlcrWAqxhuyznvwKefBHIB4+ZJneei1UFsTEHX6LEQvis+1BUqcmI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619235644; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ifm2fxgCSWYQVKvG212FQYqtVj/7tF8nlbZ8PPsjktc=; b=QPr3sNWFtuVmERJWryHmSbCml19aH7QdDquizS0uf8qY5bZJtE1j90l2GHNi0G3+2waInWY+pT/zlp4Dv0OeqhQHJ1AQBFfl3lWSVOayuD9V6lE75HQAcIi9iLKvkExYcCKB9vbouy4DnXqOi0KKbEpnUoV35TdeV65CiXzU87k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619235644574727.1972900550604; Fri, 23 Apr 2021 20:40:44 -0700 (PDT) Received: from localhost ([::1]:44816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1la99v-0007Jd-1G for importer@patchew.org; Fri, 23 Apr 2021 23:40:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53222) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la94D-0008TI-Lo; Fri, 23 Apr 2021 23:34:49 -0400 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:7434) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1la94B-0004MR-Ou; Fri, 23 Apr 2021 23:34:49 -0400 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 24 Apr 2021 11:34:44 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 20:15:19 -0700 Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.34]) by uls-op-cesaip02.wdc.com with ESMTP; 23 Apr 2021 20:34:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1619235286; x=1650771286; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=d14N0Y5Ry5uhxuNORztBbIKTQXqP1sBkSSfyZAQ6cWo=; b=jXHkX4CT0fVTydKP/IX/WxbXpyVRh0s+XCuzPymvYk9QOxBYDNToQSte szfPj3K45vXrExLXonMpPLMxc+JS9tvSze7WBVhZy3PrarS9WIM4KVfN6 aysjBmeL3C/+AASgdai3xqAR7gh7Kt0MyHLg7vkrL38VB392kcI1qqnNP pUAWBxH3IYp+eQeFF1ducw8IyWNzhyKGk0AV/nBgAZ+xR/Lb9QpKY2W/E dAXvOvt8J35jM3XpDJvJym3dgU0ltKI85RveunV0QMdjjbnTUPzWCd0xF lEL2hXo7bthNkOvfltKLL2fhuscY1IYraapD9guhTy1UOmmJG5zEukymX w==; IronPort-SDR: k6Z8bndjOdtBv9wPYrHx3AJtfArFTFvuVmBR2Vvm+oKDJR1JCOiOEDSNAkqTXxODSTu85axeWe vP13pvEOPf2USzBsvUWR9fQXF++7CAuLLSNqjpnVeDZjtLwDfTJAN0pBpY2DmhGpCP/7rJ/pHy hwQa8QD7peWwro4GoTTu4Y+iuNvUKAP3f1KNk3lllk8RLmrzbtzY77Sdr12wjJ3Iqt1lQDAB5w cDXfnKPFeIAUEn+UG+th09nClGyM9kT5177cfqeSdih3cRMdoT67DsTPyFa4M7SiYs0j8qM49W qGc= X-IronPort-AV: E=Sophos;i="5.82,247,1613404800"; d="scan'208";a="166115916" IronPort-SDR: NZcYKUXM12/l2WC2pjR54IbXAvHjkvF2bc8/L48FyaQKQfTaJzvJsRR7+a43WNc6MEytKv1AWQ DpPLwbnOKi9PRk8+dKxhaOpSCub4ReDidLDF9HCX3Kfe0Vuf55kkz39ePD4TdVMMjFkUfxn5E4 netT8+ccJpmFLPdHUr6eoYzBXXp2GmyWpa3AvhzPYQrXHLSOG0ZWym7ZldSOCbj0MfZAP1hwHX w+TqhmkLCdtzOE5vw0yOpujjV13pTUm8YFoVYxejByAML5Uq48jr5cDdndssrVJDk/9HV2VThe TlHaB/XNy+h/dmUc8/w79fZs IronPort-SDR: G2+MruUYzI7ksEsGf60WKZkbvOi+ZWIMkEmjA1CiTjNMge9QRTnJSf/zWh2LdbTvxyGTByv4bP /o+Xqt9H7zBzd7/FP4p4hxM1AqB25XPBrh2vOvboYe14Jx+IOiqZlf7ike3uTRREdHYKK3lWiS IASV7Zgdr49/d3W/5/piV8NQ02NGq9Mches4Zy+Izy8V9b+RiTOuFdh5sf99nuXwJGj5x47MVD Ybr2gn9a/wVh/vWtIhQZhybL3/x/nMiecAgzfeq+z67GxYiS4dwwW7jhFkKRJGNiLqEX1y6oEc OkM= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment Date: Sat, 24 Apr 2021 13:34:37 +1000 Message-Id: <024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=7413b051c=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" BugLink: https://gitlab.com/qemu-project/qemu/-/issues/6 Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index fecf0f15d5..8901ba1e1b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -288,7 +288,7 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2= _s hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma =20 -# *** RV32H Base Instruction Set *** +# *** RV64H Base Instruction Set *** hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s --=20 2.31.1