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IronPort-SDR: cXbY5UwubKcrEBP26AR9qWxkcKl+aRHsP1HlUl0HBn27hA1JsFBcKvLbLihm9teTY8ekuqzH0o NuhyWLCzG4lZ8kb1ZjBJC8+x0/JXM2Lb4yYi2U1XHWQX+8uBwrkgwx+yaco/ZGJpAlqo+INBjQ tUlYgxOu2Ag2SeITYiG2YVY8dJcSkcPhYIXwIrjRhJhW19X6RRvEqtRpC5dwxEMQHSUaWTYdUW MtAF9ZmQRrGjXORFqoIDYkR4YXl4UxJvfmijIGMAQ6PLlOCUevY0ZOUBIGyt42ORRbybAmYS72 GP8= X-IronPort-AV: E=Sophos;i="5.82,220,1613404800"; d="scan'208";a="164258266" IronPort-SDR: kEbW0DqfENotjYJNPM003tU5rLYIiuJnM26yrBGeOk2tI+JH7qvXf+t5Mo8fHk0fKSg/FdgLRj oY3H9JlZ6XG/ijNqeOf+7cJ0lOOrWNUAcSmRNcsko26oaGTmeoqtYyXJVE9Ey3RGrhFjag0cYb K7vmOvzNXRAFsNmK6lyCjUWnlhh7mIcQCggggEypwcWub5iI1y+G1wYZEjn+pgVt2K6CPkZOn2 E394xZ5UuDB4Y38v+xJhGfI4livIv7T9wkLqVLK6bO0stvEnuphY4bfFuscRR/mE4V3VjVD2S8 UDmJUASNQUSeRHlfB12qCSop IronPort-SDR: qTfIjjiwEATE/eNmoDYNxEkDjqQaFKuaqyI1yepECemBtwS27MayXmXJHlANj9p/QYOVinhVBY DKfS8D37xzhCzZQqjGqxO5TNEq1A9nmulDGmBYMvRf/yMkJY9Zd7OkE/l1I2Niuvx0r7Tj4gXQ xtnyg1VZS4j/AeHGRCDF11c9E3w7ktcf589BPLYDOnKP1MMaAKqpDpzVn9IB3TIPNwQE1t/u8O lOvbZ1S1+KMjuyemCQUcN4qykkniNDthH1hJSIYsTPuFh5r5IbYeZmAxaqveUfpWy4wt28zOaK Clg= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 1/9] target/riscv: Remove the hardcoded RVXLEN macro Date: Wed, 14 Apr 2021 09:33:16 +1000 Message-Id: <3eea7ff02e990d9d9cb906be9eb821eaf1ee5408.1618356725.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=730c0c5bd=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng --- target/riscv/cpu.h | 6 ------ target/riscv/cpu.c | 6 +++++- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0a33d387ba..ef838f5fbf 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -53,12 +53,6 @@ #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) =20 -#if defined(TARGET_RISCV32) -#define RVXLEN RV32 -#elif defined(TARGET_RISCV64) -#define RVXLEN RV64 -#endif - #define RV(x) ((target_ulong)1 << (x - 'A')) =20 #define RVI RV('I') diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d6ed80f6b..92c3195531 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -147,7 +147,11 @@ static void set_resetvec(CPURISCVState *env, int reset= vec) static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#if defined(TARGET_RISCV32) + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#elif defined(TARGET_RISCV64) + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#endif set_priv_version(env, PRIV_VERSION_1_11_0); } =20 --=20 2.31.1 From nobody Sun May 19 05:00:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1618356934; cv=none; d=zohomail.com; s=zohoarc; b=UrmNMvIc7MDD/qqn6U+WY7bFEOixmsjriQGya/UJhvDYz7uc+ChRc4rifaGLdF4NoaGE4KicA8MbSYHoay8ktvM0RzYI1oQmc4FLF9w/0RbXhnwXSrkXVt9of/88uvPK4L6zYVwW+CgHTHHKB2T42UQn2gWCAb4ZmSUZ+eEYyXw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=730c0c5bd=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 6 ------ target/riscv/csr.c | 9 ++++++++- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index caf4599207..969dd05eae 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -423,12 +423,6 @@ #define SSTATUS32_SD 0x80000000 #define SSTATUS64_SD 0x8000000000000000ULL =20 -#if defined(TARGET_RISCV32) -#define SSTATUS_SD SSTATUS32_SD -#elif defined(TARGET_RISCV64) -#define SSTATUS_SD SSTATUS64_SD -#endif - /* hstatus CSR bits */ #define HSTATUS_VSBE 0x00000020 #define HSTATUS_GVA 0x00000040 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d2585395bf..832c3bf7fd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -418,7 +418,7 @@ static const target_ulong delegable_excps =3D (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | - SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; + SSTATUS_SUM | SSTATUS_MXR; static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP; static const target_ulong hip_writable_mask =3D MIP_VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | M= IP_VSEIP; @@ -738,6 +738,13 @@ static int rmw_mip(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) { target_ulong mask =3D (sstatus_v1_10_mask); + + if (riscv_cpu_is_32bit(env)) { + mask |=3D SSTATUS32_SD; + } else { + mask |=3D SSTATUS64_SD; + } + *val =3D env->mstatus & mask; return 0; } --=20 2.31.1 From nobody Sun May 19 05:00:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="164258282" IronPort-SDR: ytOkxgzJrnL13p+M9JNAYdhL5a4vMqC6+CInhRtH7S4az86TYWEJm9S8xMRtejx2cb0Wf5y4il Pap4uHKewR2FKxjodn0+DE+KvZVBLfuA3RZpwl2ilOzrabcBACWKzJbxrt/dxpkPPvqYPDI4uK hAyDcUwJdjy0IS0NlDDgQjY3jpS93i9UMViM9HlzVv1QN7ACQwR65CEbpveOyDx1ziUSnoBEsQ YfK47pHizqlkB64OSWoJlRH6mqIkfEOsu3nwWPhmRhaQ06t3wFPCpNb8T1hSCGJvxVYh5kX5l+ GDDQtUDN4UcwvsdpTRK6QeC3 IronPort-SDR: PpxMjERwrgXzSKYUzqgdG1DgECqf08FtPc6oMknVsziCCuexmd+1rikiwAnOF3Di1nuD4ycM1w 4a4MQHQXVNgc6MLtKXIkl1trBMXOAfRXdvnafawW6ATWBftfkpmnLc9T94Ufjct3RAtrTICQwX PcSpp2fl+aLUq+bHze53wmRV2W5PGiBARwNgxmk8CQvg7Wx0uHAYfbIEeMx0mKaCfrCaMW1DAL owQDDR8bjxCopYY1R+8BJh6Z7sAM/RZFY8fVT+LollKv/x5CmoT8fcprk2+8V507r3TFouvWMW wag= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 3/9] target/riscv: Remove the hardcoded HGATP_MODE macro Date: Wed, 14 Apr 2021 09:33:36 +1000 Message-Id: <4d1cd51a6f6330b13af1be5cfd45f98d09b8b850.1618356725.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=730c0c5bd=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 11 ----------- target/riscv/cpu_helper.c | 24 +++++++++++++++--------- 2 files changed, 15 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 969dd05eae..8caab23b62 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -207,17 +207,6 @@ #define CSR_HTIMEDELTA 0x605 #define CSR_HTIMEDELTAH 0x615 =20 -#if defined(TARGET_RISCV32) -#define HGATP_MODE SATP32_MODE -#define HGATP_VMID SATP32_ASID -#define HGATP_PPN SATP32_PPN -#endif -#if defined(TARGET_RISCV64) -#define HGATP_MODE SATP64_MODE -#define HGATP_VMID SATP64_ASID -#define HGATP_PPN SATP64_PPN -#endif - /* Virtual CSRs */ #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 21c54ef561..b065ddb681 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -411,8 +411,13 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, } widened =3D 0; } else { - base =3D (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT; - vm =3D get_field(env->hgatp, HGATP_MODE); + if (riscv_cpu_is_32bit(env)) { + base =3D (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; + vm =3D get_field(env->hgatp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; + vm =3D get_field(env->hgatp, SATP64_MODE); + } widened =3D 2; } /* status.SUM will be ignored if execute on background */ @@ -615,16 +620,17 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, bool first_stage, bool two_stage) { CPUState *cs =3D env_cpu(env); - int page_fault_exceptions; + int page_fault_exceptions, vm; + if (first_stage) { - page_fault_exceptions =3D - get_field(env->satp, SATP_MODE) !=3D VM_1_10_MBARE && - !pmp_violation; + vm =3D get_field(env->satp, SATP_MODE); + } else if (riscv_cpu_is_32bit(env)) { + vm =3D get_field(env->hgatp, SATP32_MODE); } else { - page_fault_exceptions =3D - get_field(env->hgatp, HGATP_MODE) !=3D VM_1_10_MBARE && - !pmp_violation; + vm =3D get_field(env->hgatp, SATP64_MODE); } + page_fault_exceptions =3D vm !=3D VM_1_10_MBARE && !pmp_violation; + switch (access_type) { case MMU_INST_FETCH: if (riscv_cpu_virt_enabled(env) && !first_stage) { --=20 2.31.1 From nobody Sun May 19 05:00:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1618357279; cv=none; d=zohomail.com; s=zohoarc; b=Qfww6UbBvV3rCCMAH1cTchCUd7yaWYB2QiJtg2w02ZzMdvNIwYYT8E41ud2fo9yGnyPYjCssQ03l9bjLL5e37nfcFSbrw1gmDdbwiOHOi2WXymEWV6jp6ZyKxwz2v9QQlT6GC/jQXghtV99NqGqZmkUUCxTRzEBUg5dj6lPWa4A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618357279; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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IronPort-SDR: B9UlfdJIqDlwQWVNaa2qbcBlqXfCi7KQTUfM79AmCyBGZhzb4L+UQKeriXmQ+EQdx7V8MFg06v tvwo3k/DnzEPkET08293d6w+Ji3dmmbACq2Qf8x5PQ94ci/TNCrLypCIhRtm9joTvxL5HheC5U rGPKl9kSyk+G9Kv1IGjlGVvbBpig0ZuvPt3eVeKCISbELYOhKFQBA4937SKldEb1MvqEGDpmNy 37FrCY+HYeLS9AHjSua44lVVbhEjfnyNu4Vr3BFA9zOY2dzVTveuJlty4m0HjeD50+qkFg9UPO 6Z0= X-IronPort-AV: E=Sophos;i="5.82,220,1613404800"; d="scan'208";a="164660163" IronPort-SDR: EJhRY557mZzizeXN8pgNjbC4AOozKK/BO2X/jv8teJTVMCTxCAmq6lC3G0f76We8Qg0ihYOhye q7zDKDJdh9a//WvVXehjTMzC4kWQF6BlIhR7VlwYIr4dl8QQwI13zLwvAo89eqQtfHLrPD5dKo WQSX+2QIksSUX+Br+/djhjCVeRcSmfgxHWSdtMAooehiR3wmVmehRlIRHWMUpPZm2BVoyiFdp3 hveHaKJyMy89OYSE2iWg2vXfa1J3tNZzHGBoM5q12siOuypd4WZZCgUjDwoVSRXJ/DL6ol+8Y0 YChGlgnt6lR4H+txOwrh2Z/C IronPort-SDR: 8ZaFDS7RbC3m62OU+rd8esoihhdXZY6JMWPJS/E1Olh/hGcxJ3Jku4uD3lU3i3x0QwjBa8KKby nVwv/C0JBH0/8Cz8LgzTFeYeQAcYMazscVp8s5LX8GwlEn8zNEuPzRbl/20I3wcEvj/d836w41 FGBa/qaoN+ga+Gr3DbikWxkiH3mDbfGebyw1E0smhtTlX/RZUhWVtuFK1OIg/oa+qYY8w+sVp8 L4XOKBQRebQOImKJtpxUHEIwkQe+1ZMQQXVrc9Y2+WwO3NJW4FpjxOKzL8kSrBx2AmGmHr3d6u G1A= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 4/9] target/riscv: Remove the hardcoded MSTATUS_SD macro Date: Wed, 14 Apr 2021 09:33:49 +1000 Message-Id: <2d6d0483c1a1e7aedd1c410b34812ea8e076cb33.1618356725.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=730c0c5bd=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 10 ---------- target/riscv/csr.c | 12 ++++++++++-- target/riscv/translate.c | 20 ++++++++++++++++++-- 3 files changed, 28 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8caab23b62..dd643d0f63 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -387,16 +387,6 @@ #define MXL_RV64 2 #define MXL_RV128 3 =20 -#if defined(TARGET_RISCV32) -#define MSTATUS_SD MSTATUS32_SD -#define MISA_MXL MISA32_MXL -#define MXL_VAL MXL_RV32 -#elif defined(TARGET_RISCV64) -#define MSTATUS_SD MSTATUS64_SD -#define MISA_MXL MISA64_MXL -#define MXL_VAL MXL_RV64 -#endif - /* sstatus CSR bits */ #define SSTATUS_UIE 0x00000001 #define SSTATUS_SIE 0x00000002 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 832c3bf7fd..6052b2d6e9 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -492,7 +492,11 @@ static int write_mstatus(CPURISCVState *env, int csrno= , target_ulong val) =20 dirty =3D ((mstatus & MSTATUS_FS) =3D=3D MSTATUS_FS) | ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); - mstatus =3D set_field(mstatus, MSTATUS_SD, dirty); + if (riscv_cpu_is_32bit(env)) { + mstatus =3D set_field(mstatus, MSTATUS32_SD, dirty); + } else { + mstatus =3D set_field(mstatus, MSTATUS64_SD, dirty); + } env->mstatus =3D mstatus; =20 return 0; @@ -564,7 +568,11 @@ static int write_misa(CPURISCVState *env, int csrno, t= arget_ulong val) } =20 /* misa.MXL writes are not supported by QEMU */ - val =3D (env->misa & MISA_MXL) | (val & ~MISA_MXL); + if (riscv_cpu_is_32bit(env)) { + val =3D (env->misa & MISA32_MXL) | (val & ~MISA32_MXL); + } else { + val =3D (env->misa & MISA64_MXL) | (val & ~MISA64_MXL); + } =20 /* flush translation cache */ if (val !=3D env->misa) { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2f9f5ccc62..74636b9db7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -78,6 +78,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t e= xt) return ctx->misa & ext; } =20 +#ifndef CONFIG_USER_ONLY +# ifdef TARGET_RISCV32 +# define is_32bit(ctx) true +# else +static inline bool is_32bit(DisasContext *ctx) +{ + return !(ctx->misa & RV64); +} +# endif +#endif + /* * RISC-V requires NaN-boxing of narrower width floating point values. * This applies when a 32-bit value is assigned to a 64-bit FP register. @@ -369,6 +380,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_u= long imm) static void mark_fs_dirty(DisasContext *ctx) { TCGv tmp; + target_ulong sd; + if (ctx->mstatus_fs =3D=3D MSTATUS_FS) { return; } @@ -376,13 +389,16 @@ static void mark_fs_dirty(DisasContext *ctx) ctx->mstatus_fs =3D MSTATUS_FS; =20 tmp =3D tcg_temp_new(); + sd =3D is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD; + + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); =20 if (ctx->virt_enabled) { tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); } tcg_temp_free(tmp); --=20 2.31.1 From nobody Sun May 19 05:00:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1618357083; cv=none; d=zohomail.com; s=zohoarc; b=WUvokpUu4nrRqEXLOgU35vM8U8m8QXMVMqPtsnJ3wgv7xsAXh3aovYHxAN2V2T8I/qoxOdmc7JwzEBhmUnT0Z8S6R4u5Iyg/ADX5GI6/1ijmGWTSKKpEHrQpCpMYjY6FaPaD1wt5uYpZOcuvqeLBQXKB1MzAkcoW+sqM/2WwRh4= ARC-Message-Signature: i=1; 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t=1618356873; x=1649892873; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t+RiucRtPdXKOzS7snl5iFqslDJ3MG0do01OpedL8TI=; b=ibs8biC9HAXvHnbrvdHYHuFbD3r2gXztqach8lNp6tdpmY3ub3aXvb81 Q91tupVRHmLdpNeybhWG/OVZElLWMXYqFrSRXwyy2QTuagqu6qjdCQ+JK 6VjlopjuK4i3vmjCUsfrK38GDP7X7lCOD7geA2BWIEN+N/fz+chaFVd9V KA9+wco5rSt2Atx2yHOCdC00ESWhA2/lml2Mb/hXE6tOA451sM1c7T474 mZJF/rUn9Z7A2REJKNrC9pThAzaXUJ2fpfnqPkdnBGzqfVOs7d9kEd9YE O+EUp8qLp3GbbN8MPX9WrngHk/3foqIK5NaHjH6zw3twQqgp80v5loEku Q==; IronPort-SDR: 2xFPZGxpl1GooiUOKUiilWcBUbf3LAY5Y4x1MrhDUow2NVr2Nzp3J0KJP6axCbwd3VmYQ6UII0 /RqK5p9M0Gnpwshj+KrEICpDDx4CNbWStBBRJZKJ29lIs65BsxPkIHXXCkyLPCFiFw06DZ1IPm SHWYrBqKiVQ8vlq6vT96sNOfHyoChD0iEJel314Bq2ZIiWcHaZLH/cALtbbU9NQOyef68Z4Tzu rJ9rnla16rqHJKWANN3gHog+LO73hW5ASm99BtLqjNg1OaPH13DhZhlVWUIFiL8LgyyMzsvOic cHI= X-IronPort-AV: E=Sophos;i="5.82,220,1613404800"; d="scan'208";a="268875907" IronPort-SDR: vddf2xaBfWuKbgB9+cFhOP62XaTaBF+yyBMA2If9ypbRZBKiuH3meD2ORulmBS7pIBMNrT4taR HL3d13aJobiohrFUo78GxSLwW3KURNldsLRRjCU/4UaVb6jtm4lU/AC1qd2oIsmwxYr40Z8yNB o2MlqTSSe43KqawsCGoxfsbtBrmISZJVpOzoy61VyENamiiXM5WSsqyeJbp09o3QGVxaRy4BlX BGlH9Mp29iKmOeJL98vYjJAIhw6ESvDOsTjZlTUZOhZQD76ENnELmeKO8aqvVhdubG7TqTXIJq Kq+KTK6h53CluvWcunMltSMf IronPort-SDR: lKt1/3KetQ9XzB7RgkY8bzLoLFxkQ8vedY2u5++dUNfkwHkpykZRUNiIRvSk1QLOkIQmRBnqs8 7yV0gBHgMtOtP3TQpOsAdc8EYJkxQlvY2EDXs+Q2MLrMtoUEi4rSkTWd2wdOJY4x2YUnSaRbNy RamWcYb1JB7zYqDW1KY57UqgQm0fngrzZpZZbn4F5sOeORazxuqgWk0hzgEt/x2d/CmLxRd24s vnPxq36pR0ptlM0f86Q2Z87yvEfJNydVxbED9jW1IZ4jGs3eATYchb2GwXIXNPzFWvih2PVjhC gNw= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 5/9] target/riscv: Remove the hardcoded SATP_MODE macro Date: Wed, 14 Apr 2021 09:34:02 +1000 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=730c0c5bd=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 11 ----------- target/riscv/cpu_helper.c | 24 ++++++++++++++++++------ target/riscv/csr.c | 20 ++++++++++++++++---- target/riscv/monitor.c | 22 +++++++++++++++++----- 4 files changed, 51 insertions(+), 26 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index dd643d0f63..6a816ce9c2 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -452,17 +452,6 @@ #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL =20 -#if defined(TARGET_RISCV32) -#define SATP_MODE SATP32_MODE -#define SATP_ASID SATP32_ASID -#define SATP_PPN SATP32_PPN -#endif -#if defined(TARGET_RISCV64) -#define SATP_MODE SATP64_MODE -#define SATP_ASID SATP64_ASID -#define SATP_PPN SATP64_PPN -#endif - /* VM modes (mstatus.vm) privileged ISA 1.9.1 */ #define VM_1_09_MBARE 0 #define VM_1_09_MBB 1 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b065ddb681..e5e9339458 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -403,11 +403,21 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, =20 if (first_stage =3D=3D true) { if (use_background) { - base =3D (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT; - vm =3D get_field(env->vsatp, SATP_MODE); + if (riscv_cpu_is_32bit(env)) { + base =3D (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSH= IFT; + vm =3D get_field(env->vsatp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSH= IFT; + vm =3D get_field(env->vsatp, SATP64_MODE); + } } else { - base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; - vm =3D get_field(env->satp, SATP_MODE); + if (riscv_cpu_is_32bit(env)) { + base =3D (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHI= FT; + vm =3D get_field(env->satp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHI= FT; + vm =3D get_field(env->satp, SATP64_MODE); + } } widened =3D 0; } else { @@ -622,8 +632,10 @@ static void raise_mmu_exception(CPURISCVState *env, ta= rget_ulong address, CPUState *cs =3D env_cpu(env); int page_fault_exceptions, vm; =20 - if (first_stage) { - vm =3D get_field(env->satp, SATP_MODE); + if (first_stage && riscv_cpu_is_32bit(env)) { + vm =3D get_field(env->satp, SATP32_MODE); + } else if (first_stage) { + vm =3D get_field(env->satp, SATP64_MODE); } else if (riscv_cpu_is_32bit(env)) { vm =3D get_field(env->hgatp, SATP32_MODE); } else { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6052b2d6e9..8abfe33b29 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -927,21 +927,33 @@ static int read_satp(CPURISCVState *env, int csrno, t= arget_ulong *val) =20 static int write_satp(CPURISCVState *env, int csrno, target_ulong val) { + int vm, mask, asid; + if (!riscv_feature(env, RISCV_FEATURE_MMU)) { return 0; } - if (validate_vm(env, get_field(val, SATP_MODE)) && - ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) - { + + if (riscv_cpu_is_32bit(env)) { + vm =3D validate_vm(env, get_field(val, SATP32_MODE)); + mask =3D (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_P= PN); + asid =3D (val ^ env->satp) & SATP32_ASID; + } else { + vm =3D validate_vm(env, get_field(val, SATP64_MODE)); + mask =3D (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_P= PN); + asid =3D (val ^ env->satp) & SATP64_ASID; + } + + if (vm && mask) { if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { return -RISCV_EXCP_ILLEGAL_INST; } else { - if ((val ^ env->satp) & SATP_ASID) { + if (asid) { tlb_flush(env_cpu(env)); } env->satp =3D val; } } + return 0; } =20 diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index e51188f919..f7e6ea72b3 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -150,9 +150,14 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *= env) target_ulong last_size; int last_attr; =20 - base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; + if (riscv_cpu_is_32bit(env)) { + base =3D (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; + vm =3D get_field(env->satp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; + vm =3D get_field(env->satp, SATP64_MODE); + } =20 - vm =3D get_field(env->satp, SATP_MODE); switch (vm) { case VM_1_10_SV32: levels =3D 2; @@ -215,9 +220,16 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) return; } =20 - if (!(env->satp & SATP_MODE)) { - monitor_printf(mon, "No translation or protection\n"); - return; + if (riscv_cpu_is_32bit(env)) { + if (!(env->satp & SATP32_MODE)) { + monitor_printf(mon, "No translation or protection\n"); + return; + } + } else { + if (!(env->satp & SATP64_MODE)) { + monitor_printf(mon, "No translation or protection\n"); + return; + } } =20 mem_info_svxx(mon, env); --=20 2.31.1 From nobody Sun May 19 05:00:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1618356983; cv=none; d=zohomail.com; s=zohoarc; b=XRtbeGTypjWQWxPntr08GVL2PW41wIZtRhxja6573RLDFSIdRqg0qzR1VPrRnb8gQHBmb+IL7YJBVr9dprmEidkD3/ahrQTY0/zK0qWtuSbElO3upihr6gcP+3VdGvQukMBt4wqzjED3Q6qZ56bYh3Kv5DVqIIneBXaHhT4Ytrw= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=730c0c5bd=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6a816ce9c2..9f6fbe3dc5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -416,12 +416,6 @@ #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL =20 -#if defined(TARGET_RISCV32) -#define HSTATUS_WPRI HSTATUS32_WPRI -#elif defined(TARGET_RISCV64) -#define HSTATUS_WPRI HSTATUS64_WPRI -#endif - #define HCOUNTEREN_CY (1 << 0) #define HCOUNTEREN_TM (1 << 1) #define HCOUNTEREN_IR (1 << 2) --=20 2.31.1 From nobody Sun May 19 05:00:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=730c0c5bd=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng --- target/riscv/translate.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 74636b9db7..ba8fb2cda3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -67,12 +67,6 @@ typedef struct DisasContext { CPUState *cs; } DisasContext; =20 -#ifdef TARGET_RISCV64 -#define CASE_OP_32_64(X) case X: case glue(X, W) -#else -#define CASE_OP_32_64(X) case X -#endif - static inline bool has_ext(DisasContext *ctx, uint32_t ext) { return ctx->misa & ext; --=20 2.31.1 From nobody Sun May 19 05:00:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1618357072; cv=none; d=zohomail.com; s=zohoarc; b=lCmsoeOo03RQayN9N+dmYD4+GyTVDg5e21OziLU81ejuip5xb+3hFiJ+8bgWae/5SQzWNjZaJCeq9uan5kh/cwJbkVdL7Jq6C3Ggjzbb1/TzN+ZdOZtozBxNyXxPw7Mm5f77oMbaT1DiCU4fcyeIwBncxKQHe+Dq71Iyvm0g9zc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618357072; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=730c0c5bd=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis --- target/riscv/helper.h | 2 - target/riscv/insn32-64.decode | 88 ------------------------- target/riscv/insn32.decode | 67 ++++++++++++++++++- target/riscv/translate.c | 19 +++--- target/riscv/vector_helper.c | 4 -- target/riscv/insn_trans/trans_rva.c.inc | 14 +++- target/riscv/insn_trans/trans_rvd.c.inc | 43 ++++++------ target/riscv/insn_trans/trans_rvf.c.inc | 40 +++++------ target/riscv/insn_trans/trans_rvh.c.inc | 5 +- target/riscv/insn_trans/trans_rvi.c.inc | 16 +++-- target/riscv/insn_trans/trans_rvm.c.inc | 7 +- target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++------ target/riscv/meson.build | 2 +- 13 files changed, 172 insertions(+), 174 deletions(-) delete mode 100644 target/riscv/insn32-64.decode diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e3f3f41e89..cda1811512 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -241,7 +241,6 @@ DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32) -#ifdef TARGET_RISCV64 DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoaddw_v_d, void, ptr, ptr, tl, ptr, env, i32) @@ -260,7 +259,6 @@ DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, en= v, i32) DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32) -#endif DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoaddw_v_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vamoxorw_v_w, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode deleted file mode 100644 index 8157dee8b7..0000000000 --- a/target/riscv/insn32-64.decode +++ /dev/null @@ -1,88 +0,0 @@ -# -# RISC-V translation routines for the RV Instruction Set. -# -# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de -# Bastian Koppelmann, kbastian@mail.uni-paderborn.de -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2 or later, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License along = with -# this program. If not, see . - -# This is concatenated with insn32.decode for risc64 targets. -# Most of the fields and formats are there. - -%sh5 20:5 - -@sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5 = %rs1 %rd - -# *** RV64I Base Instruction Set (in addition to RV32I) *** -lwu ............ ..... 110 ..... 0000011 @i -ld ............ ..... 011 ..... 0000011 @i -sd ....... ..... ..... 011 ..... 0100011 @s -addiw ............ ..... 000 ..... 0011011 @i -slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 -srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 -sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 -addw 0000000 ..... ..... 000 ..... 0111011 @r -subw 0100000 ..... ..... 000 ..... 0111011 @r -sllw 0000000 ..... ..... 001 ..... 0111011 @r -srlw 0000000 ..... ..... 101 ..... 0111011 @r -sraw 0100000 ..... ..... 101 ..... 0111011 @r - -# *** RV64M Standard Extension (in addition to RV32M) *** -mulw 0000001 ..... ..... 000 ..... 0111011 @r -divw 0000001 ..... ..... 100 ..... 0111011 @r -divuw 0000001 ..... ..... 101 ..... 0111011 @r -remw 0000001 ..... ..... 110 ..... 0111011 @r -remuw 0000001 ..... ..... 111 ..... 0111011 @r - -# *** RV64A Standard Extension (in addition to RV32A) *** -lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld -sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st -amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st -amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st -amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st -amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st -amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st -amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st -amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st -amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st -amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st - -#*** Vector AMO operations (in addition to Zvamo) *** -vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm - -# *** RV64F Standard Extension (in addition to RV32F) *** -fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm -fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm -fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm -fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm - -# *** RV64D Standard Extension (in addition to RV32D) *** -fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm -fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm -fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 -fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm -fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm -fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 - -# *** RV32H Base Instruction Set *** -hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 -hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 -hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 84080dd18c..fecf0f15d5 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -21,6 +21,7 @@ %rs2 20:5 %rs1 15:5 %rd 7:5 +%sh5 20:5 =20 %sh10 20:10 %csr 20:12 @@ -86,6 +87,8 @@ @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 @sfence_vm ....... ..... ..... ... ..... ....... %rs1 =20 +# Formats 64: +@sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5 = %rs1 %rd =20 # *** Privileged Instructions *** ecall 000000000000 00000 000 00000 1110011 @@ -144,6 +147,20 @@ csrrwi ............ ..... 101 ..... 1110011 @csr csrrsi ............ ..... 110 ..... 1110011 @csr csrrci ............ ..... 111 ..... 1110011 @csr =20 +# *** RV64I Base Instruction Set (in addition to RV32I) *** +lwu ............ ..... 110 ..... 0000011 @i +ld ............ ..... 011 ..... 0000011 @i +sd ....... ..... ..... 011 ..... 0100011 @s +addiw ............ ..... 000 ..... 0011011 @i +slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 +srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 +sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 +addw 0000000 ..... ..... 000 ..... 0111011 @r +subw 0100000 ..... ..... 000 ..... 0111011 @r +sllw 0000000 ..... ..... 001 ..... 0111011 @r +srlw 0000000 ..... ..... 101 ..... 0111011 @r +sraw 0100000 ..... ..... 101 ..... 0111011 @r + # *** RV32M Standard Extension *** mul 0000001 ..... ..... 000 ..... 0110011 @r mulh 0000001 ..... ..... 001 ..... 0110011 @r @@ -154,6 +171,13 @@ divu 0000001 ..... ..... 101 ..... 0110011 @r rem 0000001 ..... ..... 110 ..... 0110011 @r remu 0000001 ..... ..... 111 ..... 0110011 @r =20 +# *** RV64M Standard Extension (in addition to RV32M) *** +mulw 0000001 ..... ..... 000 ..... 0111011 @r +divw 0000001 ..... ..... 100 ..... 0111011 @r +divuw 0000001 ..... ..... 101 ..... 0111011 @r +remw 0000001 ..... ..... 110 ..... 0111011 @r +remuw 0000001 ..... ..... 111 ..... 0111011 @r + # *** RV32A Standard Extension *** lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st @@ -167,6 +191,19 @@ amomax_w 10100 . . ..... ..... 010 ..... 0101111 @at= om_st amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st =20 +# *** RV64A Standard Extension (in addition to RV32A) *** +lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld +sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st +amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st +amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st +amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st +amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st +amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st +amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st +amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st +amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st +amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st + # *** RV32F Standard Extension *** flw ............ ..... 010 ..... 0000111 @i fsw ....... ..... ..... 010 ..... 0100111 @s @@ -195,6 +232,12 @@ fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_= rm fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 =20 +# *** RV64F Standard Extension (in addition to RV32F) *** +fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm +fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm + # *** RV32D Standard Extension *** fld ............ ..... 011 ..... 0000111 @i fsd ....... ..... ..... 011 ..... 0100111 @s @@ -223,6 +266,14 @@ fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_= rm fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm =20 +# *** RV64D Standard Extension (in addition to RV32D) *** +fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm +fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm +fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 +fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm +fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm +fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 + # *** RV32H Base Instruction Set *** hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2 hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2 @@ -237,7 +288,10 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r= 2_s hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma =20 -# *** RV32V Extension *** +# *** RV32H Base Instruction Set *** +hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 +hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 +hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s =20 # *** Vector loads and stores are encoded within LOADFP/STORE-FP *** vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm @@ -592,3 +646,14 @@ vcompress_vm 010111 - ..... ..... 010 ..... 1010111= @r =20 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r + +#*** Vector AMO operations (in addition to Zvamo) *** +vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm +vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ba8fb2cda3..0ded4f9882 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -72,15 +72,13 @@ static inline bool has_ext(DisasContext *ctx, uint32_t = ext) return ctx->misa & ext; } =20 -#ifndef CONFIG_USER_ONLY -# ifdef TARGET_RISCV32 -# define is_32bit(ctx) true -# else +#ifdef TARGET_RISCV32 +# define is_32bit(ctx) true +#else static inline bool is_32bit(DisasContext *ctx) { - return !(ctx->misa & RV64); + return (ctx->misa & RV32) =3D=3D RV32; } -# endif #endif =20 /* @@ -436,6 +434,12 @@ EX_SH(12) } \ } while (0) =20 +#define REQUIRE_64BIT(ctx) do { \ + if (is_32bit(ctx)) { \ + return false; \ + } \ +} while (0) + static int ex_rvc_register(DisasContext *ctx, int reg) { return 8 + reg; @@ -483,7 +487,6 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *= a, return true; } =20 -#ifdef TARGET_RISCV64 static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) { tcg_gen_add_tl(ret, arg1, arg2); @@ -544,8 +547,6 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *= a, return true; } =20 -#endif - static bool gen_arith(DisasContext *ctx, arg_r *a, void(*func)(TCGv, TCGv, TCGv)) { diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a156573d28..a64c86b7e4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -751,7 +751,6 @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_= MIN, l) GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l) GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l) GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l) -#ifdef TARGET_RISCV64 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l) GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q) GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l) @@ -770,7 +769,6 @@ GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_= MINU, l) GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q) GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l) GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q) -#endif =20 static inline void vext_amo_noatomic(void *vs3, void *v0, target_ulong base, @@ -814,7 +812,6 @@ void HELPER(NAME)(void *vs3, void *v0, target_ulong bas= e, \ GETPC()); \ } =20 -#ifdef TARGET_RISCV64 GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq) GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq) GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq) @@ -833,7 +830,6 @@ GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, = clearq) GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq) GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq) GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq) -#endif GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl) GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl) GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index be8a9f06dd..ab2ec4f0a5 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -165,60 +165,68 @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_am= omaxu_w *a) return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_T= ESL)); } =20 -#ifdef TARGET_RISCV64 - static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a) { + REQUIRE_64BIT(ctx); return gen_lr(ctx, a, MO_ALIGN | MO_TEQ); } =20 static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a) { + REQUIRE_64BIT(ctx); return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ)); } =20 static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ)); } =20 static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TE= Q)); } =20 static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TE= Q)); } =20 static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TE= Q)); } =20 static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ= )); } =20 static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_T= EQ)); } =20 static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_T= EQ)); } =20 static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_T= EQ)); } =20 static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a) { + REQUIRE_64BIT(ctx); return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_T= EQ)); } -#endif diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 4f832637fa..39645a6134 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -358,18 +358,17 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fc= vt_d_wu *a) return true; } =20 -#ifdef TARGET_RISCV64 - static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + REQUIRE_64BIT(ctx); =20 - TCGv t0 =3D tcg_temp_new(); + TCGv_i64 t0 =3D tcg_temp_new_i64(); gen_set_rm(ctx, a->rm); gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); + gen_set_gpr(a->rd, (TCGv) t0); + tcg_temp_free_i64(t0); return true; } =20 @@ -377,12 +376,13 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fc= vt_lu_d *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + REQUIRE_64BIT(ctx); =20 - TCGv t0 =3D tcg_temp_new(); + TCGv_i64 t0 =3D tcg_temp_new_i64(); gen_set_rm(ctx, a->rm); gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); + gen_set_gpr(a->rd, (TCGv) t0); + tcg_temp_free_i64(t0); return true; } =20 @@ -390,8 +390,9 @@ static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_= d *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + REQUIRE_64BIT(ctx); =20 - gen_set_gpr(a->rd, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, (TCGv) cpu_fpr[a->rs1]); return true; } =20 @@ -399,13 +400,14 @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcv= t_d_l *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + REQUIRE_64BIT(ctx); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + gen_get_gpr((TCGv) t0, a->rs1); =20 gen_set_rm(ctx, a->rm); gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0); - tcg_temp_free(t0); + tcg_temp_free_i64(t0); mark_fs_dirty(ctx); return true; } @@ -414,13 +416,14 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fc= vt_d_lu *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + REQUIRE_64BIT(ctx); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + gen_get_gpr((TCGv) t0, a->rs1); =20 gen_set_rm(ctx, a->rm); gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0); - tcg_temp_free(t0); + tcg_temp_free_i64(t0); mark_fs_dirty(ctx); return true; } @@ -429,13 +432,13 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_= d_x *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + REQUIRE_64BIT(ctx); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + gen_get_gpr((TCGv) t0, a->rs1); =20 - tcg_gen_mov_tl(cpu_fpr[a->rd], t0); - tcg_temp_free(t0); + tcg_gen_mov_tl((TCGv) cpu_fpr[a->rd], (TCGv) t0); + tcg_temp_free_i64(t0); mark_fs_dirty(ctx); return true; } -#endif diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index 3dfec8211d..327a2b2fab 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -303,11 +303,11 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_= x_w *a) =20 TCGv t0 =3D tcg_temp_new(); =20 -#if defined(TARGET_RISCV64) - tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]); -#else - tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]); -#endif + if (!is_32bit(ctx)) { + tcg_gen_ext32s_tl((TCGv) t0, (TCGv) cpu_fpr[a->rs1]); + } else { + tcg_gen_extrl_i64_i32((TCGv_i32) t0, cpu_fpr[a->rs1]); + } =20 gen_set_gpr(a->rd, t0); tcg_temp_free(t0); @@ -415,17 +415,17 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_= w_x *a) return true; } =20 -#ifdef TARGET_RISCV64 static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + REQUIRE_64BIT(ctx); =20 - TCGv t0 =3D tcg_temp_new(); + TCGv_i64 t0 =3D tcg_temp_new_i64(); gen_set_rm(ctx, a->rm); gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); + gen_set_gpr(a->rd, (TCGv) t0); + tcg_temp_free_i64(t0); return true; } =20 @@ -433,12 +433,13 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fc= vt_lu_s *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + REQUIRE_64BIT(ctx); =20 - TCGv t0 =3D tcg_temp_new(); + TCGv_i64 t0 =3D tcg_temp_new_i64(); gen_set_rm(ctx, a->rm); gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); + gen_set_gpr(a->rd, (TCGv) t0); + tcg_temp_free_i64(t0); return true; } =20 @@ -446,15 +447,16 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcv= t_s_l *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + REQUIRE_64BIT(ctx); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + gen_get_gpr((TCGv) t0, a->rs1); =20 gen_set_rm(ctx, a->rm); gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); + tcg_temp_free_i64(t0); return true; } =20 @@ -462,15 +464,15 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fc= vt_s_lu *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + REQUIRE_64BIT(ctx); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + gen_get_gpr((TCGv) t0, a->rs1); =20 gen_set_rm(ctx, a->rm); gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); + tcg_temp_free_i64(t0); return true; } -#endif diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index ce7ed5affb..beb66be670 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -203,10 +203,10 @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w = *a) #endif } =20 -#ifdef TARGET_RISCV64 static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a) { REQUIRE_EXT(ctx, RVH); + REQUIRE_64BIT(ctx); #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -229,6 +229,7 @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu = *a) static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) { REQUIRE_EXT(ctx, RVH); + REQUIRE_64BIT(ctx); #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -251,6 +252,7 @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) { REQUIRE_EXT(ctx, RVH); + REQUIRE_64BIT(ctx); #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); @@ -269,7 +271,6 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) return false; #endif } -#endif =20 static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a) { diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index d04ca0394c..1340676209 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -204,22 +204,23 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a) return gen_store(ctx, a, MO_TESL); } =20 -#ifdef TARGET_RISCV64 static bool trans_lwu(DisasContext *ctx, arg_lwu *a) { + REQUIRE_64BIT(ctx); return gen_load(ctx, a, MO_TEUL); } =20 static bool trans_ld(DisasContext *ctx, arg_ld *a) { + REQUIRE_64BIT(ctx); return gen_load(ctx, a, MO_TEQ); } =20 static bool trans_sd(DisasContext *ctx, arg_sd *a) { + REQUIRE_64BIT(ctx); return gen_store(ctx, a, MO_TEQ); } -#endif =20 static bool trans_addi(DisasContext *ctx, arg_addi *a) { @@ -361,14 +362,15 @@ static bool trans_and(DisasContext *ctx, arg_and *a) return gen_arith(ctx, a, &tcg_gen_and_tl); } =20 -#ifdef TARGET_RISCV64 static bool trans_addiw(DisasContext *ctx, arg_addiw *a) { + REQUIRE_64BIT(ctx); return gen_arith_imm_tl(ctx, a, &gen_addw); } =20 static bool trans_slliw(DisasContext *ctx, arg_slliw *a) { + REQUIRE_64BIT(ctx); TCGv source1; source1 =3D tcg_temp_new(); gen_get_gpr(source1, a->rs1); @@ -383,6 +385,7 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a) =20 static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { + REQUIRE_64BIT(ctx); TCGv t =3D tcg_temp_new(); gen_get_gpr(t, a->rs1); tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt); @@ -395,6 +398,7 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a) =20 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { + REQUIRE_64BIT(ctx); TCGv t =3D tcg_temp_new(); gen_get_gpr(t, a->rs1); tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt); @@ -405,16 +409,19 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw = *a) =20 static bool trans_addw(DisasContext *ctx, arg_addw *a) { + REQUIRE_64BIT(ctx); return gen_arith(ctx, a, &gen_addw); } =20 static bool trans_subw(DisasContext *ctx, arg_subw *a) { + REQUIRE_64BIT(ctx); return gen_arith(ctx, a, &gen_subw); } =20 static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { + REQUIRE_64BIT(ctx); TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 @@ -433,6 +440,7 @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a) =20 static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { + REQUIRE_64BIT(ctx); TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 @@ -453,6 +461,7 @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a) =20 static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { + REQUIRE_64BIT(ctx); TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 @@ -473,7 +482,6 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a) =20 return true; } -#endif =20 static bool trans_fence(DisasContext *ctx, arg_fence *a) { diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_tr= ans/trans_rvm.c.inc index 47cd6edc72..7f541e35ca 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -87,34 +87,37 @@ static bool trans_remu(DisasContext *ctx, arg_remu *a) return gen_arith(ctx, a, &gen_remu); } =20 -#ifdef TARGET_RISCV64 static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { REQUIRE_EXT(ctx, RVM); + REQUIRE_64BIT(ctx); return gen_arith(ctx, a, &gen_mulw); } =20 static bool trans_divw(DisasContext *ctx, arg_divw *a) { REQUIRE_EXT(ctx, RVM); + REQUIRE_64BIT(ctx); return gen_arith_div_w(ctx, a, &gen_div); } =20 static bool trans_divuw(DisasContext *ctx, arg_divuw *a) { REQUIRE_EXT(ctx, RVM); + REQUIRE_64BIT(ctx); return gen_arith_div_uw(ctx, a, &gen_divu); } =20 static bool trans_remw(DisasContext *ctx, arg_remw *a) { REQUIRE_EXT(ctx, RVM); + REQUIRE_64BIT(ctx); return gen_arith_div_w(ctx, a, &gen_rem); } =20 static bool trans_remuw(DisasContext *ctx, arg_remuw *a) { REQUIRE_EXT(ctx, RVM); + REQUIRE_64BIT(ctx); return gen_arith_div_uw(ctx, a, &gen_remu); } -#endif diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 887c6b8883..47914a3b69 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -705,7 +705,6 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8= _t seq) gen_helper_vamominuw_v_w, gen_helper_vamomaxuw_v_w }; -#ifdef TARGET_RISCV64 static gen_helper_amo *const fnsd[18] =3D { gen_helper_vamoswapw_v_d, gen_helper_vamoaddw_v_d, @@ -726,7 +725,6 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8= _t seq) gen_helper_vamominud_v_d, gen_helper_vamomaxud_v_d }; -#endif =20 if (tb_cflags(s->base.tb) & CF_PARALLEL) { gen_helper_exit_atomic(cpu_env); @@ -734,12 +732,12 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uin= t8_t seq) return true; } else { if (s->sew =3D=3D 3) { -#ifdef TARGET_RISCV64 - fn =3D fnsd[seq]; -#else - /* Check done in amo_check(). */ - g_assert_not_reached(); -#endif + if (!is_32bit(s)) { + fn =3D fnsd[seq]; + } else { + /* Check done in amo_check(). */ + g_assert_not_reached(); + } } else { assert(seq < ARRAY_SIZE(fnsw)); fn =3D fnsw[seq]; @@ -769,6 +767,11 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a) ((1 << s->sew) >=3D 4)); } =20 +static bool amo_check64(DisasContext *s, arg_rwdvm* a) +{ + return !is_32bit(s) && amo_check(s, a); +} + GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check) GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check) GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check) @@ -778,17 +781,15 @@ GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_chec= k) GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check) GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check) GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check) -#ifdef TARGET_RISCV64 -GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check) -#endif +GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check64) +GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check64) =20 /* *** Vector Integer Arithmetic Instructions diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 88ab850682..24bf049164 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -7,7 +7,7 @@ gen32 =3D [ =20 gen64 =3D [ decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode= ', '--static-decode=3Ddecode_insn16', '--insnwidth=3D16']), - decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode= ', '--static-decode=3Ddecode_insn32']), + decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), ] =20 riscv_ss =3D ss.source_set() --=20 2.31.1 From nobody Sun May 19 05:00:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1618357285; cv=none; d=zohomail.com; s=zohoarc; b=dsTfzoZPubCFBOzhv5At2EnPGE3ym6cgotI8Fuz/3v8B1FxRPs1Xw+TywLlVyOCM0T6g83bSfCe1X3A2Qjk83bfkafM9CUiv5PafUWV5nt5IZ1M+vykWjlzeERUaFqBYSCSOtcQk6Hk3qZe4tJmURV5O/YNjhIyX1migIRCpAqg= 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alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This patch removes the insn16-32.decode and insn16-64.decode decode files and consolidates the instructions into the general RISC-V insn16.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn16-32.decode | 28 ------------------- target/riscv/insn16-64.decode | 36 ------------------------- target/riscv/insn16.decode | 30 +++++++++++++++++++++ target/riscv/insn_trans/trans_rvi.c.inc | 6 +++++ target/riscv/meson.build | 11 +++----- 5 files changed, 39 insertions(+), 72 deletions(-) delete mode 100644 target/riscv/insn16-32.decode delete mode 100644 target/riscv/insn16-64.decode diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode deleted file mode 100644 index 0819b17028..0000000000 --- a/target/riscv/insn16-32.decode +++ /dev/null @@ -1,28 +0,0 @@ -# -# RISC-V translation routines for the RVXI Base Integer Instruction Set. -# -# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de -# Bastian Koppelmann, kbastian@mail.uni-paderborn.de -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2 or later, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License along = with -# this program. If not, see . - -# *** RV32C Standard Extension (Quadrant 0) *** -flw 011 ... ... .. ... 00 @cl_w -fsw 111 ... ... .. ... 00 @cs_w - -# *** RV32C Standard Extension (Quadrant 1) *** -jal 001 ........... 01 @cj rd=3D1 # C.JAL - -# *** RV32C Standard Extension (Quadrant 2) *** -flw 011 . ..... ..... 10 @c_lwsp -fsw 111 . ..... ..... 10 @c_swsp diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode deleted file mode 100644 index 672e1e916f..0000000000 --- a/target/riscv/insn16-64.decode +++ /dev/null @@ -1,36 +0,0 @@ -# -# RISC-V translation routines for the RVXI Base Integer Instruction Set. -# -# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de -# Bastian Koppelmann, kbastian@mail.uni-paderborn.de -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2 or later, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License along = with -# this program. If not, see . - -# *** RV64C Standard Extension (Quadrant 0) *** -ld 011 ... ... .. ... 00 @cl_d -sd 111 ... ... .. ... 00 @cs_d - -# *** RV64C Standard Extension (Quadrant 1) *** -{ - illegal 001 - 00000 ----- 01 # c.addiw, RES rd=3D0 - addiw 001 . ..... ..... 01 @ci -} -subw 100 1 11 ... 00 ... 01 @cs_2 -addw 100 1 11 ... 01 ... 01 @cs_2 - -# *** RV64C Standard Extension (Quadrant 2) *** -{ - illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=3D0 - ld 011 . ..... ..... 10 @c_ldsp -} -sd 111 . ..... ..... 10 @c_sdsp diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 1cb93876fe..2e9212663c 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -92,6 +92,16 @@ lw 010 ... ... .. ... 00 @cl_w fsd 101 ... ... .. ... 00 @cs_d sw 110 ... ... .. ... 00 @cs_w =20 +# *** RV32C and RV64C specific Standard Extension (Quadrant 0) *** +{ + ld 011 ... ... .. ... 00 @cl_d + flw 011 ... ... .. ... 00 @cl_w +} +{ + sd 111 ... ... .. ... 00 @cs_d + fsw 111 ... ... .. ... 00 @cs_w +} + # *** RV32/64C Standard Extension (Quadrant 1) *** addi 000 . ..... ..... 01 @ci addi 010 . ..... ..... 01 @c_li @@ -111,6 +121,15 @@ jal 101 ........... 01 @cj rd=3D0= # C.J beq 110 ... ... ..... 01 @cb_z bne 111 ... ... ..... 01 @cb_z =20 +# *** RV64C and RV32C specific Standard Extension (Quadrant 1) *** +{ + c64_illegal 001 - 00000 ----- 01 # c.addiw, RES rd=3D0 + addiw 001 . ..... ..... 01 @ci + jal 001 ........... 01 @cj rd=3D1 # C.JAL +} +subw 100 1 11 ... 00 ... 01 @cs_2 +addw 100 1 11 ... 01 ... 01 @cs_2 + # *** RV32/64C Standard Extension (Quadrant 2) *** slli 000 . ..... ..... 10 @c_shift2 fld 001 . ..... ..... 10 @c_ldsp @@ -130,3 +149,14 @@ fld 001 . ..... ..... 10 @c_ldsp } fsd 101 ...... ..... 10 @c_sdsp sw 110 . ..... ..... 10 @c_swsp + +# *** RV32C and RV64C specific Standard Extension (Quadrant 2) *** +{ + c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=3D0 + ld 011 . ..... ..... 10 @c_ldsp + flw 011 . ..... ..... 10 @c_lwsp +} +{ + sd 111 . ..... ..... 10 @c_sdsp + fsw 111 . ..... ..... 10 @c_swsp +} diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 1340676209..bd93f634cf 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -24,6 +24,12 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *= a) return true; } =20 +static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a) +{ + REQUIRE_64BIT(ctx); + return trans_illegal(ctx, a); +} + static bool trans_lui(DisasContext *ctx, arg_lui *a) { if (a->rd !=3D 0) { diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 24bf049164..af6c3416b7 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -1,18 +1,13 @@ # FIXME extra_args should accept files() dir =3D meson.current_source_dir() -gen32 =3D [ - decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode= ', '--static-decode=3Ddecode_insn16', '--insnwidth=3D16']), - decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), -] =20 -gen64 =3D [ - decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode= ', '--static-decode=3Ddecode_insn16', '--insnwidth=3D16']), +gen =3D [ + decodetree.process('insn16.decode', extra_args: ['--static-decode=3Ddeco= de_insn16', '--insnwidth=3D16']), decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), ] =20 riscv_ss =3D ss.source_set() -riscv_ss.add(when: 'TARGET_RISCV32', if_true: gen32) -riscv_ss.add(when: 'TARGET_RISCV64', if_true: gen64) +riscv_ss.add(gen) riscv_ss.add(files( 'cpu.c', 'cpu_helper.c', --=20 2.31.1