From nobody Tue May 21 00:42:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612426138; cv=none; d=zohomail.com; s=zohoarc; b=OkK6cLAop4YgecI1PrbX7lJqqjNU8Dh3akBD3wfVni1Fpmj/ICnyoIQ2Ru7Zw0ftOScsCXLl3mDMIjqQIqIAECjhn4e6ONMx++3ST73TtmwbDopipXQeNydUqI9Aq4rIXPRgi8qVtLUxNS4JirRb2pldUAawS/DmHob311FVa3c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612426138; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=kx+Swya/jsv/GqzfkA9OtLeh+jrxbm/uWyD2RnGaSH4=; b=aQeB5IwokQYZ5sTb8W+gjxiEHkwu9ZQOxzOXQOTUeNLWJRnIpZoBAIJpbRAGvcqjqbdUIXxmEihAbu90rTYeJCZfgcyCddlFl2V4aTpCBBN5C8nUMjgfS+/fY6B2Fnt64Z5RwXizQAOs4tOQ4hxkf0A8bVUCiWgst3KPPJ4XViE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612426138169290.97567167251316; Thu, 4 Feb 2021 00:08:58 -0800 (PST) Received: from localhost ([::1]:34658 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7Zh8-0003K1-74 for importer@patchew.org; Thu, 04 Feb 2021 03:08:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54492) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7ZeL-0008U9-4m for qemu-devel@nongnu.org; Thu, 04 Feb 2021 03:06:01 -0500 Received: from mga05.intel.com ([192.55.52.43]:43412) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7ZeJ-0007VQ-HA for qemu-devel@nongnu.org; Thu, 04 Feb 2021 03:06:00 -0500 Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:05:44 -0800 Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:05:44 -0800 IronPort-SDR: R3hOf81Evuy+5lOXbQb7G283VY/iwUX6VM+jAOe7KcVTrb2rDCaD3B74mJYt7YAr7mXloPyW7x KCoDNpSKlSZw== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="266025480" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="266025480" IronPort-SDR: m8luV541/tpxDU7tugHta+7izQwwO59gFpK8+8LdHBhbIhWadEVdAGcrZ9l6ksBUrroi0N0TDE sdW5J618yFuQ== X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="372302429" From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, imammedo@redhat.com, mst@redhat.com, marcel.apfelbaum@gmail.com Subject: [PATCH 1/4] acpi/core: always set SCI_EN when SMM isn't supported Date: Thu, 4 Feb 2021 00:04:08 -0800 Message-Id: <644e597907e95c0366502e7124b28c577f896e5c.1612424814.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.43; envelope-from=isaku.yamahata@intel.com; helo=mga05.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Isaku Yamahata Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Isaku Yamahata If SMM is not supported, ACPI fixed hardware doesn't support legacy-mode. ACPI-only platform. Where SCI_EN in PM1_CNT register is always set. The bit tells OS legacy mode(SCI_EN cleared) or ACPI mode(SCI_EN set). ACPI spec 4.8.10.1 PM1 Event Grouping PM1 Eanble Registers > For ACPI-only platforms (where SCI_EN is always set) Signed-off-by: Isaku Yamahata --- hw/acpi/core.c | 11 ++++++++++- hw/acpi/ich9.c | 2 +- hw/acpi/piix4.c | 3 ++- hw/isa/vt82c686.c | 2 +- include/hw/acpi/acpi.h | 4 +++- 5 files changed, 17 insertions(+), 5 deletions(-) diff --git a/hw/acpi/core.c b/hw/acpi/core.c index 7170bff657..1e004d0078 100644 --- a/hw/acpi/core.c +++ b/hw/acpi/core.c @@ -579,6 +579,10 @@ void acpi_pm1_cnt_update(ACPIREGS *ar, bool sci_enable, bool sci_disable) { /* ACPI specs 3.0, 4.7.2.5 */ + if (ar->pm1.cnt.acpi_only) { + return; + } + if (sci_enable) { ar->pm1.cnt.cnt |=3D ACPI_BITMASK_SCI_ENABLE; } else if (sci_disable) { @@ -608,11 +612,13 @@ static const MemoryRegionOps acpi_pm_cnt_ops =3D { }; =20 void acpi_pm1_cnt_init(ACPIREGS *ar, MemoryRegion *parent, - bool disable_s3, bool disable_s4, uint8_t s4_val) + bool disable_s3, bool disable_s4, uint8_t s4_val, + bool acpi_only) { FWCfgState *fw_cfg; =20 ar->pm1.cnt.s4_val =3D s4_val; + ar->pm1.cnt.acpi_only =3D acpi_only; ar->wakeup.notify =3D acpi_notify_wakeup; qemu_register_wakeup_notifier(&ar->wakeup); =20 @@ -638,6 +644,9 @@ void acpi_pm1_cnt_init(ACPIREGS *ar, MemoryRegion *pare= nt, void acpi_pm1_cnt_reset(ACPIREGS *ar) { ar->pm1.cnt.cnt =3D 0; + if (ar->pm1.cnt.acpi_only) { + ar->pm1.cnt.cnt |=3D ACPI_BITMASK_SCI_ENABLE; + } } =20 /* ACPI GPE */ diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 5ff4e01c36..1a34d7f621 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -282,7 +282,7 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, pm->disable_s3, pm->disable= _s4, - pm->s4_val); + pm->s4_val, !smm_enabled); =20 acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN); memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm, diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 669be5bbf6..0cddf91de5 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -496,7 +496,8 @@ static void piix4_pm_realize(PCIDevice *dev, Error **er= rp) =20 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); - acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_= val); + acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_= val, + !s->smm_enabled); acpi_gpe_init(&s->ar, GPE_LEN); =20 s->powerdown_notifier.notify =3D piix4_pm_powerdown_req; diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index a6f5a0843d..071b64b497 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -240,7 +240,7 @@ static void vt82c686b_pm_realize(PCIDevice *dev, Error = **errp) =20 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); - acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2); + acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2, false); } =20 static Property via_pm_properties[] =3D { diff --git a/include/hw/acpi/acpi.h b/include/hw/acpi/acpi.h index 22b0b65bb2..9e8a76f2e2 100644 --- a/include/hw/acpi/acpi.h +++ b/include/hw/acpi/acpi.h @@ -128,6 +128,7 @@ struct ACPIPM1CNT { MemoryRegion io; uint16_t cnt; uint8_t s4_val; + bool acpi_only; }; =20 struct ACPIGPE { @@ -163,7 +164,8 @@ void acpi_pm1_evt_init(ACPIREGS *ar, acpi_update_sci_fn= update_sci, =20 /* PM1a_CNT: piix and ich9 don't implement PM1b CNT. */ void acpi_pm1_cnt_init(ACPIREGS *ar, MemoryRegion *parent, - bool disable_s3, bool disable_s4, uint8_t s4_val); + bool disable_s3, bool disable_s4, uint8_t s4_val, + bool acpi_only); void acpi_pm1_cnt_update(ACPIREGS *ar, bool sci_enable, bool sci_disable); void acpi_pm1_cnt_reset(ACPIREGS *ar); --=20 2.17.1 From nobody Tue May 21 00:42:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612426070; cv=none; d=zohomail.com; s=zohoarc; b=lbe9nzg477amz4I/GsBfH+h2YR48/5Lexg5NOmGQeqB9WRTkgAT68glBtPdVIuftqTHoGCzl+Wx8vtrrmdNAfxz6gGW917J6Wtie9am4O/j4y9CWgoCBNQMGG26RowzZNxcQVymrQoycmqQNyERhX9jc80jdUC+n8iNGxHiBakQ= ARC-Message-Signature: i=1; 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Thu, 04 Feb 2021 03:07:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54518) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7ZeN-0008W9-C5 for qemu-devel@nongnu.org; Thu, 04 Feb 2021 03:06:03 -0500 Received: from mga05.intel.com ([192.55.52.43]:43425) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7ZeL-0007bn-PO for qemu-devel@nongnu.org; Thu, 04 Feb 2021 03:06:03 -0500 Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:05:44 -0800 Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:05:44 -0800 IronPort-SDR: Y2Ut96peg5QAvLUbiKWfX5bQF9uNsjO8DoQtQj4MUqcIQmCLAI6HFv0QKtQlGyVlSC83mtk6+9 DTtNAhnfV1xw== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="266025484" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="266025484" IronPort-SDR: jAkbOG2Wf/OeSJZ8WTmuyBQsw2RS1VpZN4SEhEkulb3Mh2M0Qn/RKApptl35KeKIiLBcvh/yLt kH1MZwaLIvmg== X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="372302433" From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, imammedo@redhat.com, mst@redhat.com, marcel.apfelbaum@gmail.com Subject: [PATCH 2/4] acpi: set fadt.smi_cmd to zero when SMM is not supported Date: Thu, 4 Feb 2021 00:04:09 -0800 Message-Id: <194cd393260d2692fac98cc24cfd67e6cc98582b.1612424814.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.43; envelope-from=isaku.yamahata@intel.com; helo=mga05.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Isaku Yamahata Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Isaku Yamahata From table 5.9 SMI_CMD of ACPI spec > This field is reserved and must be zero on system > that does not support System Management mode. So when smm is not enabled, set it to zero to comform to the spec. Signed-off-by: Isaku Yamahata --- hw/i386/acpi-build.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index f56d699c7f..005bcc2886 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -139,6 +139,8 @@ const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = =3D { static void init_common_fadt_data(MachineState *ms, Object *o, AcpiFadtData *data) { + X86MachineState *x86ms =3D X86_MACHINE(ms); + bool smm_enabled =3D x86_machine_is_smm_enabled(x86ms); uint32_t io =3D object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, N= ULL); AmlAddressSpace as =3D AML_AS_SYSTEM_IO; AcpiFadtData fadt =3D { @@ -159,12 +161,12 @@ static void init_common_fadt_data(MachineState *ms, O= bject *o, .rtc_century =3D RTC_CENTURY, .plvl2_lat =3D 0xfff /* C2 state not supported */, .plvl3_lat =3D 0xfff /* C3 state not supported */, - .smi_cmd =3D ACPI_PORT_SMI_CMD, + .smi_cmd =3D smm_enabled ? ACPI_PORT_SMI_CMD : 0, .sci_int =3D object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NUL= L), .acpi_enable_cmd =3D - object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL= ), + smm_enabled ? object_property_get_uint(o, ACPI_PM_PROP_ACPI_EN= ABLE_CMD, NULL) : 0, .acpi_disable_cmd =3D - object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NUL= L), + smm_enabled ? object_property_get_uint(o, ACPI_PM_PROP_ACPI_DI= SABLE_CMD, NULL) : 0, .pm1a_evt =3D { .space_id =3D as, .bit_width =3D 4 * 8, .address = =3D io }, .pm1a_cnt =3D { .space_id =3D as, .bit_width =3D 2 * 8, .address =3D io + 0x04 }, --=20 2.17.1 From nobody Tue May 21 00:42:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612426074; cv=none; d=zohomail.com; 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a="266025486" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="266025486" IronPort-SDR: hNxORws1avm9T/7bsPJBVsp80ZyqY8GN1bwNRTYriO1hqnnnZzwDTwwsBHnr5qPjI05ST2qcY6 AfbpF+TGXofQ== X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="372302438" From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, imammedo@redhat.com, mst@redhat.com, marcel.apfelbaum@gmail.com Subject: [PATCH 3/4] hw/i386: declare ACPI mother board resource for MMCONFIG region Date: Thu, 4 Feb 2021 00:04:10 -0800 Message-Id: <052f8372cd04dcab1940c2fbf530d06fd8c85cc4.1612424814.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.43; envelope-from=isaku.yamahata@intel.com; helo=mga05.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Isaku Yamahata Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Isaku Yamahata Declare PNP0C01 device to reserve MMCONFIG region to conform to the spec better and play nice with guest BIOSes/OSes. According to PCI Firmware Specification, MMCONFIG region must be reserved by declaring a motherboard resource. It's optional to reserve the region in memory map by Int 15 E820h or EFIGetMemoryMap. If guest BIOS doesn't reserve the region in memory map without the reservation by mother board resource, guest linux abandons to use MMCFG. TDVF [0] [1] doesn't reserve MMCONFIG the region in memory map. On the other hand OVMF reserves it in memory map without declaring a motherboard resource. With memory map reservation, linux guest uses MMCONFIG region. However it doesn't comply to PCI Firmware specification. [0] TDX: Intel Trust Domain Extension https://software.intel.com/content/www/us/en/develop/articles/intel-tru= st-domain-extensions.html [1] TDX Virtual Firmware https://github.com/tianocore/edk2-staging/tree/TDVF Signed-off-by: Isaku Yamahata Acked-by: Jiewen Yao --- hw/i386/acpi-build.c | 172 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 172 insertions(+) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 005bcc2886..6e38f67120 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1062,6 +1062,177 @@ static void build_q35_pci0_int(Aml *table) aml_append(table, sb_scope); } =20 +static Aml *build_q35_dram_controller(void) +{ + /* + * DSDT is created with revision 1 which means 32bit integer. + * When the method of _CRS is called to determine MMCONFIG region, + * only port io is allowed to access PCI configuration space. + * It means qword access isn't allowed. + * + * Device(DRAC) + * { + * Name(_HID, EisaId("PNP0C01")) + * OperationRegion(DRR0, PCI_Config, 0x0000000000000060, 0x8) + * Field(DRR0, DWordAcc, Lock, Preserve) + * { + * PEBL, 4, + * PEBH, 4 + * } + * Name(RBUF, ResourceTemplate() + * { + * QWordMemory(ResourceConsumer, + * PosDecode, + * MinFixed, + * MaxFixed, + * NonCacheable, + * ReadWrite, + * 0x0000000000000000, // Granularity + * 0x0000000000000000, // Range Minimum + * 0x0000000000000000, // Range Maxium + * 0x0000000000000000, // Translation Offset, + * 0x0000000000000000, // Length, + * ,, + * _MCF, + * AddressRangeMemory, + * TypeStatic + * ) + * }) + * Method(_CRS, 0x0, NotSerialized) + * { + * CreateDWordField(RBUF, DRAC._MCF._MIN, MINL) + * CreateDWordField(RBUF, DRAC._MCF._MIN + 4, MINH) + * CreateDWordField(RBUF, DRAC._MCF._MAX, MAXL) + * CreateDWordField(RBUF, DRAC._MCF._MAX + 4, MAXH) + * CreateQWordField(RBUF, DRAC._MCF._LEN, _LEN) + * + * Local0 =3D PEBL + * Local1 =3D Local0 & 0x1 // PCIEXBAR PCIEBAREN + * Local2 =3D Local0 & 0x6 // PCIEXBAR LENGTH + * Local3 =3D Local0 & ~0x7 // PCIEXBAR base address low 32bit + * Local4 =3D PEBH // PCIEXBAR base address high 32bit + * If (Local1 =3D=3D 1) { + * MINL =3D Local3 + * MINH =3D Local4 + * MAXL =3D Local3 + * MAXH =3D Local4 + * + * If (Local2 =3D=3D 0) { + * _LEN =3D 256 * 1024 * 1024 + * } + * If (Local2 =3D=3D 0x2) { + * _LEN =3D 128 * 1024 * 1024 + * } + * If (Local2 =3D=3D 0x4) { + * _LEN =3D 64 * 1024 * 1024 + * } + * } + * return (RBUF) + * } + * } + */ + + Aml *dev; + Aml *field; + Aml *rbuf; + Aml *resource_template; + Aml *crs; + + /* DRAM controller */ + dev =3D aml_device("DRAC"); + + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); + /* 5.1.6 PCIEXBAR: Bus 0:Device 0:Function 0:offset 0x60 */ + aml_append(dev, aml_operation_region("DRR0", AML_PCI_CONFIG, + aml_int(0x0000000000000060), 0x8)= ); + field =3D aml_field("DRR0", AML_DWORD_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("PEBL", 32)); + aml_append(field, aml_named_field("PEBH", 32)); + aml_append(dev, field); + + resource_template =3D aml_resource_template(); + aml_append(resource_template, aml_qword_memory(AML_POS_DECODE, + AML_MIN_FIXED, + AML_MAX_FIXED, + AML_NON_CACHEABLE, + AML_READ_WRITE, + 0x0000000000000000, + 0x0000000000000000, + 0x0000000000000000, + 0x0000000000000000, + 0x0000000000000000)); + rbuf =3D aml_name_decl("RBUF", resource_template); + aml_append(dev, rbuf); + + crs =3D aml_method("_CRS", 0, AML_SERIALIZED); + { + Aml *rbuf_name; + Aml *local0; + Aml *local1; + Aml *local2; + Aml *local3; + Aml *local4; + Aml *ifc; + + rbuf_name =3D aml_name("RBUF"); + aml_append(crs, aml_create_dword_field(rbuf_name, + aml_int(14), "MINL")); + aml_append(crs, aml_create_dword_field(rbuf_name, + aml_int(14 + 4), "MINH")); + aml_append(crs, aml_create_dword_field(rbuf_name, + aml_int(22), "MAXL")); + aml_append(crs, aml_create_dword_field(rbuf_name, + aml_int(22 + 4), "MAXH")); + aml_append(crs, aml_create_qword_field(rbuf_name, + aml_int(38), "_LEN")); + + local0 =3D aml_local(0); + aml_append(crs, aml_store(aml_name("PEBL"), local0)); + local1 =3D aml_local(1); + aml_append(crs, aml_and(local0, aml_int(0x1), local1)); + local2 =3D aml_local(2); + aml_append(crs, aml_and(local0, aml_int(0x6), local2)); + local3 =3D aml_local(3); + aml_append(crs, aml_and(local0, aml_int((uint32_t)~0x7), local3)); + local4 =3D aml_local(4); + aml_append(crs, aml_store(aml_name("PEBH"), local4)); + + ifc =3D aml_if(aml_equal(local1, aml_int(0x1))); + { + Aml *_len; + Aml *ifc0; + Aml *ifc2; + Aml *ifc4; + + aml_append(ifc, aml_store(local3, aml_name("MINL"))); + aml_append(ifc, aml_store(local4, aml_name("MINH"))); + aml_append(ifc, aml_store(local3, aml_name("MAXL"))); + aml_append(ifc, aml_store(local4, aml_name("MAXH"))); + + _len =3D aml_name("_LEN"); + ifc0 =3D aml_if(aml_equal(local2, aml_int(0x0))); + aml_append(ifc0, + aml_store(aml_int(256 * 1024 * 1024), _len)); + aml_append(ifc, ifc0); + + ifc2 =3D aml_if(aml_equal(local2, aml_int(0x2))); + aml_append(ifc2, + aml_store(aml_int(128 * 1024 * 1024), _len)); + aml_append(ifc, ifc2); + + ifc4 =3D aml_if(aml_equal(local2, aml_int(0x4))); + aml_append(ifc4, + aml_store(aml_int(64 * 1024 * 1024), _len)); + aml_append(ifc, ifc4); + } + aml_append(crs, ifc); + aml_append(crs, aml_return(rbuf_name)); + } + aml_append(dev, crs); + + return dev; +} + static void build_q35_isa_bridge(Aml *table) { Aml *dev; @@ -1246,6 +1417,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dev, aml_name_decl("_UID", aml_int(0))); aml_append(dev, build_q35_osc_method()); aml_append(sb_scope, dev); + aml_append(sb_scope, build_q35_dram_controller()); =20 if (pm->smi_on_cpuhp) { /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ --=20 2.17.1 From nobody Tue May 21 00:42:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612426257; cv=none; d=zohomail.com; s=zohoarc; b=L28aLxmgASsOKzfWIiaIoSjjGUtKFA9Ygo7OvDUvm6E9aZ7KB11vZytcaxJme1K+jPcJZamyVzuQcId8Wcx8kKpKnpeHMA9k0PzXhpWcsfa9sq3nOkxP5UUbHKCfYUNKJ/rfU2uuxEUwoRCx5bjZ+7e1ZofoexwgP4VDFJFurLE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612426257; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; 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Thu, 04 Feb 2021 03:06:04 -0500 Received: from mga05.intel.com ([192.55.52.43]:43427) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7ZeM-0007ds-IM for qemu-devel@nongnu.org; Thu, 04 Feb 2021 03:06:04 -0500 Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:05:45 -0800 Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:05:45 -0800 IronPort-SDR: feX8yt0esTLxlpydBvze27UXDvi1oEvfC6H/9/nzsCWpjUvc70mmSeXM51tku1aWW1IEd91Mc0 ew4gj3u4KOFQ== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="266025487" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="266025487" IronPort-SDR: XlJJZeXo220pxYhtCsOhzdY32/VgQnE5Lse3RUuRRD8/wWgF1URv2G7IVaVyFfmmyc4uetwG5c p0OGwF9B33cQ== X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="372302442" From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, imammedo@redhat.com, mst@redhat.com, marcel.apfelbaum@gmail.com Subject: [PATCH 4/4] i386: acpi: Don't build HPET ACPI entry if HPET is disabled Date: Thu, 4 Feb 2021 00:04:11 -0800 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.43; envelope-from=isaku.yamahata@intel.com; helo=mga05.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sean Christopherson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Sean Christopherson Omit HPET AML if the HPET is disabled, QEMU is not emulating it and the guest may get confused by seeing HPET in the ACPI tables without a "physical" device present. Signed-off-by: Sean Christopherson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/acpi-build.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 6e38f67120..a4fcd14a93 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1401,7 +1401,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(sb_scope, dev); aml_append(dsdt, sb_scope); =20 - build_hpet_aml(dsdt); + if (misc->has_hpet) { + build_hpet_aml(dsdt); + } build_piix4_isa_bridge(dsdt); build_isa_devices_aml(dsdt); if (pm->pcihp_bridge_en || pm->pcihp_root_en) { @@ -1446,7 +1448,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, =20 aml_append(dsdt, sb_scope); =20 - build_hpet_aml(dsdt); + if (misc->has_hpet) { + build_hpet_aml(dsdt); + } build_q35_isa_bridge(dsdt); build_isa_devices_aml(dsdt); build_q35_pci0_int(dsdt); --=20 2.17.1