From nobody Sat May 18 04:30:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1604466735; cv=none; d=zohomail.com; s=zohoarc; b=nRvirxh0w+wT0An8HEbqAPUoRXYozxy/YaVTh8iPFoqR9Gr97OjO6sLZ/XnTlZs21xKu44op1nO1FWihFG2Zv5qpDMx2mIURVHbUsrhReXffdsMp4R89e6r+If8B4kDJI1XYOSfXeNH9HamtIVIJ2E59tkmgxToIczYmCMPjZVw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604466735; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=C8CblMTRJ34mRplplKfb6lCKFiEcxR78MpESnHnc2n0=; b=aqJjtjEXJFlXzFy9qHvzOcVMf2JafEVA4Li9P3nZvX4KJGKB1+lllvIZsnGc+/EypznRATAZST0y7eOxxoeSUOZjRc+4+f50KEMYd4D3D7H98dCi61+XS8OSkjZhSbSAebUUq3TAwL3s6k3Oo1pUSd4KrAaWCqU11NkULy04YJ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604466735826908.7996391681373; Tue, 3 Nov 2020 21:12:15 -0800 (PST) Received: from localhost ([::1]:51030 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kaB5i-0002pW-Rf for importer@patchew.org; Wed, 04 Nov 2020 00:12:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60130) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kaAp3-000430-0D; Tue, 03 Nov 2020 23:55:01 -0500 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:17614) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kaAoy-0005iz-2B; Tue, 03 Nov 2020 23:55:00 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 04 Nov 2020 12:54:54 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2020 20:41:02 -0800 Received: from usa003000.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.60.113]) by uls-op-cesaip01.wdc.com with ESMTP; 03 Nov 2020 20:54:54 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604465695; x=1636001695; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RisuKMhLqPB7mhA2jscmhvu/EDaATgNa1/SbhqIyQWg=; b=XWI60Lc15rHzeVQAYnZyiBIyHBRCYo/xYJ6RE84fARXHg1ya4SP20uXD WHc9BbJwaGdLQYsbGwq3cyxgmcr+T3bEZ+yqayrShlhtuWF94TQOGeCh7 iwng3CxCpDX0YmE/dUSkFNbOCyGSBvFJo2IUQvQd4iO1NYe6+4j6jp2dL uZI6GldkwGpGX7vqTuFiWJ3qjeJZ38bzM1KVxrUy0iZo5xnXEP8p/1UoP lePsDznYCARHPh9wc2YxctCU8vuWtrMkCnuUixIYT8/TtXI6pAnqZTcxN 69z0Ar2lWPYKaci8HdNv3bw38VmUn/Y+TrWbobZCHiqsUY6GZccx9yUz/ g==; IronPort-SDR: VUyVQOYT2vuzoZFqM1BNbFS0XMyhSgxsArTvgvKc/hCtHGAjVA9KkSXRrXVt1ERXe6N92oVoUn k+cxl5l7Xk+KY88yp0TMQ1ob+bKxvaiYQmP0HNumg8LRYwsMAuQP4Qd+JCXojNWwCxbULSUd9s ONDUBrLp2ej83tvZ7E6foWjeoCm8mQranPAK5XuTf56z8bRA4LY3sY1n2OiYFBJ42JNKnbEobM HZQm+nYLn+qZEBdbWxt/hQWQOKv7y9jq2l97StNtgc64/6hPuKPj9+2Mc7V198pEolg7yU2bD7 4b0= X-IronPort-AV: E=Sophos;i="5.77,449,1596470400"; d="scan'208";a="151656927" IronPort-SDR: B5wgJZncStMPBuEBii5s7GQAfWYs0Fh0/7Dc6DRLsiVJJsTINYOqo19bVQLaPHBNr5y4C9OVR8 q3mblVnrb7iFl4asxajkopUwnt5ow4+xUsZWqJSgxfDdA0+/Ic2fMFbkt+mD5ozLsD5DHZPGKW h44MajNmYsUDViI+B48Twn5BsjCVT9nDBVzc5ZtbFYSGKp1YuJaQAFib4LYI0YQ2eSb8KgN8GM BmVADkLcmHb5Sd5eaorHmVbe0cHGh4t1VFRy/9fXE6xPWsqc31slXSLCA/Z5Rf0/RwfpIGpaeA i0OK48xEmaFmPnUbGLK8Z56c IronPort-SDR: EeS4b9xAsleFAb0WXJvbYMLmdz2mrxHL6Q24JNLWdo4SJBzAmy1TMCX9bfeUMjez2PEhIx7we0 JbIzxZQ2ApA42YFh7hByllIyK1cVg5LEz5LFlygI8Qe+CCpldwEAR9QhHCQkGx350ftBHlQUvI rVeuT90ZCorWyHejp9B2a3QLBVslAzdzIRcdCtBESeZMHKgEXGuuJaZZbsXsyqX4JP/PGCrVgZ wZdmeiGsBiKTrg4KM9muKmL/9X3EPX9fq4L3fh9S8410qTx2q8LiksXwpEiD2fwssWfInoH5dl BZE= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 1/5] target/riscv: Add a virtualised MMU Mode Date: Tue, 3 Nov 2020 20:43:23 -0800 Message-Id: <4b301bc0ea36da962fc1605371b65019ac3073df.1604464950.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=57073d1dd=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/03 23:54:51 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, richard.henderson@linaro.org, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add a new MMU mode that includes the current virt mode. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu-param.h | 11 ++++++++++- target/riscv/cpu.h | 4 +++- target/riscv/cpu_helper.c | 2 +- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index 664fc1d371..e4cf3c01eb 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -18,6 +18,15 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ #endif #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ -#define NB_MMU_MODES 4 +/* + * The current MMU Modes are: + * - U mode 0b000 + * - S mode 0b001 + * - M mode 0b011 + * - U mode HLV/HLVX/HSV 0b100 + * - S mode HLV/HLVX/HSV 0b101 + * - M mode HLV/HLVX/HSV 0b111 + */ +#define NB_MMU_MODES 6 =20 #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 87b68affa8..5d8e54c426 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -363,7 +363,9 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState = *env, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); =20 -#define TB_FLAGS_MMU_MASK 3 +#define TB_FLAGS_MMU_MASK 7 +#define TB_FLAGS_PRIV_MMU_MASK 3 +#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) #define TB_FLAGS_MSTATUS_FS MSTATUS_FS =20 typedef CPURISCVState CPUArchState; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3eb3a034db..9dfa7af401 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -323,7 +323,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, * (riscv_cpu_do_interrupt) is correct */ MemTxResult res; MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; - int mode =3D mmu_idx; + int mode =3D mmu_idx & TB_FLAGS_PRIV_MMU_MASK; bool use_background =3D false; =20 /* --=20 2.28.0 From nobody Sat May 18 04:30:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1604466860; cv=none; d=zohomail.com; s=zohoarc; b=XkvrIN0+NgEbh6vYC5PUUKgk12ANhKKenQGaf+wF0loKcEzYiv/5OtbhI1H55hOpNa2GtAgZeho00ewimnyYY6lY93L5LXU8HcgvZY7JN1hKdwgh3n9V2XtVvFGU2J+IBq2VVPyjvKUNj7MOxxirjXo7Fy86jVWO21tdjdd1aWI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604466860; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7Fpp+86I3W394QPSXP89qMVh0wIBHjHCwK0JsUpw/9A=; b=bLjWl/XENc8jZmOV72cK7RxIVPWgLYL1YZdA640mnjgk1+86dWoRpWZbVUfLqlcHbuLF6sjsgzRhNWotbUte9Gotg1IA32fZy+tMbJvNP34Jr17GkXbxDdE7d0yKRVrME87zDvyqvT6P+VY1Vic/KneKvn4p5PEoLXnSeqXjIEU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160446686062920.58420517401248; Tue, 3 Nov 2020 21:14:20 -0800 (PST) Received: from localhost ([::1]:57718 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kaB7j-0005Ym-Bx for importer@patchew.org; Wed, 04 Nov 2020 00:14:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60164) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kaAp5-00048B-1s; Tue, 03 Nov 2020 23:55:03 -0500 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:17620) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kaAp2-0005k1-Lc; Tue, 03 Nov 2020 23:55:02 -0500 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 04 Nov 2020 12:54:57 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2020 20:39:55 -0800 Received: from usa003000.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.60.113]) by uls-op-cesaip02.wdc.com with ESMTP; 03 Nov 2020 20:54:57 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604465700; x=1636001700; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0cnh9t+t9g0YgjdwBXPqSgwt7Z2fQx44mGqfUiJG5h4=; b=LBgzK4NMj61/Mrrlc54etyPUyZ9T5YH0Be5H+sDoRStVhwqeGec1rxGy hTWXfY08BrbQtxQIXJusUwNcVUGEEp/XJaL3FZbvvlwE5pz4wr00U5aJ2 YoG7zaRvOeSNxditNeugkpiAg3ChlGbh29p6S3hMjqhTprIepZ4SyAlxG 3WljHPXPhxBK2aL5aKj9smkgbcXAl1RdVXONM3Zc07T4rR3zK3PoireZN 796yyK+diiH6rjOZoeA4pQM9hyl8MAJ3MMuRo8ULjAQ+FyzeK+v46QAI3 pG7HqxDE1h0lKXylS3vrfkXvM4d4ijBKAlbx/gsqvI7RWoFA2RqoZirMS g==; IronPort-SDR: eiaPOCjCAivFnCOlz483Sbn4q4yHIMhg2Xiv7mDWCfLewDuaNJA+r5DnCuVcUpEzKJpwtsh00S YeDMuPV4MXD7WcJPimlIuo1pwjD3HdmUPGOoyV4I0rCzTvResWWcafDljOR+4DwhfQszdLLd3f F9qN6nHyyFUa2eEf1dO9YYecJO45YnR8ITJjZ2rpftpcbJnF+cP5Eisz6gMMumEv4R/E9DCM0q s+FJTzuSzYmn66DLc+yBOsDWc6HccQgiLDSwN9e5Ez4njOMdkZDQQ+wjr7ler9VhZLYE+hfbMt ZZw= X-IronPort-AV: E=Sophos;i="5.77,449,1596470400"; d="scan'208";a="151656930" IronPort-SDR: zxU5t4CJ2It1i320/2VAHK97/k9/+a07ol9lJIbJfv9dFDKhayE1AHGUYA6gww65GrwnWw7V7a BMQtzmTToeOq3rG6/pRnDJb8hbXDcEFm6LRaiPmLepDKGrsOUb/cAPoTT1LFH34W0N/SyUkDjf h11mX+M1sLBQ0jubCMVppU15ru+jj2Ap89uFBxBU5vRSMioAhy1syZzk0Xf0QDdZUKhm+rJAZD M1uNmiFIPG6BfrqNWY0mlCsrACLgMF9Rk6qmRS+GiU4yTsFMzXhY0PAz+SyDf6hFMBUMJO/IRS x+Q7eyo2XndUQ8AJ/DxoggGv IronPort-SDR: NkRqUrVR00i4zen0TVFblCluK3P433CpMjAj+Q45c8EFfvZoILllI2JOXT76+iz6BAHdbOhR4p Fy9ynpOT2SGeyUfHQ62HyxPeu2RGcrRfEf7yRBcqAXUO58NzEvHz/1rQJixBdlM9VN7mihlClU 3+ucu4RM/wR7XxpVw2SIGguUoGTborT6/22agaxrztLA9zN4B8+fx1TkWxO5Z30XBslffX1WQg HVWqZTVBjHvIoAFrfYfQRy0j1mDHnlNjmcgIWmSqdPl1MmdQqfjGudNaL4IECZG5Evjs48o0yu eu4= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses Date: Tue, 3 Nov 2020 20:43:26 -0800 Message-Id: X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=57073d1dd=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/03 23:54:51 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, richard.henderson@linaro.org, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" When performing the hypervisor load/store operations set the MMU mode to indicate that we are virtualised. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/op_helper.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index e20d56dcb8..548c5851ec 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -235,30 +235,31 @@ target_ulong helper_hyp_load(CPURISCVState *env, targ= et_ulong address, (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { target_ulong pte; + int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 riscv_cpu_set_two_stage_lookup(env, true); =20 switch (memop) { case MO_SB: - pte =3D cpu_ldsb_data_ra(env, address, GETPC()); + pte =3D cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_UB: - pte =3D cpu_ldub_data_ra(env, address, GETPC()); + pte =3D cpu_ldub_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TESW: - pte =3D cpu_ldsw_data_ra(env, address, GETPC()); + pte =3D cpu_ldsw_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEUW: - pte =3D cpu_lduw_data_ra(env, address, GETPC()); + pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TESL: - pte =3D cpu_ldl_data_ra(env, address, GETPC()); + pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEUL: - pte =3D cpu_ldl_data_ra(env, address, GETPC()); + pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEQ: - pte =3D cpu_ldq_data_ra(env, address, GETPC()); + pte =3D cpu_ldq_mmuidx_ra(env, address, mmu_idx, GETPC()); break; default: g_assert_not_reached(); @@ -284,23 +285,25 @@ void helper_hyp_store(CPURISCVState *env, target_ulon= g address, (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { + int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; + riscv_cpu_set_two_stage_lookup(env, true); =20 switch (memop) { case MO_SB: case MO_UB: - cpu_stb_data_ra(env, address, val, GETPC()); + cpu_stb_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; case MO_TESW: case MO_TEUW: - cpu_stw_data_ra(env, address, val, GETPC()); + cpu_stw_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; case MO_TESL: case MO_TEUL: - cpu_stl_data_ra(env, address, val, GETPC()); + cpu_stl_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; case MO_TEQ: - cpu_stq_data_ra(env, address, val, GETPC()); + cpu_stq_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; default: g_assert_not_reached(); @@ -326,15 +329,16 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, ta= rget_ulong address, (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { target_ulong pte; + int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 riscv_cpu_set_two_stage_lookup(env, true); =20 switch (memop) { case MO_TEUW: - pte =3D cpu_lduw_data_ra(env, address, GETPC()); + pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEUL: - pte =3D cpu_ldl_data_ra(env, address, GETPC()); + pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); break; default: g_assert_not_reached(); --=20 2.28.0 From nobody Sat May 18 04:30:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1604466269; cv=none; d=zohomail.com; s=zohoarc; b=IO6h3yUy1Ub9CYBf2elWAKx6pvzJ7ke9UeI2MdwDYVj1sCeZX3qWhiY7Pmthg1ow5cGB4epPf5VpCulr+E72N+kLo+HJCxuC0ESQRkjSz395csRCF1prIoedn+IHdk0hkRJXSsO9cLIKkUsiwHiVFeU/WQAv+WrzLM5JsvdrI6s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604466269; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q4pWuwHEJJYN0UBkCuDNHGO/kOCAvlgHdWUL+uAiJcU=; b=jiTU0GewSFD6ohzWDxP+FGJauUcYjskOV1G7hDIlixcEnlZFfboJGqZQovSvN/tyNA6GKvlTxNdr9EJLrko8eJaGJQvfaAOpW+sr4POwVgtNOeciWqvdu5p+XGb4Nx/mz2b4SKHXbdoT4JeG343lEeXF3tBjm3TTL9rmlRTIboQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160446626988862.25667933037107; Tue, 3 Nov 2020 21:04:29 -0800 (PST) Received: from localhost ([::1]:54348 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kaAyC-0000uS-Hw for importer@patchew.org; Wed, 04 Nov 2020 00:04:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60166) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kaAp5-0004Af-SW; Tue, 03 Nov 2020 23:55:03 -0500 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:17610) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kaAp3-0005i4-8d; Tue, 03 Nov 2020 23:55:03 -0500 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 04 Nov 2020 12:55:00 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2020 20:39:58 -0800 Received: from usa003000.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.60.113]) by uls-op-cesaip02.wdc.com with ESMTP; 03 Nov 2020 20:55:00 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604465701; x=1636001701; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GctOS9l5Jb3XAXB+4Gm9TXKQvlbYOUdTBgjag0qfN/A=; b=TZmVLQvZV6ML95zKUJdSYFPossOJTNv78dnMo18ffMCntypV/GCI/ELg 8UR37yWTKgpnMYhmve8GTHOZi4bwiloUMbGH8YBnNuH0zxaHeU263IKy8 xeF2jIe9h8ynISUKHyTi5Hpnb6UiNG5Hehd0tEMkC+zU24X4XnlCzYKiF N8kFkAniLjO0dDd3GkTUFdj3us/EnSQuTGXsh7OSh79P4bfZBoED7BP0k 84wiRNnXuEavSNEbjV5rOKT9H41NyDM232Yt3lyMJMpe6Nrr9GN+SVG3g tkboKxXJJXdzc2CpTtC4IjCMbDMMtts22vk+mu6xY8GKTqBjAilwawox+ Q==; IronPort-SDR: /3WvYCxC/k9oLgoVx6ROUOOjxpA9SReELr2rCA1AA9AurX4Dh2GQTeHomL4XAQxe6Pg16jke3g yD/CEniJ1k7TW6BG243GJMyuIKqu2oNPm0DvhPh6o5/pA21wJRMGVCaWg/7MModMWGsIbTik2K iXOHIVo+i/DxBVjHC2Qlb14XlgxBOPZdCznfw+/mC0+NqyuwQc0o/MifRB9pYnPvI3Uhwa24j1 LuBKaEwHY3LwdRKNyM4Jq1SHZXhl4iQndRVJTKotjo4IL1xx1/BMR2E3bn8LUiLDYM2utflhLZ Nok= X-IronPort-AV: E=Sophos;i="5.77,449,1596470400"; d="scan'208";a="151656935" IronPort-SDR: vpuCGCtDtUus+TqykMijI0pqdZ+UhvYgeo0jPaek6EVZO9Jg5Kmf7PlKbZr7dFQbFwU3EonE8f ddZ+sldEO0HH9wE4DF3U0lBue1u2tXKDfhbsEHkdUt4rW5Vm5Ww/fKIdDIz6v65rc17c3bLdPT Vvwwe1Q9jcSxxK0xWUH7e/PkDc8X8xAPXNO72IxkTCREoHgxMbIQHlBwdaz0SN2BSok06qZbvO 1/qRP2egbD2s158WO+CoXgDrcSMN6N6vnXwkTqlMSehS4E41ML4XgoQdtSkIznlsasngk9iN88 /IYdYHVnfH5apU1S60nWvTR/ IronPort-SDR: Hqpa5zeyPrIxX/yzXLPNQuq84fvbfEOeHFjL9cteXPDttTQzpvPNjliHZNSrfz+UheriZy52yL d/zTk48/e8nGDWVHJYAh008tkQk68rzQX6jOOw9mpZs2seU/bpZbj1dcgZbB+D9ruTMml4uaHW 6ZjHUHGgpdWOBGj+q5PVRrzHoH5wE3tymXRXp8W0wEVKG17znoVN/sLq/iv1Sh2OTPLcsq5mgS YmQleKVMrw4Uj3ch7U06YUgJlbAHujk32zXsviVQdsJgbGVK3GTB+EZ27/jh4hlSHneku7puey pKc= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 3/5] target/riscv: Remove the HS_TWO_STAGE flag Date: Tue, 3 Nov 2020 20:43:29 -0800 Message-Id: X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=57073d1dd=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/03 23:54:51 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, richard.henderson@linaro.org, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The HS_TWO_STAGE flag is no longer required as the MMU index contains the information if we are performing a two stage access. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 3 +- target/riscv/cpu_bits.h | 1 - target/riscv/cpu_helper.c | 60 ++++++++++++++++----------------------- target/riscv/op_helper.c | 12 -------- 4 files changed, 25 insertions(+), 51 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5d8e54c426..0cf48a1521 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -323,8 +323,7 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); -bool riscv_cpu_two_stage_lookup(CPURISCVState *env); -void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable); +bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index daedad8691..24b24c69c5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -469,7 +469,6 @@ * page table fault. */ #define FORCE_HS_EXCEP 2 -#define HS_TWO_STAGE 4 =20 /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9dfa7af401..a2787b1d48 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -207,22 +207,9 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, = bool enable) env->virt =3D set_field(env->virt, FORCE_HS_EXCEP, enable); } =20 -bool riscv_cpu_two_stage_lookup(CPURISCVState *env) +bool riscv_cpu_two_stage_lookup(int mmu_idx) { - if (!riscv_has_ext(env, RVH)) { - return false; - } - - return get_field(env->virt, HS_TWO_STAGE); -} - -void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable) -{ - if (!riscv_has_ext(env, RVH)) { - return; - } - - env->virt =3D set_field(env->virt, HS_TWO_STAGE, enable); + return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; } =20 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) @@ -333,7 +320,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, * was called. Background registers will be used if the guest has * forced a two stage translation to be on (in HS or M mode). */ - if (riscv_cpu_two_stage_lookup(env) && access_type !=3D MMU_INST_FETCH= ) { + if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx= )) { use_background =3D true; } =20 @@ -572,7 +559,7 @@ restart: =20 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type, bool pmp_violat= ion, - bool first_stage) + bool first_stage, bool two_stage) { CPUState *cs =3D env_cpu(env); int page_fault_exceptions; @@ -595,8 +582,7 @@ static void raise_mmu_exception(CPURISCVState *env, tar= get_ulong address, } break; case MMU_DATA_LOAD: - if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env= )) && - !first_stage) { + if (two_stage && !first_stage) { cs->exception_index =3D RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; } else { cs->exception_index =3D page_fault_exceptions ? @@ -604,8 +590,7 @@ static void raise_mmu_exception(CPURISCVState *env, tar= get_ulong address, } break; case MMU_DATA_STORE: - if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env= )) && - !first_stage) { + if (two_stage && !first_stage) { cs->exception_index =3D RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAUL= T; } else { cs->exception_index =3D page_fault_exceptions ? @@ -696,6 +681,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, int prot, prot2; bool pmp_violation =3D false; bool first_stage_error =3D true; + bool two_stage_lookup =3D false; int ret =3D TRANSLATE_FAIL; int mode =3D mmu_idx; target_ulong tlb_size =3D 0; @@ -715,11 +701,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, access_type !=3D MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV) && get_field(env->mstatus, MSTATUS_MPV)) { - riscv_cpu_set_two_stage_lookup(env, true); + two_stage_lookup =3D true; } =20 if (riscv_cpu_virt_enabled(env) || - (riscv_cpu_two_stage_lookup(env) && access_type !=3D MMU_INST_FETC= H)) { + ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && + access_type !=3D MMU_INST_FETCH)) { /* Two stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, &env->guest_phys_fault_addr, access_typ= e, @@ -782,14 +769,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, __func__, address, ret, pa, prot); } =20 - /* We did the two stage lookup based on MPRV, unset the lookup */ - if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_M && - access_type !=3D MMU_INST_FETCH && - get_field(env->mstatus, MSTATUS_MPRV) && - get_field(env->mstatus, MSTATUS_MPV)) { - riscv_cpu_set_two_stage_lookup(env, false); - } - if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret =3D=3D TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { @@ -811,7 +790,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } else if (probe) { return false; } else { - raise_mmu_exception(env, address, access_type, pmp_violation, firs= t_stage_error); + raise_mmu_exception(env, address, access_type, pmp_violation, + first_stage_error, + riscv_cpu_virt_enabled(env) || + riscv_cpu_two_stage_lookup(mmu_idx)); riscv_raise_exception(env, cs->exception_index, retaddr); } =20 @@ -915,9 +897,16 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { target_ulong hdeleg =3D async ? env->hideleg : env->hedeleg; + bool two_stage_lookup =3D false; + + if (env->priv =3D=3D PRV_M || + (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + two_stage_lookup =3D true; + } =20 - if ((riscv_cpu_virt_enabled(env) || - riscv_cpu_two_stage_lookup(env)) && write_tval) { + if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write= _tval) { /* * If we are writing a guest virtual address to stval, set * this to 1. If we are trapping to VS we will set this to= 0 @@ -955,11 +944,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_force_hs_excep(env, 0); } else { /* Trap into HS mode */ - if (!riscv_cpu_two_stage_lookup(env)) { + if (!two_stage_lookup) { env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); } - riscv_cpu_set_two_stage_lookup(env, false); htval =3D env->guest_phys_fault_addr; } } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 548c5851ec..5759850e69 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -237,8 +237,6 @@ target_ulong helper_hyp_load(CPURISCVState *env, target= _ulong address, target_ulong pte; int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 - riscv_cpu_set_two_stage_lookup(env, true); - switch (memop) { case MO_SB: pte =3D cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC()); @@ -265,8 +263,6 @@ target_ulong helper_hyp_load(CPURISCVState *env, target= _ulong address, g_assert_not_reached(); } =20 - riscv_cpu_set_two_stage_lookup(env, false); - return pte; } =20 @@ -287,8 +283,6 @@ void helper_hyp_store(CPURISCVState *env, target_ulong = address, get_field(env->hstatus, HSTATUS_HU))) { int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 - riscv_cpu_set_two_stage_lookup(env, true); - switch (memop) { case MO_SB: case MO_UB: @@ -309,8 +303,6 @@ void helper_hyp_store(CPURISCVState *env, target_ulong = address, g_assert_not_reached(); } =20 - riscv_cpu_set_two_stage_lookup(env, false); - return; } =20 @@ -331,8 +323,6 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, targ= et_ulong address, target_ulong pte; int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 - riscv_cpu_set_two_stage_lookup(env, true); - switch (memop) { case MO_TEUW: pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); @@ -344,8 +334,6 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, targ= et_ulong address, g_assert_not_reached(); } =20 - riscv_cpu_set_two_stage_lookup(env, false); - return pte; } =20 --=20 2.28.0 From nobody Sat May 18 04:30:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1604466984; cv=none; d=zohomail.com; s=zohoarc; b=SQOoaz5UDE4avUXHC14HyOso4+/J8IXaf5P4z96U6+FdLK2XJufPibSurON+oaljzJ+rgDHfo6W08+ZePj6tgfGgIGhjsr8R1XRW1rEuFkDck89dlYOdED93UvROJLLMFaFlHy43a6VcTszb0cgm2IVE5iP+uNghqQDOWTK73u0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604466984; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Svr2FNbREaAiAaJJrL2Pa3T5KCQdqQ6UR6vGDL9KNXU=; b=NzsK58MtCPExkopn8AAz98w0tEHh/uaCgR5+mZVh7iBqzXibMDprmUp4Ewc1mKlbeV3PIpcTTz5pf0vgBI5tmPyg3p4DoxSR+FX79/HXfZkCJ/KyYBWqzeYk3CL95iCXJpIjRlnD+2uZI9yQJHydLxV2X3OO0C3ycuPoHPoSl4c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604466984302491.3529239814584; Tue, 3 Nov 2020 21:16:24 -0800 (PST) Received: from localhost ([::1]:35880 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kaB9j-0008FG-4w for importer@patchew.org; Wed, 04 Nov 2020 00:16:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60198) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kaApA-0004MN-Ij; Tue, 03 Nov 2020 23:55:10 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:21931) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kaAp7-0005ml-2v; Tue, 03 Nov 2020 23:55:08 -0500 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 04 Nov 2020 13:10:15 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2020 20:41:11 -0800 Received: from usa003000.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.60.113]) by uls-op-cesaip01.wdc.com with ESMTP; 03 Nov 2020 20:55:02 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604466618; x=1636002618; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oebXz+FU0S0tCY1aSc+EvOPS+hmZUBeVgzx3vCpSopA=; b=eySjWvaF/tCz3mzPbhuJ6uXaJElScCp9Q/z+iBeIq9cARCt7UAJhvBvT FNUnaIlh7fOSpP3+P+JeFunMHltIdkuE9/Jt8j6paASuOHA+DUmxk3R+Y SwsYLxa3F41LhOvt1JgxXChLSJkLyY/n7Qs8LveBOC1nZOYA94Rjz1HrN R1S4jr1LIoo/zyi4YlTJtRt6n7ZhVx6Z4Oz6sAc4UAEihtOprbnC0Y5BZ mbeeS0ltMxo1Bdcb+gfI2np5Ft/MPOo+4O2ZggSmzR218pMBDn8Mi2AWw EPmYrezIyBBKCWmY+ZTCzl5QfMeUYkxcjDRa5vXuCBMrJKOB2ujcuvwJt A==; IronPort-SDR: db5BYLD/4mKbLmUwoGF5lo7R9rjXCPF8Ik49p2K5ZHyrOCpaOcDxyQb/3xeql3AcEZusgVNEut KSMPpSd8zyOWQK6Px6wvZxCB0KmDnVSrckweYB1qVSwBzcm5KBvvrc5Ae25+UJH4xwqsCyCJJs PPcWeO7rwUsE1mhlZztqh+S3HU64drP9LvD7RuLAfY4LTW6RNQYipx8bsiG8+r0YI0FqUkX1/A QZjgaijhwD5TheOErYy0Hmbr5CsmSqiYAupbg0HKB+uFf0mwkj5kxV0H/TRZ5Ql4LVe1AhqTSh ilg= X-IronPort-AV: E=Sophos;i="5.77,449,1596470400"; d="scan'208";a="255296318" IronPort-SDR: M8BhJKivNDHTfmIqrXapveidP0wepz+Idi3NvluD4adTDYL8BLWIEsrObxoya2vR0dJAwUwjTd bvOpJwL7/vNgMhwmEFherSIBWvtN2h4TOlLn8UPuofvtAif1I8qqKmMu1IHxBxCNo1dOBsqFVg stzUwRGcnrJbx5iShlrGRJecCjeSqGHgrQBn18L69EMS9zLQArzXtwMV/hyT2Q0D1SbwGdBrAf BgNUdb5CtCj9HJpgJVEPjP3ihqZvNTbPIl2YGuuwOf6OcI69qH1l10/qkVkarZ//A9Dt33w7Gn EQqqslTQ7002hYBZWE0++Au8 IronPort-SDR: 11GRjl6uRXk/LXGntNOrv/fJGZA3oz4og1dVCOUzu7b4JLlzsqaN8kb1gUQV7iMdTtl9VYKtS+ HcdYvEJOAZOUe3h6g5qkucKRE2iyjMGege5GqVvCyB5oUwD0d+WZUvtV81MIGqumw/QZR/gUck WhPEE0b9kNw0WRyXEV7b4CZIthEF/pPT5RCkvtTaW38hQ7zPeDKXtcNmv/8DgOgOrnsLhgIYKo S0VsRObl3KoZeBXioe8YwCmjUCjv2c3Fxs7wi9uY08kN1+pv+NG6ryHiD1O1icPsp1CemKyVe+ ol4= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 4/5] target/riscv: Remove the hyp load and store functions Date: Tue, 3 Nov 2020 20:43:31 -0800 Message-Id: <189ac3e53ef2854824d18aad7074c6649f17de2c.1604464950.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=57073d1dd=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/03 23:55:03 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, richard.henderson@linaro.org, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Remove the special Virtulisation load and store functions and just use the standard tcg tcg_gen_qemu_ld_tl() and tcg_gen_qemu_st_tl() functions instead. As part of this change we ensure we still run an access check to make sure we can perform the operations. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 12 +++ target/riscv/helper.h | 2 - target/riscv/op_helper.c | 86 ----------------- target/riscv/translate.c | 2 + target/riscv/insn_trans/trans_rvh.c.inc | 123 +++++++++--------------- 5 files changed, 59 insertions(+), 166 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0cf48a1521..c0a326c843 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -375,6 +375,8 @@ FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) FIELD(TB_FLAGS, LMUL, 3, 2) FIELD(TB_FLAGS, SEW, 5, 3) FIELD(TB_FLAGS, VILL, 8, 1) +/* Is a Hypervisor instruction load/store allowed? */ +FIELD(TB_FLAGS, HLSX, 9, 1) =20 /* * A simplification for VLMAX @@ -421,7 +423,17 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState = *env, target_ulong *pc, if (riscv_cpu_fp_enabled(env)) { flags |=3D env->mstatus & MSTATUS_FS; } + + if (riscv_has_ext(env, RVH)) { + if (env->priv =3D=3D PRV_M || + (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); + } + } #endif + *pflags =3D flags; } =20 diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 4b690147fb..ee35311052 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -81,8 +81,6 @@ DEF_HELPER_1(tlb_flush, void, env) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) -DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl) -DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl) DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) #endif =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 5759850e69..980d4f39e1 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -227,92 +227,6 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } =20 -target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, - target_ulong attrs, target_ulong memop) -{ - if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - target_ulong pte; - int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; - - switch (memop) { - case MO_SB: - pte =3D cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_UB: - pte =3D cpu_ldub_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TESW: - pte =3D cpu_ldsw_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEUW: - pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TESL: - pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEUL: - pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEQ: - pte =3D cpu_ldq_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - default: - g_assert_not_reached(); - } - - return pte; - } - - if (riscv_cpu_virt_enabled(env)) { - riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); - } else { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } - return 0; -} - -void helper_hyp_store(CPURISCVState *env, target_ulong address, - target_ulong val, target_ulong attrs, target_ulong m= emop) -{ - if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; - - switch (memop) { - case MO_SB: - case MO_UB: - cpu_stb_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - case MO_TESW: - case MO_TEUW: - cpu_stw_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - case MO_TESL: - case MO_TEUL: - cpu_stl_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - case MO_TEQ: - cpu_stq_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - default: - g_assert_not_reached(); - } - - return; - } - - if (riscv_cpu_virt_enabled(env)) { - riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); - } else { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } -} - target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, target_ulong attrs, target_ulong memop) { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 79dca2291b..554d52a4be 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -56,6 +56,7 @@ typedef struct DisasContext { to reset this known value. */ int frm; bool ext_ifencei; + bool hlsx; /* vector extension */ bool vill; uint8_t lmul; @@ -807,6 +808,7 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->frm =3D -1; /* unknown rounding mode */ ctx->ext_ifencei =3D cpu->cfg.ext_ifencei; ctx->vlen =3D cpu->cfg.vlen; + ctx->hlsx =3D FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill =3D FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index 881c9ef4d2..cc197e7186 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -16,26 +16,34 @@ * this program. If not, see . */ =20 +#ifndef CONFIG_USER_ONLY +static void check_access(DisasContext *ctx) { + if (!ctx->hlsx) { + if (ctx->virt_enabled) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } + } +} +#endif + static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) { REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_SB); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_SB); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -48,20 +56,16 @@ static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESW); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TESW); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -74,20 +78,16 @@ static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESL); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TESL); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -100,20 +100,16 @@ static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_b= u *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_UB); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_UB); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -126,20 +122,15 @@ static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_h= u *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); =20 - gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUW); + check_access(ctx); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_get_gpr(t0, a->rs1); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEUW); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -152,20 +143,16 @@ static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_SB); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_SB); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -178,20 +165,16 @@ static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESW); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TESW); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -204,20 +187,16 @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESL); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TESL); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -231,20 +210,16 @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_w= u *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUL); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEUL); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -257,20 +232,16 @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEQ); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEQ); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -283,20 +254,16 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEQ); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TEQ); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; --=20 2.28.0 From nobody Sat May 18 04:30:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1604466477; cv=none; d=zohomail.com; s=zohoarc; b=cNzpRnz7SXVY6juFwt6T382ZWekHDUl50HvfgvEUzZ67HEnuydbn+sK3RcD/wyOAA48tGq3x5DZvGbIdxw+ALauc1ltyHOJ9/83676kdMRpMXjFvxp18VK1PLD9HVt1Wv9IVn8j+slTd+yyOkvMaRgAZo4TBxblPV6Hzn+RB2zU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604466477; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UCgCM0xR+x05QXkCVEOhhQ0lKWG6soHfxxhCqVe2j80=; b=B/WhDbDJZVA+WCjWRUIf9V2l4OhhIbzWzfwRtUuDhABvhFsPYnEbxP/QvHYR9qy6h1eH3NGjo2fSjo5AFMm/4aJWjOwWra3wWKvoAmbHbSJ1hoRu5N35qI8oi42o4D4v6SDSk488MyPr8k9m/MdbFPQp39Md+EP0UhWTPaV2VR8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604466477153848.8780074792751; Tue, 3 Nov 2020 21:07:57 -0800 (PST) Received: from localhost ([::1]:35086 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kaB1W-0004gX-Ul for importer@patchew.org; Wed, 04 Nov 2020 00:07:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60210) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kaApC-0004ND-GZ; Tue, 03 Nov 2020 23:55:10 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:21933) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kaAp9-0005nq-Dn; Tue, 03 Nov 2020 23:55:10 -0500 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 04 Nov 2020 13:10:19 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2020 20:41:14 -0800 Received: from usa003000.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.60.113]) by uls-op-cesaip01.wdc.com with ESMTP; 03 Nov 2020 20:55:05 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604466622; x=1636002622; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3ASiHykrJWkIM9t2dOvM+UqrUoVsXYneSkga2iFI3YM=; b=JuyzOJaipV9EpCvV7+E1sy8x/gSq0b3iLF4DIJyAzxAq4PYhitJQy9+V koov6p3x33lT5dAzbY9b7hIILTEzMfSUHpeERI0x6zFCGwlwfJoI3pvwq LVta/AJt/1nlv90o/kkgZChaJJujDMDqHLGVhkOZqy4A/8i6hrXAtA7V2 vWCD7Y7xIgI6bG+nYwajZP3JMLyFAYSznX7MVYtSb1ZQgV4mXPzdEI84d YLNbyUUDHpLugS5xnS93sivC7NTdMHoJOIE9Bks6lQMjaKKUYTVoDaSI1 K4GH7dIFJ28wVl1FzPnpkniqLBC5IfS4UNQ2M9hQL4Go9VY9weupWbhcD Q==; IronPort-SDR: 6j0EfC85/8rTHho+vbNPwfAmoLiHwtaGAMkEzGADzzi/GOi8Mz0F2m5C8upi/sVyyTvoPoZr/7 ScyoMKXcuDGtbk9vH3F+EWbrKEO1PL+0d01Lq0Fv8vDrJ3CZeVIFHjGqcmJ2vwD7QQChjSyQq9 3on+odECj7OVCyvQbLtZPXYz6xJ80t/WWEZyKVcqaMB9RXRzYO4AfxBFa1CCV7xB+sL6QC3QfZ 0/bkc61lTTyYsrza36arPcMdydOeMvI0VqROqIZ8jVVlzxRLhEiWKaV632ut/kzPbGAYHyhUeS DUU= X-IronPort-AV: E=Sophos;i="5.77,449,1596470400"; d="scan'208";a="255296321" IronPort-SDR: 4R1GPGFhk+ZFWckMiEJwCVfcrk9/mjbiddzHHOOhdybfP/SXc6epdTcM1FdZjRfbYFnvY4EQ6t c//9I9SMCpihQg/ZOVh2ou8gg8nLglDIX6R8u6sa07rqjBRUSis0394wMLCzgyXbk0sUWdWoV8 IyRafyCYO2axWntixi7R7Ff1HXuxgkMY+aCGSsliQ4+kLK1+jcEgB2ktAW6mAfVudUtTUG6rxR X08EmI1jIUwTpfFcrLmuEAOpdAeUN7OV2KDnOqelmmo9ckwqHKN3Y35v9zzYowzhcfYM8UJ1h9 RbyQdptiF9Zf2HtHD+eGDNme IronPort-SDR: xGdA7S243VrYTIRgWgP4n9nb4bWseJ7n2y6UbWN55vyBprJTB6VZhLE6RFcwxSkubLaN3UFgMp Qlr9HN0yiBIEo+4mHszvVKM/BmWF39kOTa6vQF5AkxfMsP9qkbMT1sbK3YW6w0mjfIKX5H0ToP tO9loUm/A8MvJoij/ZH2riaFQPFkpVKrO3wevENYbBD0/Ibpi9oEx9xtIy74pU1npgeCx8t7KF SDyQUl2imCAR8tJdY6QbSY4JzxtWPjg4OpzD7dzugHsc14DoHOg21v8lzXJTB6gheBR81dyk0g qkg= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 5/5] target/riscv: Split the Hypervisor execute load helpers Date: Tue, 3 Nov 2020 20:43:34 -0800 Message-Id: <5b1550f0faa3c435cc77f3c1ae811dea98ab9e36.1604464950.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=57073d1dd=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/03 23:55:03 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, richard.henderson@linaro.org, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Signature date is -145 seconds in the future.) Content-Type: text/plain; charset="utf-8" Split the hypervisor execute load functions into two seperate functions. This avoids us having to pass the memop to the C helper functions. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 3 ++- target/riscv/op_helper.c | 36 +++++++------------------ target/riscv/insn_trans/trans_rvh.c.inc | 20 +++++--------- 3 files changed, 17 insertions(+), 42 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index ee35311052..939731c345 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -81,7 +81,8 @@ DEF_HELPER_1(tlb_flush, void, env) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) -DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) +DEF_HELPER_2(hyp_hlvx_hu, tl, env, tl) +DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl) #endif =20 /* Vector functions */ diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 980d4f39e1..d55def76cf 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -227,36 +227,18 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } =20 -target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, - target_ulong attrs, target_ulong memop) +target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address) { - if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - target_ulong pte; - int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; - - switch (memop) { - case MO_TEUW: - pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEUL: - pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - default: - g_assert_not_reached(); - } + int mmu_idx =3D cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK; =20 - return pte; - } + return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); +} =20 - if (riscv_cpu_virt_enabled(env)) { - riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); - } else { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } - return 0; +target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address) +{ + int mmu_idx =3D cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK; + + return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); } =20 #endif /* !CONFIG_USER_ONLY */ diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index cc197e7186..ce7ed5affb 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -277,20 +277,16 @@ static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx= _hu *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUW); =20 - gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_helper_hyp_hlvx_hu(t1, cpu_env, t0); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -303,20 +299,16 @@ static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx= _wu *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUL); =20 - gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_helper_hyp_hlvx_wu(t1, cpu_env, t0); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; --=20 2.28.0