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charset="utf-8" Add a new MMU mode that includes the current virt mode. Signed-off-by: Alistair Francis --- target/riscv/cpu-param.h | 2 +- target/riscv/cpu.h | 4 +++- target/riscv/cpu_helper.c | 6 +++++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index 664fc1d371..502ed6489e 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -18,6 +18,6 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ #endif #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ -#define NB_MMU_MODES 4 +#define NB_MMU_MODES 8 =20 #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de4705bb57..8ac01f3a64 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -365,7 +365,9 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState = *env, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); =20 -#define TB_FLAGS_MMU_MASK 3 +#define TB_FLAGS_MMU_MASK 7 +#define TB_FLAGS_PRIV_MMU_MASK 3 +#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) #define TB_FLAGS_MSTATUS_FS MSTATUS_FS =20 typedef CPURISCVState CPUArchState; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4652082df1..46b62a0f37 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -30,6 +30,10 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #ifdef CONFIG_USER_ONLY return 0; #else + if (riscv_cpu_virt_enabled(env)) { + return env->priv | TB_FLAGS_PRIV_HYP_ACCESS_MASK; + } + return env->priv; #endif } @@ -336,7 +340,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, * (riscv_cpu_do_interrupt) is correct */ MemTxResult res; MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; - int mode =3D mmu_idx; + int mode =3D mmu_idx & 0x3; bool use_background =3D false; =20 /* --=20 2.28.0 From nobody Thu May 2 05:02:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" When performing the hypervisor load/store operations set the MMU mode to indicate that we are virtualised. Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 4ce73575a7..bc6df6c8c9 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -238,30 +238,31 @@ target_ulong helper_hyp_load(CPURISCVState *env, targ= et_ulong address, (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { target_ulong pte; + int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 riscv_cpu_set_two_stage_lookup(env, true); =20 switch (memop) { case MO_SB: - pte =3D cpu_ldsb_data_ra(env, address, GETPC()); + pte =3D cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_UB: - pte =3D cpu_ldub_data_ra(env, address, GETPC()); + pte =3D cpu_ldub_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TESW: - pte =3D cpu_ldsw_data_ra(env, address, GETPC()); + pte =3D cpu_ldsw_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEUW: - pte =3D cpu_lduw_data_ra(env, address, GETPC()); + pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TESL: - pte =3D cpu_ldl_data_ra(env, address, GETPC()); + pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEUL: - pte =3D cpu_ldl_data_ra(env, address, GETPC()); + pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEQ: - pte =3D cpu_ldq_data_ra(env, address, GETPC()); + pte =3D cpu_ldq_mmuidx_ra(env, address, mmu_idx, GETPC()); break; default: g_assert_not_reached(); @@ -287,23 +288,25 @@ void helper_hyp_store(CPURISCVState *env, target_ulon= g address, (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { + int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; + riscv_cpu_set_two_stage_lookup(env, true); =20 switch (memop) { case MO_SB: case MO_UB: - cpu_stb_data_ra(env, address, val, GETPC()); + cpu_stb_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; case MO_TESW: case MO_TEUW: - cpu_stw_data_ra(env, address, val, GETPC()); + cpu_stw_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; case MO_TESL: case MO_TEUL: - cpu_stl_data_ra(env, address, val, GETPC()); + cpu_stl_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; case MO_TEQ: - cpu_stq_data_ra(env, address, val, GETPC()); + cpu_stq_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; default: g_assert_not_reached(); @@ -329,15 +332,16 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, ta= rget_ulong address, (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { target_ulong pte; + int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 riscv_cpu_set_two_stage_lookup(env, true); =20 switch (memop) { case MO_TEUW: - pte =3D cpu_lduw_data_ra(env, address, GETPC()); + pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEUL: - pte =3D cpu_ldl_data_ra(env, address, GETPC()); + pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); break; default: g_assert_not_reached(); --=20 2.28.0 From nobody Thu May 2 05:02:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1603470012; cv=none; d=zohomail.com; s=zohoarc; b=CycqRDthd8ZAWPj5Ah+XOFRgiIKI5lpUaD8uIpKh2X/5ZohxQP71awKDIhYUZV7GzNu3yZBpvHIxg91Ghqqv1VW3Yd54TVr3zr2aCvBTc/Jc6J5JrhEFDdpC0RkyYFwdSqQJ8gdTZ25uP1jY66skGXysrWOIl+0cSA/cmdRDWUo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603470012; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9VWGMVqVh1MJ7Anc/IVjXSHTHk8F86ejeJ/h7Mpq62U=; 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charset="utf-8" The HS_TWO_STAGE flag is no longer required as the MMU index contains the information if we are performing a two stage access. Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 +- target/riscv/cpu_bits.h | 1 - target/riscv/cpu_helper.c | 61 ++++++++++++++++----------------------- target/riscv/op_helper.c | 12 -------- 4 files changed, 26 insertions(+), 51 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8ac01f3a64..694f51ebd4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -325,8 +325,7 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); -bool riscv_cpu_two_stage_lookup(CPURISCVState *env); -void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable); +bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index bd36062877..20b6ec4ec5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -480,7 +480,6 @@ * page table fault. */ #define FORCE_HS_EXCEP 2 -#define HS_TWO_STAGE 4 =20 /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 46b62a0f37..a1f94ea518 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -224,22 +224,9 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, = bool enable) env->virt =3D set_field(env->virt, FORCE_HS_EXCEP, enable); } =20 -bool riscv_cpu_two_stage_lookup(CPURISCVState *env) +bool riscv_cpu_two_stage_lookup(int mmu_idx) { - if (!riscv_has_ext(env, RVH)) { - return false; - } - - return get_field(env->virt, HS_TWO_STAGE); -} - -void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable) -{ - if (!riscv_has_ext(env, RVH)) { - return; - } - - env->virt =3D set_field(env->virt, HS_TWO_STAGE, enable); + return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; } =20 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) @@ -350,7 +337,8 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, * was called. Background registers will be used if the guest has * forced a two stage translation to be on (in HS or M mode). */ - if (riscv_cpu_two_stage_lookup(env) && access_type !=3D MMU_INST_FETCH= ) { + if ((!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_id= x)) + && access_type !=3D MMU_INST_FETCH) { use_background =3D true; } =20 @@ -589,7 +577,7 @@ restart: =20 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type, bool pmp_violat= ion, - bool first_stage) + bool first_stage, bool two_stage) { CPUState *cs =3D env_cpu(env); int page_fault_exceptions; @@ -612,8 +600,7 @@ static void raise_mmu_exception(CPURISCVState *env, tar= get_ulong address, } break; case MMU_DATA_LOAD: - if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env= )) && - !first_stage) { + if (two_stage && !first_stage) { cs->exception_index =3D RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; } else { cs->exception_index =3D page_fault_exceptions ? @@ -621,8 +608,7 @@ static void raise_mmu_exception(CPURISCVState *env, tar= get_ulong address, } break; case MMU_DATA_STORE: - if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env= )) && - !first_stage) { + if (two_stage && !first_stage) { cs->exception_index =3D RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAUL= T; } else { cs->exception_index =3D page_fault_exceptions ? @@ -713,6 +699,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, int prot, prot2; bool pmp_violation =3D false; bool first_stage_error =3D true; + bool two_stage_lookup =3D false; int ret =3D TRANSLATE_FAIL; int mode =3D mmu_idx; target_ulong tlb_size =3D 0; @@ -732,11 +719,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, access_type !=3D MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV) && MSTATUS_MPV_ISSET(env)) { - riscv_cpu_set_two_stage_lookup(env, true); + two_stage_lookup =3D true; } =20 if (riscv_cpu_virt_enabled(env) || - (riscv_cpu_two_stage_lookup(env) && access_type !=3D MMU_INST_FETC= H)) { + ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && + access_type !=3D MMU_INST_FETCH)) { /* Two stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, &env->guest_phys_fault_addr, access_typ= e, @@ -799,14 +787,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, __func__, address, ret, pa, prot); } =20 - /* We did the two stage lookup based on MPRV, unset the lookup */ - if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_M && - access_type !=3D MMU_INST_FETCH && - get_field(env->mstatus, MSTATUS_MPRV) && - MSTATUS_MPV_ISSET(env)) { - riscv_cpu_set_two_stage_lookup(env, false); - } - if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret =3D=3D TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { @@ -828,7 +808,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } else if (probe) { return false; } else { - raise_mmu_exception(env, address, access_type, pmp_violation, firs= t_stage_error); + raise_mmu_exception(env, address, access_type, pmp_violation, + first_stage_error, + riscv_cpu_virt_enabled(env) || + riscv_cpu_two_stage_lookup(mmu_idx)); riscv_raise_exception(env, cs->exception_index, retaddr); } =20 @@ -932,9 +915,16 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { target_ulong hdeleg =3D async ? env->hideleg : env->hedeleg; + bool two_stage_lookup =3D false; + + if (env->priv =3D=3D PRV_M || + (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + two_stage_lookup =3D true; + } =20 - if ((riscv_cpu_virt_enabled(env) || - riscv_cpu_two_stage_lookup(env)) && write_tval) { + if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write= _tval) { /* * If we are writing a guest virtual address to stval, set * this to 1. If we are trapping to VS we will set this to= 0 @@ -972,11 +962,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_force_hs_excep(env, 0); } else { /* Trap into HS mode */ - if (!riscv_cpu_two_stage_lookup(env)) { + if (!two_stage_lookup) { env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); } - riscv_cpu_set_two_stage_lookup(env, false); htval =3D env->guest_phys_fault_addr; } } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index bc6df6c8c9..556a23f031 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -240,8 +240,6 @@ target_ulong helper_hyp_load(CPURISCVState *env, target= _ulong address, target_ulong pte; int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 - riscv_cpu_set_two_stage_lookup(env, true); - switch (memop) { case MO_SB: pte =3D cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC()); @@ -268,8 +266,6 @@ target_ulong helper_hyp_load(CPURISCVState *env, target= _ulong address, g_assert_not_reached(); } =20 - riscv_cpu_set_two_stage_lookup(env, false); - return pte; } =20 @@ -290,8 +286,6 @@ void helper_hyp_store(CPURISCVState *env, target_ulong = address, get_field(env->hstatus, HSTATUS_HU))) { int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 - riscv_cpu_set_two_stage_lookup(env, true); - switch (memop) { case MO_SB: case MO_UB: @@ -312,8 +306,6 @@ void helper_hyp_store(CPURISCVState *env, target_ulong = address, g_assert_not_reached(); } =20 - riscv_cpu_set_two_stage_lookup(env, false); - return; } =20 @@ -334,8 +326,6 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, targ= et_ulong address, target_ulong pte; int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 - riscv_cpu_set_two_stage_lookup(env, true); - switch (memop) { case MO_TEUW: pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); @@ -347,8 +337,6 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, targ= et_ulong address, g_assert_not_reached(); } =20 - riscv_cpu_set_two_stage_lookup(env, false); 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IronPort-SDR: BT9135chvvcBujuW5ChbpeEdEcIiOJkkJR+OGif05ZyLUjEJKUgX/sBxZKmAgoLFiHqOlI9oNZ IPJimreVFIoY6dEdkPoD+MiHh+VBgsOzOORNJSsGEOfeRcF7aODgIuKQwAbFCmaIRuPbRWDdn6 8lz/lP/IaFjWq/2zxz6QAGpx1oTphgeKs8whYPQ4e+5eF3gW3fXVRM8A/fpDUrHH1CcKTZ+Xtg WQ3xiXYW8goqgpZnn55FUbStS/mE4fTH4eQYLnfy5ETsmZCadbf8Jaut0NsYWjUUKI+NRicJDM OV0= X-IronPort-AV: E=Sophos;i="5.77,408,1596470400"; d="scan'208";a="260636279" IronPort-SDR: kkea90N4W+8JQHU/J69VoEVMKVkUY7U80uTkQ0WOAHXOYATxmzArLMYoxQhnKTL9ClKsVRUcAH i1KIuu9NDS+GN8iRWL6H/zPYbRpREFUAwJZ72i6bcFoAfXgGgZCwcIYD09TRDv1nAwqd8DkWmW JHyLHXogEtaNF96IuCue9oruDLPc5Xn3bWvpsniMaifAtiOmn8bHJC/6urlDbuv/ndXdIug3aP zFc1sbFlVdrEzM7UgRxgj/cK71HeAy/02VfSIEMnxthSTlALpecrcxp3TsLsf8swHAVcvO5vtr FbOsaR72PCfg9F39jaYOAVGt IronPort-SDR: evh9wMZ50kH5BN6mqjv/DZqfcteo6/7JSbAHDBpKNoJ4XN+OF1OHFs8Pgf5+5/LxnEsrQgnxr7 Hzq7UIOKGHtr+9vlc36tTDXZEywuhK83OGh66oX8lhOYiNcr/GgfzoPAr1WG6UCN8RCBjgmyCn Dp1sx7S4uT0DVoYMg6x0IFzLSQa2gqWCVdXYM8Y0z6fdGgcyKtIMkVzcgah2xGom+MepsxgHz0 MKHNtferLn5qvghSr0Ht9mBwlXkvBtTSTCIwXCXbxBZ4Bqq3JAny04pFtc4X7dV1ptPzr6sZYp Wj0= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 4/5] target/riscv: Remove the hyp load and store functions Date: Fri, 23 Oct 2020 08:26:10 -0700 Message-Id: <86ffdfec0896d397154ce1481417b424cb194119.1603466725.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=558518344=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/23 11:37:20 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, richard.henderson@linaro.org, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Remove the special Virtulisation load and store functions and just use the standard tcg tcg_gen_qemu_ld_tl() and tcg_gen_qemu_st_tl() functions instead. As part of this change we ensure we still run an access check to make sure we can perform the operations. Signed-off-by: Alistair Francis --- target/riscv/helper.h | 3 +- target/riscv/op_helper.c | 72 +-------------- target/riscv/insn_trans/trans_rvh.c.inc | 111 +++++++----------------- 3 files changed, 35 insertions(+), 151 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 4b690147fb..7dbdd117d2 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -81,8 +81,7 @@ DEF_HELPER_1(tlb_flush, void, env) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) -DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl) -DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl) +DEF_HELPER_1(hyp_access_check, void, env) DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) #endif =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 556a23f031..95281db3ec 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -230,82 +230,12 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } =20 -target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, - target_ulong attrs, target_ulong memop) +void helper_hyp_access_check(CPURISCVState *env) { if (env->priv =3D=3D PRV_M || (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { - target_ulong pte; - int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; - - switch (memop) { - case MO_SB: - pte =3D cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_UB: - pte =3D cpu_ldub_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TESW: - pte =3D cpu_ldsw_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEUW: - pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TESL: - pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEUL: - pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEQ: - pte =3D cpu_ldq_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - default: - g_assert_not_reached(); - } - - return pte; - } - - if (riscv_cpu_virt_enabled(env)) { - riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); - } else { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } - return 0; -} - -void helper_hyp_store(CPURISCVState *env, target_ulong address, - target_ulong val, target_ulong attrs, target_ulong m= emop) -{ - if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; - - switch (memop) { - case MO_SB: - case MO_UB: - cpu_stb_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - case MO_TESW: - case MO_TEUW: - cpu_stw_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - case MO_TESL: - case MO_TEUL: - cpu_stl_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - case MO_TEQ: - cpu_stq_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - default: - g_assert_not_reached(); - } - return; } =20 diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index 881c9ef4d2..79968701e9 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -22,20 +22,16 @@ static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_SB); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_SB); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -48,20 +44,16 @@ static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESW); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TESW); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -74,20 +66,16 @@ static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESL); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TESL); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -100,20 +88,16 @@ static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu= *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_UB); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_UB); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -126,20 +110,15 @@ static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_h= u *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); =20 - gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUW); + gen_helper_hyp_access_check(cpu_env); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_get_gpr(t0, a->rs1); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEUW); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -152,20 +131,16 @@ static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_SB); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_SB); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -178,20 +153,16 @@ static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESW); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TESW); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -204,20 +175,16 @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESL); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TESL); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -231,20 +198,16 @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_w= u *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUL); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEUL); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -257,20 +220,16 @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEQ); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEQ); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -283,20 +242,16 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + gen_helper_hyp_access_check(cpu_env); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEQ); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TEQ); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; --=20 2.28.0 From nobody Thu May 2 05:02:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="260636284" IronPort-SDR: 57ls42kE9sR7HTXaKorJXBclfpOz2fCLH0sDMSwXva5eMzK9HqeEID8VUgCmpePthKtYdBA1Nr 0iTmy7Eolm5ZfKaVjRs4wZVLv1c/vxYyDG/QS14/IzaNYOiQ3EyiFF3O5bi/ptdU2Lk8dlEa/v 2ojF5xbAxOGRY4gtXyAdE+bWL5/O9qCshxMmLQmJZ2Ef1qN1ra84T6bxdZUOd3fQT2SCvWciji i8J1vSAf15NHvDIRwbjLO7IRwEXUeRpBzaLqOfDLfzDMC90E/3jHz9CFS4bC4+x21wRfsa7z45 T+lkquuGp0yBcRyli6FzRv59 IronPort-SDR: oU2wtARq1RddWBFXtDA2OPRyAOXHq2ihqRC4UgEhQROnXM2boXaZeS18aRXfb6UhEe3LnZ7HQC WwIvy2BmaAQEoRXd5PctQ1GqWfX55uGO4BYE7OAOV9jcH0m1ub1TUeEq5e04n6JTRH7GgQ4/hD ZEhX0mDTaTRrt9gyzYdqdvmG3UBW8s716x0gTSXnzbLuSZFW6LCnP/y7bBxAmUdein85k7Mkte 1cQy76l8HBko15JS2WeVxle2mspk0KGkxRJVHukkIvhSIZtiXN5Co8rJMPOMfEi+noXdWKI5Bg Xk8= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 5/5] target/riscv: Split the Hypervisor execute load helpers Date: Fri, 23 Oct 2020 08:26:13 -0700 Message-Id: <0baa57b4d690d5022bbfe488b93d1a7e552ae7a1.1603466725.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Split the hypervisor execute load functions into two seperate functions. This avoids us having to pass the memop to the C helper functions. Signed-off-by: Alistair Francis --- target/riscv/helper.h | 3 +- target/riscv/op_helper.c | 38 ++++++++++++++----------- target/riscv/insn_trans/trans_rvh.c.inc | 16 ++--------- 3 files changed, 26 insertions(+), 31 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 7dbdd117d2..ae50730273 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -82,7 +82,8 @@ DEF_HELPER_1(tlb_flush, void, env) DEF_HELPER_1(hyp_tlb_flush, void, env) DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) DEF_HELPER_1(hyp_access_check, void, env) -DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) +DEF_HELPER_2(hyp_hlvx_hu, tl, env, tl) +DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl) #endif =20 /* Vector functions */ diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 95281db3ec..065aa57d97 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -246,28 +246,34 @@ void helper_hyp_access_check(CPURISCVState *env) } } =20 -target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, - target_ulong attrs, target_ulong memop) +target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address) { if (env->priv =3D=3D PRV_M || (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { - target_ulong pte; - int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; - - switch (memop) { - case MO_TEUW: - pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEUL: - pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - default: - g_assert_not_reached(); - } + int mmu_idx =3D cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCES= S_MASK; + + return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); + } + + if (riscv_cpu_virt_enabled(env)) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); + } else { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + return 0; +} + +target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address) +{ + if (env->priv =3D=3D PRV_M || + (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + int mmu_idx =3D cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCES= S_MASK; =20 - return pte; + return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); } =20 if (riscv_cpu_virt_enabled(env)) { diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index 79968701e9..f3ffd742d3 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -265,20 +265,14 @@ static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx= _hu *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUW); =20 - gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_helper_hyp_hlvx_hu(t1, cpu_env, t0); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -291,20 +285,14 @@ static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx= _wu *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUL); =20 - gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_helper_hyp_hlvx_wu(t1, cpu_env, t0); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; --=20 2.28.0