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charset="utf-8" Allow the user to specify the main application CPU for the sifive_u machine. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Palmer Dabbelt Tested-by: Bin Meng --- include/hw/riscv/sifive_u.h | 1 + hw/riscv/sifive_u.c | 18 +++++++++++++----- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 22e7e6efa1..a9f7b4a084 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -48,6 +48,7 @@ typedef struct SiFiveUSoCState { CadenceGEMState gem; =20 uint32_t serial; + char *cpu_type; } SiFiveUSoCState; =20 #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6ad975d692..5f3ad9bc0f 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -424,6 +424,8 @@ static void sifive_u_machine_init(MachineState *machine) object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_= SOC); object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, &error_abort); + object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, + &error_abort); qdev_realize(DEVICE(&s->soc), NULL, &error_abort); =20 /* register RAM */ @@ -590,6 +592,11 @@ static void sifive_u_machine_class_init(ObjectClass *o= c, void *data) mc->init =3D sifive_u_machine_init; mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; +#if defined(TARGET_RISCV32) + mc->default_cpu_type =3D TYPE_RISCV_CPU_SIFIVE_U34; +#elif defined(TARGET_RISCV64) + mc->default_cpu_type =3D TYPE_RISCV_CPU_SIFIVE_U54; +#endif mc->default_cpus =3D mc->min_cpus; =20 object_class_property_add_bool(oc, "start-in-flash", @@ -618,7 +625,6 @@ type_init(sifive_u_machine_init_register_types) =20 static void sifive_u_soc_instance_init(Object *obj) { - MachineState *ms =3D MACHINE(qdev_get_machine()); SiFiveUSoCState *s =3D RISCV_U_SOC(obj); =20 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUS= TER); @@ -636,10 +642,6 @@ static void sifive_u_soc_instance_init(Object *obj) =20 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, TYPE_RISCV_HART_ARRAY); - qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1= ); - qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); - qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU); - qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); =20 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); @@ -661,6 +663,11 @@ static void sifive_u_soc_realize(DeviceState *dev, Err= or **errp) int i; NICInfo *nd =3D &nd_table[0]; =20 + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1= ); + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); + qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); + qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); + sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); /* @@ -792,6 +799,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) =20 static Property sifive_u_soc_props[] =3D { DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), + DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), DEFINE_PROP_END_OF_LIST() }; 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charset="utf-8" Instead of returning the unused entry address from riscv_load_firmware() instead return the end address. Also return the end address from riscv_find_and_load_firmware(). This tells the caller if a firmware was loaded and how big it is. This can be used to determine the load address of the next image (usually the kernel). Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Palmer Dabbelt Tested-by: Bin Meng --- include/hw/riscv/boot.h | 8 ++++---- hw/riscv/boot.c | 28 +++++++++++++++++----------- 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 451338780a..0acbd8aa6e 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -23,10 +23,10 @@ #include "exec/cpu-defs.h" #include "hw/loader.h" =20 -void riscv_find_and_load_firmware(MachineState *machine, - const char *default_machine_firmware, - hwaddr firmware_load_addr, - symbol_fn_t sym_cb); +target_ulong riscv_find_and_load_firmware(MachineState *machine, + const char *default_machine_firm= ware, + hwaddr firmware_load_addr, + symbol_fn_t sym_cb); char *riscv_find_firmware(const char *firmware_filename); target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 21adaae56e..fa699308a0 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -40,12 +40,13 @@ #define fw_dynamic_info_data(__val) cpu_to_le64(__val) #endif =20 -void riscv_find_and_load_firmware(MachineState *machine, - const char *default_machine_firmware, - hwaddr firmware_load_addr, - symbol_fn_t sym_cb) +target_ulong riscv_find_and_load_firmware(MachineState *machine, + const char *default_machine_firm= ware, + hwaddr firmware_load_addr, + symbol_fn_t sym_cb) { char *firmware_filename =3D NULL; + target_ulong firmware_end_addr =3D firmware_load_addr; =20 if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) { /* @@ -60,9 +61,12 @@ void riscv_find_and_load_firmware(MachineState *machine, =20 if (firmware_filename) { /* If not "none" load the firmware */ - riscv_load_firmware(firmware_filename, firmware_load_addr, sym_cb); + firmware_end_addr =3D riscv_load_firmware(firmware_filename, + firmware_load_addr, sym_cb= ); g_free(firmware_filename); } + + return firmware_end_addr; } =20 char *riscv_find_firmware(const char *firmware_filename) @@ -91,17 +95,19 @@ target_ulong riscv_load_firmware(const char *firmware_f= ilename, hwaddr firmware_load_addr, symbol_fn_t sym_cb) { - uint64_t firmware_entry; + uint64_t firmware_entry, firmware_size, firmware_end; =20 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, - &firmware_entry, NULL, NULL, NULL, + &firmware_entry, NULL, &firmware_end, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - return firmware_entry; + return firmware_end; } =20 - if (load_image_targphys_as(firmware_filename, firmware_load_addr, - ram_size, NULL) > 0) { - return firmware_load_addr; + firmware_size =3D load_image_targphys_as(firmware_filename, + firmware_load_addr, ram_size, N= ULL); + + if (firmware_size > 0) { + return firmware_load_addr + firmware_size; } =20 error_report("could not load firmware '%s'", firmware_filename); --=20 2.28.0 From nobody Sun May 19 13:34:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1602635628; cv=none; d=zohomail.com; s=zohoarc; b=ZOwfDb0a2INv94Wdy+lckvGwUyQndsLMCkYNDIVoZ+rlJMhsHucPf7TUfV5dpqrSpx7WLa+WEn8TPUqzN7Py3D65N/mK0lt6RvtDHUo+uS4YiWBHd9On7zeQiQDY+FZ+NAKBHdPKdmqNBNV7hGrw+psuB20DMCDjz+qlbwjht+Y= ARC-Message-Signature: i=1; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Palmer Dabbelt Tested-by: Bin Meng --- include/hw/riscv/boot.h | 2 ++ hw/riscv/boot.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 0acbd8aa6e..2975ed1a31 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -23,6 +23,8 @@ #include "exec/cpu-defs.h" #include "hw/loader.h" =20 +bool riscv_is_32_bit(MachineState *machine); + target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firm= ware, hwaddr firmware_load_addr, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index fa699308a0..5dea644f47 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -40,6 +40,15 @@ #define fw_dynamic_info_data(__val) cpu_to_le64(__val) #endif =20 +bool riscv_is_32_bit(MachineState *machine) +{ + if (!strncmp(machine->cpu_type, "rv32", 4)) { + return true; + } else { + return false; + } +} + target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firm= ware, hwaddr firmware_load_addr, --=20 2.28.0 From nobody Sun May 19 13:34:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Instead of loading the kernel at a hardcoded start address, let's load the kernel at the next alligned address after the end of the firmware. This should have no impact for current users of OpenSBI, but will allow loading a noMMU kernel at the start of memory. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Palmer Dabbelt Tested-by: Bin Meng --- include/hw/riscv/boot.h | 3 +++ hw/riscv/boot.c | 19 ++++++++++++++----- hw/riscv/opentitan.c | 3 ++- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 10 ++++++++-- hw/riscv/spike.c | 11 ++++++++--- hw/riscv/virt.c | 11 ++++++++--- 7 files changed, 45 insertions(+), 15 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 2975ed1a31..0b01988727 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -25,6 +25,8 @@ =20 bool riscv_is_32_bit(MachineState *machine); =20 +target_ulong riscv_calc_kernel_start_addr(MachineState *machine, + target_ulong firmware_end_addr); target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firm= ware, hwaddr firmware_load_addr, @@ -34,6 +36,7 @@ target_ulong riscv_load_firmware(const char *firmware_fil= ename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); target_ulong riscv_load_kernel(const char *kernel_filename, + target_ulong firmware_end_addr, symbol_fn_t sym_cb); hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, uint64_t kernel_entry, hwaddr *start); diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 5dea644f47..9b3fe3fb1e 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -33,10 +33,8 @@ #include =20 #if defined(TARGET_RISCV32) -# define KERNEL_BOOT_ADDRESS 0x80400000 #define fw_dynamic_info_data(__val) cpu_to_le32(__val) #else -# define KERNEL_BOOT_ADDRESS 0x80200000 #define fw_dynamic_info_data(__val) cpu_to_le64(__val) #endif =20 @@ -49,6 +47,15 @@ bool riscv_is_32_bit(MachineState *machine) } } =20 +target_ulong riscv_calc_kernel_start_addr(MachineState *machine, + target_ulong firmware_end_addr) { + if (riscv_is_32_bit(machine)) { + return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); + } else { + return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); + } +} + target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firm= ware, hwaddr firmware_load_addr, @@ -123,7 +130,9 @@ target_ulong riscv_load_firmware(const char *firmware_f= ilename, exit(1); } =20 -target_ulong riscv_load_kernel(const char *kernel_filename, symbol_fn_t sy= m_cb) +target_ulong riscv_load_kernel(const char *kernel_filename, + target_ulong kernel_start_addr, + symbol_fn_t sym_cb) { uint64_t kernel_entry; =20 @@ -138,9 +147,9 @@ target_ulong riscv_load_kernel(const char *kernel_filen= ame, symbol_fn_t sym_cb) return kernel_entry; } =20 - if (load_image_targphys_as(kernel_filename, KERNEL_BOOT_ADDRESS, + if (load_image_targphys_as(kernel_filename, kernel_start_addr, ram_size, NULL) > 0) { - return KERNEL_BOOT_ADDRESS; + return kernel_start_addr; } =20 error_report("could not load kernel '%s'", kernel_filename); diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 0531bd879b..cc758b78b8 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -75,7 +75,8 @@ static void opentitan_board_init(MachineState *machine) } =20 if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, NULL); + riscv_load_kernel(machine->kernel_filename, + memmap[IBEX_DEV_RAM].base, NULL); } } =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index fcfac16816..59bac4cc9a 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_m= emory); =20 if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, NULL); + riscv_load_kernel(machine->kernel_filename, + memmap[SIFIVE_E_DEV_DTIM].base, NULL); } } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 5f3ad9bc0f..b2472c6627 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -415,6 +415,7 @@ static void sifive_u_machine_init(MachineState *machine) MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *flash0 =3D g_new(MemoryRegion, 1); target_ulong start_addr =3D memmap[SIFIVE_U_DEV_DRAM].base; + target_ulong firmware_end_addr, kernel_start_addr; uint32_t start_addr_hi32 =3D 0x00000000; int i; uint32_t fdt_load_addr; @@ -474,10 +475,15 @@ static void sifive_u_machine_init(MachineState *machi= ne) break; } =20 - riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL); + firmware_end_addr =3D riscv_find_and_load_firmware(machine, BIOS_FILEN= AME, + start_addr, NULL); =20 if (machine->kernel_filename) { - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, NULL); + kernel_start_addr =3D riscv_calc_kernel_start_addr(machine, + firmware_end_addr= ); + + kernel_entry =3D riscv_load_kernel(machine->kernel_filename, + kernel_start_addr, NULL); =20 if (machine->initrd_filename) { hwaddr start; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 3fd152a035..facac6e7d2 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -195,6 +195,7 @@ static void spike_board_init(MachineState *machine) MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); + target_ulong firmware_end_addr, kernel_start_addr; uint32_t fdt_load_addr; uint64_t kernel_entry; char *soc_name; @@ -261,12 +262,16 @@ static void spike_board_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, mask_rom); =20 - riscv_find_and_load_firmware(machine, BIOS_FILENAME, - memmap[SPIKE_DRAM].base, - htif_symbol_callback); + firmware_end_addr =3D riscv_find_and_load_firmware(machine, BIOS_FILEN= AME, + memmap[SPIKE_DRAM].ba= se, + htif_symbol_callback); =20 if (machine->kernel_filename) { + kernel_start_addr =3D riscv_calc_kernel_start_addr(machine, + firmware_end_addr= ); + kernel_entry =3D riscv_load_kernel(machine->kernel_filename, + kernel_start_addr, htif_symbol_callback); =20 if (machine->initrd_filename) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 41bd2f38ba..6bfd10dfc7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -493,6 +493,7 @@ static void virt_machine_init(MachineState *machine) char *plic_hart_config, *soc_name; size_t plic_hart_config_len; target_ulong start_addr =3D memmap[VIRT_DRAM].base; + target_ulong firmware_end_addr, kernel_start_addr; uint32_t fdt_load_addr; uint64_t kernel_entry; DeviceState *mmio_plic, *virtio_plic, *pcie_plic; @@ -602,11 +603,15 @@ static void virt_machine_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, mask_rom); =20 - riscv_find_and_load_firmware(machine, BIOS_FILENAME, - memmap[VIRT_DRAM].base, NULL); + firmware_end_addr =3D riscv_find_and_load_firmware(machine, BIOS_FILEN= AME, + start_addr, NULL); =20 if (machine->kernel_filename) { - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, NULL); + kernel_start_addr =3D riscv_calc_kernel_start_addr(machine, + firmware_end_addr= ); + + kernel_entry =3D riscv_load_kernel(machine->kernel_filename, + kernel_start_addr, NULL); =20 if (machine->initrd_filename) { hwaddr start; --=20 2.28.0