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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 62fe1ecc8f..eda7057663 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -435,7 +435,7 @@ restart: hwaddr vbase; =20 /* Do the second stage translation on the base PTE address. */ - get_physical_address(env, &vbase, &vbase_prot, base, access_ty= pe, + get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_= LOAD, mmu_idx, false, true); =20 pte_addr =3D vbase + idx * ptesize; --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu_helper.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index eda7057663..75d2ae3434 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -435,8 +435,13 @@ restart: hwaddr vbase; =20 /* Do the second stage translation on the base PTE address. */ - get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_= LOAD, - mmu_idx, false, true); + int vbase_ret =3D get_physical_address(env, &vbase, &vbase_pro= t, + base, MMU_DATA_LOAD, + mmu_idx, false, true); + + if (vbase_ret !=3D TRANSLATE_SUCCESS) { + return vbase_ret; + } =20 pte_addr =3D vbase + idx * ptesize; } else { --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="139561719" IronPort-SDR: 4ezoAGmnmxzKeGIsjArcyHebTMfjmhhuWpCDtpBjdNsTEwpFkoVquKyURF59+xRfpLKVnm/Jyb oTpJjcw3LhCfR+LEBHcquWjLDOPMZxE48= IronPort-SDR: OfjdVt6DP7XW5KtHbDZsg517s4BenlBI/FRIkJyMUDrPpsVcPHS/aD6SA/t44VibPTBhjGGYQU eOvjVAR7AKYg== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 03/17] target/riscv: Move the hfence instructions to the rvh decode Date: Thu, 4 Jun 2020 18:20:50 -0700 Message-Id: <6f88ddc816f7828e4b58acc82e3e4b61bd86e158.1591319882.git.alistair@alistair23.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=4185f83b6=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/04 21:29:30 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, anup.pate@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Also correct the name of the VVMA instruction. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 8 ++- .../riscv/insn_trans/trans_privileged.inc.c | 38 ------------- target/riscv/insn_trans/trans_rvh.inc.c | 57 +++++++++++++++++++ target/riscv/translate.c | 1 + 4 files changed, 63 insertions(+), 41 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvh.inc.c diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b883672e63..4c8d1215ce 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -64,7 +64,7 @@ @r2 ....... ..... ..... ... ..... ....... %rs1 %rd =20 @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 -@hfence_bvma ....... ..... ..... ... ..... ....... %rs2 %rs1 +@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1 =20 @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @@ -77,8 +77,6 @@ uret 0000000 00010 00000 000 00000 1110011 sret 0001000 00010 00000 000 00000 1110011 mret 0011000 00010 00000 000 00000 1110011 wfi 0001000 00101 00000 000 00000 1110011 -hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma -hfence_bvma 0010001 ..... ..... 000 00000 1110011 @hfence_bvma sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm =20 @@ -207,3 +205,7 @@ fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm + +# *** RV32H Base Instruction Set *** +hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma +hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/= insn_trans/trans_privileged.inc.c index 5f26e0f5ea..2a61a853bf 100644 --- a/target/riscv/insn_trans/trans_privileged.inc.c +++ b/target/riscv/insn_trans/trans_privileged.inc.c @@ -95,41 +95,3 @@ static bool trans_sfence_vm(DisasContext *ctx, arg_sfenc= e_vm *a) { return false; } - -static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) -{ -#ifndef CONFIG_USER_ONLY - if (has_ext(ctx, RVH)) { - /* Hpervisor extensions exist */ - /* - * if (env->priv =3D=3D PRV_M || - * (env->priv =3D=3D PRV_S && - * !riscv_cpu_virt_enabled(env) && - * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { - */ - gen_helper_tlb_flush(cpu_env); - return true; - /* } */ - } -#endif - return false; -} - -static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a) -{ -#ifndef CONFIG_USER_ONLY - if (has_ext(ctx, RVH)) { - /* Hpervisor extensions exist */ - /* - * if (env->priv =3D=3D PRV_M || - * (env->priv =3D=3D PRV_S && - * !riscv_cpu_virt_enabled(env) && - * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { - */ - gen_helper_tlb_flush(cpu_env); - return true; - /* } */ - } -#endif - return false; -} diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_tr= ans/trans_rvh.inc.c new file mode 100644 index 0000000000..2c0359819d --- /dev/null +++ b/target/riscv/insn_trans/trans_rvh.inc.c @@ -0,0 +1,57 @@ +/* + * RISC-V translation routines for the RVXI Base Integer Instruction Set. + * + * Copyright (c) 2020 Western Digital + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) +{ +#ifndef CONFIG_USER_ONLY + if (ctx->priv_ver >=3D PRIV_VERSION_1_10_0 && + has_ext(ctx, RVH)) { + /* Hpervisor extensions exist */ + /* + * if (env->priv =3D=3D PRV_M || + * (env->priv =3D=3D PRV_S && + * !riscv_cpu_virt_enabled(env) && + * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { + */ + gen_helper_tlb_flush(cpu_env); + return true; + /* } */ + } +#endif + return false; +} + +static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a) +{ +#ifndef CONFIG_USER_ONLY + if (ctx->priv_ver >=3D PRIV_VERSION_1_10_0 && + has_ext(ctx, RVH)) { + /* Hpervisor extensions exist */ + /* + * if (env->priv =3D=3D PRV_M || + * (env->priv =3D=3D PRV_S && + * !riscv_cpu_virt_enabled(env) && + * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { + */ + gen_helper_tlb_flush(cpu_env); + return true; + /* } */ + } +#endif + return false; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 43bf7e39a6..ce71ca7a92 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -711,6 +711,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, #include "insn_trans/trans_rva.inc.c" #include "insn_trans/trans_rvf.inc.c" #include "insn_trans/trans_rvd.inc.c" +#include "insn_trans/trans_rvh.inc.c" #include "insn_trans/trans_privileged.inc.c" =20 /* Include the auto-generated decoder for 16 bit insn */ --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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IronPort-SDR: jT8YayPcgiSI27bsTQE9+yg7vWRCKDdSzCO3QddPlkvPDMkG4strU4N6CcK362H7Ftm4xfQYzT /nwzB1WERjBEunDtVsAl7enjRAXotndVooBJLY5ONJzMS6UGWwuG3FXJ3RMb06P7tjxzI+A+00 cotCVjvnofPbbaBYpc1mBUzIX1AQkJ2V80r5315OS+FSi8RFkWFYhITCR0UgIv4hZ3dDjtVAKK EJ0RSDjEnlwbNqlw9/OGgVUEHgcuQvnDNKfwOWfyt7IONxcF55nvoRNWDvariu0pzACV67BBEh GO8= X-IronPort-AV: E=Sophos;i="5.73,474,1583164800"; d="scan'208";a="143573555" IronPort-SDR: rBLSyOicbtdmiqXN5beUek44QVsOzgtClvBpqt2+ThmKJ9jusY+rWQ0d2Hvo/r6f2nEEsegdbw 2P9j9Kzy5YntNLWca3Qjg009dTAxgqHZE= IronPort-SDR: C8vJXJw4ijA4hUhRonxqTv1WJ+xqP0L72uqueMoTsO4V4bWWwfe41zV+vNfm/VYBXZZkVsjoXp /UBo0VD0MCKQ== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 04/17] target/riscv: Implement checks for hfence Date: Thu, 4 Jun 2020 18:20:53 -0700 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Call the helper_hyp_tlb_flush() function on hfence instructions which will generate an illegal insruction execption if we don't have permission to flush the Hypervisor level TLBs. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 ++++ target/riscv/insn_trans/trans_rvh.inc.c | 32 +++++-------------------- target/riscv/op_helper.c | 13 ++++++++++ 3 files changed, 24 insertions(+), 26 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index debb22a480..b36be978d5 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -76,3 +76,8 @@ DEF_HELPER_2(mret, tl, env, tl) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) #endif + +/* Hypervisor functions */ +#ifndef CONFIG_USER_ONLY +DEF_HELPER_1(hyp_tlb_flush, void, env) +#endif diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_tr= ans/trans_rvh.inc.c index 2c0359819d..263b652d90 100644 --- a/target/riscv/insn_trans/trans_rvh.inc.c +++ b/target/riscv/insn_trans/trans_rvh.inc.c @@ -18,40 +18,20 @@ =20 static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) { + REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY - if (ctx->priv_ver >=3D PRIV_VERSION_1_10_0 && - has_ext(ctx, RVH)) { - /* Hpervisor extensions exist */ - /* - * if (env->priv =3D=3D PRV_M || - * (env->priv =3D=3D PRV_S && - * !riscv_cpu_virt_enabled(env) && - * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { - */ - gen_helper_tlb_flush(cpu_env); - return true; - /* } */ - } + gen_helper_hyp_tlb_flush(cpu_env); + return true; #endif return false; } =20 static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a) { + REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY - if (ctx->priv_ver >=3D PRIV_VERSION_1_10_0 && - has_ext(ctx, RVH)) { - /* Hpervisor extensions exist */ - /* - * if (env->priv =3D=3D PRV_M || - * (env->priv =3D=3D PRV_S && - * !riscv_cpu_virt_enabled(env) && - * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { - */ - gen_helper_tlb_flush(cpu_env); - return true; - /* } */ - } + gen_helper_hyp_tlb_flush(cpu_env); + return true; #endif return false; } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index b0c49efc4a..7cccd42a1e 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -194,4 +194,17 @@ void helper_tlb_flush(CPURISCVState *env) } } =20 +void helper_hyp_tlb_flush(CPURISCVState *env) +{ + CPUState *cs =3D env_cpu(env); + + if (env->priv =3D=3D PRV_M || + (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env))) { + tlb_flush(cs); + return; + } + + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); +} + #endif /* !CONFIG_USER_ONLY */ --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1591320809; cv=none; d=zohomail.com; s=zohoarc; b=BWvzdmItp3fWAXv50qkb7RSRWOopJEaa+F/yCWsaO3eTaEI3lNtgVPC+66tI9OZsMoI5ffbjtO+QR59V9mIu3e64ldp3onjEUWYc+PO8de5b4OH1wW9NDXcDjglzoCUpdGZctNZWt8V93B26ioiQCbu+HYe3m3mLtcb/SDQH/qQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591320809; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 18 ++++++++++++++++++ 3 files changed, 21 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 80569f0d44..93ae472490 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -295,6 +295,8 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); +bool riscv_cpu_two_stage_lookup(CPURISCVState *env); +void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7f64ee1174..f52711ac32 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -452,6 +452,7 @@ * page table fault. */ #define FORCE_HS_EXCEP 2 +#define HS_TWO_STAGE 4 =20 /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 75d2ae3434..68abccc993 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -220,6 +220,24 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, = bool enable) env->virt =3D set_field(env->virt, FORCE_HS_EXCEP, enable); } =20 +bool riscv_cpu_two_stage_lookup(CPURISCVState *env) +{ + if (!riscv_has_ext(env, RVH)) { + return false; + } + + return get_field(env->virt, HS_TWO_STAGE); +} + +void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + env->virt =3D set_field(env->virt, HS_TWO_STAGE, enable); +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env =3D &cpu->env; --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1591320937; cv=none; d=zohomail.com; s=zohoarc; b=WT67t5dzB24A3JoptQYbUbbvew45Hj/KE2uf8rM5eB81wuEm1/2HJBtMq2OtAMPgi5uYz9LY91MW9Ps1ZU8tKtwD7m0i9zElcZDzAu5NpK0nkosm8oSY5KZD0t3y/856oimpraT/YqLksh3KiD2T+TpyJySz8VPgofhTo8s6RQY= ARC-Message-Signature: i=1; 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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/helper.h | 3 + target/riscv/insn32-64.decode | 5 + target/riscv/insn32.decode | 11 + target/riscv/insn_trans/trans_rvh.inc.c | 340 ++++++++++++++++++++++++ target/riscv/op_helper.c | 114 ++++++++ 6 files changed, 474 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f52711ac32..bb4ee3fc35 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -428,6 +428,7 @@ #define HSTATUS_SP2V 0x00000200 #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTSR 0x00400000 +#define HSTATUS_HU 0x00000200 =20 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b36be978d5..d020d1459c 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -80,4 +80,7 @@ DEF_HELPER_1(tlb_flush, void, env) /* Hypervisor functions */ #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) +DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl) +DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl) +DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) #endif diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 380bf791bc..24feef4e0f 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -70,3 +70,8 @@ fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 + +# *** RV32H Base Instruction Set *** +hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 +hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 +hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4c8d1215ce..18bbe08ebb 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -62,6 +62,7 @@ @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd @r2 ....... ..... ..... ... ..... ....... %rs1 %rd +@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 =20 @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 @hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1 @@ -207,5 +208,15 @@ fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_= rm fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm =20 # *** RV32H Base Instruction Set *** +hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2 +hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2 +hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2 +hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2 +hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2 +hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2 +hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2 +hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s +hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s +hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_tr= ans/trans_rvh.inc.c index 263b652d90..db650ae62a 100644 --- a/target/riscv/insn_trans/trans_rvh.inc.c +++ b/target/riscv/insn_trans/trans_rvh.inc.c @@ -16,6 +16,346 @@ * this program. If not, see . */ =20 +static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_SB); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESW); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESL); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_UB); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUW); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv dat =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_SB); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv dat =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESW); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv dat =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESL); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +#ifdef TARGET_RISCV64 +static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUL); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEQ); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv dat =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEQ); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} +#endif + +static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUW); + + gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUL); + + gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) { REQUIRE_EXT(ctx, RVH); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 7cccd42a1e..e0053699cc 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -207,4 +207,118 @@ void helper_hyp_tlb_flush(CPURISCVState *env) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 +target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, + target_ulong attrs, target_ulong memop) +{ + if (env->priv =3D=3D PRV_M || + (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + target_ulong pte; + + riscv_cpu_set_two_stage_lookup(env, true); + + switch (memop) { + case MO_SB: + pte =3D cpu_ldsb_data(env, address); + break; + case MO_UB: + pte =3D cpu_ldub_data(env, address); + break; + case MO_TESW: + pte =3D cpu_ldsw_data(env, address); + break; + case MO_TEUW: + pte =3D cpu_lduw_data(env, address); + break; + case MO_TESL: + pte =3D cpu_ldl_data(env, address); + break; + case MO_TEUL: + pte =3D cpu_ldl_data(env, address); + break; + case MO_TEQ: + pte =3D cpu_ldq_data(env, address); + break; + default: + g_assert_not_reached(); + } + + riscv_cpu_set_two_stage_lookup(env, false); + + return pte; + } + + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + return 0; +} + +void helper_hyp_store(CPURISCVState *env, target_ulong address, + target_ulong val, target_ulong attrs, target_ulong m= emop) +{ + if (env->priv =3D=3D PRV_M || + (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + riscv_cpu_set_two_stage_lookup(env, true); + + switch (memop) { + case MO_SB: + case MO_UB: + cpu_stb_data(env, address, val); + break; + case MO_TESW: + case MO_TEUW: + cpu_stw_data(env, address, val); + break; + case MO_TESL: + case MO_TEUL: + cpu_stl_data(env, address, val); + break; + case MO_TEQ: + cpu_stq_data(env, address, val); + break; + default: + g_assert_not_reached(); + } + + riscv_cpu_set_two_stage_lookup(env, false); + + return; + } + + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); +} + +target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, + target_ulong attrs, target_ulong memop) +{ + if (env->priv =3D=3D PRV_M || + (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + target_ulong pte; + + riscv_cpu_set_two_stage_lookup(env, true); + + switch (memop) { + case MO_TEUL: + pte =3D cpu_ldub_data(env, address); + break; + case MO_TEUW: + pte =3D cpu_lduw_data(env, address); + break; + default: + g_assert_not_reached(); + } + + riscv_cpu_set_two_stage_lookup(env, false); + + return pte; + } + + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + return 0; +} + #endif /* !CONFIG_USER_ONLY */ --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1591320931; cv=none; d=zohomail.com; s=zohoarc; b=IWwomEMSmqFhSoCRn9iF0/R8XVTsPZpaAWmktHtrPUSqCdltZIN6WPe+iV6nJeZpRUpPUcUllkpHm7WkwxImOG7/7R9AN29cSCD7Kaw1viKNGrMVGKdSrsewbdp+jC7WUksz2Zhwk7r1+8mNz9oSOzydxo1yvIO6388zF5xQIAU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591320931; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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IronPort-SDR: 1YyF/+xMDRij6uu8gfKBCDehyMpsRXc3+GDTa1shLsfy/EsT2Uz1Sxdy+tmJyHR6fRJR8Beihw yeEcCVEw5FlnB8tW6OPn7/ppHtUBrWgjhbcDdbNUuUZzs/JAYyr/HGQLg0Zul6mfbrvFUt6ExI qfwHnYz5VqgxBS5NGqpVqnwb6x8SOrh58gnagEBQRP6AWfVyRpA01v+QhSjPlkyDb59icCrB1q zvvGz8kr4M5WIDBsLGT1+fRqfNP3qmLBli59ihrPfsymhtTFxhSpdOBmENb/SOpihi5DQzDtv8 pBQ= X-IronPort-AV: E=Sophos;i="5.73,474,1583164800"; d="scan'208";a="143573564" IronPort-SDR: /tjDAdRgErrpNwtknTD/6RUkLdIB/4yiUNoJS+FtHLgErj3oslEjg6nCrc/YrikqKa+bo+hmGV W3RSDEcdMBWrDhuFqf7niQPVRg5ZBX7O8= IronPort-SDR: Ke3c3Tz71RjJOKu+buhGh2Mx2CJk4uOoMjsYP+kfoFIcjbd6YmRPSqBHwSMQbc0NFykgsPCMxG XE0PEMzqUfvg== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 07/17] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions Date: Thu, 4 Jun 2020 18:21:01 -0700 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 54 +++++++++++++++------------------------ 1 file changed, 21 insertions(+), 33 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 68abccc993..1521c14b72 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -340,22 +340,13 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, * was called. Background registers will be used if the guest has * forced a two stage translation to be on (in HS or M mode). */ + if (riscv_cpu_two_stage_lookup(env) && access_type !=3D MMU_INST_FETCH= ) { + use_background =3D true; + } + if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { if (get_field(env->mstatus, MSTATUS_MPRV)) { mode =3D get_field(env->mstatus, MSTATUS_MPP); - - if (riscv_has_ext(env, RVH) && - MSTATUS_MPV_ISSET(env)) { - use_background =3D true; - } - } - } - - if (mode =3D=3D PRV_S && access_type !=3D MMU_INST_FETCH && - riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { - if (get_field(env->hstatus, HSTATUS_SPRV)) { - mode =3D get_field(env->mstatus, SSTATUS_SPP); - use_background =3D true; } } =20 @@ -705,8 +696,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, hwaddr pa =3D 0; int prot, prot2; bool pmp_violation =3D false; - bool m_mode_two_stage =3D false; - bool hs_mode_two_stage =3D false; bool first_stage_error =3D true; int ret =3D TRANSLATE_FAIL; int mode =3D mmu_idx; @@ -716,30 +705,21 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); =20 - /* - * Determine if we are in M mode and MPRV is set or in HS mode and SPR= V is - * set and we want to access a virtulisation address. - */ - if (riscv_has_ext(env, RVH)) { - m_mode_two_stage =3D env->priv =3D=3D PRV_M && - access_type !=3D MMU_INST_FETCH && - get_field(env->mstatus, MSTATUS_MPRV) && - MSTATUS_MPV_ISSET(env); - - hs_mode_two_stage =3D env->priv =3D=3D PRV_S && - !riscv_cpu_virt_enabled(env) && - access_type !=3D MMU_INST_FETCH && - get_field(env->hstatus, HSTATUS_SPRV) && - get_field(env->hstatus, HSTATUS_SPV); - } - if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { if (get_field(env->mstatus, MSTATUS_MPRV)) { mode =3D get_field(env->mstatus, MSTATUS_MPP); } } =20 - if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_sta= ge) { + if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_M && + access_type !=3D MMU_INST_FETCH && + get_field(env->mstatus, MSTATUS_MPRV) && + MSTATUS_MPV_ISSET(env)) { + riscv_cpu_set_two_stage_lookup(env, true); + } + + if (riscv_cpu_virt_enabled(env) || + (riscv_cpu_two_stage_lookup(env) && access_type !=3D MMU_INST_FETC= H)) { /* Two stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, access_type, mmu_idx, true, true); @@ -791,6 +771,14 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, __func__, address, ret, pa, prot); } =20 + /* We did the two stage lookup based on MPRV, unset the lookup */ + if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_M && + access_type !=3D MMU_INST_FETCH && + get_field(env->mstatus, MSTATUS_MPRV) && + MSTATUS_MPV_ISSET(env)) { + riscv_cpu_set_two_stage_lookup(env, false); + } + if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret =3D=3D TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/csr.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 383be0a955..53665b0985 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -854,7 +854,6 @@ static int read_htinst(CPURISCVState *env, int csrno, t= arget_ulong *val) =20 static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) { - env->htinst =3D val; return 0; } =20 --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1591321040; cv=none; d=zohomail.com; s=zohoarc; b=Av2blbO9A11kzMMenZfpb6An7XpoH06t+33YC+Bt9P7mGEqRk9bazqVs4pU1zrENRP49uSJhaTZj2Hbm08Hn4Lw6i1s4r/4HgsMW2KZWKgTlXS3RUG/wTuxJ4/MDSQLnN3JpGLgOk/auRbbF9ijTfm87l1JskoyGcOPIEiIYdZY= ARC-Message-Signature: i=1; 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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 5 +++-- target/riscv/cpu_helper.c | 20 ++++++++++++++++---- target/riscv/csr.c | 6 +++--- 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index bb4ee3fc35..028e268faa 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -364,10 +364,10 @@ #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ #if defined(TARGET_RISCV64) -#define MSTATUS_MTL 0x4000000000ULL +#define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL #elif defined(TARGET_RISCV32) -#define MSTATUS_MTL 0x00000040 +#define MSTATUS_GVA 0x00000040 #define MSTATUS_MPV 0x00000080 #endif =20 @@ -429,6 +429,7 @@ #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTSR 0x00400000 #define HSTATUS_HU 0x00000200 +#define HSTATUS_GVA 0x00000040 =20 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1521c14b72..3b1a2f75ca 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -892,6 +892,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_has_ext(env, RVH)) { target_ulong hdeleg =3D async ? env->hideleg : env->hedeleg; =20 + if (riscv_cpu_virt_enabled(env) && tval) { + /* + * If we are writing a guest virtual address to stval, set + * this to 1. If we are trapping to VS we will set this to= 0 + * later. + */ + env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 1); + } + if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && !force_hs_execp) { /* @@ -902,6 +911,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) cause =3D=3D IRQ_VS_EXT) cause =3D cause - 1; /* Trap to VS mode */ + env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 0); } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ riscv_cpu_swap_hypervisor_regs(env); @@ -950,13 +960,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) #ifdef TARGET_RISCV32 env->mstatush =3D set_field(env->mstatush, MSTATUS_MPV, riscv_cpu_virt_enabled(env)); - env->mstatush =3D set_field(env->mstatush, MSTATUS_MTL, - riscv_cpu_force_hs_excep_enabled(en= v)); + if (riscv_cpu_virt_enabled(env) && tval) { + env->mstatush =3D set_field(env->mstatush, MSTATUS_GVA, 1); + } #else env->mstatus =3D set_field(env->mstatus, MSTATUS_MPV, riscv_cpu_virt_enabled(env)); - env->mstatus =3D set_field(env->mstatus, MSTATUS_MTL, - riscv_cpu_force_hs_excep_enabled(env= )); + if (riscv_cpu_virt_enabled(env) && tval) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_GVA, 1); + } #endif =20 mtval2 =3D env->guest_phys_fault_addr; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 53665b0985..69a3c8379c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -335,10 +335,10 @@ static int write_mstatus(CPURISCVState *env, int csrn= o, target_ulong val) MSTATUS_TW; #if defined(TARGET_RISCV64) /* - * RV32: MPV and MTL are not in mstatus. The current plan is to + * RV32: MPV and GVA are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. */ - mask |=3D MSTATUS_MTL | MSTATUS_MPV; + mask |=3D MSTATUS_MPV | MSTATUS_GVA; #endif =20 mstatus =3D (mstatus & ~mask) | (val & mask); @@ -364,7 +364,7 @@ static int write_mstatush(CPURISCVState *env, int csrno= , target_ulong val) tlb_flush(env_cpu(env)); } =20 - val &=3D MSTATUS_MPV | MSTATUS_MTL; + val &=3D MSTATUS_MPV | MSTATUS_GVA; =20 env->mstatush =3D val; =20 --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1591321162; cv=none; d=zohomail.com; s=zohoarc; b=aInxz3xpno1mibLJEIPpFvZfC568cLNEYdyn6uWuA1Lo6uZLX+sXXX9oHVip/FstNJVyhUKJ8Hrt9ee3uTT2BFf9nnnwV1ekRHAK3Q+kkt5anJO3s/AoHJuhkcZNAwZVzhRlL2gKwMpSae8tUj85o6HxdcEpRm0x2irBulo3xB4= ARC-Message-Signature: i=1; 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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3b1a2f75ca..4ea39d5641 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -903,14 +903,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && !force_hs_execp) { + /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode inte= rrupt * no if hypervisor has delegated one of hs mode's interru= pt */ if (cause =3D=3D IRQ_VS_TIMER || cause =3D=3D IRQ_VS_SOFT = || - cause =3D=3D IRQ_VS_EXT) + cause =3D=3D IRQ_VS_EXT) { cause =3D cause - 1; - /* Trap to VS mode */ + } env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 0); } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1591320802; cv=none; d=zohomail.com; s=zohoarc; b=cZJEymJIWlstLtYNsGc2K+3etwS5K7WNuIGGpCCpg4chY9Np4Qp5SdGd/BdBfCKPBdj7CBnFXlo9KM4TqJSfOkRywQJDzV5zQufaiedK7dSIlnLA3zw0d6dhhuX8PSromH2BGC8YnXFMPhKA5YxdYV44kjMdBzP0ZdP09o/M9vI= ARC-Message-Signature: i=1; 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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 8 +------- target/riscv/op_helper.c | 8 ++------ target/riscv/translate.c | 10 ---------- 4 files changed, 4 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 028e268faa..6b97c27711 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -430,6 +430,7 @@ #define HSTATUS_VTSR 0x00400000 #define HSTATUS_HU 0x00000200 #define HSTATUS_GVA 0x00000040 +#define HSTATUS_SPVP 0x00000100 =20 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4ea39d5641..c4085e5870 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -916,9 +916,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ riscv_cpu_swap_hypervisor_regs(env); - env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2V, - get_field(env->hstatus, HSTATUS_S= PV)); - env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2P, + env->hstatus =3D set_field(env->hstatus, HSTATUS_SPVP, get_field(env->mstatus, SSTATUS_S= PP)); env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); @@ -929,10 +927,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_force_hs_excep(env, 0); } else { /* Trap into HS mode */ - env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2V, - get_field(env->hstatus, HSTATUS_S= PV)); - env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2P, - get_field(env->mstatus, SSTATUS_S= PP)); env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index e0053699cc..efc2d854eb 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -97,12 +97,8 @@ target_ulong helper_sret(CPURISCVState *env, target_ulon= g cpu_pc_deb) prev_priv =3D get_field(mstatus, MSTATUS_SPP); prev_virt =3D get_field(hstatus, HSTATUS_SPV); =20 - hstatus =3D set_field(hstatus, HSTATUS_SPV, - get_field(hstatus, HSTATUS_SP2V)); - mstatus =3D set_field(mstatus, MSTATUS_SPP, - get_field(hstatus, HSTATUS_SP2P)); - hstatus =3D set_field(hstatus, HSTATUS_SP2V, 0); - hstatus =3D set_field(hstatus, HSTATUS_SP2P, 0); + hstatus =3D set_field(hstatus, HSTATUS_SPV, 0); + mstatus =3D set_field(mstatus, MSTATUS_SPP, 0); mstatus =3D set_field(mstatus, SSTATUS_SIE, get_field(mstatus, SSTATUS_SPIE)); mstatus =3D set_field(mstatus, SSTATUS_SPIE, 1); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ce71ca7a92..1d973b62e9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -754,16 +754,6 @@ static void riscv_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { ctx->virt_enabled =3D riscv_cpu_virt_enabled(env); - if (env->priv_ver =3D=3D PRV_M && - get_field(env->mstatus, MSTATUS_MPRV) && - MSTATUS_MPV_ISSET(env)) { - ctx->virt_enabled =3D true; - } else if (env->priv =3D=3D PRV_S && - !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_SPRV) && - get_field(env->hstatus, HSTATUS_SPV)) { - ctx->virt_enabled =3D true; - } } else { ctx->virt_enabled =3D false; } --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1591320811; cv=none; d=zohomail.com; s=zohoarc; b=C+ZFgo6I6lK+zSMEr0GwISPIf/4M272P+8KIgOwNYWe61StddiKYm0MvKhtmaNKV3f9HqZrwADHYil44TvgVIGVTjJ5jK7FiRO6trhmMzHa7O3demK/HU9HwxTYNytAL3142fC/cFQ1F+c1ZhU22LA0p7llGmgHb/KLcV9k4BLw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591320811; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6b97c27711..8a145e0a32 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -422,15 +422,17 @@ #endif =20 /* hstatus CSR bits */ -#define HSTATUS_SPRV 0x00000001 +#define HSTATUS_VSBE 0x00000020 +#define HSTATUS_GVA 0x00000040 #define HSTATUS_SPV 0x00000080 -#define HSTATUS_SP2P 0x00000100 -#define HSTATUS_SP2V 0x00000200 +#define HSTATUS_SPVP 0x00000100 +#define HSTATUS_HU 0x00000200 +#define HSTATUS_VGEIN 0x0003F000 #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTSR 0x00400000 -#define HSTATUS_HU 0x00000200 -#define HSTATUS_GVA 0x00000040 -#define HSTATUS_SPVP 0x00000100 +#if defined(TARGET_RISCV64) +#define HSTATUS_VSXL 0x300000000 +#endif =20 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/csr.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 69a3c8379c..973404d0aa 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -768,12 +768,21 @@ static int write_satp(CPURISCVState *env, int csrno, = target_ulong val) static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) { *val =3D env->hstatus; +#ifdef TARGET_RISCV64 + /* We only support 64-bit VSXL */ + *val =3D set_field(*val, HSTATUS_VSXL, 2); +#endif return 0; } =20 static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { env->hstatus =3D val; +#ifdef TARGET_RISCV64 + if (get_field(val, HSTATUS_VSXL) !=3D 2) { + qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN optio= ns."); + } +#endif return 0; } =20 --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; 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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/csr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 973404d0aa..5b64539efb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -772,6 +772,8 @@ static int read_hstatus(CPURISCVState *env, int csrno, = target_ulong *val) /* We only support 64-bit VSXL */ *val =3D set_field(*val, HSTATUS_VSXL, 2); #endif + /* We only support little endian */ + *val =3D set_field(*val, HSTATUS_VSBE, 0); return 0; } =20 @@ -783,6 +785,9 @@ static int write_hstatus(CPURISCVState *env, int csrno,= target_ulong val) qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN optio= ns."); } #endif + if (get_field(val, HSTATUS_VSBE) !=3D 0) { + qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.= "); + } return 0; } =20 --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; 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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8a145e0a32..690f327828 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -182,9 +182,12 @@ #define CSR_HIDELEG 0x603 #define CSR_HIE 0x604 #define CSR_HCOUNTEREN 0x606 +#define CSR_HGEIE 0x607 #define CSR_HTVAL 0x643 +#define CSR_HVIP 0x645 #define CSR_HIP 0x644 #define CSR_HTINST 0x64A +#define CSR_HGEIP 0xE12 #define CSR_HGATP 0x680 #define CSR_HTIMEDELTA 0x605 #define CSR_HTIMEDELTAH 0x615 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5b64539efb..9990a0dd09 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -815,12 +815,25 @@ static int write_hideleg(CPURISCVState *env, int csrn= o, target_ulong val) return 0; } =20 +static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask) +{ + int ret =3D rmw_mip(env, 0, ret_value, new_value, + write_mask & hip_writable_mask); + + *ret_value &=3D hip_writable_mask; + + return ret; +} + static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { int ret =3D rmw_mip(env, 0, ret_value, new_value, write_mask & hip_writable_mask); =20 + *ret_value &=3D hip_writable_mask; + return ret; } =20 @@ -848,6 +861,18 @@ static int write_hcounteren(CPURISCVState *env, int cs= rno, target_ulong val) return 0; } =20 +static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val) +{ + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + return 0; +} + +static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val) +{ + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + return 0; +} + static int read_htval(CPURISCVState *env, int csrno, target_ulong *val) { *val =3D env->htval; @@ -871,6 +896,18 @@ static int write_htinst(CPURISCVState *env, int csrno,= target_ulong val) return 0; } =20 +static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val) +{ + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + return 0; +} + +static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val) +{ + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + return 0; +} + static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val) { *val =3D env->hgatp; @@ -1268,11 +1305,14 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE]= =3D { [CSR_HSTATUS] =3D { hmode, read_hstatus, write_hstat= us }, [CSR_HEDELEG] =3D { hmode, read_hedeleg, write_hedel= eg }, [CSR_HIDELEG] =3D { hmode, read_hideleg, write_hidel= eg }, + [CSR_HVIP] =3D { hmode, NULL, NULL, rmw_hvip = }, [CSR_HIP] =3D { hmode, NULL, NULL, rmw_hip = }, [CSR_HIE] =3D { hmode, read_hie, write_hie = }, [CSR_HCOUNTEREN] =3D { hmode, read_hcounteren, write_hcoun= teren }, + [CSR_HGEIE] =3D { hmode, read_hgeie, write_hgeie= }, [CSR_HTVAL] =3D { hmode, read_htval, write_htval= }, [CSR_HTINST] =3D { hmode, read_htinst, write_htins= t }, + [CSR_HGEIP] =3D { hmode, read_hgeip, write_hgeip= }, [CSR_HGATP] =3D { hmode, read_hgatp, write_hgatp= }, [CSR_HTIMEDELTA] =3D { hmode, read_htimedelta, write_htime= delta }, #if defined(TARGET_RISCV32) --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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IronPort-SDR: yJhNQEm1APh4Tqzx90lqFUUVKRSKPLRgLbaKrOOiOUvvHDyJRXacUq5GJQLRF/s3TcmjSSSRGj 7J7m8cd4XBq1fPRZzbYf+sJzUO1+NjE9BggjU5q4t8nV/TzhaPrJ5OSBAkZ3Dbek54EogHZAkb vGMO/eF89wdWLFAGpzjE/mcmlO769OqhPk83kOCym3/ks7VW/SBEh3AAb7mh5RZHxaM1PaFz9V 9Rk3928gVAmsEwapcVoUYAkM+l9IPrg/7umMlFAV7Q4tb1OzvXc4OdZOGuas0KIHZwdqsk3Et9 rqk= X-IronPort-AV: E=Sophos;i="5.73,474,1583164800"; d="scan'208";a="242127071" IronPort-SDR: N2nRLyvfz4dqizsYgN7Q7rVCwGCNtBINMOlmrXavUxMuUCRTxfK//PO/7V3YZ3VLbfa8Io9oam 2iJQVcOwTlfZaBZFaMWhTBCO69hqYRdlw= IronPort-SDR: 5NSR7Cz/Tq5FBjEijCh2GBmxmFurVGGKJ5gynlyQDbAce7c44dkJ7FGajbUTJ2QG37Gl0Bn+rq YpifhsXL2MLA== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 16/17] target/riscv: Return the exception from invalid CSR accesses Date: Thu, 4 Jun 2020 18:21:27 -0700 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=4185f83b6=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/04 21:30:00 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, anup.pate@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" When performing a CSR access let's return a negative exception value on an error instead of -1. This will allow us to specify the exception in future patches. Signed-off-by: Alistair Francis --- target/riscv/csr.c | 46 ++++++++++++++++++++-------------------- target/riscv/op_helper.c | 18 ++++++++++------ 2 files changed, 35 insertions(+), 29 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9990a0dd09..0c53438605 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -47,7 +47,7 @@ static int fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif return 0; @@ -61,7 +61,7 @@ static int ctr(CPURISCVState *env, int csrno) =20 if (!cpu->cfg.ext_counters) { /* The Counters extensions is not enabled */ - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif return 0; @@ -89,7 +89,7 @@ static int hmode(CPURISCVState *env, int csrno) } } =20 - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 static int pmp(CPURISCVState *env, int csrno) @@ -103,7 +103,7 @@ static int read_fflags(CPURISCVState *env, int csrno, t= arget_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif *val =3D riscv_cpu_get_fflags(env); @@ -114,7 +114,7 @@ static int write_fflags(CPURISCVState *env, int csrno, = target_ulong val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; #endif @@ -126,7 +126,7 @@ static int read_frm(CPURISCVState *env, int csrno, targ= et_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif *val =3D env->frm; @@ -137,7 +137,7 @@ static int write_frm(CPURISCVState *env, int csrno, tar= get_ulong val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; #endif @@ -149,7 +149,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, tar= get_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif *val =3D (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) @@ -161,7 +161,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, ta= rget_ulong val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; #endif @@ -223,7 +223,7 @@ static int read_time(CPURISCVState *env, int csrno, tar= get_ulong *val) uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D env->rdtime_fn() + delta; @@ -236,7 +236,7 @@ static int read_timeh(CPURISCVState *env, int csrno, ta= rget_ulong *val) uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D (env->rdtime_fn() + delta) >> 32; @@ -502,7 +502,7 @@ static int write_mcounteren(CPURISCVState *env, int csr= no, target_ulong val) static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *v= al) { if (env->priv_ver < PRIV_VERSION_1_11_0) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } *val =3D env->mcounteren; return 0; @@ -512,7 +512,7 @@ static int read_mscounteren(CPURISCVState *env, int csr= no, target_ulong *val) static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong v= al) { if (env->priv_ver < PRIV_VERSION_1_11_0) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } env->mcounteren =3D val; return 0; @@ -736,7 +736,7 @@ static int read_satp(CPURISCVState *env, int csrno, tar= get_ulong *val) } =20 if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } else { *val =3D env->satp; } @@ -753,7 +753,7 @@ static int write_satp(CPURISCVState *env, int csrno, ta= rget_ulong val) ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) { if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } else { if((val ^ env->satp) & SATP_ASID) { tlb_flush(env_cpu(env)); @@ -923,7 +923,7 @@ static int write_hgatp(CPURISCVState *env, int csrno, t= arget_ulong val) static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *va= l) { if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 #if defined(TARGET_RISCV32) @@ -937,7 +937,7 @@ static int read_htimedelta(CPURISCVState *env, int csrn= o, target_ulong *val) static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong va= l) { if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 #if defined(TARGET_RISCV32) @@ -952,7 +952,7 @@ static int write_htimedelta(CPURISCVState *env, int csr= no, target_ulong val) static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *v= al) { if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D env->htimedelta >> 32; @@ -962,7 +962,7 @@ static int read_htimedeltah(CPURISCVState *env, int csr= no, target_ulong *val) static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong v= al) { if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 env->htimedelta =3D deposit64(env->htimedelta, 32, 32, (uint64_t)val); @@ -1160,18 +1160,18 @@ int riscv_csrrw(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, =20 if ((write_mask && read_only) || (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif =20 /* ensure the CSR extension is enabled. */ if (!cpu->cfg.ext_icsr) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 /* check predicate */ if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) = < 0) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 /* execute combined read/write operation if it exists */ @@ -1181,7 +1181,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target= _ulong *ret_value, =20 /* if no accessor exists then return failure */ if (!csr_ops[csrno].read) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 /* read old value */ diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index efc2d854eb..80d632777b 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -43,8 +43,10 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulo= ng src, target_ulong csr) { target_ulong val =3D 0; - if (riscv_csrrw(env, csr, &val, src, -1) < 0) { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + int ret =3D riscv_csrrw(env, csr, &val, src, -1); + + if (ret < 0) { + riscv_raise_exception(env, -ret, GETPC()); } return val; } @@ -53,8 +55,10 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulo= ng src, target_ulong csr, target_ulong rs1_pass) { target_ulong val =3D 0; - if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + int ret =3D riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0); + + if (ret < 0) { + riscv_raise_exception(env, -ret, GETPC()); } return val; } @@ -63,8 +67,10 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulo= ng src, target_ulong csr, target_ulong rs1_pass) { target_ulong val =3D 0; - if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + int ret =3D riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0); + + if (ret < 0) { + riscv_raise_exception(env, -ret, GETPC()); } return val; } --=20 2.26.2 From nobody Sun Apr 28 05:23:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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IronPort-SDR: OKfpnROFraPGghyvTwRQh2NJtdkJRh8E7S2BTVyE6M6DOgTOqKcWpHnXzAxZ0PxGM5GNs2CYvo 1xaNjYLTY+fteVn5TsBLieuSsRBbs4M/8Wc7wKLfOBZ+NLTzKFoU8QM8Pz10YoPKrNjhCu1eAa 49gdhxxI2wLtq/WoC3GQL1NeVhAEOpZwnJYEjQNGMgZPaKpZBT4zHORu/okMXKM/VG1NzbVQ29 zDWmgU8pOUGS89Pjd6/rKhktOJVxnAbjWxmFgbizfM3lAUQOXCpqwK+jG6qmZilPboIJ3rDNZ6 ++4= X-IronPort-AV: E=Sophos;i="5.73,474,1583164800"; d="scan'208";a="242127074" IronPort-SDR: xaN3f4KkLXVuUwQ4AdZpIQJdbCONtPaUayN461UsL7RrA5zChhmypZKTpqGO0k4vUoIJe1ANJ5 PYQOAxnf/9wzlGpRF0VaWYMhnDIuNpYtk= IronPort-SDR: nW3FLPfTD5ZoXt9O4yRPaRVX+6W18ka6PcMRLSWbmisOQTJIrRsc0i92pv/U1ARVpbaQa6r9Fx b8KQuRKn2HYA== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 17/17] target/riscv: Support the Virtual Instruction fault Date: Thu, 4 Jun 2020 18:21:29 -0700 Message-Id: <399681975d78747509166baccabc870a7646048a.1591319882.git.alistair@alistair23.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=4185f83b6=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/04 21:30:00 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, anup.pate@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 6 +++ target/riscv/helper.h | 1 + target/riscv/csr.c | 64 ++++++++++++++++++++++++- target/riscv/insn_trans/trans_rvh.inc.c | 2 +- target/riscv/op_helper.c | 42 ++++++++++++++-- 5 files changed, 109 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 690f327828..30fa746d10 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -446,6 +446,11 @@ #define HSTATUS_WPRI HSTATUS64_WPRI #endif =20 +#define HCOUNTEREN_CY (1 << 0) +#define HCOUNTEREN_TM (1 << 1) +#define HCOUNTEREN_IR (1 << 2) +#define HCOUNTEREN_HPM3 (1 << 3) + /* Privilege modes */ #define PRV_U 0 #define PRV_S 1 @@ -538,6 +543,7 @@ #define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0= */ #define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14 #define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15 +#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16 #define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17 =20 #define RISCV_EXCP_INT_FLAG 0x80000000 diff --git a/target/riscv/helper.h b/target/riscv/helper.h index d020d1459c..2df7e09766 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -80,6 +80,7 @@ DEF_HELPER_1(tlb_flush, void, env) /* Hypervisor functions */ #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) +DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl) DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl) DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0c53438605..4909059baf 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -63,6 +63,61 @@ static int ctr(CPURISCVState *env, int csrno) /* The Counters extensions is not enabled */ return -RISCV_EXCP_ILLEGAL_INST; } + + if (riscv_cpu_virt_enabled(env)) { + switch (csrno) { + case CSR_CYCLE: + if (!get_field(env->hcounteren, HCOUNTEREN_CY) && + get_field(env->mcounteren, HCOUNTEREN_CY)) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; + case CSR_TIME: + if (!get_field(env->hcounteren, HCOUNTEREN_TM) && + get_field(env->mcounteren, HCOUNTEREN_TM)) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; + case CSR_INSTRET: + if (!get_field(env->hcounteren, HCOUNTEREN_IR) && + get_field(env->mcounteren, HCOUNTEREN_IR)) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; + case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: + if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)= ) && + get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))= ) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; +#if defined(TARGET_RISCV32) + case CSR_CYCLEH: + if (!get_field(env->hcounteren, HCOUNTEREN_CY) && + get_field(env->mcounteren, HCOUNTEREN_CY)) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; + case CSR_TIMEH: + if (!get_field(env->hcounteren, HCOUNTEREN_TM) && + get_field(env->mcounteren, HCOUNTEREN_TM)) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; + case CSR_INSTRETH: + if (!get_field(env->hcounteren, HCOUNTEREN_IR) && + get_field(env->mcounteren, HCOUNTEREN_IR)) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; + case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: + if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H= )) && + get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)= )) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; +#endif + } + } #endif return 0; } @@ -86,6 +141,8 @@ static int hmode(CPURISCVState *env, int csrno) if ((env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || env->priv =3D=3D PRV_M) { return 0; + } else { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } } =20 @@ -272,6 +329,7 @@ static const target_ulong delegable_excps =3D (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | + (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | @@ -1170,9 +1228,13 @@ int riscv_csrrw(CPURISCVState *env, int csrno, targe= t_ulong *ret_value, } =20 /* check predicate */ - if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) = < 0) { + if (!csr_ops[csrno].predicate) { return -RISCV_EXCP_ILLEGAL_INST; } + ret =3D csr_ops[csrno].predicate(env, csrno); + if (ret < 0) { + return ret; + } =20 /* execute combined read/write operation if it exists */ if (csr_ops[csrno].op) { diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_tr= ans/trans_rvh.inc.c index db650ae62a..881c9ef4d2 100644 --- a/target/riscv/insn_trans/trans_rvh.inc.c +++ b/target/riscv/insn_trans/trans_rvh.inc.c @@ -360,7 +360,7 @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sf= ence_vma *a) { REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY - gen_helper_hyp_tlb_flush(cpu_env); + gen_helper_hyp_gvma_tlb_flush(cpu_env); return true; #endif return false; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 80d632777b..d1f1a46335 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -94,6 +94,11 @@ target_ulong helper_sret(CPURISCVState *env, target_ulon= g cpu_pc_deb) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 + if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_VTSR)) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); + } + mstatus =3D env->mstatus; =20 if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { @@ -176,7 +181,7 @@ void helper_wfi(CPURISCVState *env) if ((env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TW)) || riscv_cpu_virt_enabled(env)) { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { cs->halted =3D 1; cs->exception_index =3D EXCP_HLT; @@ -191,6 +196,9 @@ void helper_tlb_flush(CPURISCVState *env) (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM))) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_VTVM)) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { tlb_flush(cs); } @@ -200,6 +208,10 @@ void helper_hyp_tlb_flush(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); =20 + if (env->priv =3D=3D PRV_S && riscv_cpu_virt_enabled(env)) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); + } + if (env->priv =3D=3D PRV_M || (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env))) { tlb_flush(cs); @@ -209,6 +221,16 @@ void helper_hyp_tlb_flush(CPURISCVState *env) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 +void helper_hyp_gvma_tlb_flush(CPURISCVState *env) +{ + if (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env) && + get_field(env->mstatus, MSTATUS_TVM)) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + helper_hyp_tlb_flush(env); +} + target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, target_ulong attrs, target_ulong memop) { @@ -251,7 +273,11 @@ target_ulong helper_hyp_load(CPURISCVState *env, targe= t_ulong address, return pte; } =20 - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + if (riscv_cpu_virt_enabled(env)) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); + } else { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } return 0; } =20 @@ -289,7 +315,11 @@ void helper_hyp_store(CPURISCVState *env, target_ulong= address, return; } =20 - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + if (riscv_cpu_virt_enabled(env)) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); + } else { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } } =20 target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, @@ -319,7 +349,11 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, tar= get_ulong address, return pte; } =20 - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + if (riscv_cpu_virt_enabled(env)) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); + } else { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } return 0; } =20 --=20 2.26.2