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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=4104b2603=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/28 18:24:44 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The ISA specific Spike machines have been deprecated in QEMU since 4.1, let's finally remove them. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng Reviewed-by: Thomas Huth --- docs/system/deprecated.rst | 17 +-- include/hw/riscv/spike.h | 6 +- hw/riscv/spike.c | 217 ------------------------------------- 3 files changed, 12 insertions(+), 228 deletions(-) diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst index f0061f94aa..50927bad74 100644 --- a/docs/system/deprecated.rst +++ b/docs/system/deprecated.rst @@ -379,13 +379,6 @@ This machine has been renamed ``fuloong2e``. These machine types are very old and likely can not be used for live migra= tion from old QEMU versions anymore. A newer machine type should be used instea= d. =20 -``spike_v1.9.1`` and ``spike_v1.10`` (since 4.1) -'''''''''''''''''''''''''''''''''''''''''''''''' - -The version specific Spike machines have been deprecated in favour of the -generic ``spike`` machine. If you need to specify an older version of the = RISC-V -spec you can use the ``-cpu rv64gcsu,priv_spec=3Dv1.9.1`` command line arg= ument. - Device options -------------- =20 @@ -493,6 +486,16 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfw= d_remove`` (removed in 5.0 The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and 'hostfwd_remove' HMP commands has been replaced by ``netdev_id``. =20 +System emulator machines +------------------------ + +``spike_v1.9.1`` and ``spike_v1.10`` (removed in 5.1) +''''''''''''''''''''''''''''''''''''''''''''''''''''' + +The version specific Spike machines have been removed in favour of the +generic ``spike`` machine. If you need to specify an older version of the = RISC-V +spec you can use the ``-cpu rv64gcsu,priv_spec=3Dv1.10.0`` command line ar= gument. + Related binaries ---------------- =20 diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index dc770421bc..1cd72b85d6 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -39,11 +39,9 @@ enum { }; =20 #if defined(TARGET_RISCV32) -#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1 -#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 +#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32 #elif defined(TARGET_RISCV64) -#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1 -#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0 +#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64 #endif =20 #endif diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index d0c4843712..7bbbdb5036 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -257,221 +257,6 @@ static void spike_board_init(MachineState *machine) false); } =20 -static void spike_v1_10_0_board_init(MachineState *machine) -{ - const struct MemmapEntry *memmap =3D spike_memmap; - - SpikeState *s =3D g_new0(SpikeState, 1); - MemoryRegion *system_memory =3D get_system_memory(); - MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); - int i; - unsigned int smp_cpus =3D machine->smp.cpus; - - if (!qtest_enabled()) { - info_report("The Spike v1.10.0 machine has been deprecated. " - "Please use the generic spike machine and specify the = ISA " - "versions using -cpu."); - } - - /* Initialize SOC */ - object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc= ), - TYPE_RISCV_HART_ARRAY, &error_abort, NULL); - object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type", - &error_abort); - object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", - &error_abort); - object_property_set_bool(OBJECT(&s->soc), true, "realized", - &error_abort); - - /* register system main memory (actual RAM) */ - memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", - machine->ram_size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, - main_mem); - - /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); - - /* boot rom */ - memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", - memmap[SPIKE_MROM].size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, - mask_rom); - - if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, htif_symbol_callback); - } - - /* reset vector */ - uint32_t reset_vec[8] =3D { - 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ - 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ - 0xf1402573, /* csrr a0, mhartid */ -#if defined(TARGET_RISCV32) - 0x0182a283, /* lw t0, 24(t0) */ -#elif defined(TARGET_RISCV64) - 0x0182b283, /* ld t0, 24(t0) */ -#endif - 0x00028067, /* jr t0 */ - 0x00000000, - memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */ - 0x00000000, - /* dtb: */ - }; - - /* copy in the reset vector in little_endian byte order */ - for (i =3D 0; i < sizeof(reset_vec) >> 2; i++) { - reset_vec[i] =3D cpu_to_le32(reset_vec[i]); - } - rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), - memmap[SPIKE_MROM].base, &address_space_memory); - - /* copy in the device tree */ - if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > - memmap[SPIKE_MROM].size - sizeof(reset_vec)) { - error_report("not enough space to store device-tree"); - exit(1); - } - qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); - rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), - memmap[SPIKE_MROM].base + sizeof(reset_vec), - &address_space_memory); - - /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(= 0)); - - /* Core Local Interruptor (timer and IPI) */ - sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, - smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, - false); -} - -static void spike_v1_09_1_board_init(MachineState *machine) -{ - const struct MemmapEntry *memmap =3D spike_memmap; - - SpikeState *s =3D g_new0(SpikeState, 1); - MemoryRegion *system_memory =3D get_system_memory(); - MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); - int i; - unsigned int smp_cpus =3D machine->smp.cpus; - - if (!qtest_enabled()) { - info_report("The Spike v1.09.1 machine has been deprecated. " - "Please use the generic spike machine and specify the = ISA " - "versions using -cpu."); - } - - /* Initialize SOC */ - object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc= ), - TYPE_RISCV_HART_ARRAY, &error_abort, NULL); - object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type", - &error_abort); - object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", - &error_abort); - object_property_set_bool(OBJECT(&s->soc), true, "realized", - &error_abort); - - /* register system main memory (actual RAM) */ - memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", - machine->ram_size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, - main_mem); - - /* boot rom */ - memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", - memmap[SPIKE_MROM].size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, - mask_rom); - - if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, htif_symbol_callback); - } - - /* reset vector */ - uint32_t reset_vec[8] =3D { - 0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui = */ - 0x00028067, /* jump to DRAM_BASE */ - 0x00000000, /* reserved */ - memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string poin= ter */ - 0, 0, 0, 0 /* trap vector */ - }; - - /* part one of config string - before memory size specified */ - const char *config_string_tmpl =3D - "platform {\n" - " vendor ucb;\n" - " arch spike;\n" - "};\n" - "rtc {\n" - " addr 0x%" PRIx64 "x;\n" - "};\n" - "ram {\n" - " 0 {\n" - " addr 0x%" PRIx64 "x;\n" - " size 0x%" PRIx64 "x;\n" - " };\n" - "};\n" - "core {\n" - " 0" " {\n" - " " "0 {\n" - " isa %s;\n" - " timecmp 0x%" PRIx64 "x;\n" - " ipi 0x%" PRIx64 "x;\n" - " };\n" - " };\n" - "};\n"; - - /* build config string with supplied memory size */ - char *isa =3D riscv_isa_string(&s->soc.harts[0]); - char *config_string =3D g_strdup_printf(config_string_tmpl, - (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE, - (uint64_t)memmap[SPIKE_DRAM].base, - (uint64_t)ram_size, isa, - (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE, - (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE); - g_free(isa); - size_t config_string_len =3D strlen(config_string); - - /* copy in the reset vector in little_endian byte order */ - for (i =3D 0; i < sizeof(reset_vec) >> 2; i++) { - reset_vec[i] =3D cpu_to_le32(reset_vec[i]); - } - rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), - memmap[SPIKE_MROM].base, &address_space_memory); - - /* copy in the config string */ - rom_add_blob_fixed_as("mrom.reset", config_string, config_string_len, - memmap[SPIKE_MROM].base + sizeof(reset_vec), - &address_space_memory); - - /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(= 0)); - - /* Core Local Interruptor (timer and IPI) */ - sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, - smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, - false); - - g_free(config_string); -} - -static void spike_v1_09_1_machine_init(MachineClass *mc) -{ - mc->desc =3D "RISC-V Spike Board (Privileged ISA v1.9.1)"; - mc->init =3D spike_v1_09_1_board_init; - mc->max_cpus =3D 1; -} - -static void spike_v1_10_0_machine_init(MachineClass *mc) -{ - mc->desc =3D "RISC-V Spike Board (Privileged ISA v1.10)"; - mc->init =3D spike_v1_10_0_board_init; - mc->max_cpus =3D 1; -} - static void spike_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Spike Board"; @@ -481,6 +266,4 @@ static void spike_machine_init(MachineClass *mc) mc->default_cpu_type =3D SPIKE_V1_10_0_CPU; } =20 -DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) -DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) DEFINE_MACHINE("spike", spike_machine_init) --=20 2.26.2 From nobody Thu May 16 18:22:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- docs/system/deprecated.rst | 33 ++++++++++++++++++--------------- target/riscv/cpu.h | 7 ------- target/riscv/cpu.c | 28 ---------------------------- tests/qtest/machine-none-test.c | 4 ++-- 4 files changed, 20 insertions(+), 52 deletions(-) diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst index 50927bad74..a6664bfca9 100644 --- a/docs/system/deprecated.rst +++ b/docs/system/deprecated.rst @@ -314,21 +314,6 @@ should be used instead of the 1.09.1 version. System emulator CPUS -------------------- =20 -RISC-V ISA CPUs (since 4.1) -''''''''''''''''''''''''''' - -The RISC-V cpus with the ISA version in the CPU name have been depcreated.= The -four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.= 1`` and -``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``p= riv_spec`` -option when using the ``rv32`` or ``rv64`` CPUs. - -RISC-V ISA CPUs (since 4.1) -''''''''''''''''''''''''''' - -The RISC-V no MMU cpus have been depcreated. The two CPUs: ``rv32imacu-nom= mu`` and -``rv64imacu-nommu`` should no longer be used. Instead the MMU status can b= e specified -via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs. - ``compat`` property of server class POWER CPUs (since 5.0) '''''''''''''''''''''''''''''''''''''''''''''''''''''''''' =20 @@ -486,6 +471,24 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfw= d_remove`` (removed in 5.0 The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and 'hostfwd_remove' HMP commands has been replaced by ``netdev_id``. =20 +System emulator CPUS +-------------------- + +RISC-V ISA CPUs (removed in 5.1) +'''''''''''''''''''''''''''''''' + +The RISC-V cpus with the ISA version in the CPU name have been removed. The +four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.= 1`` and +``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``p= riv_spec`` +option when using the ``rv32`` or ``rv64`` CPUs. + +RISC-V ISA CPUs (removed in 5.1) +'''''''''''''''''''''''''''''''' + +The RISC-V no MMU cpus have been removed. The two CPUs: ``rv32imacu-nommu`= ` and +``rv64imacu-nommu`` can no longer be used. Instead the MMU status can be s= pecified +via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs. + System emulator machines ------------------------ =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d0e7f5b9c5..76b98d7a33 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -40,13 +40,6 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") -/* Deprecated */ -#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nom= mu") -#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9= .1") -#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.1= 0.0") -#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nom= mu") -#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9= .1") -#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.1= 0.0") =20 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 059d71f2c7..112f2e3a2f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -135,16 +135,6 @@ static void riscv_base32_cpu_init(Object *obj) set_misa(env, 0); } =20 -static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_09_1); - set_resetvec(env, DEFAULT_RSTVEC); - set_feature(env, RISCV_FEATURE_MMU); - set_feature(env, RISCV_FEATURE_PMP); -} - static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -182,16 +172,6 @@ static void riscv_base64_cpu_init(Object *obj) set_misa(env, 0); } =20 -static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_09_1); - set_resetvec(env, DEFAULT_RSTVEC); - set_feature(env, RISCV_FEATURE_MMU); - set_feature(env, RISCV_FEATURE_PMP); -} - static void rv64gcsu_priv1_10_0_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -621,18 +601,10 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_in= it), - /* Depreacted */ - DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_in= it), - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_in= it) #elif defined(TARGET_RISCV64) DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_in= it), - /* Deprecated */ - DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_in= it), - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_in= it) #endif }; =20 diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-tes= t.c index 8bb54a6360..b52311ec2e 100644 --- a/tests/qtest/machine-none-test.c +++ b/tests/qtest/machine-none-test.c @@ -54,8 +54,8 @@ static struct arch2cpu cpus_map[] =3D { { "xtensa", "dc233c" }, { "xtensaeb", "fsf" }, { "hppa", "hppa" }, - { "riscv64", "rv64gcsu-v1.10.0" }, - { "riscv32", "rv32gcsu-v1.9.1" }, + { "riscv64", "sifive-u54" }, + { "riscv32", "sifive-u34" }, { "rx", "rx62n" }, }; =20 --=20 2.26.2 From nobody Thu May 16 18:22:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1590705188; cv=none; d=zohomail.com; s=zohoarc; b=TmbM5uIJizxbO7FY76TX4t23TKCYJGCwhC9g9uY8ATPEF03o3/agY8jeZxNlgnevHeafy1hYFL+m22aaPdaM8k++g9dffQydIY5t0O7cNdCbmxBjtXATeAkztLugNyPaQnbHAdeq5i2bA0au8/Am7UdllxclqaiC8UnANavxq1A= ARC-Message-Signature: i=1; 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charset="utf-8" The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since 4.1. It's not commonly used so let's remove support for it. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- docs/system/deprecated.rst | 20 +-- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 2 - target/riscv/cpu_helper.c | 82 ++++------- target/riscv/csr.c | 138 ++++-------------- .../riscv/insn_trans/trans_privileged.inc.c | 18 +-- target/riscv/monitor.c | 5 - target/riscv/op_helper.c | 17 +-- 8 files changed, 73 insertions(+), 210 deletions(-) diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst index a6664bfca9..38865daafc 100644 --- a/docs/system/deprecated.rst +++ b/docs/system/deprecated.rst @@ -301,16 +301,6 @@ The ``acl_show``, ``acl_reset``, ``acl_policy``, ``acl= _add``, and ``acl_remove`` commands are deprecated with no replacement. Authorization for VNC should be performed using the pluggable QAuthZ objects. =20 -Guest Emulator ISAs -------------------- - -RISC-V ISA privledge specification version 1.09.1 (since 4.1) -''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' - -The RISC-V ISA privledge specification version 1.09.1 has been deprecated. -QEMU supports both the newer version 1.10.0 and the ratified version 1.11.= 0, these -should be used instead of the 1.09.1 version. - System emulator CPUS -------------------- =20 @@ -471,6 +461,16 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfw= d_remove`` (removed in 5.0 The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and 'hostfwd_remove' HMP commands has been replaced by ``netdev_id``. =20 +Guest Emulator ISAs +------------------- + +RISC-V ISA privledge specification version 1.09.1 (removed in 5.1) +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +The RISC-V ISA privledge specification version 1.09.1 has been removed. +QEMU supports both the newer version 1.10.0 and the ratified version 1.11.= 0, these +should be used instead of the 1.09.1 version. + System emulator CPUS -------------------- =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 76b98d7a33..c022539012 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -73,7 +73,6 @@ enum { RISCV_FEATURE_MISA }; =20 -#define PRIV_VERSION_1_09_1 0x00010901 #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 112f2e3a2f..eeb91f8513 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -368,8 +368,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) priv_version =3D PRIV_VERSION_1_11_0; } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { priv_version =3D PRIV_VERSION_1_10_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) { - priv_version =3D PRIV_VERSION_1_09_1; } else { error_setg(errp, "Unsupported privilege spec version '%s'", diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index bc80aa87cf..62fe1ecc8f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -364,57 +364,36 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, mxr =3D get_field(env->vsstatus, MSTATUS_MXR); } =20 - if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { - if (first_stage =3D=3D true) { - if (use_background) { - base =3D (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIF= T; - vm =3D get_field(env->vsatp, SATP_MODE); - } else { - base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; - vm =3D get_field(env->satp, SATP_MODE); - } - widened =3D 0; + if (first_stage =3D=3D true) { + if (use_background) { + base =3D (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT; + vm =3D get_field(env->vsatp, SATP_MODE); } else { - base =3D (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT; - vm =3D get_field(env->hgatp, HGATP_MODE); - widened =3D 2; - } - sum =3D get_field(env->mstatus, MSTATUS_SUM); - switch (vm) { - case VM_1_10_SV32: - levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; - case VM_1_10_SV39: - levels =3D 3; ptidxbits =3D 9; ptesize =3D 8; break; - case VM_1_10_SV48: - levels =3D 4; ptidxbits =3D 9; ptesize =3D 8; break; - case VM_1_10_SV57: - levels =3D 5; ptidxbits =3D 9; ptesize =3D 8; break; - case VM_1_10_MBARE: - *physical =3D addr; - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TRANSLATE_SUCCESS; - default: - g_assert_not_reached(); + base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; + vm =3D get_field(env->satp, SATP_MODE); } - } else { widened =3D 0; - base =3D (hwaddr)(env->sptbr) << PGSHIFT; - sum =3D !get_field(env->mstatus, MSTATUS_PUM); - vm =3D get_field(env->mstatus, MSTATUS_VM); - switch (vm) { - case VM_1_09_SV32: - levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; - case VM_1_09_SV39: - levels =3D 3; ptidxbits =3D 9; ptesize =3D 8; break; - case VM_1_09_SV48: - levels =3D 4; ptidxbits =3D 9; ptesize =3D 8; break; - case VM_1_09_MBARE: - *physical =3D addr; - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TRANSLATE_SUCCESS; - default: - g_assert_not_reached(); - } + } else { + base =3D (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT; + vm =3D get_field(env->hgatp, HGATP_MODE); + widened =3D 2; + } + sum =3D get_field(env->mstatus, MSTATUS_SUM); + switch (vm) { + case VM_1_10_SV32: + levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; + case VM_1_10_SV39: + levels =3D 3; ptidxbits =3D 9; ptesize =3D 8; break; + case VM_1_10_SV48: + levels =3D 4; ptidxbits =3D 9; ptesize =3D 8; break; + case VM_1_10_SV57: + levels =3D 5; ptidxbits =3D 9; ptesize =3D 8; break; + case VM_1_10_MBARE: + *physical =3D addr; + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TRANSLATE_SUCCESS; + default: + g_assert_not_reached(); } =20 CPUState *cs =3D env_cpu(env); @@ -588,7 +567,6 @@ static void raise_mmu_exception(CPURISCVState *env, tar= get_ulong address, int page_fault_exceptions; if (first_stage) { page_fault_exceptions =3D - (env->priv_ver >=3D PRIV_VERSION_1_10_0) && get_field(env->satp, SATP_MODE) !=3D VM_1_10_MBARE && !pmp_violation; } else { @@ -941,8 +919,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) } =20 s =3D env->mstatus; - s =3D set_field(s, MSTATUS_SPIE, env->priv_ver >=3D PRIV_VERSION_1= _10_0 ? - get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->p= riv)); + s =3D set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); s =3D set_field(s, MSTATUS_SPP, env->priv); s =3D set_field(s, MSTATUS_SIE, 0); env->mstatus =3D s; @@ -979,8 +956,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) } =20 s =3D env->mstatus; - s =3D set_field(s, MSTATUS_MPIE, env->priv_ver >=3D PRIV_VERSION_1= _10_0 ? - get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->p= riv)); + s =3D set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); s =3D set_field(s, MSTATUS_MPP, env->priv); s =3D set_field(s, MSTATUS_MIE, 0); env->mstatus =3D s; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 11d184cd16..383be0a955 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -58,31 +58,11 @@ static int ctr(CPURISCVState *env, int csrno) #if !defined(CONFIG_USER_ONLY) CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); - uint32_t ctr_en =3D ~0u; =20 if (!cpu->cfg.ext_counters) { /* The Counters extensions is not enabled */ return -1; } - - /* - * The counters are always enabled at run time on newer priv specs, as= the - * CSR has changed from controlling that the counters can be read to - * controlling that the counters increment. - */ - if (env->priv_ver > PRIV_VERSION_1_09_1) { - return 0; - } - - if (env->priv < PRV_M) { - ctr_en &=3D env->mcounteren; - } - if (env->priv < PRV_S) { - ctr_en &=3D env->scounteren; - } - if (!(ctr_en & (1u << (csrno & 31)))) { - return -1; - } #endif return 0; } @@ -293,9 +273,6 @@ static const target_ulong delegable_excps =3D (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); -static const target_ulong sstatus_v1_9_mask =3D SSTATUS_SIE | SSTATUS_SPIE= | - SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | - SSTATUS_SUM | SSTATUS_SD; static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; @@ -304,20 +281,11 @@ static const target_ulong hip_writable_mask =3D MIP_V= SSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask =3D MIP_VSSIP; =20 #if defined(TARGET_RISCV32) -static const char valid_vm_1_09[16] =3D { - [VM_1_09_MBARE] =3D 1, - [VM_1_09_SV32] =3D 1, -}; static const char valid_vm_1_10[16] =3D { [VM_1_10_MBARE] =3D 1, [VM_1_10_SV32] =3D 1 }; #elif defined(TARGET_RISCV64) -static const char valid_vm_1_09[16] =3D { - [VM_1_09_MBARE] =3D 1, - [VM_1_09_SV39] =3D 1, - [VM_1_09_SV48] =3D 1, -}; static const char valid_vm_1_10[16] =3D { [VM_1_10_MBARE] =3D 1, [VM_1_10_SV39] =3D 1, @@ -347,8 +315,7 @@ static int read_mstatus(CPURISCVState *env, int csrno, = target_ulong *val) =20 static int validate_vm(CPURISCVState *env, target_ulong vm) { - return (env->priv_ver >=3D PRIV_VERSION_1_10_0) ? - valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf]; + return valid_vm_1_10[vm & 0xf]; } =20 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) @@ -358,34 +325,21 @@ static int write_mstatus(CPURISCVState *env, int csrn= o, target_ulong val) int dirty; =20 /* flush tlb on mstatus fields that affect VM */ - if (env->priv_ver <=3D PRIV_VERSION_1_09_1) { - if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | - MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { - tlb_flush(env_cpu(env)); - } - mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | - MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | - MSTATUS_MPP | MSTATUS_MXR | - (validate_vm(env, get_field(val, MSTATUS_VM)) ? - MSTATUS_VM : 0); + if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | + MSTATUS_MPRV | MSTATUS_SUM)) { + tlb_flush(env_cpu(env)); } - if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { - if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | - MSTATUS_MPRV | MSTATUS_SUM)) { - tlb_flush(env_cpu(env)); - } - mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | - MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | - MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | - MSTATUS_TW; + mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | + MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | + MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | + MSTATUS_TW; #if defined(TARGET_RISCV64) - /* - * RV32: MPV and MTL are not in mstatus. The current plan is to - * add them to mstatush. For now, we just don't support it. - */ - mask |=3D MSTATUS_MTL | MSTATUS_MPV; + /* + * RV32: MPV and MTL are not in mstatus. The current plan is to + * add them to mstatush. For now, we just don't support it. + */ + mask |=3D MSTATUS_MTL | MSTATUS_MPV; #endif - } =20 mstatus =3D (mstatus & ~mask) | (val & mask); =20 @@ -534,18 +488,12 @@ static int write_mtvec(CPURISCVState *env, int csrno,= target_ulong val) =20 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *va= l) { - if (env->priv_ver < PRIV_VERSION_1_10_0) { - return -1; - } *val =3D env->mcounteren; return 0; } =20 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong va= l) { - if (env->priv_ver < PRIV_VERSION_1_10_0) { - return -1; - } env->mcounteren =3D val; return 0; } @@ -553,8 +501,7 @@ static int write_mcounteren(CPURISCVState *env, int csr= no, target_ulong val) /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *v= al) { - if (env->priv_ver > PRIV_VERSION_1_09_1 - && env->priv_ver < PRIV_VERSION_1_11_0) { + if (env->priv_ver < PRIV_VERSION_1_11_0) { return -1; } *val =3D env->mcounteren; @@ -564,32 +511,13 @@ static int read_mscounteren(CPURISCVState *env, int c= srno, target_ulong *val) /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong v= al) { - if (env->priv_ver > PRIV_VERSION_1_09_1 - && env->priv_ver < PRIV_VERSION_1_11_0) { + if (env->priv_ver < PRIV_VERSION_1_11_0) { return -1; } env->mcounteren =3D val; return 0; } =20 -static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *v= al) -{ - if (env->priv_ver > PRIV_VERSION_1_09_1) { - return -1; - } - *val =3D env->scounteren; - return 0; -} - -static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong v= al) -{ - if (env->priv_ver > PRIV_VERSION_1_09_1) { - return -1; - } - env->scounteren =3D val; - return 0; -} - /* Machine Trap Handling */ static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) { @@ -663,16 +591,14 @@ static int rmw_mip(CPURISCVState *env, int csrno, tar= get_ulong *ret_value, /* Supervisor Trap Setup */ static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) { - target_ulong mask =3D ((env->priv_ver >=3D PRIV_VERSION_1_10_0) ? - sstatus_v1_10_mask : sstatus_v1_9_mask); + target_ulong mask =3D (sstatus_v1_10_mask); *val =3D env->mstatus & mask; return 0; } =20 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong mask =3D ((env->priv_ver >=3D PRIV_VERSION_1_10_0) ? - sstatus_v1_10_mask : sstatus_v1_9_mask); + target_ulong mask =3D (sstatus_v1_10_mask); target_ulong newval =3D (env->mstatus & ~mask) | (val & mask); return write_mstatus(env, CSR_MSTATUS, newval); } @@ -722,18 +648,12 @@ static int write_stvec(CPURISCVState *env, int csrno,= target_ulong val) =20 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *va= l) { - if (env->priv_ver < PRIV_VERSION_1_10_0) { - return -1; - } *val =3D env->scounteren; return 0; } =20 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong va= l) { - if (env->priv_ver < PRIV_VERSION_1_10_0) { - return -1; - } env->scounteren =3D val; return 0; } @@ -812,15 +732,15 @@ static int read_satp(CPURISCVState *env, int csrno, t= arget_ulong *val) { if (!riscv_feature(env, RISCV_FEATURE_MMU)) { *val =3D 0; - } else if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { - if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { - return -1; - } else { - *val =3D env->satp; - } + return 0; + } + + if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { + return -1; } else { - *val =3D env->sptbr; + *val =3D env->satp; } + return 0; } =20 @@ -829,13 +749,7 @@ static int write_satp(CPURISCVState *env, int csrno, t= arget_ulong val) if (!riscv_feature(env, RISCV_FEATURE_MMU)) { return 0; } - if (env->priv_ver <=3D PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { - tlb_flush(env_cpu(env)); - env->sptbr =3D val & (((target_ulong) - 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); - } - if (env->priv_ver >=3D PRIV_VERSION_1_10_0 && - validate_vm(env, get_field(val, SATP_MODE)) && + if (validate_vm(env, get_field(val, SATP_MODE)) && ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) { if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { @@ -1313,8 +1227,6 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D { [CSR_MSTATUSH] =3D { any, read_mstatush, write_mstatush= }, #endif =20 - /* Legacy Counter Setup (priv v1.9.1) */ - [CSR_MUCOUNTEREN] =3D { any, read_mucounteren, write_mucounte= ren }, [CSR_MSCOUNTEREN] =3D { any, read_mscounteren, write_mscounte= ren }, =20 /* Machine Trap Handling */ diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/= insn_trans/trans_privileged.inc.c index 76c2fad71c..5f26e0f5ea 100644 --- a/target/riscv/insn_trans/trans_privileged.inc.c +++ b/target/riscv/insn_trans/trans_privileged.inc.c @@ -85,30 +85,21 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a) static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a) { #ifndef CONFIG_USER_ONLY - if (ctx->priv_ver >=3D PRIV_VERSION_1_10_0) { - gen_helper_tlb_flush(cpu_env); - return true; - } + gen_helper_tlb_flush(cpu_env); + return true; #endif return false; } =20 static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a) { -#ifndef CONFIG_USER_ONLY - if (ctx->priv_ver <=3D PRIV_VERSION_1_09_1) { - gen_helper_tlb_flush(cpu_env); - return true; - } -#endif return false; } =20 static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) { #ifndef CONFIG_USER_ONLY - if (ctx->priv_ver >=3D PRIV_VERSION_1_10_0 && - has_ext(ctx, RVH)) { + if (has_ext(ctx, RVH)) { /* Hpervisor extensions exist */ /* * if (env->priv =3D=3D PRV_M || @@ -127,8 +118,7 @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sf= ence_vma *a) static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a) { #ifndef CONFIG_USER_ONLY - if (ctx->priv_ver >=3D PRIV_VERSION_1_10_0 && - has_ext(ctx, RVH)) { + if (has_ext(ctx, RVH)) { /* Hpervisor extensions exist */ /* * if (env->priv =3D=3D PRV_M || diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index d725a7a36e..b569f08387 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -215,11 +215,6 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) return; } =20 - if (env->priv_ver < PRIV_VERSION_1_10_0) { - monitor_printf(mon, "Privileged mode < 1.10 unsupported\n"); - return; - } - if (!(env->satp & SATP_MODE)) { monitor_printf(mon, "No translation or protection\n"); return; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index c6412f680c..b0c49efc4a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -84,8 +84,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong= cpu_pc_deb) riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); } =20 - if (env->priv_ver >=3D PRIV_VERSION_1_10_0 && - get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >=3D PRV_M)) { + if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >=3D PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 @@ -119,10 +118,8 @@ target_ulong helper_sret(CPURISCVState *env, target_ul= ong cpu_pc_deb) } else { prev_priv =3D get_field(mstatus, MSTATUS_SPP); =20 - mstatus =3D set_field(mstatus, - env->priv_ver >=3D PRIV_VERSION_1_10_0 ? - MSTATUS_SIE : MSTATUS_UIE << prev_priv, - get_field(mstatus, MSTATUS_SPIE)); + mstatus =3D set_field(mstatus, MSTATUS_SIE, + get_field(mstatus, MSTATUS_SPIE)); mstatus =3D set_field(mstatus, MSTATUS_SPIE, 1); mstatus =3D set_field(mstatus, MSTATUS_SPP, PRV_U); env->mstatus =3D mstatus; @@ -147,10 +144,8 @@ target_ulong helper_mret(CPURISCVState *env, target_ul= ong cpu_pc_deb) target_ulong mstatus =3D env->mstatus; target_ulong prev_priv =3D get_field(mstatus, MSTATUS_MPP); target_ulong prev_virt =3D MSTATUS_MPV_ISSET(env); - mstatus =3D set_field(mstatus, - env->priv_ver >=3D PRIV_VERSION_1_10_0 ? - MSTATUS_MIE : MSTATUS_UIE << prev_priv, - get_field(mstatus, MSTATUS_MPIE)); + mstatus =3D set_field(mstatus, MSTATUS_MIE, + get_field(mstatus, MSTATUS_MPIE)); mstatus =3D set_field(mstatus, MSTATUS_MPIE, 1); mstatus =3D set_field(mstatus, MSTATUS_MPP, PRV_U); #ifdef TARGET_RISCV32 @@ -177,7 +172,6 @@ void helper_wfi(CPURISCVState *env) CPUState *cs =3D env_cpu(env); =20 if ((env->priv =3D=3D PRV_S && - env->priv_ver >=3D PRIV_VERSION_1_10_0 && get_field(env->mstatus, MSTATUS_TW)) || riscv_cpu_virt_enabled(env)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); @@ -193,7 +187,6 @@ void helper_tlb_flush(CPURISCVState *env) CPUState *cs =3D env_cpu(env); if (!(env->priv >=3D PRV_S) || (env->priv =3D=3D PRV_S && - env->priv_ver >=3D PRIV_VERSION_1_10_0 && get_field(env->mstatus, MSTATUS_TVM))) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } else { --=20 2.26.2 From nobody Thu May 16 18:22:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1590705409; cv=none; d=zohomail.com; s=zohoarc; b=mTAG7n3Krnx1hfFNjYTZ+sMgGFRNyflnfxhulnT+lds7V2SvJ1AJKwgPMYO3chcWeiANZtsNcySD8R87/kuQnHcu8dx7+4ITrOQi4rhPFXXYHHJxM6wjs43cUdHh1lXP0IqOnq3+p7Uj6+Dmi3n1HKhBol2ox0q/sgGmoh+a8IY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=4104b2603=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/28 18:24:44 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Update the -bios deprecation documentation to describe the new behaviour. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- docs/system/deprecated.rst | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst index 38865daafc..8c445d4062 100644 --- a/docs/system/deprecated.rst +++ b/docs/system/deprecated.rst @@ -138,25 +138,23 @@ the backing storage specified with ``-mem-path`` can = actually provide the guest RAM configured with ``-m`` and QEMU will fail to start up if RAM allocation is unsuccessful. =20 -RISC-V ``-bios`` (since 4.1) +RISC-V ``-bios`` (since 5.1) '''''''''''''''''''''''''''' =20 QEMU 4.1 introduced support for the -bios option in QEMU for RISC-V for the -RISC-V virt machine and sifive_u machine. - -QEMU 4.1 has no changes to the default behaviour to avoid breakages. This -default will change in a future QEMU release, so please prepare now. All u= sers -of the virt or sifive_u machine must change their command line usage. - -QEMU 4.1 has three options, please migrate to one of these three: - 1. ``-bios none`` - This is the current default behavior if no -bios opti= on - is included. QEMU will not automatically load any firmware. It is up +RISC-V virt machine and sifive_u machine. QEMU 4.1 had no changes to the +default behaviour to avoid breakages. + +QEMU 5.1 changes the default behaviour from ``-bios none`` to ``-bios defa= ult``. + +QEMU 5.1 has three options: + 1. ``-bios default`` - This is the current default behavior if no -bios o= ption + is included. This option will load the default OpenSBI firmware auto= matically. + The firmware is included with the QEMU release and no user interacti= on is + required. All a user needs to do is specify the kernel they want to = boot + with the -kernel option + 2. ``-bios none`` - QEMU will not automatically load any firmware. It is = up to the user to load all the images they need. - 2. ``-bios default`` - In a future QEMU release this will become the defa= ult - behaviour if no -bios option is specified. This option will load the - default OpenSBI firmware automatically. The firmware is included with - the QEMU release and no user interaction is required. All a user nee= ds - to do is specify the kernel they want to boot with the -kernel option 3. ``-bios `` - Tells QEMU to load the specified file as the firmwr= ae. =20 ``-tb-size`` option (since 5.0) --=20 2.26.2