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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=401675184=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/19 17:39:51 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, philmd@redhat.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Currently every c file that includes boot.h also includes loader.h before it. Which is why the build works fine. We should be able to include just boot.h though so this is a small fixup to allow that. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng --- include/hw/riscv/boot.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 474a940ad5..9daa98da08 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -21,6 +21,7 @@ #define RISCV_BOOT_H =20 #include "exec/cpu-defs.h" +#include "hw/loader.h" =20 void riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, --=20 2.26.2 From nobody Thu Dec 18 00:16:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1589924486; cv=none; d=zohomail.com; s=zohoarc; b=Rp0/YX3dFf4OA9O8jTS9OeOJBZ5ya2HpVbPcFWX79qq5FgR9sDu4w3qe0wLvCBBk5exW60qVaXY4/E4iGRfjBRSEOtyCnWi9B3cfRRZv/KHszpBJoyqX52zRrrCBA3/4n/tQIkQWZ2SSbhGBWzlMbkmoR+TK6c5s1oayojA5fdg= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=401675184=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/19 17:39:51 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, philmd@redhat.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The reset vector is set in the init function don't set it again in realize. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 059d71f2c7..5eb3c02735 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -133,6 +133,7 @@ static void riscv_base32_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, 0); + set_resetvec(env, DEFAULT_RSTVEC); } =20 static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) @@ -180,6 +181,7 @@ static void riscv_base64_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, 0); + set_resetvec(env, DEFAULT_RSTVEC); } =20 static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) @@ -399,7 +401,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) } =20 set_priv_version(env, priv_version); - set_resetvec(env, DEFAULT_RSTVEC); =20 if (cpu->cfg.mmu) { set_feature(env, RISCV_FEATURE_MMU); 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charset="utf-8" Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture. For more details on lowRISC see here: https://github.com/lowRISC/ibex Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: LIU Zhiwei --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d0e7f5b9c5..8733d7467f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -35,6 +35,7 @@ #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") +#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5eb3c02735..eb2bbc87ae 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -156,6 +156,15 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) set_feature(env, RISCV_FEATURE_PMP); } =20 +static void rv32imcu_nommu_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + set_misa(env, RV32 | RVI | RVM | RVC | RVU); + set_priv_version(env, PRIV_VERSION_1_10_0); + set_resetvec(env, 0x8090); + set_feature(env, RISCV_FEATURE_PMP); +} + static void rv32imacu_nommu_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -619,6 +628,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), #if defined(TARGET_RISCV32) DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_in= it), --=20 2.26.2 From nobody Thu Dec 18 00:16:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="240814192" IronPort-SDR: KOAq0FdxX+hwplEaG0Y9XY6O7u/ZROh2+NYwE5b6CFP2b22C/bjNUNKFZbSNWZubJ13AeUrkuv O9D2zck0Kqz+DYTdPwAlneEULVLqffBMc= IronPort-SDR: x6scoKzYlaPG1h4AqQIlGb2f62ekLrse+VAhGpxneS6MB4ievXhom8e5Lsdv2BT7W5EGYaPbJC cxvwAiJeEiKA== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 4/9] riscv: Initial commit of OpenTitan machine Date: Tue, 19 May 2020 14:31:35 -0700 Message-Id: <249f5217b56003998684359bfe7d1822dcd1a481.1589923785.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=401675184=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/19 17:39:51 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, philmd@redhat.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- default-configs/riscv32-softmmu.mak | 1 + default-configs/riscv64-softmmu.mak | 11 +- include/hw/riscv/opentitan.h | 63 +++++++++++ hw/riscv/opentitan.c | 169 ++++++++++++++++++++++++++++ MAINTAINERS | 9 ++ hw/riscv/Kconfig | 5 + hw/riscv/Makefile.objs | 1 + 7 files changed, 258 insertions(+), 1 deletion(-) create mode 100644 include/hw/riscv/opentitan.h create mode 100644 hw/riscv/opentitan.c diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-= softmmu.mak index 1ae077ed87..94a236c9c2 100644 --- a/default-configs/riscv32-softmmu.mak +++ b/default-configs/riscv32-softmmu.mak @@ -10,3 +10,4 @@ CONFIG_SPIKE=3Dy CONFIG_SIFIVE_E=3Dy CONFIG_SIFIVE_U=3Dy CONFIG_RISCV_VIRT=3Dy +CONFIG_OPENTITAN=3Dy diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-= softmmu.mak index 235c6f473f..aaf6d735bb 100644 --- a/default-configs/riscv64-softmmu.mak +++ b/default-configs/riscv64-softmmu.mak @@ -1,3 +1,12 @@ # Default configuration for riscv64-softmmu =20 -include riscv32-softmmu.mak +# Uncomment the following lines to disable these optional devices: +# +#CONFIG_PCI_DEVICES=3Dn + +# Boards: +# +CONFIG_SPIKE=3Dy +CONFIG_SIFIVE_E=3Dy +CONFIG_SIFIVE_U=3Dy +CONFIG_RISCV_VIRT=3Dy diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h new file mode 100644 index 0000000000..15a3d87ed0 --- /dev/null +++ b/include/hw/riscv/opentitan.h @@ -0,0 +1,63 @@ +/* + * QEMU RISC-V Board Compatible with OpenTitan FPGA platform + * + * Copyright (c) 2020 Western Digital + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_OPENTITAN_H +#define HW_OPENTITAN_H + +#include "hw/riscv/riscv_hart.h" + +#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" +#define RISCV_IBEX_SOC(obj) \ + OBJECT_CHECK(LowRISCIbexSoCState, (obj), TYPE_RISCV_IBEX_SOC) + +typedef struct LowRISCIbexSoCState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + RISCVHartArrayState cpus; + MemoryRegion flash_mem; + MemoryRegion rom; +} LowRISCIbexSoCState; + +typedef struct OpenTitanState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + LowRISCIbexSoCState soc; +} OpenTitanState; + +enum { + IBEX_ROM, + IBEX_RAM, + IBEX_FLASH, + IBEX_UART, + IBEX_GPIO, + IBEX_SPI, + IBEX_FLASH_CTRL, + IBEX_RV_TIMER, + IBEX_AES, + IBEX_HMAC, + IBEX_PLIC, + IBEX_PINMUX, + IBEX_ALERT_HANDLER, + IBEX_USBDEV, +}; + +#endif diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c new file mode 100644 index 0000000000..c00f0720ab --- /dev/null +++ b/hw/riscv/opentitan.c @@ -0,0 +1,169 @@ +/* + * QEMU RISC-V Board Compatible with OpenTitan FPGA platform + * + * Copyright (c) 2020 Western Digital + * + * Provides a board compatible with the OpenTitan FPGA platform: + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "hw/riscv/opentitan.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/misc/unimp.h" +#include "hw/riscv/boot.h" +#include "exec/address-spaces.h" + +static const struct MemmapEntry { + hwaddr base; + hwaddr size; +} ibex_memmap[] =3D { + [IBEX_ROM] =3D { 0x00008000, 0xc000 }, + [IBEX_RAM] =3D { 0x10000000, 0x10000 }, + [IBEX_FLASH] =3D { 0x20000000, 0x80000 }, + [IBEX_UART] =3D { 0x40000000, 0x10000 }, + [IBEX_GPIO] =3D { 0x40010000, 0x10000 }, + [IBEX_SPI] =3D { 0x40020000, 0x10000 }, + [IBEX_FLASH_CTRL] =3D { 0x40030000, 0x10000 }, + [IBEX_PINMUX] =3D { 0x40070000, 0x10000 }, + [IBEX_RV_TIMER] =3D { 0x40080000, 0x10000 }, + [IBEX_PLIC] =3D { 0x40090000, 0x10000 }, + [IBEX_AES] =3D { 0x40110000, 0x10000 }, + [IBEX_HMAC] =3D { 0x40120000, 0x10000 }, + [IBEX_ALERT_HANDLER] =3D { 0x40130000, 0x10000 }, + [IBEX_USBDEV] =3D { 0x40150000, 0x10000 } +}; + +static void riscv_opentitan_init(MachineState *machine) +{ + const struct MemmapEntry *memmap =3D ibex_memmap; + OpenTitanState *s =3D g_new0(OpenTitanState, 1); + MemoryRegion *sys_mem =3D get_system_memory(); + MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); + + /* Initialize SoC */ + object_initialize_child(OBJECT(machine), "soc", &s->soc, + sizeof(s->soc), TYPE_RISCV_IBEX_SOC, + &error_abort, NULL); + object_property_set_bool(OBJECT(&s->soc), true, "realized", + &error_abort); + + memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram", + memmap[IBEX_RAM].size, &error_fatal); + memory_region_add_subregion(sys_mem, + memmap[IBEX_RAM].base, main_mem); + + + if (machine->firmware) { + riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL= ); + } + + if (machine->kernel_filename) { + riscv_load_kernel(machine->kernel_filename, NULL); + } +} + +static void riscv_opentitan_machine_init(MachineClass *mc) +{ + mc->desc =3D "RISC-V Board compatible with OpenTitan"; + mc->init =3D riscv_opentitan_init; + mc->max_cpus =3D 1; + mc->default_cpu_type =3D TYPE_RISCV_CPU_IBEX; +} + +DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init) + +static void riscv_lowrisc_ibex_soc_init(Object *obj) +{ + LowRISCIbexSoCState *s =3D RISCV_IBEX_SOC(obj); + + object_initialize_child(obj, "cpus", &s->cpus, + sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, + &error_abort, NULL); +} + +static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **e= rrp) +{ + const struct MemmapEntry *memmap =3D ibex_memmap; + MachineState *ms =3D MACHINE(qdev_get_machine()); + LowRISCIbexSoCState *s =3D RISCV_IBEX_SOC(dev_soc); + MemoryRegion *sys_mem =3D get_system_memory(); + + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", + &error_abort); + object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", + &error_abort); + object_property_set_bool(OBJECT(&s->cpus), true, "realized", + &error_abort); + + /* Boot ROM */ + memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.r= om", + memmap[IBEX_ROM].size, &error_fatal); + memory_region_add_subregion(sys_mem, + memmap[IBEX_ROM].base, &s->rom); + + /* Flash memory */ + memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.= ibex.flash", + memmap[IBEX_FLASH].size, &error_fatal); + memory_region_add_subregion(sys_mem, memmap[IBEX_FLASH].base, + &s->flash_mem); + + create_unimplemented_device("riscv.lowrisc.ibex.uart", + memmap[IBEX_UART].base, memmap[IBEX_UART].size); + create_unimplemented_device("riscv.lowrisc.ibex.gpio", + memmap[IBEX_GPIO].base, memmap[IBEX_GPIO].size); + create_unimplemented_device("riscv.lowrisc.ibex.spi", + memmap[IBEX_SPI].base, memmap[IBEX_SPI].size); + create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", + memmap[IBEX_FLASH_CTRL].base, memmap[IBEX_FLASH_CTRL].size); + create_unimplemented_device("riscv.lowrisc.ibex.rv_timer", + memmap[IBEX_RV_TIMER].base, memmap[IBEX_RV_TIMER].size); + create_unimplemented_device("riscv.lowrisc.ibex.aes", + memmap[IBEX_AES].base, memmap[IBEX_AES].size); + create_unimplemented_device("riscv.lowrisc.ibex.hmac", + memmap[IBEX_HMAC].base, memmap[IBEX_HMAC].size); + create_unimplemented_device("riscv.lowrisc.ibex.plic", + memmap[IBEX_PLIC].base, memmap[IBEX_PLIC].size); + create_unimplemented_device("riscv.lowrisc.ibex.pinmux", + memmap[IBEX_PINMUX].base, memmap[IBEX_PINMUX].size); + create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", + memmap[IBEX_ALERT_HANDLER].base, memmap[IBEX_ALERT_HANDLER].size); + create_unimplemented_device("riscv.lowrisc.ibex.USBDEV", + memmap[IBEX_USBDEV].base, memmap[IBEX_USBDEV].size); +} + +static void riscv_lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D riscv_lowrisc_ibex_soc_realize; + /* Reason: Uses serial_hds in realize function, thus can't be used twi= ce */ + dc->user_creatable =3D false; +} + +static const TypeInfo riscv_lowrisc_ibex_soc_type_info =3D { + .name =3D TYPE_RISCV_IBEX_SOC, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(LowRISCIbexSoCState), + .instance_init =3D riscv_lowrisc_ibex_soc_init, + .class_init =3D riscv_lowrisc_ibex_soc_class_init, +}; + +static void riscv_lowrisc_ibex_soc_register_types(void) +{ + type_register_static(&riscv_lowrisc_ibex_soc_type_info); +} + +type_init(riscv_lowrisc_ibex_soc_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index 47ef3139e6..a5f6aaa266 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1230,6 +1230,15 @@ F: pc-bios/canyonlands.dt[sb] F: pc-bios/u-boot-sam460ex-20100605.bin F: roms/u-boot-sam460ex =20 +RISC-V Machines +--------------- +OpenTitan +M: Alistair Francis +L: qemu-riscv@nongnu.org +S: Supported +F: hw/riscv/opentitan.c +F: include/hw/riscv/opentitan.h + SH4 Machines ------------ R2D diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index ff9fbe958a..94d19571f7 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -27,6 +27,11 @@ config SPIKE select HTIF select SIFIVE =20 +config OPENTITAN + bool + select HART + select UNIMP + config RISCV_VIRT bool imply PCI_DEVICES diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index fc3c6dd7c8..57cc708f5d 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -1,6 +1,7 @@ obj-y +=3D boot.o obj-$(CONFIG_SPIKE) +=3D riscv_htif.o obj-$(CONFIG_HART) +=3D riscv_hart.o +obj-$(CONFIG_OPENTITAN) +=3D opentitan.o obj-$(CONFIG_SIFIVE_E) +=3D sifive_e.o obj-$(CONFIG_SIFIVE_E) +=3D sifive_e_prci.o obj-$(CONFIG_SIFIVE) +=3D sifive_clint.o --=20 2.26.2 From nobody Thu Dec 18 00:16:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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IronPort-SDR: FRm/9PkVnRMNbxMCVEh6nGLmZtMD2cRt1Ji22qezq8SkdMquuuYg7PIgzgeaDKlmEtVD73L+pw 1/KI+mCSbIDA30E3tWu6+aOELZxi731cj+pbQKamoHL9I73tTkH7nV5MY1ATer5JFYaimOJb7Z ho5vhOEKc0Hs5K95u+rmNo00Jwm2+9M0CogtcD01gZc1nAQTvQZnwN+rKzs47NuiKaGfiiYJJq MbHQQIjx1Thqmmhr0JctNEMVvHXS7Jy8yEYNg1BiPne8gBbfCi5TIdwQZOC1OGErVVnYl+1Zb2 fGs= X-IronPort-AV: E=Sophos;i="5.73,411,1583164800"; d="scan'208";a="240814195" IronPort-SDR: jAHZj/oAmQ5SUYiK3pGgeISwVauvC1o+SVM+vC+1Sf3r2fsP/z801ldedSI2VEq4WZgA2g3c3d 2rxhVwFu8ys720TSDb5SkuzYCRVznCvYE= IronPort-SDR: vo5/aEfrIDz0qIabJZDVWqazCcc9p/pU7ALHnGnqwBTjBkwyqLQMFeYJzcUTmsqHzB27agCp/N c7v6T8Nzt/Ew== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 5/9] hw/char: Initial commit of Ibex UART Date: Tue, 19 May 2020 14:31:38 -0700 Message-Id: <4ade0bb85be9bc0b6ab433bb8ad67350d7da1cd3.1589923785.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=401675184=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/19 17:39:51 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, philmd@redhat.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This is the initial commit of the Ibex UART device. Serial TX is working, while RX has been implemeneted but untested. This is based on the documentation from: https://docs.opentitan.org/hw/ip/uart/doc/ Signed-off-by: Alistair Francis --- include/hw/char/ibex_uart.h | 110 ++++++++ hw/char/ibex_uart.c | 492 ++++++++++++++++++++++++++++++++++++ MAINTAINERS | 2 + hw/char/Makefile.objs | 1 + hw/riscv/Kconfig | 4 + 5 files changed, 609 insertions(+) create mode 100644 include/hw/char/ibex_uart.h create mode 100644 hw/char/ibex_uart.c diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h new file mode 100644 index 0000000000..2bec772615 --- /dev/null +++ b/include/hw/char/ibex_uart.h @@ -0,0 +1,110 @@ +/* + * QEMU lowRISC Ibex UART device + * + * Copyright (c) 2020 Western Digital + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_IBEX_UART_H +#define HW_IBEX_UART_H + +#include "hw/sysbus.h" +#include "chardev/char-fe.h" +#include "qemu/timer.h" + +#define IBEX_UART_INTR_STATE 0x00 + #define INTR_STATE_TX_WATERMARK (1 << 0) + #define INTR_STATE_RX_WATERMARK (1 << 1) + #define INTR_STATE_TX_EMPTY (1 << 2) + #define INTR_STATE_RX_OVERFLOW (1 << 3) +#define IBEX_UART_INTR_ENABLE 0x04 +#define IBEX_UART_INTR_TEST 0x08 + +#define IBEX_UART_CTRL 0x0c + #define UART_CTRL_TX_ENABLE (1 << 0) + #define UART_CTRL_RX_ENABLE (1 << 1) + #define UART_CTRL_NF (1 << 2) + #define UART_CTRL_SLPBK (1 << 4) + #define UART_CTRL_LLPBK (1 << 5) + #define UART_CTRL_PARITY_EN (1 << 6) + #define UART_CTRL_PARITY_ODD (1 << 7) + #define UART_CTRL_RXBLVL (3 << 8) + #define UART_CTRL_NCO (0xFFFF << 16) + +#define IBEX_UART_STATUS 0x10 + #define UART_STATUS_TXFULL (1 << 0) + #define UART_STATUS_RXFULL (1 << 1) + #define UART_STATUS_TXEMPTY (1 << 2) + #define UART_STATUS_RXIDLE (1 << 4) + #define UART_STATUS_RXEMPTY (1 << 5) + +#define IBEX_UART_RDATA 0x14 +#define IBEX_UART_WDATA 0x18 + +#define IBEX_UART_FIFO_CTRL 0x1c + #define FIFO_CTRL_RXRST (1 << 0) + #define FIFO_CTRL_TXRST (1 << 1) + #define FIFO_CTRL_RXILVL (7 << 2) + #define FIFO_CTRL_RXILVL_SHIFT (2) + #define FIFO_CTRL_TXILVL (3 << 5) + #define FIFO_CTRL_TXILVL_SHIFT (5) + +#define IBEX_UART_FIFO_STATUS 0x20 +#define IBEX_UART_OVRD 0x24 +#define IBEX_UART_VAL 0x28 +#define IBEX_UART_TIMEOUT_CTRL 0x2c + +#define IBEX_UART_TX_FIFO_SIZE 16 + +#define TYPE_IBEX_UART "ibex-uart" +#define IBEX_UART(obj) \ + OBJECT_CHECK(IbexUartState, (obj), TYPE_IBEX_UART) + +typedef struct { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion mmio; + + uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE]; + uint32_t tx_level; + + QEMUTimer *fifo_trigger_handle; + uint64_t char_tx_time; + + uint32_t uart_intr_state; + uint32_t uart_intr_enable; + uint32_t uart_ctrl; + uint32_t uart_status; + uint32_t uart_rdata; + uint32_t uart_fifo_ctrl; + uint32_t uart_fifo_status; + uint32_t uart_ovrd; + uint32_t uart_val; + uint32_t uart_timeout_ctrl; + + CharBackend chr; + qemu_irq tx_watermark; + qemu_irq rx_watermark; + qemu_irq tx_empty; + qemu_irq rx_overflow; +} IbexUartState; +#endif /* HW_IBEX_UART_H */ diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c new file mode 100644 index 0000000000..c416325d73 --- /dev/null +++ b/hw/char/ibex_uart.c @@ -0,0 +1,492 @@ +/* + * QEMU lowRISC Ibex UART device + * + * Copyright (c) 2020 Western Digital + * + * For details check the documentation here: + * https://docs.opentitan.org/hw/ip/uart/doc/ + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/char/ibex_uart.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" + +static void ibex_uart_update_irqs(IbexUartState *s) +{ + if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_TX_WATERMARK= ) { + qemu_set_irq(s->tx_watermark, 1); + } else { + qemu_set_irq(s->tx_watermark, 0); + } + + if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_RX_WATERMARK= ) { + qemu_set_irq(s->rx_watermark, 1); + } else { + qemu_set_irq(s->rx_watermark, 0); + } + + if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_TX_EMPTY) { + qemu_set_irq(s->tx_empty, 1); + } else { + qemu_set_irq(s->tx_empty, 0); + } + + if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_RX_OVERFLOW)= { + qemu_set_irq(s->rx_overflow, 1); + } else { + qemu_set_irq(s->rx_overflow, 0); + } +} + +static int ibex_uart_can_receive(void *opaque) +{ + IbexUartState *s =3D opaque; + + if (s->uart_ctrl & UART_CTRL_RX_ENABLE) { + return 1; + } + + return 0; +} + +static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size) +{ + IbexUartState *s =3D opaque; + uint8_t rx_fifo_level =3D (s->uart_fifo_ctrl & FIFO_CTRL_RXILVL) + >> FIFO_CTRL_RXILVL_SHIFT; + + s->uart_rdata =3D *buf; + + s->uart_status &=3D ~UART_STATUS_RXIDLE; + s->uart_status &=3D ~UART_STATUS_RXEMPTY; + + if (size > rx_fifo_level) { + s->uart_intr_state |=3D INTR_STATE_RX_WATERMARK; + } + + ibex_uart_update_irqs(s); +} + +static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond, + void *opaque) +{ + IbexUartState *s =3D opaque; + uint8_t tx_fifo_level =3D (s->uart_fifo_ctrl & FIFO_CTRL_TXILVL) + >> FIFO_CTRL_TXILVL_SHIFT; + int ret; + + /* instant drain the fifo when there's no back-end */ + if (!qemu_chr_fe_backend_connected(&s->chr)) { + s->tx_level =3D 0; + return FALSE; + } + + if (!s->tx_level) { + s->uart_status &=3D UART_STATUS_TXFULL; + s->uart_status |=3D UART_STATUS_TXEMPTY; + s->uart_intr_state |=3D INTR_STATE_TX_EMPTY; + s->uart_intr_state &=3D ~INTR_STATE_TX_WATERMARK; + ibex_uart_update_irqs(s); + return FALSE; + } + + ret =3D qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level); + + if (ret >=3D 0) { + s->tx_level -=3D ret; + memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_level); + } + + if (s->tx_level) { + guint r =3D qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, + ibex_uart_xmit, s); + if (!r) { + s->tx_level =3D 0; + return FALSE; + } + } + + /* Clear the TX Full bit */ + if (s->tx_level !=3D IBEX_UART_TX_FIFO_SIZE) { + s->uart_status &=3D ~UART_STATUS_TXFULL; + } + + /* Disable the TX_WATERMARK IRQ */ + if (s->tx_level < tx_fifo_level) { + s->uart_intr_state &=3D ~INTR_STATE_TX_WATERMARK; + } + + /* Set TX empty */ + if (s->tx_level =3D=3D 0) { + s->uart_status |=3D UART_STATUS_TXEMPTY; + s->uart_intr_state |=3D INTR_STATE_TX_EMPTY; + } + + ibex_uart_update_irqs(s); + return FALSE; +} + +static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf, + int size) +{ + uint64_t current_time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint8_t tx_fifo_level =3D (s->uart_fifo_ctrl & FIFO_CTRL_TXILVL) + >> FIFO_CTRL_TXILVL_SHIFT; + + if (size > IBEX_UART_TX_FIFO_SIZE - s->tx_level) { + size =3D IBEX_UART_TX_FIFO_SIZE - s->tx_level; + qemu_log_mask(LOG_GUEST_ERROR, "ibex_uart: TX FIFO overflow"); + } + + memcpy(s->tx_fifo + s->tx_level, buf, size); + s->tx_level +=3D size; + + if (s->tx_level > 0) { + s->uart_status &=3D ~UART_STATUS_TXEMPTY; + } + + if (s->tx_level >=3D tx_fifo_level) { + s->uart_intr_state |=3D INTR_STATE_TX_WATERMARK; + ibex_uart_update_irqs(s); + } + + if (s->tx_level =3D=3D IBEX_UART_TX_FIFO_SIZE) { + s->uart_status |=3D UART_STATUS_TXFULL; + } + + timer_mod(s->fifo_trigger_handle, current_time + + (s->char_tx_time * 4)); +} + +static void ibex_uart_reset(DeviceState *dev) +{ + IbexUartState *s =3D IBEX_UART(dev); + + s->uart_intr_state =3D 0x00000000; + s->uart_intr_state =3D 0x00000000; + s->uart_intr_enable =3D 0x00000000; + s->uart_ctrl =3D 0x00000000; + s->uart_status =3D 0x0000003c; + s->uart_rdata =3D 0x00000000; + s->uart_fifo_ctrl =3D 0x00000000; + s->uart_fifo_status =3D 0x00000000; + s->uart_ovrd =3D 0x00000000; + s->uart_val =3D 0x00000000; + s->uart_timeout_ctrl =3D 0x00000000; + + s->tx_level =3D 0; + + s->char_tx_time =3D (NANOSECONDS_PER_SECOND / 230400) * 10; + + ibex_uart_update_irqs(s); +} + +static uint64_t ibex_uart_read(void *opaque, hwaddr addr, + unsigned int size) +{ + IbexUartState *s =3D opaque; + uint64_t retvalue =3D 0; + + switch (addr) { + case IBEX_UART_INTR_STATE: + retvalue =3D s->uart_intr_state; + break; + case IBEX_UART_INTR_ENABLE: + retvalue =3D s->uart_intr_enable; + break; + case IBEX_UART_INTR_TEST: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: wdata is write only\n", __func__); + break; + + case IBEX_UART_CTRL: + retvalue =3D s->uart_ctrl; + break; + case IBEX_UART_STATUS: + retvalue =3D s->uart_status; + break; + + case IBEX_UART_RDATA: + retvalue =3D s->uart_rdata; + if (s->uart_ctrl & UART_CTRL_RX_ENABLE) { + qemu_chr_fe_accept_input(&s->chr); + + s->uart_status |=3D UART_STATUS_RXIDLE; + s->uart_status |=3D UART_STATUS_RXEMPTY; + } + break; + case IBEX_UART_WDATA: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: wdata is write only\n", __func__); + break; + + case IBEX_UART_FIFO_CTRL: + retvalue =3D s->uart_fifo_ctrl; + break; + case IBEX_UART_FIFO_STATUS: + retvalue =3D s->uart_fifo_status; + + retvalue |=3D s->tx_level & 0x1F; + + qemu_log_mask(LOG_UNIMP, + "%s: RX fifos are not supported\n", __func__); + break; + + case IBEX_UART_OVRD: + retvalue =3D s->uart_ovrd; + qemu_log_mask(LOG_UNIMP, + "%s: ovrd is not supported\n", __func__); + break; + case IBEX_UART_VAL: + retvalue =3D s->uart_val; + qemu_log_mask(LOG_UNIMP, + "%s: val is not supported\n", __func__); + break; + case IBEX_UART_TIMEOUT_CTRL: + retvalue =3D s->uart_timeout_ctrl; + qemu_log_mask(LOG_UNIMP, + "%s: timeout_ctrl is not supported\n", __func__); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + return 0; + } + + return retvalue; +} + +static void ibex_uart_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + IbexUartState *s =3D opaque; + uint32_t value =3D val64; + + switch (addr) { + case IBEX_UART_INTR_STATE: + /* Write 1 clear */ + s->uart_intr_state &=3D ~value; + ibex_uart_update_irqs(s); + break; + case IBEX_UART_INTR_ENABLE: + s->uart_intr_enable =3D value; + ibex_uart_update_irqs(s); + break; + case IBEX_UART_INTR_TEST: + s->uart_intr_state |=3D value; + ibex_uart_update_irqs(s); + break; + + case IBEX_UART_CTRL: + s->uart_ctrl =3D value; + + if (value & UART_CTRL_NF) { + qemu_log_mask(LOG_UNIMP, + "%s: UART_CTRL_NF is not supported\n", __func__); + } + if (value & UART_CTRL_SLPBK) { + qemu_log_mask(LOG_UNIMP, + "%s: UART_CTRL_SLPBK is not supported\n", __func= __); + } + if (value & UART_CTRL_LLPBK) { + qemu_log_mask(LOG_UNIMP, + "%s: UART_CTRL_LLPBK is not supported\n", __func= __); + } + if (value & UART_CTRL_PARITY_EN) { + qemu_log_mask(LOG_UNIMP, + "%s: UART_CTRL_PARITY_EN is not supported\n", + __func__); + } + if (value & UART_CTRL_PARITY_ODD) { + qemu_log_mask(LOG_UNIMP, + "%s: UART_CTRL_PARITY_ODD is not supported\n", + __func__); + } + if (value & UART_CTRL_RXBLVL) { + qemu_log_mask(LOG_UNIMP, + "%s: UART_CTRL_RXBLVL is not supported\n", __fun= c__); + } + if (value & UART_CTRL_NCO) { + uint64_t baud =3D ((value & UART_CTRL_NCO) >> 16); + baud *=3D 1000; + baud /=3D 2 ^ 20; + + s->char_tx_time =3D (NANOSECONDS_PER_SECOND / baud) * 10; + } + break; + case IBEX_UART_STATUS: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: status is read only\n", __func__); + break; + + case IBEX_UART_RDATA: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: rdata is read only\n", __func__); + break; + case IBEX_UART_WDATA: + uart_write_tx_fifo(s, (uint8_t *) &value, 1); + break; + + case IBEX_UART_FIFO_CTRL: + s->uart_fifo_ctrl =3D value; + + if (value & FIFO_CTRL_RXRST) { + qemu_log_mask(LOG_UNIMP, + "%s: RX fifos are not supported\n", __func__); + } + if (value & FIFO_CTRL_TXRST) { + s->tx_level =3D 0; + } + break; + case IBEX_UART_FIFO_STATUS: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: fifo_status is read only\n", __func__); + break; + + case IBEX_UART_OVRD: + s->uart_ovrd =3D value; + qemu_log_mask(LOG_UNIMP, + "%s: ovrd is not supported\n", __func__); + break; + case IBEX_UART_VAL: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: val is read only\n", __func__); + break; + case IBEX_UART_TIMEOUT_CTRL: + s->uart_timeout_ctrl =3D value; + qemu_log_mask(LOG_UNIMP, + "%s: timeout_ctrl is not supported\n", __func__); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + } +} + +static void fifo_trigger_update(void *opaque) +{ + IbexUartState *s =3D opaque; + + if (s->uart_ctrl & UART_CTRL_TX_ENABLE) { + ibex_uart_xmit(NULL, G_IO_OUT, s); + } +} + +static const MemoryRegionOps ibex_uart_ops =3D { + .read =3D ibex_uart_read, + .write =3D ibex_uart_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, +}; + +static int cadence_uart_post_load(void *opaque, int version_id) +{ + IbexUartState *s =3D opaque; + + ibex_uart_update_irqs(s); + return 0; +} + +static const VMStateDescription vmstate_ibex_uart =3D { + .name =3D TYPE_IBEX_UART, + .version_id =3D 1, + .minimum_version_id =3D 1, + .post_load =3D cadence_uart_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8_ARRAY(tx_fifo, IbexUartState, + IBEX_UART_TX_FIFO_SIZE), + VMSTATE_UINT32(tx_level, IbexUartState), + VMSTATE_UINT64(char_tx_time, IbexUartState), + VMSTATE_TIMER_PTR(fifo_trigger_handle, IbexUartState), + VMSTATE_UINT32(uart_intr_state, IbexUartState), + VMSTATE_UINT32(uart_intr_enable, IbexUartState), + VMSTATE_UINT32(uart_ctrl, IbexUartState), + VMSTATE_UINT32(uart_status, IbexUartState), + VMSTATE_UINT32(uart_rdata, IbexUartState), + VMSTATE_UINT32(uart_fifo_ctrl, IbexUartState), + VMSTATE_UINT32(uart_fifo_status, IbexUartState), + VMSTATE_UINT32(uart_ovrd, IbexUartState), + VMSTATE_UINT32(uart_val, IbexUartState), + VMSTATE_UINT32(uart_timeout_ctrl, IbexUartState), + VMSTATE_END_OF_LIST() + } +}; + +static Property ibex_uart_properties[] =3D { + DEFINE_PROP_CHR("chardev", IbexUartState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ibex_uart_init(Object *obj) +{ + IbexUartState *s =3D IBEX_UART(obj); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_overflow); + + memory_region_init_io(&s->mmio, obj, &ibex_uart_ops, s, + TYPE_IBEX_UART, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void ibex_uart_realize(DeviceState *dev, Error **errp) +{ + IbexUartState *s =3D IBEX_UART(dev); + + s->fifo_trigger_handle =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + fifo_trigger_update, s); + + qemu_chr_fe_set_handlers(&s->chr, ibex_uart_can_receive, + ibex_uart_receive, NULL, NULL, + s, NULL, true); +} + +static void ibex_uart_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D ibex_uart_reset; + dc->realize =3D ibex_uart_realize; + dc->vmsd =3D &vmstate_ibex_uart; + device_class_set_props(dc, ibex_uart_properties); +} + +static const TypeInfo ibex_uart_info =3D { + .name =3D TYPE_IBEX_UART, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IbexUartState), + .instance_init =3D ibex_uart_init, + .class_init =3D ibex_uart_class_init, +}; + +static void ibex_uart_register_types(void) +{ + type_register_static(&ibex_uart_info); +} + +type_init(ibex_uart_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index a5f6aaa266..7d27a44d15 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1237,7 +1237,9 @@ M: Alistair Francis L: qemu-riscv@nongnu.org S: Supported F: hw/riscv/opentitan.c +F: hw/char/ibex_uart.c F: include/hw/riscv/opentitan.h +F: include/hw/char/ibex_uart.h =20 SH4 Machines ------------ diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs index 9e9a6c1aff..633996be5b 100644 --- a/hw/char/Makefile.objs +++ b/hw/char/Makefile.objs @@ -12,6 +12,7 @@ common-obj-$(CONFIG_VIRTIO_SERIAL) +=3D virtio-console.o common-obj-$(CONFIG_XILINX) +=3D xilinx_uartlite.o common-obj-$(CONFIG_XEN) +=3D xen_console.o common-obj-$(CONFIG_CADENCE) +=3D cadence_uart.o +common-obj-$(CONFIG_IBEX) +=3D ibex_uart.o =20 common-obj-$(CONFIG_EXYNOS4) +=3D exynos4210_uart.o common-obj-$(CONFIG_COLDFIRE) +=3D mcf_uart.o diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 94d19571f7..28947ef3e0 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -4,6 +4,9 @@ config HTIF config HART bool =20 +config IBEX + bool + config SIFIVE bool select MSI_NONBROKEN @@ -29,6 +32,7 @@ config SPIKE =20 config OPENTITAN bool + select IBEX select HART select UNIMP =20 --=20 2.26.2 From nobody Thu Dec 18 00:16:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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IronPort-SDR: V54GoKxgCcSBzfCsAwOPzXxx9IjWAqxUEjQGZi86kMJnKZ6U1bmVnOI/Uz/lpJufG5Uq6FU9Lg HhWuDjnX/a/Ty3wlKF8qd3hMb83DBvhxN0uiQ8JDeUfK8gFBYHz8/oTibL69X1jF6V3ce+iP0n CBTHzEXAi48+iHeudY3jBxtjaCHn+jaJihIBsYzuxZRnDJOd4r+v5THFuYd6UIhbziDRCxbcBV GDuFOUl3xVi65orSekKON1ZIVX20MhJPKhbL+vG//UNvApX3ARhJK/2R1UeJ88I1qkFnQokewl 7DY= X-IronPort-AV: E=Sophos;i="5.73,411,1583164800"; d="scan'208";a="240814200" IronPort-SDR: 5GGlCo6zi66GJWG22cAc1spgR3ftkmp1Yf7Q/rWjJyMVa+bMNe/NzbtGruT6rpHi29Ey0hqMTN 4X99fyf2Cqo0zpObvhYszXXcoAM8PB3wo= IronPort-SDR: eUeqXox3rXE6JExt9ngHhPfckaikBDaHVxMW/SpCoV9/VQLl6Q/mgy53PCICsMfWzKKMZef224 VJLWmA80yQIw== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC Date: Tue, 19 May 2020 14:31:41 -0700 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=401675184=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/19 17:39:51 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, philmd@redhat.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The Ibex core contains a PLIC that although similar to the RISC-V spec is not RISC-V spec compliant. This patch implements a Ibex PLIC in a somewhat generic way. As the current RISC-V PLIC needs tidying up, my hope is that as the Ibex PLIC move towards spec compliance this PLIC implementation can be updated until it can replace the current PLIC. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/intc/ibex_plic.h | 63 +++++++++ hw/intc/ibex_plic.c | 261 ++++++++++++++++++++++++++++++++++++ MAINTAINERS | 2 + hw/intc/Makefile.objs | 1 + 4 files changed, 327 insertions(+) create mode 100644 include/hw/intc/ibex_plic.h create mode 100644 hw/intc/ibex_plic.c diff --git a/include/hw/intc/ibex_plic.h b/include/hw/intc/ibex_plic.h new file mode 100644 index 0000000000..ddc7909903 --- /dev/null +++ b/include/hw/intc/ibex_plic.h @@ -0,0 +1,63 @@ +/* + * QEMU RISC-V lowRISC Ibex PLIC + * + * Copyright (c) 2020 Western Digital + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_IBEX_PLIC_H +#define HW_IBEX_PLIC_H + +#include "hw/sysbus.h" + +#define TYPE_IBEX_PLIC "ibex-plic" +#define IBEX_PLIC(obj) \ + OBJECT_CHECK(IbexPlicState, (obj), TYPE_IBEX_PLIC) + +typedef struct IbexPlicState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + + uint32_t *pending; + uint32_t *source; + uint32_t *priority; + uint32_t *enable; + uint32_t threshold; + uint32_t claim; + + /* config */ + uint32_t num_cpus; + uint32_t num_sources; + + uint32_t pending_base; + uint32_t pending_num; + + uint32_t source_base; + uint32_t source_num; + + uint32_t priority_base; + uint32_t priority_num; + + uint32_t enable_base; + uint32_t enable_num; + + uint32_t threshold_base; + + uint32_t claim_base; +} IbexPlicState; + +#endif /* HW_IBEX_PLIC_H */ diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c new file mode 100644 index 0000000000..41079518c6 --- /dev/null +++ b/hw/intc/ibex_plic.c @@ -0,0 +1,261 @@ +/* + * QEMU RISC-V lowRISC Ibex PLIC + * + * Copyright (c) 2020 Western Digital + * + * Documentation avaliable: https://docs.opentitan.org/hw/ip/rv_plic/doc/ + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/qdev-properties.h" +#include "hw/core/cpu.h" +#include "hw/boards.h" +#include "hw/pci/msi.h" +#include "target/riscv/cpu_bits.h" +#include "target/riscv/cpu.h" +#include "hw/intc/ibex_plic.h" + +static bool addr_between(uint32_t addr, uint32_t base, uint32_t num) +{ + uint32_t end =3D base + (num * 0x04); + + if (addr >=3D base && addr < end) { + return true; + } + + return false; +} + +static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool lev= el) +{ + int pending_num =3D irq / 32; + + s->pending[pending_num] |=3D level << (irq % 32); +} + +static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context) +{ + int i; + + for (i =3D 0; i < s->pending_num; i++) { + uint32_t irq_num =3D ctz64(s->pending[i]) + (i * 32); + + if (!(s->pending[i] & s->enable[i])) { + /* No pending and enabled IRQ */ + continue; + } + + if (s->priority[irq_num] > s->threshold) { + if (!s->claim) { + s->claim =3D irq_num; + } + return true; + } + } + + return false; +} + +static void ibex_plic_update(IbexPlicState *s) +{ + CPUState *cpu; + int level, i; + + for (i =3D 0; i < s->num_cpus; i++) { + cpu =3D qemu_get_cpu(i); + + if (!cpu) { + continue; + } + + level =3D ibex_plic_irqs_pending(s, 0); + + riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level)= ); + } +} + +static void ibex_plic_reset(DeviceState *dev) +{ + IbexPlicState *s =3D IBEX_PLIC(dev); + + s->threshold =3D 0x00000000; + s->claim =3D 0x00000000; +} + +static uint64_t ibex_plic_read(void *opaque, hwaddr addr, + unsigned int size) +{ + IbexPlicState *s =3D opaque; + int offset; + uint32_t ret =3D 0; + + if (addr_between(addr, s->pending_base, s->pending_num)) { + offset =3D (addr - s->pending_base) / 4; + ret =3D s->pending[offset]; + } else if (addr_between(addr, s->source_base, s->source_num)) { + qemu_log_mask(LOG_UNIMP, + "%s: Interrupt source mode not supported\n", __func_= _); + } else if (addr_between(addr, s->priority_base, s->priority_num)) { + offset =3D (addr - s->priority_base) / 4; + ret =3D s->priority[offset]; + } else if (addr_between(addr, s->enable_base, s->enable_num)) { + offset =3D (addr - s->enable_base) / 4; + ret =3D s->enable[offset]; + } else if (addr_between(addr, s->threshold_base, 1)) { + ret =3D s->threshold; + } else if (addr_between(addr, s->claim_base, 1)) { + int pending_num =3D s->claim / 32; + s->pending[pending_num] &=3D ~(1 << (s->claim % 32)); + + ret =3D s->claim; + } + + return ret; +} + +static void ibex_plic_write(void *opaque, hwaddr addr, + uint64_t value, unsigned int size) +{ + IbexPlicState *s =3D opaque; + + if (addr_between(addr, s->pending_base, s->pending_num)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Pending registers are read only\n", __func__); + } else if (addr_between(addr, s->source_base, s->source_num)) { + qemu_log_mask(LOG_UNIMP, + "%s: Interrupt source mode not supported\n", __func_= _); + } else if (addr_between(addr, s->priority_base, s->priority_num)) { + uint32_t irq =3D ((addr - s->priority_base) >> 2) + 1; + s->priority[irq] =3D value & 7; + } else if (addr_between(addr, s->enable_base, s->enable_num)) { + uint32_t enable_reg =3D (addr - s->enable_base) / 4; + + s->enable[enable_reg] =3D value; + } else if (addr_between(addr, s->threshold_base, 1)) { + s->threshold =3D value & 3; + } else if (addr_between(addr, s->claim_base, 1)) { + if (s->claim =3D=3D value) { + /* Interrupt was completed */ + s->claim =3D 0; + } + } + + ibex_plic_update(s); +} + +static const MemoryRegionOps ibex_plic_ops =3D { + .read =3D ibex_plic_read, + .write =3D ibex_plic_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + } +}; + +static void ibex_plic_irq_request(void *opaque, int irq, int level) +{ + IbexPlicState *s =3D opaque; + + ibex_plic_irqs_set_pending(s, irq, level > 0); + ibex_plic_update(s); +} + +static Property ibex_plic_properties[] =3D { + DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1), + DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80), + + DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0), + DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3), + + DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c), + DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3), + + DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18= ), + DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80), + + DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200), + DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3), + + DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x= 20c), + + DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ibex_plic_init(Object *obj) +{ + IbexPlicState *s =3D IBEX_PLIC(obj); + + memory_region_init_io(&s->mmio, obj, &ibex_plic_ops, s, + TYPE_IBEX_PLIC, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void ibex_plic_realize(DeviceState *dev, Error **errp) +{ + IbexPlicState *s =3D IBEX_PLIC(dev); + int i; + + s->pending =3D g_new0(uint32_t, s->pending_num); + s->source =3D g_new0(uint32_t, s->source_num); + s->priority =3D g_new0(uint32_t, s->priority_num); + s->enable =3D g_new0(uint32_t, s->enable_num); + + qdev_init_gpio_in(dev, ibex_plic_irq_request, s->num_sources); + + /* + * We can't allow the supervisor to control SEIP as this would allow t= he + * supervisor to clear a pending external interrupt which will result = in + * a lost interrupt in the case a PLIC is attached. The SEIP bit must = be + * hardware controlled when a PLIC is attached. + */ + MachineState *ms =3D MACHINE(qdev_get_machine()); + unsigned int smp_cpus =3D ms->smp.cpus; + for (i =3D 0; i < smp_cpus; i++) { + RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(i)); + if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) { + error_report("SEIP already claimed"); + exit(1); + } + } + + msi_nonbroken =3D true; +} + +static void ibex_plic_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D ibex_plic_reset; + device_class_set_props(dc, ibex_plic_properties); + dc->realize =3D ibex_plic_realize; +} + +static const TypeInfo ibex_plic_info =3D { + .name =3D TYPE_IBEX_PLIC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IbexPlicState), + .instance_init =3D ibex_plic_init, + .class_init =3D ibex_plic_class_init, +}; + +static void ibex_plic_register_types(void) +{ + type_register_static(&ibex_plic_info); +} + +type_init(ibex_plic_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index 7d27a44d15..34b7c1745d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1238,8 +1238,10 @@ L: qemu-riscv@nongnu.org S: Supported F: hw/riscv/opentitan.c F: hw/char/ibex_uart.c +F: hw/intc/ibex_plic.c F: include/hw/riscv/opentitan.h F: include/hw/char/ibex_uart.h +F: include/hw/intc/ibex_plic.h =20 SH4 Machines ------------ diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index f726d87532..a61e6728fe 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -49,3 +49,4 @@ obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_cpuif.o obj-$(CONFIG_MIPS_CPS) +=3D mips_gic.o obj-$(CONFIG_NIOS2) +=3D nios2_iic.o obj-$(CONFIG_OMPIC) +=3D ompic.o +obj-$(CONFIG_IBEX) +=3D ibex_plic.o --=20 2.26.2 From nobody Thu Dec 18 00:16:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/riscv/opentitan.h | 3 +++ hw/riscv/opentitan.c | 19 +++++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 15a3d87ed0..8d6a09b696 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -20,6 +20,7 @@ #define HW_OPENTITAN_H =20 #include "hw/riscv/riscv_hart.h" +#include "hw/intc/ibex_plic.h" =20 #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" #define RISCV_IBEX_SOC(obj) \ @@ -31,6 +32,8 @@ typedef struct LowRISCIbexSoCState { =20 /*< public >*/ RISCVHartArrayState cpus; + IbexPlicState plic; + MemoryRegion flash_mem; MemoryRegion rom; } LowRISCIbexSoCState; diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index c00f0720ab..3926321d8c 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -25,6 +25,7 @@ #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" #include "exec/address-spaces.h" +#include "sysemu/sysemu.h" =20 static const struct MemmapEntry { hwaddr base; @@ -92,6 +93,9 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj) object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); + + sysbus_init_child_obj(obj, "plic", &s->plic, + sizeof(s->plic), TYPE_IBEX_PLIC); } =20 static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **e= rrp) @@ -100,6 +104,9 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState = *dev_soc, Error **errp) MachineState *ms =3D MACHINE(qdev_get_machine()); LowRISCIbexSoCState *s =3D RISCV_IBEX_SOC(dev_soc); MemoryRegion *sys_mem =3D get_system_memory(); + DeviceState *dev; + SysBusDevice *busdev; + Error *err =3D NULL; =20 object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", &error_abort); @@ -120,6 +127,16 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState= *dev_soc, Error **errp) memory_region_add_subregion(sys_mem, memmap[IBEX_FLASH].base, &s->flash_mem); =20 + /* PLIC */ + dev =3D DEVICE(&s->plic); + object_property_set_bool(OBJECT(&s->plic), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, memmap[IBEX_PLIC].base); + create_unimplemented_device("riscv.lowrisc.ibex.uart", memmap[IBEX_UART].base, memmap[IBEX_UART].size); create_unimplemented_device("riscv.lowrisc.ibex.gpio", @@ -134,8 +151,6 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState = *dev_soc, Error **errp) memmap[IBEX_AES].base, memmap[IBEX_AES].size); create_unimplemented_device("riscv.lowrisc.ibex.hmac", memmap[IBEX_HMAC].base, memmap[IBEX_HMAC].size); - create_unimplemented_device("riscv.lowrisc.ibex.plic", - memmap[IBEX_PLIC].base, memmap[IBEX_PLIC].size); create_unimplemented_device("riscv.lowrisc.ibex.pinmux", memmap[IBEX_PINMUX].base, memmap[IBEX_PINMUX].size); create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", --=20 2.26.2 From nobody Thu Dec 18 00:16:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; 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IronPort-SDR: WH2+AMm9dvjasVUaUKNy0tQQPfhv17emnElEj9hOH2kVziHk7mzWyNgu2PjCpfZkTX3Iu8+vR6 w0pElZJ8/WRgr1GHBacqbebPMvG3iYbt4Kemj/OEOwoLPU5r/ysC4en+IiVC5+3/EDjJ4kqQ0o rJJNe7rx+1SV6RB8cdQTwsGPqGzdbK23p/bxVedYtGnCFUdEyGE77HuKAGQNjVSm66OWLMfckp EfiRNJiissGm5UEqwerK1OQbTVND/TKu8ZPdjod8bhT2WjQFgUXUyiedCpY1GOQag2NtGOKrMO bfo= X-IronPort-AV: E=Sophos;i="5.73,411,1583164800"; d="scan'208";a="240814210" IronPort-SDR: c3B6DngkAGBEpMCIFVuYQM0ru/rkW15zbj7Fhb7qNeH7U4AQYfHALQ0u+RRyZwq+k6zfM62eZR wZ6A4K53sZv7LuEyFzmgNHWsQomAAN1mY= IronPort-SDR: N1rVSjNerjkXaCFajXnxxbcyrrD2LIQTydDmxzRp+0HuC786Y5gIlZe5uN2Y19Zx3E24plU4Ar PemXjgrriYAw== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 8/9] riscv/opentitan: Connect the UART device Date: Tue, 19 May 2020 14:31:47 -0700 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/riscv/opentitan.h | 13 +++++++++++++ hw/riscv/opentitan.c | 24 ++++++++++++++++++++++-- 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 8d6a09b696..825a3610bc 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -21,6 +21,7 @@ =20 #include "hw/riscv/riscv_hart.h" #include "hw/intc/ibex_plic.h" +#include "hw/char/ibex_uart.h" =20 #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" #define RISCV_IBEX_SOC(obj) \ @@ -33,6 +34,7 @@ typedef struct LowRISCIbexSoCState { /*< public >*/ RISCVHartArrayState cpus; IbexPlicState plic; + IbexUartState uart; =20 MemoryRegion flash_mem; MemoryRegion rom; @@ -63,4 +65,15 @@ enum { IBEX_USBDEV, }; =20 +enum { + IBEX_UART_RX_PARITY_ERR_IRQ =3D 0x28, + IBEX_UART_RX_TIMEOUT_IRQ =3D 0x27, + IBEX_UART_RX_BREAK_ERR_IRQ =3D 0x26, + IBEX_UART_RX_FRAME_ERR_IRQ =3D 0x25, + IBEX_UART_RX_OVERFLOW_IRQ =3D 0x24, + IBEX_UART_TX_EMPTY_IRQ =3D 0x23, + IBEX_UART_RX_WATERMARK_IRQ =3D 0x22, + IBEX_UART_TX_WATERMARK_IRQ =3D 0x21 +}; + #endif diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 3926321d8c..a6c0b949ca 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -96,6 +96,9 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj) =20 sysbus_init_child_obj(obj, "plic", &s->plic, sizeof(s->plic), TYPE_IBEX_PLIC); + + sysbus_init_child_obj(obj, "uart", &s->uart, + sizeof(s->uart), TYPE_IBEX_UART); } =20 static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **e= rrp) @@ -137,8 +140,25 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState= *dev_soc, Error **errp) busdev =3D SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, memmap[IBEX_PLIC].base); =20 - create_unimplemented_device("riscv.lowrisc.ibex.uart", - memmap[IBEX_UART].base, memmap[IBEX_UART].size); + /* UART */ + dev =3D DEVICE(&(s->uart)); + qdev_prop_set_chr(dev, "chardev", serial_hd(0)); + object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, memmap[IBEX_UART].base); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic), + IBEX_UART_TX_WATERMARK_IRQ)); + sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic), + IBEX_UART_RX_WATERMARK_IRQ)); + sysbus_connect_irq(busdev, 2, qdev_get_gpio_in(DEVICE(&s->plic), + IBEX_UART_TX_EMPTY_IRQ)); + sysbus_connect_irq(busdev, 3, qdev_get_gpio_in(DEVICE(&s->plic), + IBEX_UART_RX_OVERFLOW_IRQ)); + create_unimplemented_device("riscv.lowrisc.ibex.gpio", memmap[IBEX_GPIO].base, memmap[IBEX_GPIO].size); create_unimplemented_device("riscv.lowrisc.ibex.spi", --=20 2.26.2 From nobody Thu Dec 18 00:16:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; 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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/pmp.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 0e6b640fbd..607a991260 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -233,12 +233,16 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ul= ong addr, return true; } =20 - /* - * if size is unknown (0), assume that all bytes - * from addr to the end of the page will be accessed. - */ if (size =3D=3D 0) { - pmp_size =3D -(addr | TARGET_PAGE_MASK); + if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + /* + * If size is unknown (0), assume that all bytes + * from addr to the end of the page will be accessed. + */ + pmp_size =3D -(addr | TARGET_PAGE_MASK); + } else { + pmp_size =3D sizeof(target_ulong); + } } else { pmp_size =3D size; } --=20 2.26.2