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charset="utf-8" Signed-off-by: Cameron Esfahani --- target/i386/cpu.h | 2 ++ target/i386/hvf/hvf.c | 1 + target/i386/hvf/vmx.h | 15 ++++++++------- target/i386/hvf/x86.c | 6 +++--- target/i386/hvf/x86.h | 34 ---------------------------------- target/i386/hvf/x86_mmu.c | 2 +- target/i386/hvf/x86_task.c | 3 ++- 7 files changed, 17 insertions(+), 46 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 60d797d594..1286ec6e7a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -225,6 +225,8 @@ typedef enum X86Seg { #define CR0_NE_MASK (1U << 5) #define CR0_WP_MASK (1U << 16) #define CR0_AM_MASK (1U << 18) +#define CR0_NW_MASK (1U << 29) +#define CR0_CD_MASK (1U << 30) #define CR0_PG_MASK (1U << 31) =20 #define CR4_VME_MASK (1U << 0) diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index d72543dc31..fef1ee7d70 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -455,6 +455,7 @@ void hvf_reset_vcpu(CPUState *cpu) { wvmcs(cpu->hvf_fd, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]); } =20 + macvm_set_cr0(cpu->hvf_fd, CR0_CD_MASK | CR0_NW_MASK | CR0_ET_MASK); macvm_set_cr0(cpu->hvf_fd, 0x60000010); =20 wvmcs(cpu->hvf_fd, VMCS_CR4_MASK, CR4_VMXE_MASK); diff --git a/target/i386/hvf/vmx.h b/target/i386/hvf/vmx.h index 03d2c79b9c..8ec2e6414e 100644 --- a/target/i386/hvf/vmx.h +++ b/target/i386/hvf/vmx.h @@ -121,9 +121,10 @@ static inline void macvm_set_cr0(hv_vcpuid_t vcpu, uin= t64_t cr0) uint64_t pdpte[4] =3D {0, 0, 0, 0}; uint64_t efer =3D rvmcs(vcpu, VMCS_GUEST_IA32_EFER); uint64_t old_cr0 =3D rvmcs(vcpu, VMCS_GUEST_CR0); - uint64_t mask =3D CR0_PG | CR0_CD | CR0_NW | CR0_NE | CR0_ET; + uint64_t mask =3D CR0_PG_MASK | CR0_CD_MASK | CR0_NW_MASK | + CR0_NE_MASK | CR0_ET_MASK; =20 - if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) && + if ((cr0 & CR0_PG_MASK) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE_MASK= ) && !(efer & MSR_EFER_LME)) { address_space_read(&address_space_memory, rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f, @@ -138,17 +139,17 @@ static inline void macvm_set_cr0(hv_vcpuid_t vcpu, ui= nt64_t cr0) wvmcs(vcpu, VMCS_CR0_SHADOW, cr0); =20 if (efer & MSR_EFER_LME) { - if (!(old_cr0 & CR0_PG) && (cr0 & CR0_PG)) { + if (!(old_cr0 & CR0_PG_MASK) && (cr0 & CR0_PG_MASK)) { enter_long_mode(vcpu, cr0, efer); } - if (/*(old_cr0 & CR0_PG) &&*/ !(cr0 & CR0_PG)) { + if (!(cr0 & CR0_PG_MASK)) { exit_long_mode(vcpu, cr0, efer); } } =20 /* Filter new CR0 after we are finished examining it above. */ - cr0 =3D (cr0 & ~(mask & ~CR0_PG)); - wvmcs(vcpu, VMCS_GUEST_CR0, cr0 | CR0_NE | CR0_ET); + cr0 =3D (cr0 & ~(mask & ~CR0_PG_MASK)); + wvmcs(vcpu, VMCS_GUEST_CR0, cr0 | CR0_NE_MASK | CR0_ET_MASK); =20 hv_vcpu_invalidate_tlb(vcpu); hv_vcpu_flush(vcpu); @@ -156,7 +157,7 @@ static inline void macvm_set_cr0(hv_vcpuid_t vcpu, uint= 64_t cr0) =20 static inline void macvm_set_cr4(hv_vcpuid_t vcpu, uint64_t cr4) { - uint64_t guest_cr4 =3D cr4 | CR4_VMXE; + uint64_t guest_cr4 =3D cr4 | CR4_VMXE_MASK; =20 wvmcs(vcpu, VMCS_GUEST_CR4, guest_cr4); wvmcs(vcpu, VMCS_CR4_SHADOW, cr4); diff --git a/target/i386/hvf/x86.c b/target/i386/hvf/x86.c index 3afcedc7fc..668c02de6e 100644 --- a/target/i386/hvf/x86.c +++ b/target/i386/hvf/x86.c @@ -119,7 +119,7 @@ bool x86_read_call_gate(struct CPUState *cpu, struct x8= 6_call_gate *idt_desc, bool x86_is_protected(struct CPUState *cpu) { uint64_t cr0 =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0); - return cr0 & CR0_PE; + return cr0 & CR0_PE_MASK; } =20 bool x86_is_real(struct CPUState *cpu) @@ -150,13 +150,13 @@ bool x86_is_long64_mode(struct CPUState *cpu) bool x86_is_paging_mode(struct CPUState *cpu) { uint64_t cr0 =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0); - return cr0 & CR0_PG; + return cr0 & CR0_PG_MASK; } =20 bool x86_is_pae_enabled(struct CPUState *cpu) { uint64_t cr4 =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_CR4); - return cr4 & CR4_PAE; + return cr4 & CR4_PAE_MASK; } =20 target_ulong linear_addr(struct CPUState *cpu, target_ulong addr, X86Seg s= eg) diff --git a/target/i386/hvf/x86.h b/target/i386/hvf/x86.h index c95d5b2116..bc0170b2a8 100644 --- a/target/i386/hvf/x86.h +++ b/target/i386/hvf/x86.h @@ -100,40 +100,6 @@ typedef struct x86_reg_flags { }; } __attribute__ ((__packed__)) x86_reg_flags; =20 -typedef enum x86_reg_cr0 { - CR0_PE =3D (1L << 0), - CR0_MP =3D (1L << 1), - CR0_EM =3D (1L << 2), - CR0_TS =3D (1L << 3), - CR0_ET =3D (1L << 4), - CR0_NE =3D (1L << 5), - CR0_WP =3D (1L << 16), - CR0_AM =3D (1L << 18), - CR0_NW =3D (1L << 29), - CR0_CD =3D (1L << 30), - CR0_PG =3D (1L << 31), -} x86_reg_cr0; - -typedef enum x86_reg_cr4 { - CR4_VME =3D (1L << 0), - CR4_PVI =3D (1L << 1), - CR4_TSD =3D (1L << 2), - CR4_DE =3D (1L << 3), - CR4_PSE =3D (1L << 4), - CR4_PAE =3D (1L << 5), - CR4_MSE =3D (1L << 6), - CR4_PGE =3D (1L << 7), - CR4_PCE =3D (1L << 8), - CR4_OSFXSR =3D (1L << 9), - CR4_OSXMMEXCPT =3D (1L << 10), - CR4_VMXE =3D (1L << 13), - CR4_SMXE =3D (1L << 14), - CR4_FSGSBASE =3D (1L << 16), - CR4_PCIDE =3D (1L << 17), - CR4_OSXSAVE =3D (1L << 18), - CR4_SMEP =3D (1L << 20), -} x86_reg_cr4; - /* 16 bit Task State Segment */ typedef struct x86_tss_segment16 { uint16_t link; diff --git a/target/i386/hvf/x86_mmu.c b/target/i386/hvf/x86_mmu.c index 65d4603dbf..8f38eccffc 100644 --- a/target/i386/hvf/x86_mmu.c +++ b/target/i386/hvf/x86_mmu.c @@ -130,7 +130,7 @@ static bool test_pt_entry(struct CPUState *cpu, struct = gpt_translation *pt, =20 uint32_t cr0 =3D rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0); /* check protection */ - if (cr0 & CR0_WP) { + if (cr0 & CR0_WP_MASK) { if (pt->write_access && !pte_write_access(pte)) { return false; } diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c index 1daac6cc2b..5e41d09b89 100644 --- a/target/i386/hvf/x86_task.c +++ b/target/i386/hvf/x86_task.c @@ -174,7 +174,8 @@ void vmx_handle_task_switch(CPUState *cpu, x68_segment_= selector tss_sel, int rea //ret =3D task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, = &next_tss_desc); VM_PANIC("task_switch_16"); =20 - macvm_set_cr0(cpu->hvf_fd, rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0) | CR0_TS= ); + macvm_set_cr0(cpu->hvf_fd, + rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0) | CR0_TS_MASK); x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg); vmx_write_segment_descriptor(cpu, &vmx_seg, R_TR); =20 --=20 2.24.0 From nobody Tue May 7 23:47:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Date: Mon, 30 Mar 2020 17:16:05 -0700 Message-id: <17777cc82122d29903bad7268b4c33e83b27d9a6.1585607927.git.dirty@apple.com> X-Mailer: git-send-email 2.24.0 In-reply-to: References: MIME-version: 1.0 Content-transfer-encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-03-30_07:2020-03-30, 2020-03-30 signatures=0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 17.151.62.67 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Cameron Esfahani From: Cameron Esfahani via X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Cameron Esfahani Reviewed-by: Roman Bolshakov --- target/i386/hvf/vmx.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/i386/hvf/vmx.h b/target/i386/hvf/vmx.h index 8ec2e6414e..1a1b150c97 100644 --- a/target/i386/hvf/vmx.h +++ b/target/i386/hvf/vmx.h @@ -121,6 +121,7 @@ static inline void macvm_set_cr0(hv_vcpuid_t vcpu, uint= 64_t cr0) uint64_t pdpte[4] =3D {0, 0, 0, 0}; uint64_t efer =3D rvmcs(vcpu, VMCS_GUEST_IA32_EFER); uint64_t old_cr0 =3D rvmcs(vcpu, VMCS_GUEST_CR0); + uint64_t changed_cr0 =3D old_cr0 ^ cr0; uint64_t mask =3D CR0_PG_MASK | CR0_CD_MASK | CR0_NW_MASK | CR0_NE_MASK | CR0_ET_MASK; =20 @@ -139,11 +140,12 @@ static inline void macvm_set_cr0(hv_vcpuid_t vcpu, ui= nt64_t cr0) wvmcs(vcpu, VMCS_CR0_SHADOW, cr0); =20 if (efer & MSR_EFER_LME) { - if (!(old_cr0 & CR0_PG_MASK) && (cr0 & CR0_PG_MASK)) { - enter_long_mode(vcpu, cr0, efer); - } - if (!(cr0 & CR0_PG_MASK)) { - exit_long_mode(vcpu, cr0, efer); + if (changed_cr0 & CR0_PG_MASK) { + if (cr0 & CR0_PG_MASK) { + enter_long_mode(vcpu, cr0, efer); + } else { + exit_long_mode(vcpu, cr0, efer); + } } } =20 --=20 2.24.0 From nobody Tue May 7 23:47:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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charset="utf-8" macOS lazily enables AVX512. Explicitly enable it if the processor supports it. cpu_x86_cpuid() tries to handle OSXSAVE but refers to env->cr[4] for the guest copy of CR4. HVF doesn't support caching CPUID values like KVM, so we need to track it ourselves. Signed-off-by: Cameron Esfahani --- target/i386/cpu.h | 1 + target/i386/hvf/hvf.c | 68 ++++++++++++++++++++++++++++++++++++++-- target/i386/hvf/vmx.h | 9 +++++- target/i386/hvf/x86hvf.c | 2 +- 4 files changed, 76 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 1286ec6e7a..f3864d0fac 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1591,6 +1591,7 @@ typedef struct CPUX86State { struct kvm_nested_state *nested_state; #endif #if defined(CONFIG_HVF) + bool osxsave_enabled; HVFX86EmulatorState *hvf_emul; #endif =20 diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index fef1ee7d70..68a85c3b9b 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -65,6 +65,7 @@ =20 #include #include +#include =20 #include "exec/address-spaces.h" #include "hw/i386/apic_internal.h" @@ -458,7 +459,7 @@ void hvf_reset_vcpu(CPUState *cpu) { macvm_set_cr0(cpu->hvf_fd, CR0_CD_MASK | CR0_NW_MASK | CR0_ET_MASK); macvm_set_cr0(cpu->hvf_fd, 0x60000010); =20 - wvmcs(cpu->hvf_fd, VMCS_CR4_MASK, CR4_VMXE_MASK); + wvmcs(cpu->hvf_fd, VMCS_CR4_MASK, CR4_VMXE_MASK | CR4_OSXSAVE_MASK); wvmcs(cpu->hvf_fd, VMCS_CR4_SHADOW, 0x0); wvmcs(cpu->hvf_fd, VMCS_GUEST_CR4, CR4_VMXE_MASK); =20 @@ -541,6 +542,55 @@ static void dummy_signal(int sig) { } =20 +static bool enable_avx512_thread_state(void) +{ + x86_avx512_state_t state; + uint32_t ebx; + kern_return_t ret; + unsigned int count; + + /* + * macOS lazily enables AVX512 support. Enable it explicitly if the + * processor supports it. + */ + + host_cpuid(7, 0, NULL, &ebx, NULL, NULL); + if ((ebx & CPUID_7_0_EBX_AVX512F) =3D=3D 0) { + return false; + } + + memset(&state, 0, sizeof(x86_avx512_state_t)); + + /* Get AVX state */ + count =3D x86_AVX_STATE_COUNT; + ret =3D thread_get_state(mach_thread_self(), + x86_AVX_STATE, + (thread_state_t) &state, + &count); + if (ret !=3D KERN_SUCCESS) { + return false; + } + if (count !=3D x86_AVX_STATE_COUNT) { + return false; + } + if (state.ash.flavor !=3D x86_AVX_STATE64) { + return false; + } + state.ash.flavor =3D x86_AVX512_STATE64; + state.ash.count =3D x86_AVX512_STATE64_COUNT; + + /* Now set as AVX512 */ + ret =3D thread_set_state(mach_thread_self(), + state.ash.flavor, + (thread_state_t) &state.ufs.as64, + state.ash.count); + if (ret !=3D KERN_SUCCESS) { + return false; + } + + return true; +} + int hvf_init_vcpu(CPUState *cpu) { =20 @@ -826,6 +876,18 @@ int hvf_vcpu_exec(CPUState *cpu) =20 cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx); =20 + if (rax =3D=3D 1) { + /* + * cpu_x86_cpuid tries to handle OSXSAVE but refers to + * env->cr[4] for the guest copy of CR4. This isn't + * updated regularly so we track it ourselves in + * env->osxsave_enabled. + */ + if ((rcx & CPUID_EXT_XSAVE) && env->osxsave_enabled) { + rcx |=3D CPUID_EXT_OSXSAVE; + } + } + wreg(cpu->hvf_fd, HV_X86_RAX, rax); wreg(cpu->hvf_fd, HV_X86_RBX, rbx); wreg(cpu->hvf_fd, HV_X86_RCX, rcx); @@ -889,7 +951,7 @@ int hvf_vcpu_exec(CPUState *cpu) break; } case 4: { - macvm_set_cr4(cpu->hvf_fd, RRX(env, reg)); + macvm_set_cr4(env, cpu->hvf_fd, RRX(env, reg)); break; } case 8: { @@ -966,6 +1028,8 @@ static int hvf_accel_init(MachineState *ms) hv_return_t ret; HVFState *s; =20 + enable_avx512_thread_state(); + ret =3D hv_vm_create(HV_VM_DEFAULT); assert_hvf_ok(ret); =20 diff --git a/target/i386/hvf/vmx.h b/target/i386/hvf/vmx.h index 1a1b150c97..dccd5ceb0f 100644 --- a/target/i386/hvf/vmx.h +++ b/target/i386/hvf/vmx.h @@ -157,13 +157,20 @@ static inline void macvm_set_cr0(hv_vcpuid_t vcpu, ui= nt64_t cr0) hv_vcpu_flush(vcpu); } =20 -static inline void macvm_set_cr4(hv_vcpuid_t vcpu, uint64_t cr4) +static inline void macvm_set_cr4(CPUX86State *env, hv_vcpuid_t vcpu, + uint64_t cr4) { uint64_t guest_cr4 =3D cr4 | CR4_VMXE_MASK; =20 wvmcs(vcpu, VMCS_GUEST_CR4, guest_cr4); wvmcs(vcpu, VMCS_CR4_SHADOW, cr4); =20 + /* + * Track whether OSXSAVE is enabled so we can properly return it + * for CPUID 1. + */ + env->osxsave_enabled =3D ((cr4 & CR4_OSXSAVE_MASK) !=3D 0); + hv_vcpu_invalidate_tlb(vcpu); hv_vcpu_flush(vcpu); } diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index edefe5319a..bd25bf19c4 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -100,7 +100,7 @@ void hvf_put_segments(CPUState *cpu_state) vmx_update_tpr(cpu_state); wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IA32_EFER, env->efer); =20 - macvm_set_cr4(cpu_state->hvf_fd, env->cr[4]); + macvm_set_cr4(env, cpu_state->hvf_fd, env->cr[4]); macvm_set_cr0(cpu_state->hvf_fd, env->cr[0]); =20 hvf_set_segment(cpu_state, &seg, &env->segs[R_CS], false); --=20 2.24.0