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charset="utf-8" Split the file into clear machine and SoC sections. Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 107 ++++++++++++++++++++++---------------------- 1 file changed, 54 insertions(+), 53 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 156a003642..9a0145b5b4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -399,6 +399,60 @@ static void riscv_sifive_u_init(MachineState *machine) &address_space_memory); } =20 +static bool sifive_u_get_start_in_flash(Object *obj, Error **errp) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + return s->start_in_flash; +} + +static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **e= rrp) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + s->start_in_flash =3D value; +} + +static void riscv_sifive_u_machine_instance_init(Object *obj) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + s->start_in_flash =3D false; + object_property_add_bool(obj, "start-in-flash", sifive_u_get_start_in_= flash, + sifive_u_set_start_in_flash, NULL); + object_property_set_description(obj, "start-in-flash", + "Set on to tell QEMU's ROM to jump to = " \ + "flash. Otherwise QEMU will jump to DR= AM", + NULL); +} + + +static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; + mc->init =3D riscv_sifive_u_init; + mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; + mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; + mc->default_cpus =3D mc->min_cpus; +} + +static const TypeInfo riscv_sifive_u_machine_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("sifive_u"), + .parent =3D TYPE_MACHINE, + .class_init =3D riscv_sifive_u_machine_class_init, + .instance_init =3D riscv_sifive_u_machine_instance_init, + .instance_size =3D sizeof(SiFiveUState), +}; + +static void riscv_sifive_u_machine_init_register_types(void) +{ + type_register_static(&riscv_sifive_u_machine_typeinfo); +} + +type_init(riscv_sifive_u_machine_init_register_types) + static void riscv_sifive_u_soc_init(Object *obj) { MachineState *ms =3D MACHINE(qdev_get_machine()); @@ -439,33 +493,6 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_CADENCE_GEM); } =20 -static bool sifive_u_get_start_in_flash(Object *obj, Error **errp) -{ - SiFiveUState *s =3D RISCV_U_MACHINE(obj); - - return s->start_in_flash; -} - -static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **e= rrp) -{ - SiFiveUState *s =3D RISCV_U_MACHINE(obj); - - s->start_in_flash =3D value; -} - -static void riscv_sifive_u_machine_instance_init(Object *obj) -{ - SiFiveUState *s =3D RISCV_U_MACHINE(obj); - - s->start_in_flash =3D false; - object_property_add_bool(obj, "start-in-flash", sifive_u_get_start_in_= flash, - sifive_u_set_start_in_flash, NULL); - object_property_set_description(obj, "start-in-flash", - "Set on to tell QEMU's ROM to jump to = " \ - "flash. Otherwise QEMU will jump to DR= AM", - NULL); -} - static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); @@ -603,29 +630,3 @@ static void riscv_sifive_u_soc_register_types(void) } =20 type_init(riscv_sifive_u_soc_register_types) - -static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - - mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; - mc->init =3D riscv_sifive_u_init; - mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; - mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; - mc->default_cpus =3D mc->min_cpus; -} - -static const TypeInfo riscv_sifive_u_machine_typeinfo =3D { - .name =3D MACHINE_TYPE_NAME("sifive_u"), - .parent =3D TYPE_MACHINE, - .class_init =3D riscv_sifive_u_machine_class_init, - .instance_init =3D riscv_sifive_u_machine_instance_init, - .instance_size =3D sizeof(SiFiveUState), -}; - -static void riscv_sifive_u_machine_init_register_types(void) -{ - type_register_static(&riscv_sifive_u_machine_typeinfo); -} - -type_init(riscv_sifive_u_machine_init_register_types) --=20 2.25.1 From nobody Thu Nov 13 21:52:17 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1583363510; cv=none; d=zohomail.com; s=zohoarc; b=lemNQMKeMUBg6Tz/ZfmytD6qGfLgUkO4zCkw+K+jBnwMHEQenVXf+9evdGw8jjECpBfbQED4TPfKC/KLoa5jc4RXVMmLNyERa+U9KiXUmir5TWanEd3lZVcziHHv1unosO547ICoIi0kkfPJ/KHFtkouq4wcBdVqFcYOjeWtKlI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583363510; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" At present the board serial number is hard-coded to 1, and passed to OTP model during initialization. Firmware (FSBL, U-Boot) uses the serial number to generate a unique MAC address for the on-chip ethernet controller. When multiple QEMU 'sifive_u' instances are created and connected to the same subnet, they all have the same MAC address hence it creates a unusable network. A new "serial" property is introduced to the sifive_u SoC to specify the board serial number. When not given, the default serial number 1 is used. Suggested-by: Bin Meng Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/riscv/sifive_u.c | 8 +++++++- include/hw/riscv/sifive_u.h | 2 ++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9a0145b5b4..aed8249d0b 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -488,7 +488,6 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_SIFIVE_U_PRCI); sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp), TYPE_SIFIVE_U_OTP); - qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL); sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), TYPE_CADENCE_GEM); } @@ -581,6 +580,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev= , Error **errp) object_property_set_bool(OBJECT(&s->prci), true, "realized", &err); sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].bas= e); =20 + qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); object_property_set_bool(OBJECT(&s->otp), true, "realized", &err); sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base); =20 @@ -607,10 +607,16 @@ static void riscv_sifive_u_soc_realize(DeviceState *d= ev, Error **errp) memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); } =20 +static Property riscv_sifive_u_soc_props[] =3D { + DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), + DEFINE_PROP_END_OF_LIST() +}; + static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); =20 + device_class_set_props(dc, riscv_sifive_u_soc_props); dc->realize =3D riscv_sifive_u_soc_realize; /* Reason: Uses serial_hds in realize function, thus can't be used twi= ce */ dc->user_creatable =3D false; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 82667b5746..a2baa1de5f 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -42,6 +42,8 @@ typedef struct SiFiveUSoCState { SiFiveUPRCIState prci; SiFiveUOTPState otp; CadenceGEMState gem; + + uint32_t serial; } SiFiveUSoCState; =20 #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") --=20 2.25.1 From nobody Thu Nov 13 21:52:17 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1583363549; cv=none; d=zohomail.com; s=zohoarc; b=A5hWfRNqYNakk1017/4j6/kv8h9DkDkUmjGUDVmubWsV9KkeHrXT26ng/17jRNcyfwDQycTahP2pLE5kUFzLWHcUt/qbs/mhT7Ji/W0bP/viqZep3/Wt8g5fXLGl8VegAqw48mLy0Oh7Km4/BhnoFLVoPFlFg6uVYY/UlSZcA68= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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d="scan'208";a="131477247" IronPort-SDR: axKrKTCEOTEJ08L/PWoWqH/QHKexsBnmjAW5yvJ6qOc+mQPsNEpqGZ94iNLL/8vlwh8W5rZBBv MIDBZFCONH8rA3xnKU9wok/XMiHEuoarqhGOc2szisbfOgKtjCO6Gz8owSyoD4onojZ6sRDs8c 6Xvrrs1M9nmZJDgMfudVMYb39rZsis0JQR4rDyYWf87QjawRjtwlskL4Jq/Ui7jJdJrdBKCQTT JexwSvWWi2tYqCIgFstf8YNZSxODt25Ge+cfhsUL6cnkYiarVNaxDbzaN4B87YF42L6iY24njm +xm7nL5jwFbDKLp8Kf9ihbgN IronPort-SDR: pCYkyyjdUfZ4L5T2j+POINtVe9Mnim3T5sxviv2INBJNgDwd+x2LITu0IXmY92qTi3oOJPqBTO dl/M37Gi9/kMu7d73LWVHR9wo5HTImO63ASgNSAISekojbQKnvkCGkfbuhwo0q5RbUhsex+w5I qvNDy6or8BP90gsNF/4MZQgWjcixzt5g1jZiWcWKboYZkNeOso1ICWaoenBAC6GNyIiyGhKbTZ /d1Nue3BQNhReX3ntWRp5yJq0GRBF/zOkDp0kOIN/DKjm9MU1NEbzt722F1/O15CjU4prPGlio Sp0= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 3/3] riscv/sifive_u: Add a serial property to the sifive_u machine Date: Wed, 4 Mar 2020 15:02:33 -0800 Message-Id: <237a53529eae97b79e63938cd45672f1420ab954.1583362888.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Bin Meng At present the board serial number is hard-coded to 1, and passed to OTP model during initialization. Firmware (FSBL, U-Boot) uses the serial number to generate a unique MAC address for the on-chip ethernet controller. When multiple QEMU 'sifive_u' instances are created and connected to the same subnet, they all have the same MAC address hence it creates a unusable network. A new "serial" property is introduced to specify the board serial number. When not given, the default serial number 1 is used. Signed-off-by: Bin Meng Reviewed-by: Palmer Dabbelt Reviewed-by: Alistair Francis Message-Id: <1573916930-19068-1-git-send-email-bmeng.cn@gmail.com> [ Changed by AF: - Use the SoC's serial property to pass the info to the SoC - Fixup commit title - Rebase on file restructuring ] Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 20 ++++++++++++++++++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 21 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index aed8249d0b..4299a5addc 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -34,6 +34,7 @@ #include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "hw/boards.h" #include "hw/loader.h" #include "hw/sysbus.h" @@ -322,6 +323,8 @@ static void riscv_sifive_u_init(MachineState *machine) object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), TYPE_RISCV_U_SOC, &error_abort, NULL); + object_property_set_uint(OBJECT(&s->soc), s->serial, "serial", + &error_abort); object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort); =20 @@ -413,6 +416,18 @@ static void sifive_u_set_start_in_flash(Object *obj, b= ool value, Error **errp) s->start_in_flash =3D value; } =20 +static void sifive_u_get_serial(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + visit_type_uint32(v, name, (uint32_t *)opaque, errp); +} + +static void sifive_u_set_serial(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + visit_type_uint32(v, name, (uint32_t *)opaque, errp); +} + static void riscv_sifive_u_machine_instance_init(Object *obj) { SiFiveUState *s =3D RISCV_U_MACHINE(obj); @@ -424,6 +439,11 @@ static void riscv_sifive_u_machine_instance_init(Objec= t *obj) "Set on to tell QEMU's ROM to jump to = " \ "flash. Otherwise QEMU will jump to DR= AM", NULL); + + s->serial =3D OTP_SERIAL; + object_property_add(obj, "serial", "uint32", sifive_u_get_serial, + sifive_u_set_serial, NULL, &s->serial, NULL); + object_property_set_description(obj, "serial", "Board serial number", = NULL); } =20 =20 diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index a2baa1de5f..16c297ec5f 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -61,6 +61,7 @@ typedef struct SiFiveUState { int fdt_size; =20 bool start_in_flash; + uint32_t serial; } SiFiveUState; =20 enum { --=20 2.25.1