From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580519372143279.09162270202523; Fri, 31 Jan 2020 17:09:32 -0800 (PST) Received: from localhost ([::1]:33970 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhHu-0002Fr-AN for importer@patchew.org; Fri, 31 Jan 2020 20:09:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56443) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhGk-0000X5-UP for qemu-devel@nongnu.org; Fri, 31 Jan 2020 20:08:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixhGj-00066T-M4 for qemu-devel@nongnu.org; Fri, 31 Jan 2020 20:08:18 -0500 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:17114) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ixhGj-00065s-E6; Fri, 31 Jan 2020 20:08:17 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 01 Feb 2020 09:08:15 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2020 17:01:23 -0800 Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.158.235]) by uls-op-cesaip02.wdc.com with ESMTP; 31 Jan 2020 17:08:15 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1580519297; x=1612055297; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bMmHPvXTwmFm3v6KSxU5UHxjO/nB6/a5heNzTy1ycD8=; b=HZWLYbPSB8VXi5H1JHgFEX94W0EQNC2g+2CDwo1QSdViROUZedec+s41 USCtFRsZNnVDVJRsq28ZMHJ7y4vs+EjAtN+n4wvrhBX4Fk5hS42ClNeiT z8KShcsyaMYNhQgQmBCoUCS4TRzMVqPb8KEYMwafIY2VJ3lkLdfROZseB BjPz53lhSdn//OX1okxU9JaD650yr7aRX16ffKVthWWYcq/qLWyfrZDl+ 4osKjZHko+yec+E2lvkDaZ3qbssrp/VKguIKYrpkwwxiSWiEh7/JX6at8 q6QmZCwNkJ+pxJwkC9ei0rTqIxezaSWq4wm3u8gcGdZQ1d5L9puJi2dDG w==; IronPort-SDR: zmOYbKfOkGSq5wB0jsA8CyuTSAusU0GY8yQkWQh8JGsPMaafoumctnILxaBY5BSlJYWoAiMZYq +gfSC6MyptR+x8s4Axa7Ru8d/AHKh3DGQ/1In4Uce08DdKV944vsnrMWCtvgE5R+tsQXL+BhS3 L5HC5OZzcz+fM2Lif1PUYGrPXxgvOl8X93bx5Y54czkqWpqmYQ35gZaX9hTA8rdu2G6fqKOsko e/mMeWSAiBKMb3FcgkX2ztQZOnBhcy06YTCni7/qPeQoFV5DnmonVpVgW74tUmRXCZViPYxmcS KyM= X-IronPort-AV: E=Sophos;i="5.70,388,1574092800"; d="scan'208";a="128872396" IronPort-SDR: LJxGCQK6coOrKVoF8KwUIxXKtqRBxO3CeGQDEx/0KE01tAGeAuHx59ddtST2U1KO5iF1rg06c+ SqgkstALUV653wrGOvE05JBzrbZJlzmKDDuZPdvQ1392xeFcfU/2QGSBeerW4fLdkw5q7n6UkN yTpPSGbURJUNU6lPSPw47RKSMcElkzQjBHwvqGnwR1BazoaFbei21uiMC26U5cj2Y46DeFsxIR 8ifD0lwgWopvk3mSh0BJbyTfDDVOP4pTE1/ZA63Ohn5raT2WXgETJjfKoOPenhDhtX4rFH9a+O mH8Bbb6MkZG3w09yPXce6pJK IronPort-SDR: xeevb+TbJDddkr4ig+lDYwU8e0OdvHxppF1aXrKM5nxXyRB4ko+yn3/pLHvtD8gxJ3D4HzqZne aNO9YMe8lTnpOso+qru8ennybY/0Mhzoz1dhwumaIHvUAZuqcRWHh2Uzw7ZxeojjvuhLe/MqU9 Oufon/xYqDE4wzl9tXVLXWQd1jfURZEKGSmDdxsi+RHq8CXfNHwPo185+OOl1yVsFWm3HVdb5S oEjMjM29CSstrGExQ+dr5EM4uDfdDzw/0iS5a3KqWwfaJLsUOxLZlyrmlxiFMwcg3YaVZL805S 4pI= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 01/35] target/riscv: Convert MIP CSR to target_ulong Date: Fri, 31 Jan 2020 17:01:38 -0800 Message-Id: X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access. Now that we don't use atomics for MIP we can change this back to a xlen CSR. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8c86ebc109..efbd676edb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -224,7 +224,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); - qemu_fprintf(f, " %s 0x%x\n", "mip ", env->mip); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de0a8d893a..95de9e58a2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -121,7 +121,7 @@ struct CPURISCVState { target_ulong mhartid; target_ulong mstatus; =20 - uint32_t mip; + target_ulong mip; uint32_t miclaim; =20 target_ulong mie; --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580519492139273.31469321499685; Fri, 31 Jan 2020 17:11:32 -0800 (PST) Received: from localhost ([::1]:34222 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhJq-0005xg-Vj for importer@patchew.org; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Chih-Min Chao Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 95de9e58a2..010125efd6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -67,6 +67,7 @@ #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') +#define RVH RV('H') =20 /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="128872401" IronPort-SDR: Ok01ic0NyNw21MFep9Y+vY0s6AkpXZwU56MkK5rbQoPLwxrlLiwpBpkIhr4wYjM8MDC6viioDZ 6JmECJ3/n2D2M13WRhWQlwLcaYUmDxvaoebtQ/csFxfq/iA+Jm0bxomlm0CDYCHr+bVIN5RwIn elyC4GBvbLcKFUOlUtrb2wDoFMF73oBaLu4gvBPuuzLmoddvvV2fz9Ocu81SZTlKohwvR9+tXX M622CyVAMxI0gaoZw7UgYbVfw30i6az9iFzCCOcQ9BNLRXcrT3Fhn5HimMo0FNthR+Tw7ZuUCx +qPcMIyGjPmEHNbuj2mRNbIX IronPort-SDR: eoiuZaOSYq8zC4xZfiNxdcFi4Ym43oq4rJSBwdE71IMUKv7OxUwoEis5lfuMEIcq5Pz0nNEomb V+WAvjHoSLYSF9HVG8O4npBd/l+tJSe3kabEYNOhVcyDIeRHZYTHCXyl1z2zEL+B+1+O/QsbWs Ii3nMUqycPLs8VAdpsGGYPduDYr4Mk31h2Znj2u/aamTYOEL/fClFv7Z/orMXTDqB0JG9vAacN g6NAKSQxHTMrP593NL99p/07h/vZybEHVP0Y8mrK7WyyyXcXEcKhHOYujvzLWsk/JnlHyBIhhV MxY= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 03/35] target/riscv: Add the Hypervisor CSRs to CPUState Date: Fri, 31 Jan 2020 17:01:43 -0800 Message-Id: <5e15673b88378ed4a7d6c2d53932f1486cb61dfd.1580518859.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add the Hypervisor CSRs to CPUState and at the same time (to avoid bisect issues) update the CSR macros for the v0.5 Hyp spec. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h | 21 +++++++++++++++++++++ target/riscv/cpu_bits.h | 34 +++++++++++++++++++++------------- target/riscv/gdbstub.c | 11 ++++++----- 3 files changed, 48 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 010125efd6..c7f7ae5c38 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -143,6 +143,27 @@ struct CPURISCVState { target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ =20 + /* Hypervisor CSRs */ + target_ulong hstatus; + target_ulong hedeleg; + target_ulong hideleg; + target_ulong hcounteren; + target_ulong htval; + target_ulong htinst; + target_ulong hgatp; + + /* Virtual CSRs */ + target_ulong vsstatus; + target_ulong vstvec; + target_ulong vsscratch; + target_ulong vsepc; + target_ulong vscause; + target_ulong vstval; + target_ulong vsatp; + + target_ulong mtval2; + target_ulong mtinst; + target_ulong scounteren; target_ulong mcounteren; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index e99834856c..25c0fb258d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -177,8 +177,14 @@ #define CSR_HSTATUS 0x600 #define CSR_HEDELEG 0x602 #define CSR_HIDELEG 0x603 -#define CSR_HCOUNTERNEN 0x606 +#define CSR_HIE 0x604 +#define CSR_HCOUNTEREN 0x606 +#define CSR_HTVAL 0x643 +#define CSR_HIP 0x644 +#define CSR_HTINST 0x64A #define CSR_HGATP 0x680 +#define CSR_HTIMEDELTA 0x605 +#define CSR_HTIMEDELTAH 0x615 =20 #if defined(TARGET_RISCV32) #define HGATP_MODE SATP32_MODE @@ -191,6 +197,20 @@ #define HGATP_PPN SATP64_PPN #endif =20 +/* Virtual CSRs */ +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSATP 0x280 + +#define CSR_MTINST 0x34a +#define CSR_MTVAL2 0x34b + /* Physical Memory Protection */ #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 @@ -313,17 +333,6 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f =20 -/* Legacy Hypervisor Trap Setup (priv v1.9.1) */ -#define CSR_HIE 0x204 -#define CSR_HTVEC 0x205 - -/* Legacy Hypervisor Trap Handling (priv v1.9.1) */ -#define CSR_HSCRATCH 0x240 -#define CSR_HEPC 0x241 -#define CSR_HCAUSE 0x242 -#define CSR_HBADADDR 0x243 -#define CSR_HIP 0x244 - /* Legacy Machine Protection and Translation (priv v1.9.1) */ #define CSR_MBASE 0x380 #define CSR_MBOUND 0x381 @@ -400,7 +409,6 @@ =20 /* hstatus CSR bits */ #define HSTATUS_SPRV 0x00000001 -#define HSTATUS_STL 0x00000040 #define HSTATUS_SPV 0x00000080 #define HSTATUS_SP2P 0x00000100 #define HSTATUS_SP2V 0x00000200 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 1a7947e019..6d606f0d90 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -130,6 +130,8 @@ static int csr_register_map[] =3D { CSR_MCAUSE, CSR_MTVAL, CSR_MIP, + CSR_MTINST, + CSR_MTVAL2, CSR_PMPCFG0, CSR_PMPCFG1, CSR_PMPCFG2, @@ -252,12 +254,11 @@ static int csr_register_map[] =3D { CSR_HEDELEG, CSR_HIDELEG, CSR_HIE, - CSR_HTVEC, - CSR_HSCRATCH, - CSR_HEPC, - CSR_HCAUSE, - CSR_HBADADDR, + CSR_HCOUNTEREN, + CSR_HTVAL, CSR_HIP, + CSR_HTINST, + CSR_HGATP, CSR_MBASE, CSR_MBOUND, CSR_MIBASE, --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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b=YWlssfJwW2G63Z/ju549sd9KFWgpXV21PjV/Lf8XkHr2H6wrOdjQKQBr KgZsxk1sgz5JhFRs92K9mKBVl634UQqvREd0CSQIAosueYxPiULYZYqtL fB5EMHrK2F16iU7V7vQrXbPLdqXSEcqcW07P7COzJECUoIXtJaQjW1nec bcFsuP//89xhU//s54D1S/qOIAkJ1FlsAYg4Tx4BGYr/uxdRU0L9z7tFp NYoaSN4QTmDf0kzJc8Ly0hBhG4oOKUBHFoDEg260GPXdC+UGiz2Z6v2dY /PuDOMqhpSxAJ901scx6VnPfCadWw7TqCsnKj5dLhWyKBxa+4gtt/icoa Q==; IronPort-SDR: uiOgO3H61nxndAssytoXePYCM/S+dYFJPNbJd0vbtuRvnsZr6J+QuGY4y+kSN6qj8V7RO8Fajs ChmAMI34ZQFUOElmTz32dwlzPBKvmPm+iRQ5FHISld2xsgEOv03Myn4O/6jMtbMGmPfa6t/kEY v19MSdiVHIUsjm0Y8FZ5Rq0WRy47AhXGASMEjS+Y2zk88ae9PMPSTEGVcsxtb+L6oIYXii1UDl gVGFJx7NWHPwOBbL7Ti5Clh/EfZ1BELtTD8cj4V/O8Fc5XAMT+lJQtHk3WQ5vNEUmiEoknYSTE gAY= X-IronPort-AV: E=Sophos;i="5.70,388,1574092800"; d="scan'208";a="128872402" IronPort-SDR: UpDMHeyob1j8UC4sv74HVVcjPf/XywpLuCGdctuRy3x3YVslTLwjXw4Shv0W+Xy4TLT2Md5okO yxHlNMTV2xqza2jOZjZ6c/qd+5aZHGSFKqqV1l77h6s1CflwqnYSMXZHDnSMzbUkc1M7Zzy9RC 3GlSQTsnY3szt3VxqtiIizTiNekrZYa0MaMLfBTfrX4gGAvlP90OpAixuHpIkUXWO3s0NFCqM+ z5xLuXWOod/XFSfewuIxvusyyikFOFZfBDzzYccXNQi3pVFwRxjC/unp8um0103J7cu19FrFxF uu0IP+kUgrslXULilfwLYTFw IronPort-SDR: dscKByiUP6t5mdmOW+gsHz2J9yzGw1XM2/RbnF/E22YFmUCJ3o8fwADVgpuzOpf2EQ1RK4jQGv EOEw4Iv5Xv2r/Egr8IGqSVOw7ZzgcH0t35Dv2waixtc/4moYEeAnc8puOBHj67WTrUavtHILC2 PFRvHllH2yCXD0DbM/KtRPYmopp5SRlG+NXKQJi8nlz1Yig8RJHgMUtTexGE3uz7MfbBMWcoFp kpNcA2+1qHi79o2N2OFtltJF3duAWlWmafUZCPc5F+VvOQtAl9Q0/jSoI4wNXnuXEA/dq/Lbqw 8fU= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 04/35] target/riscv: Add support for the new execption numbers Date: Fri, 31 Jan 2020 17:01:46 -0800 Message-Id: X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The v0.5 Hypervisor spec add new execption numbers, let's add support for those. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 8 ++++++++ target/riscv/cpu_bits.h | 35 +++++++++++++++++++---------------- target/riscv/cpu_helper.c | 7 +++++-- target/riscv/csr.c | 7 +++++-- 4 files changed, 37 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index efbd676edb..2f62f5ea19 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -67,6 +67,14 @@ const char * const riscv_excp_names[] =3D { "load_page_fault", "reserved", "store_page_fault" + "reserved", + "reserved", + "reserved", + "reserved", + "guest_exec_page_fault", + "guest_load_page_fault", + "reserved", + "guest_store_page_fault" }; =20 const char * const riscv_intr_names[] =3D { diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 25c0fb258d..9ce73c36de 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -488,22 +488,25 @@ #define DEFAULT_RSTVEC 0x1000 =20 /* Exception causes */ -#define EXCP_NONE -1 /* sentinel value */ -#define RISCV_EXCP_INST_ADDR_MIS 0x0 -#define RISCV_EXCP_INST_ACCESS_FAULT 0x1 -#define RISCV_EXCP_ILLEGAL_INST 0x2 -#define RISCV_EXCP_BREAKPOINT 0x3 -#define RISCV_EXCP_LOAD_ADDR_MIS 0x4 -#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5 -#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6 -#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7 -#define RISCV_EXCP_U_ECALL 0x8 -#define RISCV_EXCP_S_ECALL 0x9 -#define RISCV_EXCP_H_ECALL 0xa -#define RISCV_EXCP_M_ECALL 0xb -#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */ -#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */ -#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */ +#define EXCP_NONE -1 /* sentinel value */ +#define RISCV_EXCP_INST_ADDR_MIS 0x0 +#define RISCV_EXCP_INST_ACCESS_FAULT 0x1 +#define RISCV_EXCP_ILLEGAL_INST 0x2 +#define RISCV_EXCP_BREAKPOINT 0x3 +#define RISCV_EXCP_LOAD_ADDR_MIS 0x4 +#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5 +#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6 +#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7 +#define RISCV_EXCP_U_ECALL 0x8 +#define RISCV_EXCP_S_ECALL 0x9 +#define RISCV_EXCP_VS_ECALL 0xa +#define RISCV_EXCP_M_ECALL 0xb +#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0= */ +#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0= */ +#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0= */ +#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14 +#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15 +#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17 =20 #define RISCV_EXCP_INT_FLAG 0x80000000 #define RISCV_EXCP_INT_MASK 0x7fffffff diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b8e85d5b20..8f746fb06f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -526,13 +526,16 @@ void riscv_cpu_do_interrupt(CPUState *cs) static const int ecall_cause_map[] =3D { [PRV_U] =3D RISCV_EXCP_U_ECALL, [PRV_S] =3D RISCV_EXCP_S_ECALL, - [PRV_H] =3D RISCV_EXCP_H_ECALL, + [PRV_H] =3D RISCV_EXCP_VS_ECALL, [PRV_M] =3D RISCV_EXCP_M_ECALL }; =20 if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { + case RISCV_EXCP_INST_GUEST_PAGE_FAULT: + case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: + case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: case RISCV_EXCP_INST_ADDR_MIS: case RISCV_EXCP_INST_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: @@ -554,7 +557,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) } } =20 - trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 16= ? + trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23= ? (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"= ); =20 if (env->priv <=3D PRV_S && diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0e34c292c5..ca27359c7e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -242,11 +242,14 @@ static const target_ulong delegable_excps =3D (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | (1ULL << (RISCV_EXCP_U_ECALL)) | (1ULL << (RISCV_EXCP_S_ECALL)) | - (1ULL << (RISCV_EXCP_H_ECALL)) | + (1ULL << (RISCV_EXCP_VS_ECALL)) | (1ULL << (RISCV_EXCP_M_ECALL)) | (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | - (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)); + (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | + (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | + (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | + (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); static const target_ulong sstatus_v1_9_mask =3D SSTATUS_SIE | SSTATUS_SPIE= | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_SD; --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580519633812746.2831966484305; Fri, 31 Jan 2020 17:13:53 -0800 (PST) Received: from localhost ([::1]:34280 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhM8-0000zS-Bo for importer@patchew.org; Fri, 31 Jan 2020 20:13:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56565) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhGv-0000ko-Iw for qemu-devel@nongnu.org; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 6 +++--- target/riscv/cpu_bits.h | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2f62f5ea19..f7a35c74c2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -80,14 +80,14 @@ const char * const riscv_excp_names[] =3D { const char * const riscv_intr_names[] =3D { "u_software", "s_software", - "h_software", + "vs_software", "m_software", "u_timer", "s_timer", - "h_timer", + "vs_timer", "m_timer", "u_external", - "s_external", + "vs_external", "h_external", "m_external", "reserved", diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 9ce73c36de..eeaa03c0f8 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -514,29 +514,29 @@ /* Interrupt causes */ #define IRQ_U_SOFT 0 #define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 /* reserved */ +#define IRQ_VS_SOFT 2 #define IRQ_M_SOFT 3 #define IRQ_U_TIMER 4 #define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 /* reserved */ +#define IRQ_VS_TIMER 6 #define IRQ_M_TIMER 7 #define IRQ_U_EXT 8 #define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 /* reserved */ +#define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 =20 /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) #define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_VSSIP (1 << IRQ_VS_SOFT) #define MIP_MSIP (1 << IRQ_M_SOFT) #define MIP_UTIP (1 << IRQ_U_TIMER) #define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_VSTIP (1 << IRQ_VS_TIMER) #define MIP_MTIP (1 << IRQ_M_TIMER) #define MIP_UEIP (1 << IRQ_U_EXT) #define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_VSEIP (1 << IRQ_VS_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) =20 /* sip masks */ --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h | 4 ++++ target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_helper.c | 18 ++++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c7f7ae5c38..a9cbd8584e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -117,6 +117,8 @@ struct CPURISCVState { =20 #ifndef CONFIG_USER_ONLY target_ulong priv; + /* This contains QEMU specific information about the virt state. */ + target_ulong virt; target_ulong resetvec; =20 target_ulong mhartid; @@ -269,6 +271,8 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t = *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); +bool riscv_cpu_virt_enabled(CPURISCVState *env); +void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index eeaa03c0f8..2cdb0de4fe 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -430,6 +430,9 @@ #define PRV_H 2 /* Reserved */ #define PRV_M 3 =20 +/* Virtulisation Register Fields */ +#define VIRT_ONOFF 1 + /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 #define SATP32_ASID 0x7fc00000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8f746fb06f..5844e543f3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -82,6 +82,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) return false; } =20 +bool riscv_cpu_virt_enabled(CPURISCVState *env) +{ + if (!riscv_has_ext(env, RVH)) { + return false; + } + + return get_field(env->virt, VIRT_ONOFF); +} + +void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + env->virt =3D set_field(env->virt, VIRT_ONOFF, enable); +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env =3D &cpu->env; --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580519643143593.5203437042411; Fri, 31 Jan 2020 17:14:03 -0800 (PST) Received: from localhost ([::1]:34288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhMH-0001O8-SW for importer@patchew.org; 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d="scan'208";a="128872410" IronPort-SDR: 86F3ub2aInJaH7mA/oCkW8HHixJhcvuagzydjN/1oFXOlkxEJivFUuLRNhtpXU1LpkNVTB8f5l 94mlfh77y5ftqgSMrA5LO/HKKhInz/JCfGhXm9IwhmbxsyntU3xJvU7JU13Kj033ZV9K1b7awX Yyh3HC7lwfr2jr8NU/8W2MhJPuelESLdmrlAdWssvaj5ehE1kVsDKYUFNI+rxvHScph9R5mfXg QD2TRA7ytSgVyv0YSIVMFSRirYJYtNlx0jvE+a87RTkEh5m7OX/IN86ekNmHbgzVnI9nVc0Mds WvfvlQ1GeCIlZ97uNh4ClmzE IronPort-SDR: NDA60NNVOTYqjShnHlAStl+fjUFnXwfBfhE/VLx8JLrMwhVAYEdoJZ+6hO1Sou7GgEQ/X1i2lE AYKiMxTZdcDAO8ePr55Fy1RI1eqxb59aI18eMr7OTiSBGikSFPKPAjYDTJw090tjwh+TN4rzLA 7Xx89rvFtALnD7/uxehuAK25ltce9CMyS41kb0DlLB4TJka/BD0f+DSAVNoigFx0Pw8XcUuL7Y FE2Dk9VUKkxEuqD3N9j3u2AvAkNn4ThinE04yk7HWRoVllRBLjvTSnXTJ6FSeQw60wRPKm//GV f2k= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 07/35] target/riscv: Add the force HS exception mode Date: Fri, 31 Jan 2020 17:01:54 -0800 Message-Id: X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add a FORCE_HS_EXCEP mode to the RISC-V virtulisation status. This bit specifies if an exeption should be taken to HS mode no matter the current delegation status. This is used when an exeption must be taken to HS mode, such as when handling interrupts. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 6 ++++++ target/riscv/cpu_helper.c | 18 ++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a9cbd8584e..42720d65f9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -273,6 +273,8 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interru= pt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); +bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); +void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 2cdb0de4fe..ad6479796c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -432,6 +432,12 @@ =20 /* Virtulisation Register Fields */ #define VIRT_ONOFF 1 +/* This is used to save state for when we take an exception. If this is set + * that means that we want to force a HS level exception (no matter what t= he + * delegation is set to). This will occur for things such as a second level + * page table fault. + */ +#define FORCE_HS_EXCEP 2 =20 /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5844e543f3..1e28103500 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -100,6 +100,24 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bo= ol enable) env->virt =3D set_field(env->virt, VIRT_ONOFF, enable); } =20 +bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) +{ + if (!riscv_has_ext(env, RVH)) { + return false; + } + + return get_field(env->virt, FORCE_HS_EXCEP); +} + +void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + env->virt =3D set_field(env->virt, FORCE_HS_EXCEP, enable); +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env =3D &cpu->env; --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Update the CSR permission checking to work correctly when we are in HS-mode. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/csr.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ca27359c7e..c63b2f980c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -801,12 +801,22 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target= _ulong *ret_value, =20 /* check privileges and return -1 if check fails */ #if !defined(CONFIG_USER_ONLY) - int csr_priv =3D get_field(csrno, 0x300); + int effective_priv =3D env->priv; int read_only =3D get_field(csrno, 0xC00) =3D=3D 3; - if ((!env->debugger) && (env->priv < csr_priv)) { - return -1; + + if (riscv_has_ext(env, RVH) && + env->priv =3D=3D PRV_S && + !riscv_cpu_virt_enabled(env)) { + /* + * We are in S mode without virtualisation, therefore we are in HS= Mode. + * Add 1 to the effective privledge level to allow us to access the + * Hypervisor CSRs. + */ + effective_priv++; } - if (write_mask && read_only) { + + if ((write_mask && read_only) || + (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { return -1; } #endif --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580519765639917.7404387355767; Fri, 31 Jan 2020 17:16:05 -0800 (PST) Received: from localhost ([::1]:34372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhOG-0004gF-7s for importer@patchew.org; Fri, 31 Jan 2020 20:16:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56657) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhH4-00016p-2T for qemu-devel@nongnu.org; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/translate.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 14dc71156b..afa2d6eea2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -808,7 +808,15 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase,= CPUState *cpu) =20 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *c= pu) { +#ifndef CONFIG_USER_ONLY + RISCVCPU *rvcpu =3D RISCV_CPU(cpu); + CPURISCVState *env =3D &rvcpu->env; +#endif + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); +#ifndef CONFIG_USER_ONLY + qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, = env->virt); +#endif log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); } =20 --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Dump the Hypervisor registers and the current Hypervisor state. While we are editing this code let's also dump stvec and scause. Signed-off-by: Alistair Francis Signed-off-by: Atish Patra Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f7a35c74c2..44ad768a84 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -228,17 +228,50 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *= f, int flags) CPURISCVState *env =3D &cpu->env; int i; =20 +#if !defined(CONFIG_USER_ONLY) + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s %d\n", "V =3D ", riscv_cpu_virt_enabled= (env)); + } +#endif qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatu= s); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vssta= tus); + } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hidele= g); + } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedele= g); + } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec= ); + } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); + } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscaus= e); + } + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr); + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); + } #endif =20 for (i =3D 0; i < 32; i++) { --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/csr.c | 136 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 134 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c63b2f980c..bee639e92e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -98,6 +98,20 @@ static int smode(CPURISCVState *env, int csrno) return -!riscv_has_ext(env, RVS); } =20 +static int hmode(CPURISCVState *env, int csrno) +{ + if (riscv_has_ext(env, RVS) && + riscv_has_ext(env, RVH)) { + /* Hypervisor extension is supported */ + if ((env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || + env->priv =3D=3D PRV_M) { + return 0; + } + } + + return -1; +} + static int pmp(CPURISCVState *env, int csrno) { return -!riscv_feature(env, RISCV_FEATURE_PMP); @@ -226,8 +240,9 @@ static int read_timeh(CPURISCVState *env, int csrno, ta= rget_ulong *val) =20 /* Machine constants */ =20 -#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) -#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) +#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) +#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) +#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) =20 static const target_ulong delegable_ints =3D S_MODE_INTERRUPTS; static const target_ulong all_ints =3D M_MODE_INTERRUPTS | S_MODE_INTERRUP= TS; @@ -257,6 +272,7 @@ static const target_ulong sstatus_v1_10_mask =3D SSTATU= S_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP; +static const target_ulong hip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | MI= P_VSEIP; =20 #if defined(TARGET_RISCV32) static const char valid_vm_1_09[16] =3D { @@ -756,6 +772,112 @@ static int write_satp(CPURISCVState *env, int csrno, = target_ulong val) return 0; } =20 +/* Hypervisor Extensions */ +static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->hstatus; + return 0; +} + +static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + env->hstatus =3D val; + return 0; +} + +static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->hedeleg; + return 0; +} + +static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val) +{ + env->hedeleg =3D val; + return 0; +} + +static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->hideleg; + return 0; +} + +static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val) +{ + env->hideleg =3D val; + return 0; +} + +static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask) +{ + int ret =3D rmw_mip(env, 0, ret_value, new_value, + write_mask & hip_writable_mask); + + return ret; +} + +static int read_hie(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mie & VS_MODE_INTERRUPTS; + return 0; +} + +static int write_hie(CPURISCVState *env, int csrno, target_ulong val) +{ + target_ulong newval =3D (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_M= ODE_INTERRUPTS); + return write_mie(env, CSR_MIE, newval); +} + +static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *va= l) +{ + *val =3D env->hcounteren; + return 0; +} + +static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong va= l) +{ + env->hcounteren =3D val; + return 0; +} + +static int read_htval(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->htval; + return 0; +} + +static int write_htval(CPURISCVState *env, int csrno, target_ulong val) +{ + env->htval =3D val; + return 0; +} + +static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->htinst; + return 0; +} + +static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) +{ + env->htinst =3D val; + return 0; +} + +static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->hgatp; + return 0; +} + +static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val) +{ + env->hgatp =3D val; + return 0; +} + /* Physical Memory Protection */ static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) { @@ -959,6 +1081,16 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D { /* Supervisor Protection and Translation */ [CSR_SATP] =3D { smode, read_satp, write_satp = }, =20 + [CSR_HSTATUS] =3D { hmode, read_hstatus, write_hstat= us }, + [CSR_HEDELEG] =3D { hmode, read_hedeleg, write_hedel= eg }, + [CSR_HIDELEG] =3D { hmode, read_hideleg, write_hidel= eg }, + [CSR_HIP] =3D { hmode, NULL, NULL, rmw_hip = }, + [CSR_HIE] =3D { hmode, read_hie, write_hie = }, + [CSR_HCOUNTEREN] =3D { hmode, read_hcounteren, write_hcoun= teren }, + [CSR_HTVAL] =3D { hmode, read_htval, write_htval= }, + [CSR_HTINST] =3D { hmode, read_htinst, write_htins= t }, + [CSR_HGATP] =3D { hmode, read_hgatp, write_hgatp= }, + /* Physical Memory Protection */ [CSR_PMPCFG0 ... CSR_PMPADDR9] =3D { pmp, read_pmpcfg, write_pmpc= fg }, [CSR_PMPADDR0 ... CSR_PMPADDR15] =3D { pmp, read_pmpaddr, write_pmpa= ddr }, --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580519775013111.30611453781114; Fri, 31 Jan 2020 17:16:15 -0800 (PST) Received: from localhost ([::1]:34380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhOP-00055e-Kv for importer@patchew.org; Fri, 31 Jan 2020 20:16:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56730) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhHC-0001UG-A3 for qemu-devel@nongnu.org; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/csr.c | 116 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index bee639e92e..3fa8d2cfda 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -273,6 +273,7 @@ static const target_ulong sstatus_v1_10_mask =3D SSTATU= S_SIE | SSTATUS_SPIE | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP; static const target_ulong hip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | MI= P_VSEIP; +static const target_ulong vsip_writable_mask =3D MIP_VSSIP; =20 #if defined(TARGET_RISCV32) static const char valid_vm_1_09[16] =3D { @@ -878,6 +879,111 @@ static int write_hgatp(CPURISCVState *env, int csrno,= target_ulong val) return 0; } =20 +/* Virtual CSR Registers */ +static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vsstatus; + return 0; +} + +static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vsstatus =3D val; + return 0; +} + +static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask) +{ + int ret =3D rmw_mip(env, 0, ret_value, new_value, + write_mask & env->mideleg & vsip_writable_mask); + return ret; +} + +static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mie & env->mideleg & VS_MODE_INTERRUPTS; + return 0; +} + +static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) +{ + target_ulong newval =3D (env->mie & ~env->mideleg) | (val & env->midel= eg & MIP_VSSIP); + return write_mie(env, CSR_MIE, newval); +} + +static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vstvec; + return 0; +} + +static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vstvec =3D val; + return 0; +} + +static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vsscratch; + return 0; +} + +static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vsscratch =3D val; + return 0; +} + +static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vsepc; + return 0; +} + +static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vsepc =3D val; + return 0; +} + +static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vscause; + return 0; +} + +static int write_vscause(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vscause =3D val; + return 0; +} + +static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vstval; + return 0; +} + +static int write_vstval(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vstval =3D val; + return 0; +} + +static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vsatp; + return 0; +} + +static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vsatp =3D val; + return 0; +} + /* Physical Memory Protection */ static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1091,6 +1197,16 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D { [CSR_HTINST] =3D { hmode, read_htinst, write_htins= t }, [CSR_HGATP] =3D { hmode, read_hgatp, write_hgatp= }, =20 + [CSR_VSSTATUS] =3D { hmode, read_vsstatus, write_vssta= tus }, + [CSR_VSIP] =3D { hmode, NULL, NULL, rmw_vsip = }, + [CSR_VSIE] =3D { hmode, read_vsie, write_vsie = }, + [CSR_VSTVEC] =3D { hmode, read_vstvec, write_vstve= c }, + [CSR_VSSCRATCH] =3D { hmode, read_vsscratch, write_vsscr= atch }, + [CSR_VSEPC] =3D { hmode, read_vsepc, write_vsepc= }, + [CSR_VSCAUSE] =3D { hmode, read_vscause, write_vscau= se }, + [CSR_VSTVAL] =3D { hmode, read_vstval, write_vstva= l }, + [CSR_VSATP] =3D { hmode, read_vsatp, write_vsatp= }, + /* Physical Memory Protection */ [CSR_PMPCFG0 ... CSR_PMPADDR9] =3D { pmp, read_pmpcfg, write_pmpc= fg }, [CSR_PMPADDR0 ... CSR_PMPADDR15] =3D { pmp, read_pmpaddr, write_pmpa= ddr }, --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580519940528763.9755695017968; Fri, 31 Jan 2020 17:19:00 -0800 (PST) Received: from localhost ([::1]:34436 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhR5-00005U-7i for importer@patchew.org; Fri, 31 Jan 2020 20:18:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56754) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhHE-0001b7-NT for qemu-devel@nongnu.org; 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x=1612055327; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Kphn0jkVfgG8knJMnPW0CMVlXCQNQw727QC8fZenLwQ=; b=Ora3d/iq/NZsdfdzTOntUh/vtEtJSVWDVVltb/mCMk/vq3y3+U1hBw23 psI9kOi+5+0tYx3qABJ1Rlo0Zaa6vuj+GLmHkJmRwtNWbWuYDlUt3ZBN0 MS0V3TEh0MWAlhvouffV+jItDyoK0IDHXsF1JpFUa899a0pz+XwMhLUwZ c/bxNvF37yE519o1sbvsNr3IcKiF+u+uOF2bG/x8ZIKyf5hcDs+fgjJWV 06FXgcA5ltBu0q8FFsH1Iy0DsouUY0FUQW4o2IKgUB2j9e43qSVnGmiho eFBLS3vU9Xy09pObPjAjlBop4Oz158cThIwvKP5NjtvDgqeGh0EqQXrJx A==; IronPort-SDR: ktRFwKmVeS0J3aeZsuyxZGvhO2J1NtuczYEYgw3yKRSRdNavVqyePmSObbTNvJ00OSSCrquOeB 8cS39y4Nok4RcdYd69qyhsmV7E7PjxeTMAZsfzjbIlbufZsR0nsTQs0u4vKp3pNdPejoBhvzs1 CWFUO8kZirweZZ9ezIEitp2NxVQbqfXoAoJA2lDGy8xcutjh5T+9hJtKFRSS8tLenHeOnF3t0f Y1WY03HwNBvcMCyd6bq0GfdXKRtubkDqT49Jf1A7P+lI7uK6Fyxg1qbKeI+I/uczZsH55DsmuF 2u4= X-IronPort-AV: E=Sophos;i="5.70,388,1574092800"; d="scan'208";a="128872441" IronPort-SDR: mSVc8Vfdn0MVMo9FI8AHkEoDQfkY6it3myp89gQMwcAKKH48J7Uz5yZhpt9Tb/ck9vFhXPYyxq OFu/05BP7aA/la9KBxIb0rpp+oVR7qgEwxIsa1HBxCNbzkeXFnTZ0xG+Qd4qimE0AHM1XO/NzK qttp67j1h3FurkFdT6rJG7E8MQMtDxUPBjZ+Rn9UzzJqLe7KGVG/IOn67NaCQrJVJOKAvP5S9h s5GKn9GyWb2suGPAE+VP9KcSZTG2OZJMoI7j/Hp2WdNnWkvSqozhMYMgtHDvrRYWm/AC5EOrQn yFzCeXkeALxiApSlzv3sVJhl IronPort-SDR: WczzS5s+lIhWy1hegcTEP6IOwN4cOMhqMfPSJwTr6SS4ygz/aQTXpp1AEcrgR3DZqqDEgepFYS 9OaRmSb9heEfRZqzXfXCMu44wYwQVLAEpuVSQ8xO/PKCNXN/gQ5KZoZhYSNfVvsxqKplyjXxeY 9CDGFBShk8YXWFh+ARWKFvSKfETBCEwKZuYFgq/b+GEFxHSlEYVRQUUe2j8xWVcMm544rFut7A u1bBrb5bQSmT7GzRr2q/0FG1ESmSWrNdqtGaP33p0p29dmzEFjZIisVL34JJBfgQthkprPECF7 r3o= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 13/35] target/riscv: Add Hypervisor machine CSRs accesses Date: Fri, 31 Jan 2020 17:02:10 -0800 Message-Id: X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/csr.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3fa8d2cfda..f7333286bd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -984,6 +984,30 @@ static int write_vsatp(CPURISCVState *env, int csrno, = target_ulong val) return 0; } =20 +static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mtval2; + return 0; +} + +static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mtval2 =3D val; + return 0; +} + +static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mtinst; + return 0; +} + +static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mtinst =3D val; + return 0; +} + /* Physical Memory Protection */ static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1207,6 +1231,9 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D { [CSR_VSTVAL] =3D { hmode, read_vstval, write_vstva= l }, [CSR_VSATP] =3D { hmode, read_vsatp, write_vsatp= }, =20 + [CSR_MTVAL2] =3D { hmode, read_mtval2, write_mtval= 2 }, + [CSR_MTINST] =3D { hmode, read_mtinst, write_mtins= t }, + /* Physical Memory Protection */ [CSR_PMPCFG0 ... CSR_PMPADDR9] =3D { pmp, read_pmpcfg, write_pmpc= fg }, [CSR_PMPADDR0 ... CSR_PMPADDR15] =3D { pmp, read_pmpaddr, write_pmpa= ddr }, --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580520093924290.9154220845785; Fri, 31 Jan 2020 17:21:33 -0800 (PST) Received: from localhost ([::1]:34508 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhTY-0003hp-O5 for importer@patchew.org; Fri, 31 Jan 2020 20:21:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56812) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhHb-0002G5-LR for qemu-devel@nongnu.org; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h | 11 +++++++ target/riscv/cpu_bits.h | 7 +++++ target/riscv/cpu_helper.c | 61 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 42720d65f9..5b889a0065 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -125,6 +125,7 @@ struct CPURISCVState { target_ulong mstatus; =20 target_ulong mip; + uint32_t miclaim; =20 target_ulong mie; @@ -166,6 +167,15 @@ struct CPURISCVState { target_ulong mtval2; target_ulong mtinst; =20 + /* HS Backup CSRs */ + target_ulong stvec_hs; + target_ulong sscratch_hs; + target_ulong sepc_hs; + target_ulong scause_hs; + target_ulong stval_hs; + target_ulong satp_hs; + target_ulong mstatus_hs; + target_ulong scounteren; target_ulong mcounteren; =20 @@ -296,6 +306,7 @@ void riscv_cpu_list(void); #define cpu_mmu_index riscv_cpu_mmu_index =20 #ifndef CONFIG_USER_ONLY +void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value= ); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index ad6479796c..a24654d137 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -553,4 +553,11 @@ #define SIP_STIP MIP_STIP #define SIP_SEIP MIP_SEIP =20 +/* MIE masks */ +#define MIE_SEIE (1 << IRQ_S_EXT) +#define MIE_UEIE (1 << IRQ_U_EXT) +#define MIE_STIE (1 << IRQ_S_TIMER) +#define MIE_UTIE (1 << IRQ_U_TIMER) +#define MIE_SSIE (1 << IRQ_S_SOFT) +#define MIE_USIE (1 << IRQ_U_SOFT) #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1e28103500..e9d75b45d6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -82,6 +82,67 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) return false; } =20 +void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) +{ + target_ulong mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; + bool current_virt =3D riscv_cpu_virt_enabled(env); + + g_assert(riscv_has_ext(env, RVH)); + +#if defined(TARGET_RISCV64) + mstatus_mask |=3D MSTATUS64_UXL; +#endif + + if (current_virt) { + /* Current V=3D1 and we are about to change to V=3D0 */ + env->vsstatus =3D env->mstatus & mstatus_mask; + env->mstatus &=3D ~mstatus_mask; + env->mstatus |=3D env->mstatus_hs; + + env->vstvec =3D env->stvec; + env->stvec =3D env->stvec_hs; + + env->vsscratch =3D env->sscratch; + env->sscratch =3D env->sscratch_hs; + + env->vsepc =3D env->sepc; + env->sepc =3D env->sepc_hs; + + env->vscause =3D env->scause; + env->scause =3D env->scause_hs; + + env->vstval =3D env->sbadaddr; + env->sbadaddr =3D env->stval_hs; + + env->vsatp =3D env->satp; + env->satp =3D env->satp_hs; + } else { + /* Current V=3D0 and we are about to change to V=3D1 */ + env->mstatus_hs =3D env->mstatus & mstatus_mask; + env->mstatus &=3D ~mstatus_mask; + env->mstatus |=3D env->vsstatus; + + env->stvec_hs =3D env->stvec; + env->stvec =3D env->vstvec; + + env->sscratch_hs =3D env->sscratch; + env->sscratch =3D env->vsscratch; + + env->sepc_hs =3D env->sepc; + env->sepc =3D env->vsepc; + + env->scause_hs =3D env->scause; + env->scause =3D env->vscause; + + env->stval_hs =3D env->sbadaddr; + env->sbadaddr =3D env->vstval; + + env->satp_hs =3D env->satp; + env->satp =3D env->vsatp; + } +} + bool riscv_cpu_virt_enabled(CPURISCVState *env) { if (!riscv_has_ext(env, RVH)) { --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580519548554417.957272263037; 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d="scan'208";a="128872460" IronPort-SDR: kDQEfBUhasTutCvItueheC4Uh0CzqaE2knH9F4EHh/LvYxqlisHYkfBdGrsSQyKat9CBTn3Xml aSN9Ag/2qQ3CtTj5p0403JfS8zgvkHNbjdH+Sx7vWsNAOqnPqf8Lv2iOFLcb5lb8Yl1Ckl+s6/ rduqhqc5bzbsUHzN0X+iTN4hsyVB5oshZnDRRMcHpJVYb47G8uy+hSPvJIbdUoDbwuD+3PyQ9u fNCe0oETEzjXJKSY431UiHNoB0XrPUkUCw8aRo0ugsfDMy8vJZKdzuVvXgtH4vCPZ3D9HPQ4Rx R7HJ28ZKLNV6CjTS6SJ+a2Vc IronPort-SDR: NkQA4UeR3UDM2jFdQwClKgHoU+uJyNAsmuBMxUYK0o8bJFiiPUJQF1i4RvsjGGp1qZ/apDriJo Ah0BfvWnYtQ3iHEIF0uXjplcqs5EzSu3LmfObJRU/KoVr2XYC+4nby6UN7OckrEHrDlPG/kqHH KrP0lE6GsXQ/pkrSM0IKzYrrmbMY5lKnN1byfXG2mdVw8qRJZMW2ty3+/m6dMV2zxwKah3pD5P 8+yiIknNzLvaJwha+IWlqRq4hFVdJ6KnzMuowCgy2cV02ELKaqkwnyMs0UOj3M0zbuhP+BC1zq F8I= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 15/35] target/riscv: Set VS bits in mideleg for Hyp extension Date: Fri, 31 Jan 2020 17:02:15 -0800 Message-Id: <7c15db86126bf5c4343de79dae5c95a2c964cd24.1580518859.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f7333286bd..c0e942684d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -448,6 +448,9 @@ static int read_mideleg(CPURISCVState *env, int csrno, = target_ulong *val) static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) { env->mideleg =3D (env->mideleg & ~delegable_ints) | (val & delegable_i= nts); + if (riscv_has_ext(env, RVH)) { + env->mideleg |=3D VS_MODE_INTERRUPTS; + } return 0; } =20 --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="128872462" IronPort-SDR: nqLmzl9vdmJ6D8KISY3Irma4fOUUfncSqVZeuw8XZgYfCBM6V7KOVSFfgwO7kFziRWCPF3kpch cyte7OmaZKxS9K4f4t8PLdwax2iGQH/6e3K4DhISLi4+kWdwMe9nqnzW5Q6AGFMGHjBAZzrwlt WAL5zp8g1ClcvsOahDLobHsf/6TPzQEzVXb0sxbxk08emV2DWnrOrjbL1CVtxQuLSSWKWkU1y9 LwgKe4I3c7t9XcuFik9C6c0G7QME4C6R+cMbJjY2K+3F4CM5fq6fSUQ2wZUeYGFO5uabbaj6uA C55btBUpWybr3cBUwp29Ua/F IronPort-SDR: jxC2OjS2FoJegBU5dMO/n8mqIirbEmr9jQXwrs77nMgZrya7tJ2Hugu7KXdyIEmb4mphOuZIGv bHgYOGbEeJv0Shtzkd7wGt5VHRIDj4azogv4e+j05i75XJA+zlfmOxVB5aQw8BjWPNuPUpmJh+ FGUw2Z4Ds1xKti4YOm+UnewRKs7vVI3NF7lLLbdHwa4T0JvtPACHfFPB1qy3iJQoBgQM1HONYR koLupTuQdSI5LowBLrJCQnFuPqTVJxSqKWI83l0jXS20dncOGUMHQRgcbT4L2UXbq+S+8wZpru I9I= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 16/35] target/riscv: Extend the MIE CSR to support virtulisation Date: Fri, 31 Jan 2020 17:02:17 -0800 Message-Id: <2c7b5ae2fe313be30565f8370a039595607605cc.1580518859.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/csr.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c0e942684d..918678789a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -244,8 +244,10 @@ static int read_timeh(CPURISCVState *env, int csrno, t= arget_ulong *val) #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) =20 -static const target_ulong delegable_ints =3D S_MODE_INTERRUPTS; -static const target_ulong all_ints =3D M_MODE_INTERRUPTS | S_MODE_INTERRUP= TS; +static const target_ulong delegable_ints =3D S_MODE_INTERRUPTS | + VS_MODE_INTERRUPTS; +static const target_ulong all_ints =3D M_MODE_INTERRUPTS | S_MODE_INTERRUP= TS | + VS_MODE_INTERRUPTS; static const target_ulong delegable_excps =3D (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | @@ -630,13 +632,27 @@ static int write_sstatus(CPURISCVState *env, int csrn= o, target_ulong val) =20 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mie & env->mideleg; + if (riscv_cpu_virt_enabled(env)) { + /* Tell the guest the VS bits, shifted to the S bit locations */ + *val =3D (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1; + } else { + *val =3D env->mie & env->mideleg; + } return 0; } =20 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong newval =3D (env->mie & ~env->mideleg) | (val & env->midel= eg); + target_ulong newval; + + if (riscv_cpu_virt_enabled(env)) { + /* Shift the guests S bits to VS */ + newval =3D (env->mie & ~VS_MODE_INTERRUPTS) | + ((val << 1) & VS_MODE_INTERRUPTS); + } else { + newval =3D (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRU= PTS); + } + return write_mie(env, CSR_MIE, newval); } =20 --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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IronPort-SDR: 3WNXANfKrM+n6JSPvVC2Uq+bddaXQWebHlwi5FkWbux14TWq3UqH1ORuer+GbDcnr+tGeb6Qux wE/K4Rq8LthMb05J/8ffsykmZz407a+Yp4CFzOLYqzgfO1ON1eX912hh/6Joe9M7AkNtzaEFUz RU5+kTT9iSG/Lx0S3IjVn3t+MIKIVm/V2vMj9FiCBbAqSlr+k2ug/JmG/XZjCbuVG+GyNQTyhX NUTpDGk2AoZQ9FbeacpCKgALqcEZG/pcxACQgipzArg7BL/ylD2pccXL2W1kR3bEYZhtfZBiEs WCs= X-IronPort-AV: E=Sophos;i="5.70,388,1574092800"; d="scan'208";a="128872467" IronPort-SDR: L5dOPhmSK2EpcWFqR04x3vBxpo2zJsV5liMMnhwdGlgCeWF8lBl/C8lJwX1p+eZfM1UZemxxJE B6k9H/VVnPYdOb4eYdOFUsPk0rrwA+Tmq4iLCv8wh93S9z1t5fW4EgfE8uMvpvb+yJVqtkJ/zL vISBrqK9NHB4GBzzzns8J7dFnxIiKJ8D/RBNgva/qyDwyGwPIoGnBvDB+wZcjg0O62NP/usmBo 2T6+XAOO3pEZ4+5wFcNdnYgNwTWH791hbLuzX5AvafC9ZZYOrbd0ODFwUT4Fr4th9TcumbOPCt Osn38WZtxa2uDL2cV2POIROQ IronPort-SDR: arEM/C97mZQZQWiCh3DZCE9iMG5UO787EIFCJ96BijLGwG4FrEB9vf0mye8+2VejRRbQd4BBbR rfb7nkWVFuaIAorTFCsRtrpsdk+Gqt7suhbYxy6zaaF+bfCl9feNVdyAxC5CFv4zsfDKvz9cvb SvT2S+QjmwTwr8YssnFXRuT5mmTkRk3SjtwgVDY4Lta+qhRWoNYu6x/hyz1apb1P0PhD01TlyS qeGj8EeIgV5ie0zGq0gpjJwOci6CJ7TDAi+IAfNJ9c5kUXz5xmiZiauLzaBpIG+9JVuqyR6BZQ VVA= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 17/35] target/riscv: Extend the SIP CSR to support virtulisation Date: Fri, 31 Jan 2020 17:02:20 -0800 Message-Id: <39eac165cde84450279a4cbb887437fefe75fa04.1580518859.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/csr.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 918678789a..2e6700bbeb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -743,8 +743,19 @@ static int write_sbadaddr(CPURISCVState *env, int csrn= o, target_ulong val) static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { - int ret =3D rmw_mip(env, CSR_MSTATUS, ret_value, new_value, + int ret; + + if (riscv_cpu_virt_enabled(env)) { + /* Shift the new values to line up with the VS bits */ + ret =3D rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1, + (write_mask & sip_writable_mask) << 1 & env->mideleg= ); + ret &=3D vsip_writable_mask; + ret >>=3D 1; + } else { + ret =3D rmw_mip(env, CSR_MSTATUS, ret_value, new_value, write_mask & env->mideleg & sip_writable_mask); + } + *ret_value &=3D env->mideleg; return ret; } --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580519665051966.9557290166063; Fri, 31 Jan 2020 17:14:25 -0800 (PST) Received: from localhost ([::1]:34292 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhMd-0002M3-T0 for importer@patchew.org; Fri, 31 Jan 2020 20:14:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56971) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhHx-000391-JO for qemu-devel@nongnu.org; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e9d75b45d6..3984a1f1ac 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -37,13 +37,36 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { + target_ulong irqs; + target_ulong mstatus_mie =3D get_field(env->mstatus, MSTATUS_MIE); target_ulong mstatus_sie =3D get_field(env->mstatus, MSTATUS_SIE); - target_ulong pending =3D env->mip & env->mie; - target_ulong mie =3D env->priv < PRV_M || (env->priv =3D=3D PRV_M && m= status_mie); - target_ulong sie =3D env->priv < PRV_S || (env->priv =3D=3D PRV_S && m= status_sie); - target_ulong irqs =3D (pending & ~env->mideleg & -mie) | - (pending & env->mideleg & -sie); + target_ulong hs_mstatus_sie =3D get_field(env->mstatus_hs, MSTATUS_SIE= ); + + target_ulong pending =3D env->mip & env->mie & + ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + target_ulong vspending =3D (env->mip & env->mie & + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; + + target_ulong mie =3D env->priv < PRV_M || + (env->priv =3D=3D PRV_M && mstatus_mie); + target_ulong sie =3D env->priv < PRV_S || + (env->priv =3D=3D PRV_S && mstatus_sie); + target_ulong hs_sie =3D env->priv < PRV_S || + (env->priv =3D=3D PRV_S && hs_mstatus_sie); + + if (riscv_cpu_virt_enabled(env)) { + target_ulong pending_hs_irq =3D pending & -hs_sie; + + if (pending_hs_irq) { + riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP); + return ctz64(pending_hs_irq); + } + + pending =3D vspending; + } + + irqs =3D (pending & ~env->mideleg & -mie) | (pending & env->mideleg &= -sie); =20 if (irqs) { return ctz64(irqs); /* since non-zero */ --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" To ensure our TLB isn't out-of-date we flush it on all virt mode changes. Unlike priv mode this isn't saved in the mmu_idx as all guests share V=3D1. The easiest option is just to flush on all changes. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3984a1f1ac..98017df33b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -181,6 +181,11 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bo= ol enable) return; } =20 + /* Flush the TLB on all virt mode changes. */ + if (get_field(env->virt, VIRT_ONOFF) !=3D enable) { + tlb_flush(env_cpu(env)); + } + env->virt =3D set_field(env->virt, VIRT_ONOFF, enable); } =20 --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="128872474" IronPort-SDR: inSJJxgg7Wd4GoXFdcgn7oKKKnMKAWsvMPW9snef+Nl+pMs6xCnEZf+IHljtQ9HDTOcsezNQnd VvVgP9xCidYReL3mtOS3MDyjEQDG/Wu/3mI6/nGAgdQaFxf6dRRoz76maqB/zElU7HCLZ71yTE wNXYWCF6AHYep+0UvLMKAqxNJMq9K3eOZpnEvoV4cSnsyPC89weHpGGvZzEkRmP+rkltg+Cwsa C7OCAQKWSGEsqeTuH5+9jDEluF6rVlFw5mPeytFV3JxjFJxKCC6NYgEUS1YOxq0HuPDOY3CSul eHbsBP8I4TNUpKp7Q5qAqWy/ IronPort-SDR: 2kld+NC20cnGT14PoDZgdj9dmNNty2ra2a8ktLOV+gbh5Et6CtY27j1EXsTLIIue38b9gfovoG 5SDhtpnDA9jsKIu3KY/SxnSioShR0uD/g+4dTA1/9PEjwf8pOe7h8KnJ92mS2akafx3BAAq030 0BuQ97+ZLIWRXi8nsb4jznStKXZsORDmC9IrdpNGMu7/lNSmrrP9TSgiydNaqIPDULLlSGP2UJ L5UdrMlQs1uiQje9aDz2b1M5me2y6u06oEpW/9Cxfv7gk9f02dyFVAWIYaWzuCK8vm1UQWbNq8 THk= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 20/35] target/riscv: Generate illegal instruction on WFI when V=1 Date: Fri, 31 Jan 2020 17:02:28 -0800 Message-Id: X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/op_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index e87c9115bc..455eb28907 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -130,9 +130,10 @@ void helper_wfi(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); =20 - if (env->priv =3D=3D PRV_S && + if ((env->priv =3D=3D PRV_S && env->priv_ver >=3D PRIV_VERSION_1_10_0 && - get_field(env->mstatus, MSTATUS_TW)) { + get_field(env->mstatus, MSTATUS_TW)) || + riscv_cpu_virt_enabled(env)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } else { cs->halted =3D 1; --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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IronPort-SDR: Bm98mWxqg7kvLkcAffMvTym0s1IiOTBLJSFMApkygg5IENIEYYge+sDekAjqojJyjOIqIWcc5c dmGzdh4N8aMv8Te8M+B6K30+whUgK9GMwhdd7KbaWCTPQ8MViiAFMquXrFC5eZmb6D0gHvWr7r hWVfWLsrnGwvh+mKFPldf9fGshi+RtEEWPfviNr9kMobeGdn3V38+KH9/AYqP9YCr/o058n7al YlrwlmLm2wPuc9E6tpj2hkUCIeQnJ5FxExOxb6jad/6SKvZE/19qqNk1/ttxF9Vcbf5G/ysEMo /RU= X-IronPort-AV: E=Sophos;i="5.70,388,1574092800"; d="scan'208";a="128872477" IronPort-SDR: elhqgZMfbxl7zb4vN/6DugwmN7Ptlj58TBNBps5WMXJ32Da7wqvBwPSEQfJruppL439xZ9tmLZ CPOwLrl6277Hq1RL44h7kdiTdGFSzbiXlNX++lFHkkTBWnJbN4uFQ9fjYgpJp8CI0eN61hILh7 nGbjL/u85BW9F8BtCvwNvzYEOgIiEd802RDZl1iG3rTm6krtHCnef7DdSlzOVJiMdoOCz29KbR 6TU0S8zDY6k29GjAhTKK1u/c6NQO//QTds58z/gl9dQnOCl/A9j9NeoPzMnFfWPU/OFZln6uoy k88Y8oRe7cC55WkxYQiqvvFX IronPort-SDR: 4TD4fNLVQytuxwAnn7bItSiP13szMhyuSG9LjStgLJ/KkVpaYpLCD7KFnTXQnSqpcLiu3Z0vu5 MTuvNGKZoPIezrvzkAzoFxytIIfuTaKNIEP2GXz+LyYKM0DBcxtB4Kuj9x43FZKse1nPp9FHKC EUl3LdBXSgwrKm3ZoeS8UHa52lMJ4NF1Q+3N23zkupRr2Pcf0MGFQiMd1pLSWVB3K66nVs9ERH 5IjIhP112/mKxcaVKhLCocMjBCFFwVO31raK42lGFTIwHoQdGgHpbsUXI1BIB3L/1Wh1UX+cJH 3go= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 21/35] target/riscv: Add hypvervisor trap support Date: Fri, 31 Jan 2020 17:02:30 -0800 Message-Id: <7ee4badbb4dfc33ab2e75151b69559f09d733575.1580518859.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 69 +++++++++++++++++++++++++++++++++------ 1 file changed, 59 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 98017df33b..e7728cb0ca 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -639,6 +639,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + bool force_hs_execp =3D riscv_cpu_force_hs_excep_enabled(env); + target_ulong s; =20 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide * so we mask off the MSB and separate into trap type and cause. @@ -648,19 +650,14 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong deleg =3D async ? env->mideleg : env->medeleg; target_ulong tval =3D 0; =20 - static const int ecall_cause_map[] =3D { - [PRV_U] =3D RISCV_EXCP_U_ECALL, - [PRV_S] =3D RISCV_EXCP_S_ECALL, - [PRV_H] =3D RISCV_EXCP_VS_ECALL, - [PRV_M] =3D RISCV_EXCP_M_ECALL - }; - if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { case RISCV_EXCP_INST_GUEST_PAGE_FAULT: case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: + force_hs_execp =3D true; + /* fallthrough */ case RISCV_EXCP_INST_ADDR_MIS: case RISCV_EXCP_INST_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: @@ -678,7 +675,16 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* ecall is dispatched as one cause so translate based on mode */ if (cause =3D=3D RISCV_EXCP_U_ECALL) { assert(env->priv <=3D 3); - cause =3D ecall_cause_map[env->priv]; + + if (env->priv =3D=3D PRV_M) { + cause =3D RISCV_EXCP_M_ECALL; + } else if (env->priv =3D=3D PRV_S && riscv_cpu_virt_enabled(en= v)) { + cause =3D RISCV_EXCP_VS_ECALL; + } else if (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(e= nv)) { + cause =3D RISCV_EXCP_S_ECALL; + } else if (env->priv =3D=3D PRV_U) { + cause =3D RISCV_EXCP_U_ECALL; + } } } =20 @@ -688,7 +694,36 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (env->priv <=3D PRV_S && cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { /* handle the trap in S-mode */ - target_ulong s =3D env->mstatus; + if (riscv_has_ext(env, RVH)) { + target_ulong hdeleg =3D async ? env->hideleg : env->hedeleg; + + if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && + !force_hs_execp) { + /* Trap to VS mode */ + } else if (riscv_cpu_virt_enabled(env)) { + /* Trap into HS mode, from virt */ + riscv_cpu_swap_hypervisor_regs(env); + env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2V, + get_field(env->hstatus, HSTATUS_S= PV)); + env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2P, + get_field(env->mstatus, SSTATUS_S= PP)); + env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, + riscv_cpu_virt_enabled(env)); + + riscv_cpu_set_virt_enabled(env, 0); + riscv_cpu_set_force_hs_excep(env, 0); + } else { + /* Trap into HS mode */ + env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2V, + get_field(env->hstatus, HSTATUS_S= PV)); + env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2P, + get_field(env->mstatus, SSTATUS_S= PP)); + env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, + riscv_cpu_virt_enabled(env)); + } + } + + s =3D env->mstatus; s =3D set_field(s, MSTATUS_SPIE, env->priv_ver >=3D PRIV_VERSION_1= _10_0 ? get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->p= riv)); s =3D set_field(s, MSTATUS_SPP, env->priv); @@ -702,7 +737,21 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_mode(env, PRV_S); } else { /* handle the trap in M-mode */ - target_ulong s =3D env->mstatus; + if (riscv_has_ext(env, RVH)) { + if (riscv_cpu_virt_enabled(env)) { + riscv_cpu_swap_hypervisor_regs(env); + } + env->mstatus =3D set_field(env->mstatus, MSTATUS_MPV, + riscv_cpu_virt_enabled(env)); + env->mstatus =3D set_field(env->mstatus, MSTATUS_MTL, + riscv_cpu_force_hs_excep_enabled(env= )); + + /* Trapping to M mode, virt is disabled */ + riscv_cpu_set_virt_enabled(env, 0); + riscv_cpu_set_force_hs_excep(env, 0); + } + + s =3D env->mstatus; s =3D set_field(s, MSTATUS_MPIE, env->priv_ver >=3D PRIV_VERSION_1= _10_0 ? get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->p= riv)); s =3D set_field(s, MSTATUS_MPP, env->priv); --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580519777571960.635441119489; Fri, 31 Jan 2020 17:16:17 -0800 (PST) Received: from localhost ([::1]:34384 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhOR-0005Aq-Bl for importer@patchew.org; Fri, 31 Jan 2020 20:16:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57136) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhII-0003tZ-Qv for qemu-devel@nongnu.org; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/op_helper.c | 62 +++++++++++++++++++++++++++++++++------- 1 file changed, 52 insertions(+), 10 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 455eb28907..804936e9d5 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -73,6 +73,8 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulon= g src, =20 target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) { + target_ulong prev_priv, prev_virt, mstatus; + if (!(env->priv >=3D PRV_S)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } @@ -87,16 +89,46 @@ target_ulong helper_sret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 - target_ulong mstatus =3D env->mstatus; - target_ulong prev_priv =3D get_field(mstatus, MSTATUS_SPP); - mstatus =3D set_field(mstatus, - env->priv_ver >=3D PRIV_VERSION_1_10_0 ? - MSTATUS_SIE : MSTATUS_UIE << prev_priv, - get_field(mstatus, MSTATUS_SPIE)); - mstatus =3D set_field(mstatus, MSTATUS_SPIE, 1); - mstatus =3D set_field(mstatus, MSTATUS_SPP, PRV_U); + mstatus =3D env->mstatus; + + if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { + /* We support Hypervisor extensions and virtulisation is disabled = */ + target_ulong hstatus =3D env->hstatus; + + prev_priv =3D get_field(mstatus, MSTATUS_SPP); + prev_virt =3D get_field(hstatus, HSTATUS_SPV); + + hstatus =3D set_field(hstatus, HSTATUS_SPV, + get_field(hstatus, HSTATUS_SP2V)); + mstatus =3D set_field(mstatus, MSTATUS_SPP, + get_field(hstatus, HSTATUS_SP2P)); + hstatus =3D set_field(hstatus, HSTATUS_SP2V, 0); + hstatus =3D set_field(hstatus, HSTATUS_SP2P, 0); + mstatus =3D set_field(mstatus, SSTATUS_SIE, + get_field(mstatus, SSTATUS_SPIE)); + mstatus =3D set_field(mstatus, SSTATUS_SPIE, 1); + + env->mstatus =3D mstatus; + env->hstatus =3D hstatus; + + if (prev_virt) { + riscv_cpu_swap_hypervisor_regs(env); + } + + riscv_cpu_set_virt_enabled(env, prev_virt); + } else { + prev_priv =3D get_field(mstatus, MSTATUS_SPP); + + mstatus =3D set_field(mstatus, + env->priv_ver >=3D PRIV_VERSION_1_10_0 ? + MSTATUS_SIE : MSTATUS_UIE << prev_priv, + get_field(mstatus, MSTATUS_SPIE)); + mstatus =3D set_field(mstatus, MSTATUS_SPIE, 1); + mstatus =3D set_field(mstatus, MSTATUS_SPP, PRV_U); + env->mstatus =3D mstatus; + } + riscv_cpu_set_mode(env, prev_priv); - env->mstatus =3D mstatus; =20 return retpc; } @@ -114,14 +146,24 @@ target_ulong helper_mret(CPURISCVState *env, target_u= long cpu_pc_deb) =20 target_ulong mstatus =3D env->mstatus; target_ulong prev_priv =3D get_field(mstatus, MSTATUS_MPP); + target_ulong prev_virt =3D get_field(mstatus, MSTATUS_MPV); mstatus =3D set_field(mstatus, env->priv_ver >=3D PRIV_VERSION_1_10_0 ? MSTATUS_MIE : MSTATUS_UIE << prev_priv, get_field(mstatus, MSTATUS_MPIE)); mstatus =3D set_field(mstatus, MSTATUS_MPIE, 1); mstatus =3D set_field(mstatus, MSTATUS_MPP, PRV_U); - riscv_cpu_set_mode(env, prev_priv); + mstatus =3D set_field(mstatus, MSTATUS_MPV, 0); env->mstatus =3D mstatus; + riscv_cpu_set_mode(env, prev_priv); + + if (riscv_has_ext(env, RVH)) { + if (prev_virt) { + riscv_cpu_swap_hypervisor_regs(env); + } + + riscv_cpu_set_virt_enabled(env, prev_virt); + } =20 return retpc; } --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="128872481" IronPort-SDR: sfT3E2vWWLSNzuuWYPE6LOV98degS9IrklMtsn/xmzIZqr3rKw3QA7jSj5xpUPKIwXc4C5gFKz +CcIC1s0CO3CamJg+7zE0dsdhOl1VQ8I2VUPbZ18fKQsSh/EblmPj1qzrc4nIMT8iMDurwxiql T66CBSkIW9aq98kj74JRnmPIY7Io4HZXnm+h916cCkMuJncqJm1+s+jxZ9r/lGDht5Ofl9qIPs OwXN6elRVc5YvD2qZWCVRJ99nAMX6huI6FccAfvBD1VDpxVBu93uu7eYw0QHbdYvmpVBYuLloh t5kwQmNGuaddAJj8ZNCXmOzV IronPort-SDR: j2Q8935Rts0WvMAfAhyf18wtEUaDXsOEe8BgTLjrTv3IsIWUE/r0SFvERHEh4QZGeiKPK+MDRP WitFkgV7tH2dVqK65/c0n2a/fQplRcMsC7NNhD5fhZ1gE3I3FvbuZE5yWXcwZkas4xMPUZbxfd 0meSK/Pv/YPSUogXUZ4kJXr0PDueyZY8O8/T98ImcggDzsvWAKkdfX7nfoAhX0bhehpEj+aD8b 41/5VPyc7TjQrp9lAYB+zDcc86iJ8FUP6PcVesMNokSf7wAJE0yut1GOlGncjVa3ygoGYa+S0Z ZEM= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 23/35] target/riscv: Add hfence instructions Date: Fri, 31 Jan 2020 17:02:36 -0800 Message-Id: X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/insn32.decode | 23 ++++++----- .../riscv/insn_trans/trans_privileged.inc.c | 40 +++++++++++++++++++ 2 files changed, 54 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 77f794ed70..cfd9ca6d2b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -63,20 +63,25 @@ @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd @r2 ....... ..... ..... ... ..... ....... %rs1 %rd =20 +@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 +@hfence_bvma ....... ..... ..... ... ..... ....... %rs2 %rs1 + @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 @sfence_vm ....... ..... ..... ... ..... ....... %rs1 =20 =20 # *** Privileged Instructions *** -ecall 000000000000 00000 000 00000 1110011 -ebreak 000000000001 00000 000 00000 1110011 -uret 0000000 00010 00000 000 00000 1110011 -sret 0001000 00010 00000 000 00000 1110011 -hret 0010000 00010 00000 000 00000 1110011 -mret 0011000 00010 00000 000 00000 1110011 -wfi 0001000 00101 00000 000 00000 1110011 -sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma -sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm +ecall 000000000000 00000 000 00000 1110011 +ebreak 000000000001 00000 000 00000 1110011 +uret 0000000 00010 00000 000 00000 1110011 +sret 0001000 00010 00000 000 00000 1110011 +hret 0010000 00010 00000 000 00000 1110011 +mret 0011000 00010 00000 000 00000 1110011 +wfi 0001000 00101 00000 000 00000 1110011 +hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma +hfence_bvma 0010001 ..... ..... 000 00000 1110011 @hfence_bvma +sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma +sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm =20 # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/= insn_trans/trans_privileged.inc.c index c5e4b3e49a..b9b5a89b52 100644 --- a/target/riscv/insn_trans/trans_privileged.inc.c +++ b/target/riscv/insn_trans/trans_privileged.inc.c @@ -108,3 +108,43 @@ static bool trans_sfence_vm(DisasContext *ctx, arg_sfe= nce_vm *a) #endif return false; } + +static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) +{ +#ifndef CONFIG_USER_ONLY + if (ctx->priv_ver >=3D PRIV_VERSION_1_10_0 && + has_ext(ctx, RVH)) { + /* Hpervisor extensions exist */ + /* + * if (env->priv =3D=3D PRV_M || + * (env->priv =3D=3D PRV_S && + * !riscv_cpu_virt_enabled(env) && + * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { + */ + gen_helper_tlb_flush(cpu_env); + return true; + /* } */ + } +#endif + return false; +} + +static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a) +{ +#ifndef CONFIG_USER_ONLY + if (ctx->priv_ver >=3D PRIV_VERSION_1_10_0 && + has_ext(ctx, RVH)) { + /* Hpervisor extensions exist */ + /* + * if (env->priv =3D=3D PRV_M || + * (env->priv =3D=3D PRV_S && + * !riscv_cpu_virt_enabled(env) && + * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { + */ + gen_helper_tlb_flush(cpu_env); + return true; + /* } */ + } +#endif + return false; +} --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" The hret instruction does not exist in the new spec versions, so remove it from QEMU. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_privileged.inc.c | 5 ----- 2 files changed, 6 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index cfd9ca6d2b..b883672e63 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -75,7 +75,6 @@ ecall 000000000000 00000 000 00000 1110011 ebreak 000000000001 00000 000 00000 1110011 uret 0000000 00010 00000 000 00000 1110011 sret 0001000 00010 00000 000 00000 1110011 -hret 0010000 00010 00000 000 00000 1110011 mret 0011000 00010 00000 000 00000 1110011 wfi 0001000 00101 00000 000 00000 1110011 hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/= insn_trans/trans_privileged.inc.c index b9b5a89b52..76c2fad71c 100644 --- a/target/riscv/insn_trans/trans_privileged.inc.c +++ b/target/riscv/insn_trans/trans_privileged.inc.c @@ -58,11 +58,6 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) #endif } =20 -static bool trans_hret(DisasContext *ctx, arg_hret *a) -{ - return false; -} - static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580520189321536.3149356282499; Fri, 31 Jan 2020 17:23:09 -0800 (PST) Received: from localhost ([::1]:34618 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhV5-0006Kz-MQ for importer@patchew.org; Fri, 31 Jan 2020 20:23:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57139) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhIJ-0003uT-4j for qemu-devel@nongnu.org; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5b889a0065..aa04e5cca7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -332,7 +332,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState = *env, target_ulong *pc, #ifdef CONFIG_USER_ONLY *flags =3D TB_FLAGS_MSTATUS_FS; #else - *flags =3D cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); + *flags =3D cpu_mmu_index(env, 0); + if (riscv_cpu_fp_enabled(env)) { + *flags |=3D env->mstatus & MSTATUS_FS; + } #endif } =20 --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; 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IronPort-SDR: 9y38ktyTDgU+E+J2yMMKfIu7pbVw83QtnWVIjfj62+ty0PkmzR+viz0wLxssdrJyQTGv5F1g3B 1IMErmh/snHMgvpbyxk4uBRsqEwgdq5zoFUEAJvq8J//aKFgFAZ3WFzPBVhQmhL8kheQZzMvHZ shQDWj/c9h8aI3ffy++Ugzj2iQ32Tfqn6ayv7iRsuf5fszs5Wzaa9PkqSjLHUYzCRa4YWEv2DA 2ctMA995uzYhAMDxwHhTb31evLeUQYSmLyExV9k8FK/efVVQp4MAmf+3csDepSCY9EOzkYIa6D CSs= X-IronPort-AV: E=Sophos;i="5.70,388,1574092800"; d="scan'208";a="128872486" IronPort-SDR: M7nvFXEfisRLhi9RhGFdLHZ1F4BexyFo0zUyZkkUyhWGoAgMhZ27LcYTs6VYkDU/b6AJRtrUqb zxLfSpG1Ts9M9ETTZ7eOhrZvqR2F+eQzq8oiTdichuGJA8LzZEW29RJXSJ+6sW/qH5JFLATDUf QXg2j0Rp38lJgp5DyeqtraVyq1nMjwVKBxhJMHTHzxp2Ei7wnHj5bNeYrIq5NjnO5zTQke4Vpo TEL+RY7uFjRdKB/qM2v612Iq8HIzPd9Yabn8EBELhnhZFsMAinM1wTQQwjirw76bDVjK01zKR3 hk+X4B9iu0FU4/+Rvp4QNYWh IronPort-SDR: vzJ6EMeryOGQXVk4PbmP7LkX14j/9exVGiRcCApSy0sTS7LqjmKOkbVXKEotwAYdVnAPEwQzq2 dvKcPOUwo7fOkGmoKB2/98FU7HVG+JamwQhnvJhFli+xfBdUDuo1C/5KBxV+RGg5bOW+Ho4azz hfcY2NMKkv1x0lQeXnDIzRo/vmJdbCQOEnNxHMwHlcR0WoOefmAK/ImBoV8HL1U8pnRsKWLvyf 0uNnPannvO8Q4SIjqqp1tfi85bnF6J+YzyC9NnydvT3E56gqDbzm0WAQ+7qPxB21F4YeGh7Mrc Dtg= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 26/35] target/riscv: Disable guest FP support based on virtual status Date: Fri, 31 Jan 2020 17:02:44 -0800 Message-Id: X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" When the Hypervisor extension is in use we only enable floating point support when both status and vsstatus have enabled floating point support. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e7728cb0ca..827a38324c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -99,6 +99,9 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) bool riscv_cpu_fp_enabled(CPURISCVState *env) { if (env->mstatus & MSTATUS_FS) { + if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)= ) { + return false; + } return true; } =20 --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="128872487" IronPort-SDR: nVUMd2iwZrcFG1Mss0OQwccr/1sHwGpfD6nm4ao24hKfM3vxXdBSUeNsUPw5SZH56smAH7urVR vUwv9Ygu0cs4DTm4Nks0dVzIFTzV7C2YSOj9+Gw4m0L5hLORXTrwdWOnfA4fHqLOgkcJW1k2XY 5kVhcfJXxSRguavEkshNczu/qpwqkecAMjtSIdjt0MAaahYLd8NTdn3ScI0KPC8I4B+P9veRVQ tNF1WTwR5VG+Xrc2t0JNeGw4tr3f4qwXJAgpn8tfJtDxEBxTYvItgLOXG0agV6OQhoo/2QUA74 C/nCn5/jc7MW3H8LW7rEbVj4 IronPort-SDR: bv13Jda6InYd8lAhpCH3DKwvtQZwXOCA4wOn7jwq+y1ZbfCmAiC39vzsqM/mUkD7pSRNK9O+IK 9EEDi4tj8dzLQAv7QIlN8VpZ+JOTbmxiwMFbjlO4vi2tao7oLlww1jMr++ucQYgmUsjzjmwzxU z89I4Ldq7W2dVwuOzKOt5VSqpnBh72AvSf2/uW9/uPwewP7CgOe7j6Rw2zMKxuMaPVjH2Vm12B KAAsF+Bmv6ZnD1ZUu9hQ7wQuMhUjC05pVFzAV1THf7tu2NmS3Ui0NJs6n9t/ZVfmCZaTFbw6Jb ReQ= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 27/35] target/riscv: Mark both sstatus and msstatus_hs as dirty Date: Fri, 31 Jan 2020 17:02:46 -0800 Message-Id: <5f3b8fd9e9743c13fd9e40bf811303bc2937667a.1580518859.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Mark both sstatus and vsstatus as dirty (3). Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/translate.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index afa2d6eea2..61fe9f03be 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -44,6 +44,7 @@ typedef struct DisasContext { /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; target_ulong priv_ver; + bool virt_enabled; uint32_t opcode; uint32_t mstatus_fs; uint32_t misa; @@ -396,6 +397,12 @@ static void mark_fs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + + if (ctx->virt_enabled) { + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + } tcg_temp_free(tmp); } #else @@ -740,6 +747,11 @@ static void riscv_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->mem_idx =3D ctx->base.tb->flags & TB_FLAGS_MMU_MASK; ctx->mstatus_fs =3D ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; ctx->priv_ver =3D env->priv_ver; +#if !defined(CONFIG_USER_ONLY) + ctx->virt_enabled =3D riscv_cpu_virt_enabled(env); +#else + ctx->virt_enabled =3D false; +#endif ctx->misa =3D env->misa; ctx->frm =3D -1; /* unknown rounding mode */ ctx->ext_ifencei =3D cpu->cfg.ext_ifencei; --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" mark_fs_dirty() is the only place in translate.c that uses the virt_enabled bool. Let's respect the contents of MSTATUS.MPRV and HSTATUS.SPRV when setting the bool as this is used for performing floating point operations when V=3D0. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/translate.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 61fe9f03be..240fd7c971 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -748,7 +748,21 @@ static void riscv_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->mstatus_fs =3D ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; ctx->priv_ver =3D env->priv_ver; #if !defined(CONFIG_USER_ONLY) - ctx->virt_enabled =3D riscv_cpu_virt_enabled(env); + if (riscv_has_ext(env, RVH)) { + ctx->virt_enabled =3D riscv_cpu_virt_enabled(env); + if (env->priv_ver =3D=3D PRV_M && + get_field(env->mstatus, MSTATUS_MPRV) && + get_field(env->mstatus, MSTATUS_MPV)) { + ctx->virt_enabled =3D true; + } else if (env->priv =3D=3D PRV_S && + !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_SPRV) && + get_field(env->hstatus, HSTATUS_SPV)) { + ctx->virt_enabled =3D true; + } + } else { + ctx->virt_enabled =3D false; + } #else ctx->virt_enabled =3D false; #endif --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580520365846941.8424961236038; Fri, 31 Jan 2020 17:26:05 -0800 (PST) Received: from localhost ([::1]:34696 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhXu-0002Ga-Oo for importer@patchew.org; Fri, 31 Jan 2020 20:26:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57399) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhIy-0005Ai-Rn for qemu-devel@nongnu.org; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 37 ++++++++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 827a38324c..cd2d9341b9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -277,10 +277,19 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ul= ong newpriv) * * Adapted from Spike's mmu_t::translate and mmu_t::walk * + * @env: CPURISCVState + * @physical: This will be set to the calculated physical address + * @prot: The returned protection attributes + * @addr: The virtual address to be translated + * @access_type: The type of MMU access + * @mmu_idx: Indicates current privilege level + * @first_stage: Are we in first stage translation? + * Second stage is used for hypervisor guest translation */ static int get_physical_address(CPURISCVState *env, hwaddr *physical, int *prot, target_ulong addr, - int access_type, int mmu_idx) + int access_type, int mmu_idx, + bool first_stage) { /* NOTE: the env->pc value visible here will not be * correct, but the value visible to the exception handler @@ -483,13 +492,21 @@ restart: } =20 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, - MMUAccessType access_type, bool pmp_violat= ion) + MMUAccessType access_type, bool pmp_violat= ion, + bool first_stage) { CPUState *cs =3D env_cpu(env); - int page_fault_exceptions =3D - (env->priv_ver >=3D PRIV_VERSION_1_10_0) && - get_field(env->satp, SATP_MODE) !=3D VM_1_10_MBARE && - !pmp_violation; + int page_fault_exceptions; + if (first_stage) { + page_fault_exceptions =3D + (env->priv_ver >=3D PRIV_VERSION_1_10_0) && + get_field(env->satp, SATP_MODE) !=3D VM_1_10_MBARE && + !pmp_violation; + } else { + page_fault_exceptions =3D + get_field(env->hgatp, HGATP_MODE) !=3D VM_1_10_MBARE && + !pmp_violation; + } switch (access_type) { case MMU_INST_FETCH: cs->exception_index =3D page_fault_exceptions ? @@ -516,7 +533,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) int prot; int mmu_idx =3D cpu_mmu_index(&cpu->env, false); =20 - if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_id= x)) { + if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_id= x, + true)) { return -1; } return phys_addr; @@ -581,7 +599,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); =20 - ret =3D get_physical_address(env, &pa, &prot, address, access_type, mm= u_idx); + ret =3D get_physical_address(env, &pa, &prot, address, access_type, mm= u_idx, + true); =20 if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { if (get_field(env->mstatus, MSTATUS_MPRV)) { @@ -608,7 +627,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, } else if (probe) { return false; } else { - raise_mmu_exception(env, address, access_type, pmp_violation); + raise_mmu_exception(env, address, access_type, pmp_violation, true= ); riscv_raise_exception(env, cs->exception_index, retaddr); } #else --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="128872494" IronPort-SDR: kjjhJFtIgWbDGziuRiBzVeQd31kU67uIZDq07/mrO1EvvGNKhFtQgmMnRKbeAMzIQgjt0Jl5gq CgGgP9YVkpC46TYFv3SnQVhJ0mvnyPL848/2S1Xqa6f01axGmpsozdUTvTx6+Y5/gBr21yo44I tkUZQaaNYgjrvf7YfWMCOOAdTc0nAwQzQwlFz8ixTqENEde4+AbHI6q1gg50a4nO55mwIjlRlQ wZhXOakLr013Az376r+RKk2UWSv5XxUgCRR1vk8lR0l5Ka1aoTZz7UN027KmtRjVTS976pYUBt g6n4SsMYhiiDKh6jITsLD4FY IronPort-SDR: lL2On5/UrecP6izMnM5SmgTidlkhI1aU9Va9i1YPlhFGRFgCa3MO7sUZ2wGd6yozTCz1HG+u17 rp9kLmANAZzpOuo2rddiYF7HHW705e3YG/WXRXls/DupwuWJKQ9+zkcAjYcYnyzhuKZa9AArt9 m/N4MK8mE+4NqZv9ESPr2N2Oa4MTwQh89LfsbCvRn9qE4mk9hazxQYwICtLhdFhoFvgxNkz5aN LjOPfbhkX0CDAtHkmhChTKnp4WcY7SuT7EpHYeb6U814IVRN/s9+s+g/3sMlm0BkmoyXzSPypX +U0= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 30/35] target/riscv: Implement second stage MMU Date: Fri, 31 Jan 2020 17:02:56 -0800 Message-Id: <552ea58f47f89564da0d25851c3ac36937455c7f.1580518859.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 193 ++++++++++++++++++++++++++++++++++---- 2 files changed, 175 insertions(+), 19 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index aa04e5cca7..a8534fdf2b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -104,6 +104,7 @@ struct CPURISCVState { target_ulong frm; =20 target_ulong badaddr; + target_ulong guest_phys_fault_addr; =20 target_ulong priv_ver; target_ulong misa; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index cd2d9341b9..5f96631637 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -285,11 +285,12 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ul= ong newpriv) * @mmu_idx: Indicates current privilege level * @first_stage: Are we in first stage translation? * Second stage is used for hypervisor guest translation + * @two_stage: Are we going to perform two stage translation */ static int get_physical_address(CPURISCVState *env, hwaddr *physical, int *prot, target_ulong addr, int access_type, int mmu_idx, - bool first_stage) + bool first_stage, bool two_stage) { /* NOTE: the env->pc value visible here will not be * correct, but the value visible to the exception handler @@ -297,13 +298,40 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, MemTxResult res; MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; int mode =3D mmu_idx; + bool use_background =3D false; =20 + /* + * Check if we should use the background registers for the two + * stage translation. We don't need to check if we actually need + * two stage translation as that happened before this function + * was called. Background registers will be used if the guest has + * forced a two stage translation to be on (in HS or M mode). + */ if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { if (get_field(env->mstatus, MSTATUS_MPRV)) { mode =3D get_field(env->mstatus, MSTATUS_MPP); + + if (riscv_has_ext(env, RVH) && + get_field(env->mstatus, MSTATUS_MPV)) { + use_background =3D true; + } + } + } + + if (mode =3D=3D PRV_S && access_type !=3D MMU_INST_FETCH && + riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { + if (get_field(env->hstatus, HSTATUS_SPRV)) { + mode =3D get_field(env->mstatus, SSTATUS_SPP); + use_background =3D true; } } =20 + if (first_stage =3D=3D false) { + /* We are in stage 2 translation, this is similar to stage 1. */ + /* Stage 2 is always taken as U-mode */ + mode =3D PRV_U; + } + if (mode =3D=3D PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { *physical =3D addr; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -313,13 +341,30 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, *prot =3D 0; =20 hwaddr base; - int levels, ptidxbits, ptesize, vm, sum; - int mxr =3D get_field(env->mstatus, MSTATUS_MXR); + int levels, ptidxbits, ptesize, vm, sum, mxr, widened; + + if (first_stage =3D=3D true) { + mxr =3D get_field(env->mstatus, MSTATUS_MXR); + } else { + mxr =3D get_field(env->vsstatus, MSTATUS_MXR); + } =20 if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { - base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; + if (first_stage =3D=3D true) { + if (use_background) { + base =3D (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIF= T; + vm =3D get_field(env->vsatp, SATP_MODE); + } else { + base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; + vm =3D get_field(env->satp, SATP_MODE); + } + widened =3D 0; + } else { + base =3D (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT; + vm =3D get_field(env->hgatp, HGATP_MODE); + widened =3D 2; + } sum =3D get_field(env->mstatus, MSTATUS_SUM); - vm =3D get_field(env->satp, SATP_MODE); switch (vm) { case VM_1_10_SV32: levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; @@ -337,6 +382,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, g_assert_not_reached(); } } else { + widened =3D 0; base =3D (hwaddr)(env->sptbr) << PGSHIFT; sum =3D !get_field(env->mstatus, MSTATUS_PUM); vm =3D get_field(env->mstatus, MSTATUS_VM); @@ -357,9 +403,16 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, } =20 CPUState *cs =3D env_cpu(env); - int va_bits =3D PGSHIFT + levels * ptidxbits; - target_ulong mask =3D (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; - target_ulong masked_msbs =3D (addr >> (va_bits - 1)) & mask; + int va_bits =3D PGSHIFT + levels * ptidxbits + widened; + target_ulong mask, masked_msbs; + + if (TARGET_LONG_BITS > (va_bits - 1)) { + mask =3D (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; + } else { + mask =3D 0; + } + masked_msbs =3D (addr >> (va_bits - 1)) & mask; + if (masked_msbs !=3D 0 && masked_msbs !=3D mask) { return TRANSLATE_FAIL; } @@ -371,11 +424,29 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, restart: #endif for (i =3D 0; i < levels; i++, ptshift -=3D ptidxbits) { - target_ulong idx =3D (addr >> (PGSHIFT + ptshift)) & + target_ulong idx; + if (i =3D=3D 0) { + idx =3D (addr >> (PGSHIFT + ptshift)) & + ((1 << (ptidxbits + widened)) - 1); + } else { + idx =3D (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1); + } =20 /* check that physical address of PTE is legal */ - hwaddr pte_addr =3D base + idx * ptesize; + hwaddr pte_addr; + + if (two_stage && first_stage) { + hwaddr vbase; + + /* Do the second stage translation on the base PTE address. */ + get_physical_address(env, &vbase, prot, base, access_type, + mmu_idx, false, true); + + pte_addr =3D vbase + idx * ptesize; + } else { + pte_addr =3D base + idx * ptesize; + } =20 if (riscv_feature(env, RISCV_FEATURE_PMP) && !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), @@ -472,7 +543,12 @@ restart: /* for superpage mappings, make a fake leaf PTE for the TLB's benefit. */ target_ulong vpn =3D addr >> PGSHIFT; - *physical =3D (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; + if (i =3D=3D 0) { + *physical =3D (ppn | (vpn & ((1L << (ptshift + widened)) -= 1))) << + PGSHIFT; + } else { + *physical =3D (ppn | (vpn & ((1L << ptshift) - 1))) << PGS= HIFT; + } =20 /* set permissions on the TLB entry */ if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { @@ -529,14 +605,23 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; hwaddr phys_addr; int prot; int mmu_idx =3D cpu_mmu_index(&cpu->env, false); =20 - if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_id= x, - true)) { + if (get_physical_address(env, &phys_addr, &prot, addr, 0, mmu_idx, + true, riscv_cpu_virt_enabled(env))) { return -1; } + + if (riscv_cpu_virt_enabled(env)) { + if (get_physical_address(env, &phys_addr, &prot, phys_addr, + 0, mmu_idx, false, true)) { + return -1; + } + } + return phys_addr; } =20 @@ -590,17 +675,37 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; #ifndef CONFIG_USER_ONLY + vaddr im_address; hwaddr pa =3D 0; int prot; bool pmp_violation =3D false; + bool m_mode_two_stage =3D false; + bool hs_mode_two_stage =3D false; + bool first_stage_error =3D true; int ret =3D TRANSLATE_FAIL; int mode =3D mmu_idx; =20 + env->guest_phys_fault_addr =3D 0; + qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); =20 - ret =3D get_physical_address(env, &pa, &prot, address, access_type, mm= u_idx, - true); + /* + * Determine if we are in M mode and MPRV is set or in HS mode and SPR= V is + * set and we want to access a virtulisation address. + */ + if (riscv_has_ext(env, RVH)) { + m_mode_two_stage =3D env->priv =3D=3D PRV_M && + access_type !=3D MMU_INST_FETCH && + get_field(env->mstatus, MSTATUS_MPRV) && + get_field(env->mstatus, MSTATUS_MPV); + + hs_mode_two_stage =3D env->priv =3D=3D PRV_S && + !riscv_cpu_virt_enabled(env) && + access_type !=3D MMU_INST_FETCH && + get_field(env->hstatus, HSTATUS_SPRV) && + get_field(env->hstatus, HSTATUS_SPV); + } =20 if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { if (get_field(env->mstatus, MSTATUS_MPRV)) { @@ -608,9 +713,55 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } } =20 - qemu_log_mask(CPU_LOG_MMU, - "%s address=3D%" VADDR_PRIx " ret %d physical " TARGET_F= MT_plx - " prot %d\n", __func__, address, ret, pa, prot); + if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_sta= ge) { + /* Two stage lookup */ + ret =3D get_physical_address(env, &pa, &prot, address, access_type, + mmu_idx, true, true); + + qemu_log_mask(CPU_LOG_MMU, + "%s 1st-stage address=3D%" VADDR_PRIx " ret %d physi= cal " + TARGET_FMT_plx " prot %d\n", + __func__, address, ret, pa, prot); + + if (ret !=3D TRANSLATE_FAIL) { + /* Second stage lookup */ + im_address =3D pa; + + ret =3D get_physical_address(env, &pa, &prot, im_address, + access_type, mmu_idx, false, true); + + qemu_log_mask(CPU_LOG_MMU, + "%s 2nd-stage address=3D%" VADDR_PRIx " ret %d physica= l " + TARGET_FMT_plx " prot %d\n", + __func__, im_address, ret, pa, prot); + + if (riscv_feature(env, RISCV_FEATURE_PMP) && + (ret =3D=3D TRANSLATE_SUCCESS) && + !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)= ) { + ret =3D TRANSLATE_PMP_FAIL; + } + + if (ret !=3D TRANSLATE_SUCCESS) { + /* + * Guest physical address translation failed, this is a HS + * level exception + */ + first_stage_error =3D false; + env->guest_phys_fault_addr =3D (im_address | + (address & + (TARGET_PAGE_SIZE - 1))) >>= 2; + } + } + } else { + /* Single stage lookup */ + ret =3D get_physical_address(env, &pa, &prot, address, access_type, + mmu_idx, true, false); + + qemu_log_mask(CPU_LOG_MMU, + "%s address=3D%" VADDR_PRIx " ret %d physical " + TARGET_FMT_plx " prot %d\n", + __func__, address, ret, pa, prot); + } =20 if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret =3D=3D TRANSLATE_SUCCESS) && @@ -620,6 +771,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, if (ret =3D=3D TRANSLATE_PMP_FAIL) { pmp_violation =3D true; } + if (ret =3D=3D TRANSLATE_SUCCESS) { tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); @@ -627,9 +779,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } else if (probe) { return false; } else { - raise_mmu_exception(env, address, access_type, pmp_violation, true= ); + raise_mmu_exception(env, address, access_type, pmp_violation, firs= t_stage_error); riscv_raise_exception(env, cs->exception_index, retaddr); } + + return true; + #else switch (access_type) { case MMU_INST_FETCH: --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580520470023174.33003940969354; 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d="scan'208";a="128872496" IronPort-SDR: 7+zEhE5I2GKWVfw58fdXyolLOEOlJynnolLx74CscgK4Wax1IOtg/LXZILObgsiv/w2wpfi2oX OHtKWZJKAv7/CNPKQOotBpdItrfn8htRX6Bl3P0qq0zf8xovuvyt18N99Lx/dNgeobxupeT/oZ Xbau8t6Me1TCVmNsyI9sGNhQJwnLeoVB0HAg6I5DF4M/QMuyUIJPiKNr17Qh/Gpwao7k1b/m76 5N88AIG/6euawCuAeYSlug3rGRK8WwvfE4gRDbnS1V25jTRwnXGuA3ZMRQhPehpE1pu+64iDRh XEe0NhBGtCmecnfsQ4m8oOIJ IronPort-SDR: feceoVqIxADoaF8zJpF9lyUTvldpwBe8TsrWS78fBT8PPH2DAZg5O7iGgPaxa121bBZMnXt+ia Om53I7gnGNSNkDLw/BSwa47BFRaAZ6m/ERH91aPo9PkEsdqO7kolDHDafBXbKsYBMpAiCqWrVf rsjcdqsjpgfbBeIQQ/j30r1zTyYqAT5OSVLPtiA05m7THF57UPs0B50GaEyDqKpNz2S4mg/0ux HWO56DyZGcB/yzmBBepn+0PWh9Zj1Hh44sz0DAi2g3aYjCL5xccNXs/3b0hux2vvBgcrscGluk nIU= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 31/35] target/riscv: Raise the new execptions when 2nd stage translation fails Date: Fri, 31 Jan 2020 17:02:59 -0800 Message-Id: X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5f96631637..da994aba57 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -585,16 +585,28 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, } switch (access_type) { case MMU_INST_FETCH: - cs->exception_index =3D page_fault_exceptions ? - RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; + if (riscv_cpu_virt_enabled(env) && !first_stage) { + cs->exception_index =3D RISCV_EXCP_INST_GUEST_PAGE_FAULT; + } else { + cs->exception_index =3D page_fault_exceptions ? + RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; + } break; case MMU_DATA_LOAD: - cs->exception_index =3D page_fault_exceptions ? - RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; + if (riscv_cpu_virt_enabled(env) && !first_stage) { + cs->exception_index =3D RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; + } else { + cs->exception_index =3D page_fault_exceptions ? + RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; + } break; case MMU_DATA_STORE: - cs->exception_index =3D page_fault_exceptions ? - RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAUL= T; + if (riscv_cpu_virt_enabled(env) && !first_stage) { + cs->exception_index =3D RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAUL= T; + } else { + cs->exception_index =3D page_fault_exceptions ? + RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_= FAULT; + } break; default: g_assert_not_reached(); --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="128872499" IronPort-SDR: Pt3D6p+GmjM75jQI4ai8l0Z4Gmymc7s1o3XP+OZ4HiBa3Ip7v7PN0MqcdMlEm4MODflYqzMkPu 2SkZpOyxjS6eCy7EnCzBlPFcwSfm80o5qxG3yfS/FefCOcqHq/VmfcfnHoF0Rh4bTIPJYb5Zy0 4f3oeo7gVuzSRaAKocKDev/dt/noZ72dXXUAOqB+K8UbkcDMhIN511hUPdfD+/rTnZPeqFhQoi JbxrmdjCVEAeSqAUJfr1kXSQHGkc+RKcFylTAcvR5uCW4aq0bV7CZcubaYKCX9GsTScBl9GNI7 QzN1BWjZZEwW6N5xMNr3pHLc IronPort-SDR: imcKPQhyu3eFmCE8fuYvDaaG6ycdkrX3Iq3D7+zlnc+wn3F08PuP5vRpOLCXpA7gYNWvIs66iV q6R6QCEZiqcirDueV4sEyBN4ZlqO2Fwtzrc16ErT3KKcei9jvvQNBZp3AaVbVtiZs/3YD2UcBv IMhEMKKprRdnWSpgSS6tFIKwC3Dy0oUyZcP/T20RUoPYtOV1vCwiFA6n+Rdq3h0QhTAFbQ/RNR 3qS25ZMyZclMc+2NnwywBJZyQi5PMsD+bPBx1xJJZH6VITYEARu9AF0CY6Zhka4uwQcEi5474d cXA= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 32/35] target/riscv: Set htval and mtval2 on execptions Date: Fri, 31 Jan 2020 17:03:02 -0800 Message-Id: <6b6d0f06b64cc5d0a6ed6fe9357eb8c6d01c5d48.1580518859.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index da994aba57..10786a077b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -838,6 +838,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; target_ulong deleg =3D async ? env->mideleg : env->medeleg; target_ulong tval =3D 0; + target_ulong htval =3D 0; + target_ulong mtval2 =3D 0; =20 if (!async) { /* set tval to badaddr for traps with address information */ @@ -899,6 +901,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); =20 + htval =3D env->guest_phys_fault_addr; + riscv_cpu_set_virt_enabled(env, 0); riscv_cpu_set_force_hs_excep(env, 0); } else { @@ -909,6 +913,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) get_field(env->mstatus, SSTATUS_S= PP)); env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); + + htval =3D env->guest_phys_fault_addr; } } =20 @@ -921,6 +927,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->scause =3D cause | ((target_ulong)async << (TARGET_LONG_BITS = - 1)); env->sepc =3D env->pc; env->sbadaddr =3D tval; + env->htval =3D htval; env->pc =3D (env->stvec >> 2 << 2) + ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_S); @@ -935,6 +942,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mstatus =3D set_field(env->mstatus, MSTATUS_MTL, riscv_cpu_force_hs_excep_enabled(env= )); =20 + mtval2 =3D env->guest_phys_fault_addr; + /* Trapping to M mode, virt is disabled */ riscv_cpu_set_virt_enabled(env, 0); riscv_cpu_set_force_hs_excep(env, 0); @@ -949,6 +958,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mcause =3D cause | ~(((target_ulong)-1) >> async); env->mepc =3D env->pc; env->mbadaddr =3D tval; + env->mtval2 =3D mtval2; env->pc =3D (env->mtvec >> 2 << 2) + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M); --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158052054920878.48553339072748; Fri, 31 Jan 2020 17:29:09 -0800 (PST) Received: from localhost ([::1]:34760 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhat-00060w-W2 for importer@patchew.org; Fri, 31 Jan 2020 20:29:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57533) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixhJL-0005Zs-8B for qemu-devel@nongnu.org; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 3 +++ target/riscv/cpu.h | 10 ++++++++++ target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_helper.c | 17 +++++++++++++++++ target/riscv/csr.c | 25 +++++++++++++++++++++++++ target/riscv/op_helper.c | 4 ++++ 6 files changed, 62 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 44ad768a84..b27066f6a7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -237,6 +237,9 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); +#ifdef TARGET_RISCV32 + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush); +#endif if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatu= s); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vssta= tus); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a8534fdf2b..6f9c29322a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -127,6 +127,10 @@ struct CPURISCVState { =20 target_ulong mip; =20 +#ifdef TARGET_RISCV32 + target_ulong mstatush; +#endif + uint32_t miclaim; =20 target_ulong mie; @@ -164,6 +168,9 @@ struct CPURISCVState { target_ulong vscause; target_ulong vstval; target_ulong vsatp; +#ifdef TARGET_RISCV32 + target_ulong vsstatush; +#endif =20 target_ulong mtval2; target_ulong mtinst; @@ -176,6 +183,9 @@ struct CPURISCVState { target_ulong stval_hs; target_ulong satp_hs; target_ulong mstatus_hs; +#ifdef TARGET_RISCV32 + target_ulong mstatush_hs; +#endif =20 target_ulong scounteren; target_ulong mcounteren; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a24654d137..049032f2ae 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -135,6 +135,9 @@ #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 =20 +/* 32-bit only */ +#define CSR_MSTATUSH 0x310 + /* Legacy Counter Setup (priv v1.9.1) */ /* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */ #define CSR_MUCOUNTEREN 0x320 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 10786a077b..e04545adf7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -126,6 +126,11 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) env->mstatus &=3D ~mstatus_mask; env->mstatus |=3D env->mstatus_hs; =20 +#if defined(TARGET_RISCV32) + env->vsstatush =3D env->mstatush; + env->mstatush |=3D env->mstatush_hs; +#endif + env->vstvec =3D env->stvec; env->stvec =3D env->stvec_hs; =20 @@ -149,6 +154,11 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) env->mstatus &=3D ~mstatus_mask; env->mstatus |=3D env->vsstatus; =20 +#if defined(TARGET_RISCV32) + env->mstatush_hs =3D env->mstatush; + env->mstatush |=3D env->vsstatush; +#endif + env->stvec_hs =3D env->stvec; env->stvec =3D env->vstvec; =20 @@ -937,10 +947,17 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_cpu_virt_enabled(env)) { riscv_cpu_swap_hypervisor_regs(env); } +#ifdef TARGET_RISCV32 + env->mstatush =3D set_field(env->mstatush, MSTATUS_MPV, + riscv_cpu_virt_enabled(env)); + env->mstatush =3D set_field(env->mstatush, MSTATUS_MTL, + riscv_cpu_force_hs_excep_enabled(en= v)); +#else env->mstatus =3D set_field(env->mstatus, MSTATUS_MPV, riscv_cpu_virt_enabled(env)); env->mstatus =3D set_field(env->mstatus, MSTATUS_MTL, riscv_cpu_force_hs_excep_enabled(env= )); +#endif =20 mtval2 =3D env->guest_phys_fault_addr; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 2e6700bbeb..572a478e8c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -371,6 +371,27 @@ static int write_mstatus(CPURISCVState *env, int csrno= , target_ulong val) return 0; } =20 +#ifdef TARGET_RISCV32 +static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mstatush; + return 0; +} + +static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val) +{ + if ((val ^ env->mstatush) & (MSTATUS_MPV)) { + tlb_flush(env_cpu(env)); + } + + val &=3D MSTATUS_MPV | MSTATUS_MTL; + + env->mstatush =3D val; + + return 0; +} +#endif + static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) { *val =3D env->misa; @@ -1214,6 +1235,10 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D { [CSR_MTVEC] =3D { any, read_mtvec, write_mtvec = }, [CSR_MCOUNTEREN] =3D { any, read_mcounteren, write_mcounter= en }, =20 +#if defined(TARGET_RISCV32) + [CSR_MSTATUSH] =3D { any, read_mstatush, write_mstatush= }, +#endif + /* Legacy Counter Setup (priv v1.9.1) */ [CSR_MUCOUNTEREN] =3D { any, read_mucounteren, write_mucounte= ren }, [CSR_MSCOUNTEREN] =3D { any, read_mscounteren, write_mscounte= ren }, diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 804936e9d5..dca68fa96e 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -153,7 +153,11 @@ target_ulong helper_mret(CPURISCVState *env, target_ul= ong cpu_pc_deb) get_field(mstatus, MSTATUS_MPIE)); mstatus =3D set_field(mstatus, MSTATUS_MPIE, 1); mstatus =3D set_field(mstatus, MSTATUS_MPP, PRV_U); +#ifdef TARGET_RISCV32 + env->mstatush =3D set_field(env->mstatush, MSTATUS_MPV, 0); +#else mstatus =3D set_field(mstatus, MSTATUS_MPV, 0); +#endif env->mstatus =3D mstatus; riscv_cpu_set_mode(env, prev_priv); =20 --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580520102913160.24109268438076; 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d="scan'208";a="128872502" IronPort-SDR: UvToYaJt0SUlVi4jhMBu2Qp53gPgovdhr1hCn/zMNBURMjbU8/9AJ7I0U+u64JkuZy4Tg0BeDQ pKkRi9uATstkiAcJBuU0YMR7tMxwfLVaLKhKR1I1fp2WiwnWwwdTT9a32X5zpp7F063Z6lq6Ra vKqAThM3z5qMOOVuI8uVQOZWfx5lzDpo5JSd/VC6AUvvbm/Wk5eIc2gcSBFWej8ceMqnYKTqOk LvYndneo8vR6ZekEKyu5vVpKij3i0U30Cz0P8lD1Ob/LF1CcwaPqdvcoJZdvGaAkXyIue0a7fI 0mq+y1+/SFlDA+hCeuNPdqlV IronPort-SDR: g7O3Wgu2kCXv6qIvc2W1102glPZ4yrdZS4eJBjHKzoA52EgVDdftNHfMu+vH9ZCmD+YEsyJU2o MQaGosWPXyd3/3cYdnCDT71lXjWMoszprJp/ptY+zgdPbabrhXow8xVB2XePQBqcfZxcqbAPuj wTh5h96bgN4LK1LZOOhLIP4kZYMUBoLmtKpCJkjF/kD5SwW/59E0Ho+++j+wIBnKmjFEO1LaiY 8t/JviT/W1CqRYAV5rr4FIbHRxjUfjJ2zrOWdU34H8Y/Ym7bA/IqSOwGf+zl5tNwO0m2axXa7j +V8= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 34/35] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Date: Fri, 31 Jan 2020 17:03:08 -0800 Message-Id: X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add a helper macro MSTATUS_MPV_ISSET() which will determine if the MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 11 +++++++++++ target/riscv/cpu_helper.c | 4 ++-- target/riscv/op_helper.c | 2 +- target/riscv/translate.c | 2 +- 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 049032f2ae..7f64ee1174 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -363,8 +363,19 @@ #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ +#if defined(TARGET_RISCV64) #define MSTATUS_MTL 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL +#elif defined(TARGET_RISCV32) +#define MSTATUS_MTL 0x00000040 +#define MSTATUS_MPV 0x00000080 +#endif + +#ifdef TARGET_RISCV32 +# define MSTATUS_MPV_ISSET(env) get_field(env->mstatush, MSTATUS_MPV) +#else +# define MSTATUS_MPV_ISSET(env) get_field(env->mstatus, MSTATUS_MPV) +#endif =20 #define MSTATUS64_UXL 0x0000000300000000ULL #define MSTATUS64_SXL 0x0000000C00000000ULL diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e04545adf7..b9e90dfd9a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -322,7 +322,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, mode =3D get_field(env->mstatus, MSTATUS_MPP); =20 if (riscv_has_ext(env, RVH) && - get_field(env->mstatus, MSTATUS_MPV)) { + MSTATUS_MPV_ISSET(env)) { use_background =3D true; } } @@ -720,7 +720,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, m_mode_two_stage =3D env->priv =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV) && - get_field(env->mstatus, MSTATUS_MPV); + MSTATUS_MPV_ISSET(env); =20 hs_mode_two_stage =3D env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env) && diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index dca68fa96e..8736f689c2 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -146,7 +146,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) =20 target_ulong mstatus =3D env->mstatus; target_ulong prev_priv =3D get_field(mstatus, MSTATUS_MPP); - target_ulong prev_virt =3D get_field(mstatus, MSTATUS_MPV); + target_ulong prev_virt =3D MSTATUS_MPV_ISSET(env); mstatus =3D set_field(mstatus, env->priv_ver >=3D PRIV_VERSION_1_10_0 ? MSTATUS_MIE : MSTATUS_UIE << prev_priv, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 240fd7c971..ae8818efb3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -752,7 +752,7 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->virt_enabled =3D riscv_cpu_virt_enabled(env); if (env->priv_ver =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_MPRV) && - get_field(env->mstatus, MSTATUS_MPV)) { + MSTATUS_MPV_ISSET(env)) { ctx->virt_enabled =3D true; } else if (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env) && --=20 2.25.0 From nobody Mon May 6 13:18:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 5 +++++ target/riscv/cpu.h | 1 + 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b27066f6a7..c47d10b739 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -453,6 +453,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) if (cpu->cfg.ext_u) { target_misa |=3D RVU; } + if (cpu->cfg.ext_h) { + target_misa |=3D RVH; + } =20 set_misa(env, RVXLEN | target_misa); } @@ -488,6 +491,8 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), + /* This is experimental so mark with 'x-' */ + DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6f9c29322a..d52f209361 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -258,6 +258,7 @@ typedef struct RISCVCPU { bool ext_c; bool ext_s; bool ext_u; + bool ext_h; bool ext_counters; bool ext_ifencei; bool ext_icsr; --=20 2.25.0