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charset="utf-8" On reset only a single L2 cache way is enabled, the others are exposed as memory that can be used by early boot firmware. This L2 region is generally disabled using the WayEnable register at a later stage in the boot process. To allow firmware to target QEMU and the HiFive Unleashed let's add the L2 LIM (LooselyIntegrated Memory). Ideally we would want to adjust the size of this chunk of memory as the L2 Cache Controller WayEnable register is incremented. Unfortunately I don't see a nice way to handle reducing or blocking out the L2 LIM while still allowing it be re returned to all enabled from a reset. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/sifive_u.c | 16 ++++++++++++++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 17 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9f8e84bf2e..1d255ad13e 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -65,6 +65,7 @@ static const struct MemmapEntry { [SIFIVE_U_DEBUG] =3D { 0x0, 0x100 }, [SIFIVE_U_MROM] =3D { 0x1000, 0x11000 }, [SIFIVE_U_CLINT] =3D { 0x2000000, 0x10000 }, + [SIFIVE_U_L2LIM] =3D { 0x8000000, 0x2000000 }, [SIFIVE_U_PLIC] =3D { 0xc000000, 0x4000000 }, [SIFIVE_U_PRCI] =3D { 0x10000000, 0x1000 }, [SIFIVE_U_UART0] =3D { 0x10010000, 0x1000 }, @@ -431,6 +432,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev= , Error **errp) const struct MemmapEntry *memmap =3D sifive_u_memmap; MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *l2lim_mem =3D g_new(MemoryRegion, 1); qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; char *plic_hart_config; size_t plic_hart_config_len; @@ -459,6 +461,20 @@ static void riscv_sifive_u_soc_realize(DeviceState *de= v, Error **errp) memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, mask_rom); =20 + /* + * Add L2-LIM at reset size. + * This should be reduced in size as the L2 Cache Controller WayEnable + * register is incremented. Unfortunately I don't see a nice (or any) = way + * to handle reducing or blocking out the L2 LIM while still allowing = it + * be re returned to all enabled after a reset. For the time being, ju= st + * leave it enabled all the time. This won't break anything, but will = be + * too generous to misbehaving guests. + */ + memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", + memmap[SIFIVE_U_L2LIM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base, + l2lim_mem); + /* create PLIC hart topology configuration string */ plic_hart_config_len =3D (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * ms->smp.cpus; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index e4df298c23..50e3620c02 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -58,6 +58,7 @@ enum { SIFIVE_U_DEBUG, SIFIVE_U_MROM, SIFIVE_U_CLINT, + SIFIVE_U_L2LIM, SIFIVE_U_PLIC, SIFIVE_U_PRCI, SIFIVE_U_UART0, --=20 2.23.0 From nobody Wed Nov 12 08:31:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" The HiFive Unleashed uses is25wp256 SPI NOR flash. There is currently no model of this in QEMU, so to allow boot firmware developers to use QEMU to target the Unleashed let's add a chunk of memory to represent the QSPI0 memory mapped flash. This can be targeted using QEMU's -device loader command line option. In the future we can look at adding a model for the is25wp256 flash. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/sifive_u.c | 8 ++++++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 9 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 1d255ad13e..bc0e01242b 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -71,6 +71,7 @@ static const struct MemmapEntry { [SIFIVE_U_UART0] =3D { 0x10010000, 0x1000 }, [SIFIVE_U_UART1] =3D { 0x10011000, 0x1000 }, [SIFIVE_U_OTP] =3D { 0x10070000, 0x1000 }, + [SIFIVE_U_FLASH0] =3D { 0x20000000, 0x10000000 }, [SIFIVE_U_DRAM] =3D { 0x80000000, 0x0 }, [SIFIVE_U_GEM] =3D { 0x10090000, 0x2000 }, [SIFIVE_U_GEM_MGMT] =3D { 0x100a0000, 0x1000 }, @@ -313,6 +314,7 @@ static void riscv_sifive_u_init(MachineState *machine) SiFiveUState *s =3D g_new0(SiFiveUState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); + MemoryRegion *flash0 =3D g_new(MemoryRegion, 1); int i; =20 /* Initialize SoC */ @@ -328,6 +330,12 @@ static void riscv_sifive_u_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, main_mem); =20 + /* register QSPI0 Flash */ + memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", + memmap[SIFIVE_U_FLASH0].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].bas= e, + flash0); + /* create device tree */ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 50e3620c02..2a08e2a5db 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -64,6 +64,7 @@ enum { SIFIVE_U_UART0, SIFIVE_U_UART1, SIFIVE_U_OTP, + SIFIVE_U_FLASH0, SIFIVE_U_DRAM, SIFIVE_U_GEM, SIFIVE_U_GEM_MGMT --=20 2.23.0 From nobody Wed Nov 12 08:31:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; 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charset="utf-8" Instead of using the DEFINE_MACHINE() macro to define the machine let's do it manually. This allows us to specify machine properties. This patch is no functional change. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/riscv/sifive_u.c | 44 ++++++++++++++++++++++++++----------- include/hw/riscv/sifive_u.h | 7 +++++- 2 files changed, 37 insertions(+), 14 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index bc0e01242b..f5741e9a38 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -310,8 +310,7 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, static void riscv_sifive_u_init(MachineState *machine) { const struct MemmapEntry *memmap =3D sifive_u_memmap; - - SiFiveUState *s =3D g_new0(SiFiveUState, 1); + SiFiveUState *s =3D RISCV_U_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *flash0 =3D g_new(MemoryRegion, 1); @@ -433,6 +432,10 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_CADENCE_GEM); } =20 +static void riscv_sifive_u_machine_instance_init(Object *obj) +{ +} + static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); @@ -546,17 +549,6 @@ static void riscv_sifive_u_soc_realize(DeviceState *de= v, Error **errp) memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); } =20 -static void riscv_sifive_u_machine_init(MachineClass *mc) -{ - mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; - mc->init =3D riscv_sifive_u_init; - mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; - mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; - mc->default_cpus =3D mc->min_cpus; -} - -DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) - static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -580,3 +572,29 @@ static void riscv_sifive_u_soc_register_types(void) } =20 type_init(riscv_sifive_u_soc_register_types) + +static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; + mc->init =3D riscv_sifive_u_init; + mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; + mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; + mc->default_cpus =3D mc->min_cpus; +} + +static const TypeInfo riscv_sifive_u_machine_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("sifive_u"), + .parent =3D TYPE_MACHINE, + .class_init =3D riscv_sifive_u_machine_class_init, + .instance_init =3D riscv_sifive_u_machine_instance_init, + .instance_size =3D sizeof(SiFiveUState), +}; + +static void riscv_sifive_u_machine_init_register_types(void) +{ + type_register_static(&riscv_sifive_u_machine_typeinfo); +} + +type_init(riscv_sifive_u_machine_init_register_types) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 2a08e2a5db..a921079fbe 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -44,12 +44,17 @@ typedef struct SiFiveUSoCState { CadenceGEMState gem; } SiFiveUSoCState; =20 +#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") +#define RISCV_U_MACHINE(obj) \ + OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE) + typedef struct SiFiveUState { /*< private >*/ - SysBusDevice parent_obj; + MachineState parent_obj; =20 /*< public >*/ SiFiveUSoCState soc; + void *fdt; int fdt_size; } SiFiveUState; --=20 2.23.0 From nobody Wed Nov 12 08:31:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1569545737; cv=none; d=zoho.com; s=zohoarc; b=RvUXNHK1zkDmoJNpcMTENjxkgtnq4yKBcRLmFBw1Mpdu+gSbEi2E0PMTJ5b0Uo9T6QCaGzVKT0PZP04S5197Yox8VJrKdTLI3fkfoGRy1JMgTTRE5ONlmnZ2vhVungERWJaWlVTuAQLCILQemjY9cVUuDbhZg39lyplcVovv21k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; 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d="scan'208";a="119225548" IronPort-SDR: vouyPs3nx8JtSswKza0z3A9Izax2/uKqg+oFP2EVyvkU9yfODw1oIstU7ahWgfctjdVr18WSDO 7VGid4ANkxQeeAQt5h5Hmb03GMAV08xnw7I7B9bbMQjFAZFCtp+78A5HYnmu7rUXHKaUKUHnzg 99TDkZWn+bBeC2nwwISU1L0h0/3/oc9sDpN9FdHWcFBxqW16kZhNLHpEqzqEWoS0xt2RHR7E9d CJ8Kis6OUtj41cApEG6a2sBFTVdFfkbB5zIaE+xsy+kfU0dqNz2L3mRhjcRE8OoFi7cfNuzImk zRxXokvJWuomWnIHHxYtMdYu IronPort-SDR: yaymgfAkUFI9xagzkVpt6a2njHihlu3bLi3ptod/B3TkQj4Gqy55IesYp69db13Y9XZVgt/TYC j3ZpOmPVKehpkW7XCnTXLfIqFwLYd8AIulLcLRPSYxkOm6yD6Z9gftHrRnHpOahCydGzXBAs6/ G0cvb45cvwQNOw/stUhNPqjC9iyQwBxH0YXMnEQgJcRC++TzYFYcX2T/3oVIBM5TuJxaoZh4A2 JhBA0EVkoBIXnKlNr5gkZrYxBOj7NHr4BREgKGjZ0CDf55KrtxBPZ/NqOjYhEyO7jrG7e3u9yV SlQ= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property Date: Thu, 26 Sep 2019 17:44:28 -0700 Message-Id: X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add a property that when set to true QEMU will jump from the ROM code to the start of flash memory instead of DRAM which is the default behaviour. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++++++ include/hw/riscv/sifive_u.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index f5741e9a38..33b55d0d5b 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -373,6 +373,10 @@ static void riscv_sifive_u_init(MachineState *machine) /* dtb: */ }; =20 + if (s->start_in_flash) { + reset_vec[6] =3D memmap[SIFIVE_U_FLASH0].base; /* start: .dword FL= ASH0_BASE */ + } + /* copy in the reset vector in little_endian byte order */ for (i =3D 0; i < sizeof(reset_vec) >> 2; i++) { reset_vec[i] =3D cpu_to_le32(reset_vec[i]); @@ -432,8 +436,31 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_CADENCE_GEM); } =20 +static bool virt_get_start_in_flash(Object *obj, Error **errp) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + return s->start_in_flash; +} + +static void virt_set_start_in_flash(Object *obj, bool value, Error **errp) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + s->start_in_flash =3D value; +} + static void riscv_sifive_u_machine_instance_init(Object *obj) { + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + s->start_in_flash =3D false; + object_property_add_bool(obj, "start-in-flash", virt_get_start_in_flas= h, + virt_set_start_in_flash, NULL); + object_property_set_description(obj, "start-in-flash", + "Set on to tell QEMU's ROM to jump to = " \ + "flash. Otherwise QEMU will jump to DR= AM", + NULL); } =20 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index a921079fbe..2656b43c58 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -57,6 +57,8 @@ typedef struct SiFiveUState { =20 void *fdt; int fdt_size; + + bool start_in_flash; } SiFiveUState; =20 enum { --=20 2.23.0 From nobody Wed Nov 12 08:31:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; 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d="scan'208";a="119225551" IronPort-SDR: Jqzx55lkpRGymF235yvP3XH0YPc5TFcEVzQHccbam0WOomiuzWGCDs4DLccAyJDPZ6Oa1VmX48 O6XO8g2UHcPLbqFKM4MfZwHXoy6KLeuNCsQNM5ue7JsAcME5jWqnp2oC2H6sJJoYt0gKDPWqin /6h1ySiYv3Aye+ZORNRZVO/DeqiORvMTcrmjWfyCTjGevdiAH/6LeJ1okbIgW3FBrhsf0bFQ/W D0ntLpLMDMqW//9t/IN1PFgBMa066vHf4y5SGBwDiWr2RbutK8PD5iKqrQR91rGr/DlmK5IYSN lOiU+a7s0BjRew9F+x1D5EQm IronPort-SDR: NfcGtkJs7u89PC/CSEgSIDFPpMxLB99qOmty5VtKGO1AOgeqMei+n9hi4JD0jKsoWhr3u8HPAi g4i/tZ2eOUFGLLuF8dxLz3NKM/nTySrJZ9RIaoOvFwwLk6Raq6CBeAVdZjvshb8ax5qOG6xi79 /b8sLCxhNTLghWSFvOq00ROIgwEZKAno9ZWJPQDQayT4REG7PTBETo1kO0yqDHFOspDAdl4CBq sRnmCGXIZc6YoUNMUuoesXdjqzNJ+Wleb+6yyeh2KXmCgklUtq0sYNrhjhg3jxqg1C0ZSvUsmw 5jw= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 5/7] riscv/virt: Manually define the machine Date: Thu, 26 Sep 2019 17:44:31 -0700 Message-Id: <737cb09136e20293c82da7b07eb2020cc7bb99a2.1569545046.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Instead of using the DEFINE_MACHINE() macro to define the machine let's do it manually. This allows us to use the machine object to create RISCVVirtState. This is required to add children and aliases to the machine. This patch is no functional change. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/riscv/virt.c | 30 ++++++++++++++++++++++++------ include/hw/riscv/virt.h | 7 ++++++- 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d36f5625ec..e4dcbadcb5 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -362,8 +362,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion = *sys_mem, static void riscv_virt_board_init(MachineState *machine) { const struct MemmapEntry *memmap =3D virt_memmap; - - RISCVVirtState *s =3D g_new0(RISCVVirtState, 1); + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); @@ -499,12 +498,31 @@ static void riscv_virt_board_init(MachineState *machi= ne) g_free(plic_hart_config); } =20 -static void riscv_virt_board_machine_init(MachineClass *mc) +static void riscv_virt_machine_instance_init(Object *obj) { - mc->desc =3D "RISC-V VirtIO Board (Privileged ISA v1.10)"; +} + +static void riscv_virt_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "RISC-V VirtIO board"; mc->init =3D riscv_virt_board_init; - mc->max_cpus =3D 8; /* hardcoded limit in BBL */ + mc->max_cpus =3D 8; mc->default_cpu_type =3D VIRT_CPU; } =20 -DEFINE_MACHINE("virt", riscv_virt_board_machine_init) +static const TypeInfo riscv_virt_machine_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("virt"), + .parent =3D TYPE_MACHINE, + .class_init =3D riscv_virt_machine_class_init, + .instance_init =3D riscv_virt_machine_instance_init, + .instance_size =3D sizeof(RISCVVirtState), +}; + +static void riscv_virt_machine_init_register_types(void) +{ + type_register_static(&riscv_virt_machine_typeinfo); +} + +type_init(riscv_virt_machine_init_register_types) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 6e5fbe5d3b..ffcdcc6dcc 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -22,13 +22,18 @@ #include "hw/riscv/riscv_hart.h" #include "hw/sysbus.h" =20 +#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") +#define RISCV_VIRT_MACHINE(obj) \ + OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_MACHINE) + typedef struct { /*< private >*/ - SysBusDevice parent_obj; + MachineState parent; =20 /*< public >*/ RISCVHartArrayState soc; DeviceState *plic; + void *fdt; int fdt_size; } RISCVVirtState; --=20 2.23.0 From nobody Wed Nov 12 08:31:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1569545862; cv=none; d=zoho.com; s=zohoarc; b=NtqXZVRQ5cULmQsVfnfD2L+8nVN7ZtL7ktAoqkbXP/2gJOhzLB4bOlxjGcN7F8qAS9ceiKfwh+vc7/AVYGejGYLUpQ/HXHnYUYvMvy+g8FUkUyBEb/qzpUqDJVQmjuruOgNq/R2Qa/wcfIFclcEoS9j2gi3SSCrspnNZvJqDIYU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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d="scan'208";a="120012193" IronPort-SDR: 7xouPCupfsNKMwu4hXZZ4hT4+c4WPZtbKYtWP/96ATMvV81G7ft9QJWJt33YCxRAWtkIjAwcHT 0xLSzlZl7esO95vXhs3cJuvBN6haSh8NwBVvVfQABxU9lWvEM0+sgs41ZGFS/WUAbIrcHrNbOH NtmMul7iQiazaL0JTTazwqATG4HEsHLcpZYy4FCCTI/Md8Ugx0s292bKiMmFwPyvPGDQmkGYKg LuZqdi5rK799jQy7B14ZKKIfHKhgTuf7/seIo9DgCSAJvh2yrOkVw5UiAwYwp2UzT/6bbDfs0n dvwaaRIaoP2GehnwlURM3ppS IronPort-SDR: Vn3NwHD6/OL5e5vWXMlId+OU9e2HOFXFYD7E2/QakIfEr5AMXHFg6m8KygVJvTqEzMyLmRsv/X /iCN+ikzL89ea24M2cjp34Ci9x0xLHAiWAAiwWpB3hplhi2pgDTARsaXPUbB46vjnfcrxTSp5A FkEXYZADx81vVstpf0brVKyUf+se3vScYpbT6p4Lg3OTwTKhQpl8idH0OKrbH2U9V1ayF8fexn 4/ZUEZLfiJkrC3gRAz+d0kxju5Euz4y+2d4OOVp2zPKq13q4R28lJ4ymcvv0hKq6sFo4ke7VKO UQA= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 6/7] riscv/virt: Add the PFlash CFI01 device Date: Thu, 26 Sep 2019 17:44:33 -0700 Message-Id: X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.153.144 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add the CFI01 PFlash to the RISC-V virt board. This is the same PFlash from the ARM Virt board and the implementation is based on the ARM Virt board. This allows users to specify flash files from the command line. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/riscv/Kconfig | 1 + hw/riscv/virt.c | 86 +++++++++++++++++++++++++++++++++++++++++ include/hw/riscv/virt.h | 3 ++ 3 files changed, 90 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index fb19b2df3a..b12660b9f8 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -36,4 +36,5 @@ config RISCV_VIRT select SERIAL select VIRTIO_MMIO select PCI_EXPRESS_GENERIC_BRIDGE + select PFLASH_CFI01 select SIFIVE diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e4dcbadcb5..ad29e14d5f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -26,6 +26,7 @@ #include "hw/boards.h" #include "hw/loader.h" #include "hw/sysbus.h" +#include "hw/qdev-properties.h" #include "hw/char/serial.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" @@ -61,12 +62,77 @@ static const struct MemmapEntry { [VIRT_PLIC] =3D { 0xc000000, 0x4000000 }, [VIRT_UART0] =3D { 0x10000000, 0x100 }, [VIRT_VIRTIO] =3D { 0x10001000, 0x1000 }, + [VIRT_FLASH] =3D { 0x20000000, 0x2000000 }, [VIRT_DRAM] =3D { 0x80000000, 0x0 }, [VIRT_PCIE_MMIO] =3D { 0x40000000, 0x40000000 }, [VIRT_PCIE_PIO] =3D { 0x03000000, 0x00010000 }, [VIRT_PCIE_ECAM] =3D { 0x30000000, 0x10000000 }, }; =20 +#define VIRT_FLASH_SECTOR_SIZE (256 * KiB) + +static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, + const char *name, + const char *alias_prop_name) +{ + /* + * Create a single flash device. We use the same parameters as + * the flash devices on the ARM virt board. + */ + DeviceState *dev =3D qdev_create(NULL, TYPE_PFLASH_CFI01); + + qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); + qdev_prop_set_uint8(dev, "width", 4); + qdev_prop_set_uint8(dev, "device-width", 2); + qdev_prop_set_bit(dev, "big-endian", false); + qdev_prop_set_uint16(dev, "id0", 0x89); + qdev_prop_set_uint16(dev, "id1", 0x18); + qdev_prop_set_uint16(dev, "id2", 0x00); + qdev_prop_set_uint16(dev, "id3", 0x00); + qdev_prop_set_string(dev, "name", name); + + object_property_add_child(OBJECT(s), name, OBJECT(dev), + &error_abort); + object_property_add_alias(OBJECT(s), alias_prop_name, + OBJECT(dev), "drive", &error_abort); + + return PFLASH_CFI01(dev); +} + +static void virt_flash_create(RISCVVirtState *s) +{ + s->flash[0] =3D virt_flash_create1(s, "virt.flash0", "pflash0"); + s->flash[1] =3D virt_flash_create1(s, "virt.flash1", "pflash1"); +} + +static void virt_flash_map1(PFlashCFI01 *flash, + hwaddr base, hwaddr size, + MemoryRegion *sysmem) +{ + DeviceState *dev =3D DEVICE(flash); + + assert(size % VIRT_FLASH_SECTOR_SIZE =3D=3D 0); + assert(size / VIRT_FLASH_SECTOR_SIZE <=3D UINT32_MAX); + qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); + qdev_init_nofail(dev); + + memory_region_add_subregion(sysmem, base, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), + 0)); +} + +static void virt_flash_map(RISCVVirtState *s, + MemoryRegion *sysmem) +{ + hwaddr flashsize =3D virt_memmap[VIRT_FLASH].size / 2; + hwaddr flashbase =3D virt_memmap[VIRT_FLASH].base; + + virt_flash_map1(s->flash[0], flashbase, flashsize, + sysmem); + virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, + sysmem); +} + static void create_pcie_irq_map(void *fdt, char *nodename, uint32_t plic_phandle) { @@ -121,6 +187,8 @@ static void create_fdt(RISCVVirtState *s, const struct = MemmapEntry *memmap, char *nodename; uint32_t plic_phandle, phandle =3D 1; int i; + hwaddr flashsize =3D virt_memmap[VIRT_FLASH].size / 2; + hwaddr flashbase =3D virt_memmap[VIRT_FLASH].base; =20 fdt =3D s->fdt =3D create_device_tree(&s->fdt_size); if (!fdt) { @@ -316,6 +384,15 @@ static void create_fdt(RISCVVirtState *s, const struct= MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); } g_free(nodename); + + nodename =3D g_strdup_printf("/flash@%" PRIx64, flashbase); + qemu_fdt_add_subnode(s->fdt, nodename); + qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash"); + qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg", + 2, flashbase, 2, flashsize, + 2, flashbase + flashsize, 2, flashsize); + qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4); + g_free(nodename); } =20 =20 @@ -495,6 +572,15 @@ static void riscv_virt_board_init(MachineState *machin= e) 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193, serial_hd(0), DEVICE_LITTLE_ENDIAN); =20 + virt_flash_create(s); + + for (i =3D 0; i < ARRAY_SIZE(s->flash); i++) { + /* Map legacy -drive if=3Dpflash to machine properties */ + pflash_cfi01_legacy_drive(s->flash[i], + drive_get(IF_PFLASH, 0, i)); + } + virt_flash_map(s, system_memory); + g_free(plic_hart_config); } =20 diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index ffcdcc6dcc..8630f84592 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -21,6 +21,7 @@ =20 #include "hw/riscv/riscv_hart.h" #include "hw/sysbus.h" +#include "hw/block/flash.h" =20 #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") #define RISCV_VIRT_MACHINE(obj) \ @@ -33,6 +34,7 @@ typedef struct { /*< public >*/ RISCVHartArrayState soc; DeviceState *plic; + PFlashCFI01 *flash[2]; =20 void *fdt; int fdt_size; @@ -46,6 +48,7 @@ enum { VIRT_PLIC, VIRT_UART0, VIRT_VIRTIO, + VIRT_FLASH, VIRT_DRAM, VIRT_PCIE_MMIO, VIRT_PCIE_PIO, --=20 2.23.0 From nobody Wed Nov 12 08:31:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.153.141 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) If the user supplied pflash to QEMU then change the reset code to jump to the pflash base address instead of the DRAM base address. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Bin Meng --- hw/riscv/virt.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ad29e14d5f..a79d16d99a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -445,6 +445,7 @@ static void riscv_virt_board_init(MachineState *machine) MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); char *plic_hart_config; size_t plic_hart_config_len; + target_ulong start_addr =3D memmap[VIRT_DRAM].base; int i; unsigned int smp_cpus =3D machine->smp.cpus; =20 @@ -491,6 +492,14 @@ static void riscv_virt_board_init(MachineState *machin= e) } } =20 + if (drive_get(IF_PFLASH, 0, 0)) { + /* + * Pflash was supplied, let's overwrite the address we jump to aft= er + * reset to the base of the flash. + */ + start_addr =3D virt_memmap[VIRT_FLASH].base; + } + /* reset vector */ uint32_t reset_vec[8] =3D { 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ @@ -503,7 +512,7 @@ static void riscv_virt_board_init(MachineState *machine) #endif 0x00028067, /* jr t0 */ 0x00000000, - memmap[VIRT_DRAM].base, /* start: .dword memmap[VIRT_DRAM].ba= se */ + start_addr, /* start: .dword */ 0x00000000, /* dtb: */ }; --=20 2.23.0