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charset="utf-8" On reset only a single L2 cache way is enabled, the others are exposed as memory that can be used by early boot firmware. This L2 region is generally disabled using the WayEnable register at a later stage in the boot process. To allow firmware to target QEMU and the HiFive Unleashed let's add the L2 LIM (LooselyIntegrated Memory). Ideally we would want to adjust the size of this chunk of memory as the L2 Cache Controller WayEnable register is incremented. Unfortunately I don't see a nice way to handle reducing or blocking out the L2 LIM while still allowing it be re returned to all enabled from a reset. Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 15 +++++++++++++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 16 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9f8e84bf2e..de6e197882 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -65,6 +65,7 @@ static const struct MemmapEntry { [SIFIVE_U_DEBUG] =3D { 0x0, 0x100 }, [SIFIVE_U_MROM] =3D { 0x1000, 0x11000 }, [SIFIVE_U_CLINT] =3D { 0x2000000, 0x10000 }, + [SIFIVE_U_L2LIM] =3D { 0x8000000, 0x1e00000 }, [SIFIVE_U_PLIC] =3D { 0xc000000, 0x4000000 }, [SIFIVE_U_PRCI] =3D { 0x10000000, 0x1000 }, [SIFIVE_U_UART0] =3D { 0x10010000, 0x1000 }, @@ -431,6 +432,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev= , Error **errp) const struct MemmapEntry *memmap =3D sifive_u_memmap; MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *l2lim_mem =3D g_new(MemoryRegion, 1); qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; char *plic_hart_config; size_t plic_hart_config_len; @@ -459,6 +461,19 @@ static void riscv_sifive_u_soc_realize(DeviceState *de= v, Error **errp) memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, mask_rom); =20 + /* Add L2-LIM at reset size. + * This should be reduced in size as the L2 Cache Controller WayEnable + * register is incremented. Unfortunately I don't see a nice (or any) = way + * to handle reducing or blocking out the L2 LIM while still allowing = it + * be re returned to all enabled after a reset. For the time being, ju= st + * leave it enabled all the time. This won't break anything, but will = be + * too generous to misbehaving guests. + */ + memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", + memmap[SIFIVE_U_L2LIM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base, + l2lim_mem); + /* create PLIC hart topology configuration string */ plic_hart_config_len =3D (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * ms->smp.cpus; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index e4df298c23..50e3620c02 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -58,6 +58,7 @@ enum { SIFIVE_U_DEBUG, SIFIVE_U_MROM, SIFIVE_U_CLINT, + SIFIVE_U_L2LIM, SIFIVE_U_PLIC, SIFIVE_U_PRCI, SIFIVE_U_UART0, --=20 2.23.0 From nobody Sat May 4 06:34:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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IronPort-SDR: 1eRLMk0xS2Uf/6WUBMw7lXcuvU//zQuQNcMV5GgmfN34MkvnlDFllrcNa4A6HaH+1fMW9g0UT9 pM+ONw/GzJmjU6oz+8O9LvhWdmPXQVx3aOXIlYBCB/UkyAluFrAIBLKlx3De+FaL27KOAyYxhF zHMyxasOV1BDVZDezFycbt3m3yF8iDrUWGqXQI8kQxSQrMUu8/kJi1D1A5lnos/RMm4WvpbTEi HDPv8S6tCsoT8rK4ZpnBYSbEvodDAuaWlyiLc0b1Fq8jJrNqEl81g3ZDLM3SGgUzW78GKfn+Kw vro= X-IronPort-AV: E=Sophos;i="5.64,526,1559491200"; d="scan'208";a="219490589" IronPort-SDR: Km2WdYtDJoApy/rb6PwrlQB5vfET/AjBF2liPMPPhBQ7VEgcaggjJ4Cq4tY9Ci1yBd+UmlKKw7 WctBgy8LMIJd7gdnt71waTuJ7xSGqLdG0V3l/VxdqE5CX+zMWX9NVieT7UL6nYIY/BGMbrXiKU m37e8ye+k5TUeq8dlGQnzdvSAnJA97GUXCeKfHDi3B9HMHk4eXh43STesYbmDgKqpfS6s5sGPu 8pYRQyzkimhvqJldqZvLXMHeOFKO+T2dFxbt86yamjWc8AC72Gnl4agP/Aj56uHK3JVI+h1dTK 2z6VskXZsA6nBjhB8qfroQqz IronPort-SDR: OOgCCSHJ+1uRU+uYr5Ix222BOIRGNkDwPPObyN66ek/XgutSGT5Vcfq2F85d0EL7pbg1D1iNxG bQ7hSd44j+Puwra0oCr0CT0MWEm3TawrC/rsHK/MfR/gB4AKQxPi0hkODDnKPGtBur46ZNxndA zeNdbEp2hAts7bC38UVnO1p+JkbS1RPMgLPRg9KLQKBBAkce7OHeXQ6F/a2KSlyyuMJRArupNt /p/lTwQ9c6zgoDYHJOwfMdOTDNmLfSYXVyVF2Ssn1hwww5+HuPtDWaC89Dw9mETZxG2a8pz8Cj lkg= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 2/6] riscv/sifive_u: Add QSPI memory region Date: Thu, 19 Sep 2019 15:24:58 -0700 Message-Id: X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 68.232.143.124 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" There doesn't seem to be details on what QSPI the HiFive Unleashed uses. To allow boot firmware developers to use QEMU to target the Unleashed let's add a chunk of memory to represent the QSPI. This can be targeted using QEMU's -device loader command line option. Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 8 ++++++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 9 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index de6e197882..9c5d791320 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -71,6 +71,7 @@ static const struct MemmapEntry { [SIFIVE_U_UART0] =3D { 0x10010000, 0x1000 }, [SIFIVE_U_UART1] =3D { 0x10011000, 0x1000 }, [SIFIVE_U_OTP] =3D { 0x10070000, 0x1000 }, + [SIFIVE_U_FLASH0] =3D { 0x20000000, 0x2000000 }, [SIFIVE_U_DRAM] =3D { 0x80000000, 0x0 }, [SIFIVE_U_GEM] =3D { 0x10090000, 0x2000 }, [SIFIVE_U_GEM_MGMT] =3D { 0x100a0000, 0x1000 }, @@ -313,6 +314,7 @@ static void riscv_sifive_u_init(MachineState *machine) SiFiveUState *s =3D g_new0(SiFiveUState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); + MemoryRegion *flash0 =3D g_new(MemoryRegion, 1); int i; =20 /* Initialize SoC */ @@ -328,6 +330,12 @@ static void riscv_sifive_u_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, main_mem); =20 + /* register QSPI0 Flash */ + memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", + memmap[SIFIVE_U_FLASH0].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].bas= e, + flash0); + /* create device tree */ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 50e3620c02..2a08e2a5db 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -64,6 +64,7 @@ enum { SIFIVE_U_UART0, SIFIVE_U_UART1, SIFIVE_U_OTP, + SIFIVE_U_FLASH0, SIFIVE_U_DRAM, SIFIVE_U_GEM, SIFIVE_U_GEM_MGMT --=20 2.23.0 From nobody Sat May 4 06:34:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; 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charset="utf-8" Instead of using the DEFINE_MACHINE() macro to define the machine let's do it manually. This allows us to specify machine properties. This patch is no functional change. Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++---- include/hw/riscv/sifive_u.h | 7 ++++++- 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9c5d791320..c3949fb316 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -310,8 +310,7 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, static void riscv_sifive_u_init(MachineState *machine) { const struct MemmapEntry *memmap =3D sifive_u_memmap; - - SiFiveUState *s =3D g_new0(SiFiveUState, 1); + SiFiveUState *s =3D RISCV_U_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *flash0 =3D g_new(MemoryRegion, 1); @@ -545,8 +544,15 @@ static void riscv_sifive_u_soc_realize(DeviceState *de= v, Error **errp) memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); } =20 -static void riscv_sifive_u_machine_init(MachineClass *mc) +static void riscv_sifive_u_machine_instance_init(Object *obj) +{ + +} + +static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data) { + MachineClass *mc =3D MACHINE_CLASS(oc); + mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; mc->init =3D riscv_sifive_u_init; mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; @@ -554,7 +560,20 @@ static void riscv_sifive_u_machine_init(MachineClass *= mc) mc->default_cpus =3D mc->min_cpus; } =20 -DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) +static const TypeInfo riscv_sifive_u_machine_init_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("sifive_u"), + .parent =3D TYPE_MACHINE, + .class_init =3D riscv_sifive_u_machine_class_init, + .instance_init =3D riscv_sifive_u_machine_instance_init, + .instance_size =3D sizeof(SiFiveUState), +}; + +static void riscv_sifive_u_machine_init_register_types(void) +{ + type_register_static(&riscv_sifive_u_machine_init_typeinfo); +} + +type_init(riscv_sifive_u_machine_init_register_types) =20 static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) { diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 2a08e2a5db..a921079fbe 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -44,12 +44,17 @@ typedef struct SiFiveUSoCState { CadenceGEMState gem; } SiFiveUSoCState; =20 +#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") +#define RISCV_U_MACHINE(obj) \ + OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE) + typedef struct SiFiveUState { /*< private >*/ - SysBusDevice parent_obj; + MachineState parent_obj; =20 /*< public >*/ SiFiveUSoCState soc; + void *fdt; int fdt_size; } SiFiveUState; --=20 2.23.0 From nobody Sat May 4 06:34:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1568932316; cv=none; d=zoho.com; s=zohoarc; b=MPS/6Lq3wNEEqH8LgbWaCouTFciv00CzuL4P49P0o/hnUJRHnXWr1x4cXFjSJLN0s38tse4bDZyHfQ2asn5LahWWqSiF4jvWfAtM2fpPQTH4e/J4rlEqaM/5RSA5O/ZvJmRmdDs1zcU9KtOdfjqSmvH68cNjzecaE7s3EoSmRw0= ARC-Message-Signature: i=1; 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d="scan'208";a="219490592" IronPort-SDR: OYluSz2f79BPPRmrc3ArgWPxy3H/j6TgbnDzxxCkiwAoa7bw8CW4DyG4YEjsU7rDKBi+FyjVKv oiwMVfmStsaEyaYmDCrTS8AZi4I2B4f0BZauKEgZLED58sY3cmaFLaYsfQw26Gdj+NLixkOoQ6 vWtim1IJgGL0SJ+X4uf4vbSgTlZnsBl2SgDPT8L2lCdtPC+Gru4it5XcmVhSjAftloQDpq8SlY i1rLH2XJi8mqSEhba5AjIYFCxD1NDlEzgBHYtBlPmfBt3OHNnYDgVSiLMPuY5DtQ0k5YtmiOzQ yqz0bh7tPtA+Bs2xrJhMgPJF IronPort-SDR: 0zxKz3+VDzILValg0v/hUllzghAIwx7bvI/KQXqy7uSpJo3fgDiNWntkMEl7tvc7MIsYKl00Yy /YGvHj1s8DQzeHTMleUvW+R/FEpxbeWpqa+CAglbCXCytzl/2NxXSCX3J88XnbVSHBPVtTm08m ETOj5QOPoa/m7+mJ/5kYqR0ZzO3SddtpC+Gfuec0orTYIaayYF0HBOwucMa9fj+ZPpGBmYAuxH I6siqcRhA6GkeFrdy1v/FKYfgOMmfYmJ/8TqKcIOXP5RJusWga5twIZnbrNwvgj5ybgdOa1piz n0o= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 4/6] riscv/sifive_u: Add the start-in-flash property Date: Thu, 19 Sep 2019 15:25:03 -0700 Message-Id: X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 68.232.143.124 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add a property that when set to true QEMU will jump from the ROM code to the start of flash memory instead of DRAM which is the default behaviour. Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++++++ include/hw/riscv/sifive_u.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index c3949fb316..b7cd3631cd 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -373,6 +373,10 @@ static void riscv_sifive_u_init(MachineState *machine) /* dtb: */ }; =20 + if (s->start_in_flash) { + reset_vec[6] =3D memmap[SIFIVE_U_FLASH0].base; /* start: .dword FL= ASH0_BASE */ + } + /* copy in the reset vector in little_endian byte order */ for (i =3D 0; i < sizeof(reset_vec) >> 2; i++) { reset_vec[i] =3D cpu_to_le32(reset_vec[i]); @@ -544,8 +548,31 @@ static void riscv_sifive_u_soc_realize(DeviceState *de= v, Error **errp) memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); } =20 +static bool virt_get_start_in_flash(Object *obj, Error **errp) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + return s->start_in_flash; +} + +static void virt_set_start_in_flash(Object *obj, bool value, Error **errp) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + s->start_in_flash =3D value; +} + static void riscv_sifive_u_machine_instance_init(Object *obj) { + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + s->start_in_flash =3D false; + object_property_add_bool(obj, "start-in-flash", virt_get_start_in_flas= h, + virt_set_start_in_flash, NULL); + object_property_set_description(obj, "start-in-flash", + "Set on to tell QEMU's ROM to jump to = " \ + "flash. Otherwise QEMU will jump to DR= AM", + NULL); =20 } =20 diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index a921079fbe..2656b43c58 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -57,6 +57,8 @@ typedef struct SiFiveUState { =20 void *fdt; int fdt_size; + + bool start_in_flash; } SiFiveUState; =20 enum { --=20 2.23.0 From nobody Sat May 4 06:34:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1568932584; cv=none; d=zoho.com; s=zohoarc; b=bobigd6JiD9ot/XMzxJ9x2/4uzFCeKifxhl9mZCfGmQ/18lW2OpH9ZZP4KNbm5mPmKXfP6RSkTtJv21kNbuE8xQo9UbVc/6+x7BtjFje8tY0gVw1bJNUjYFKc2Bi+MmYZ5aljaplRpSmpt8Ix2b5NVlYUIPar1iaoyzyhE+9o+I= ARC-Message-Signature: i=1; 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d="scan'208";a="123146905" IronPort-SDR: FIesWdPQ7XMPR2qh3R3rTLDijVqGFzcxalFFK3DfdmACYWohqaIKasV0T2a053hB/L+cgQ/vfk X7abmbXweYWs6natcWFF/UlvkQrme9Xtb+bU8h2vE9/D93qJuf1X+LV0hFvYH6ykWyHh4B97YD RGckFph07ZFopMuRuaYUeurQz0GQBHcn9Sgd7ztHYF5B8XKnc/Gyrp0sTo9Rexh6DRSWabPAJi TnfUIvmJ/4UXtEGzUJ59WC+XNyn6HWCCREtxKd0mWceX8EsdIrQ5Mj3bdRMypkOEPvIRx7aP4r h80lcmHJvGcLa0sUhbV7P0Hc IronPort-SDR: Uq51xKAiDYDnVEQjZ+o0YKS0HFlASIAY1+osXEnDqVBehMNbcH34Rza8EIbAMqbxjdrp42qURr DrLh1BAkh5b0wDaPl7UlG9e3Ql/FxvesuM0DQiAp8E6nISum4LUaBLOJ6ovy9m8gkBw/Y+UjMm FnvuP6O5g9ZAsv0prvShzC0pzcM2X6cPkHbfiNvqQ3sXBsvCEJX+1e8kqJerSc5ZYD2FlwMNZO W0cVrtKB8EnVNerwKsFTBpIuu9KJF7Q5dZryup/MzP24gcYX3kVtJyLUHEfZhbk45uq78cOM6H D0M= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 5/6] riscv/virt: Add the PFlash CFI01 device Date: Thu, 19 Sep 2019 15:25:06 -0700 Message-Id: <0a5c141a26fada6d93d06e996a2f24e1b269ec50.1568931866.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 216.71.153.141 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add the CFI01 PFlash to the RISC-V virt board. This is the same PFlash from the ARM Virt board and the implementation is based on the ARM Virt board. This allows users to specify flash files from the command line. Signed-off-by: Alistair Francis --- hw/riscv/Kconfig | 1 + hw/riscv/virt.c | 81 +++++++++++++++++++++++++++++++++++++++++ include/hw/riscv/virt.h | 3 ++ 3 files changed, 85 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index fb19b2df3a..b12660b9f8 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -36,4 +36,5 @@ config RISCV_VIRT select SERIAL select VIRTIO_MMIO select PCI_EXPRESS_GENERIC_BRIDGE + select PFLASH_CFI01 select SIFIVE diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d36f5625ec..ca002ecea7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -26,6 +26,7 @@ #include "hw/boards.h" #include "hw/loader.h" #include "hw/sysbus.h" +#include "hw/qdev-properties.h" #include "hw/char/serial.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" @@ -61,12 +62,72 @@ static const struct MemmapEntry { [VIRT_PLIC] =3D { 0xc000000, 0x4000000 }, [VIRT_UART0] =3D { 0x10000000, 0x100 }, [VIRT_VIRTIO] =3D { 0x10001000, 0x1000 }, + [VIRT_FLASH] =3D { 0x20000000, 0x2000000 }, [VIRT_DRAM] =3D { 0x80000000, 0x0 }, [VIRT_PCIE_MMIO] =3D { 0x40000000, 0x40000000 }, [VIRT_PCIE_PIO] =3D { 0x03000000, 0x00010000 }, [VIRT_PCIE_ECAM] =3D { 0x30000000, 0x10000000 }, }; =20 +#define VIRT_FLASH_SECTOR_SIZE (256 * KiB) + +static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, + const char *name, + const char *alias_prop_name) +{ + /* + * Create a single flash device. We use the same parameters as + * the flash devices on the ARM virt board. + */ + DeviceState *dev =3D qdev_create(NULL, TYPE_PFLASH_CFI01); + + qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); + qdev_prop_set_uint8(dev, "width", 4); + qdev_prop_set_uint8(dev, "device-width", 2); + qdev_prop_set_bit(dev, "big-endian", false); + qdev_prop_set_uint16(dev, "id0", 0x89); + qdev_prop_set_uint16(dev, "id1", 0x18); + qdev_prop_set_uint16(dev, "id2", 0x00); + qdev_prop_set_uint16(dev, "id3", 0x00); + qdev_prop_set_string(dev, "name", name); + + return PFLASH_CFI01(dev); +} + +static void virt_flash_create(RISCVVirtState *s) +{ + s->flash[0] =3D virt_flash_create1(s, "virt.flash0", "pflash0"); + s->flash[1] =3D virt_flash_create1(s, "virt.flash1", "pflash1"); +} + +static void virt_flash_map1(PFlashCFI01 *flash, + hwaddr base, hwaddr size, + MemoryRegion *sysmem) +{ + DeviceState *dev =3D DEVICE(flash); + + assert(size % VIRT_FLASH_SECTOR_SIZE =3D=3D 0); + assert(size / VIRT_FLASH_SECTOR_SIZE <=3D UINT32_MAX); + qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); + qdev_init_nofail(dev); + + memory_region_add_subregion(sysmem, base, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), + 0)); +} + +static void virt_flash_map(RISCVVirtState *s, + MemoryRegion *sysmem) +{ + hwaddr flashsize =3D virt_memmap[VIRT_FLASH].size / 2; + hwaddr flashbase =3D virt_memmap[VIRT_FLASH].base; + + virt_flash_map1(s->flash[0], flashbase, flashsize, + sysmem); + virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, + sysmem); +} + static void create_pcie_irq_map(void *fdt, char *nodename, uint32_t plic_phandle) { @@ -121,6 +182,8 @@ static void create_fdt(RISCVVirtState *s, const struct = MemmapEntry *memmap, char *nodename; uint32_t plic_phandle, phandle =3D 1; int i; + hwaddr flashsize =3D virt_memmap[VIRT_FLASH].size / 2; + hwaddr flashbase =3D virt_memmap[VIRT_FLASH].base; =20 fdt =3D s->fdt =3D create_device_tree(&s->fdt_size); if (!fdt) { @@ -316,6 +379,15 @@ static void create_fdt(RISCVVirtState *s, const struct= MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); } g_free(nodename); + + nodename =3D g_strdup_printf("/flash@%" PRIx64, flashbase); + qemu_fdt_add_subnode(s->fdt, nodename); + qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash"); + qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg", + 2, flashbase, 2, flashsize, + 2, flashbase + flashsize, 2, flashsize); + qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4); + g_free(nodename); } =20 =20 @@ -496,6 +568,15 @@ static void riscv_virt_board_init(MachineState *machin= e) 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193, serial_hd(0), DEVICE_LITTLE_ENDIAN); =20 + virt_flash_create(s); + + /* Map legacy -drive if=3Dpflash to machine properties */ + for (i =3D 0; i < ARRAY_SIZE(s->flash); i++) { + pflash_cfi01_legacy_drive(s->flash[i], + drive_get(IF_PFLASH, 0, i)); + } + virt_flash_map(s, system_memory); + g_free(plic_hart_config); } =20 diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 6e5fbe5d3b..2ca8bd3512 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -21,6 +21,7 @@ =20 #include "hw/riscv/riscv_hart.h" #include "hw/sysbus.h" +#include "hw/block/flash.h" =20 typedef struct { /*< private >*/ @@ -29,6 +30,7 @@ typedef struct { /*< public >*/ RISCVHartArrayState soc; DeviceState *plic; + PFlashCFI01 *flash[2]; void *fdt; int fdt_size; } RISCVVirtState; @@ -41,6 +43,7 @@ enum { VIRT_PLIC, VIRT_UART0, VIRT_VIRTIO, + VIRT_FLASH, VIRT_DRAM, VIRT_PCIE_MMIO, VIRT_PCIE_PIO, --=20 2.23.0 From nobody Sat May 4 06:34:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1568932514; cv=none; d=zoho.com; s=zohoarc; b=gqncf3u0dUZoI7ZDGh77DR7Kxfm/d3exxTjCuIbbNx4fpusrMlBYYMOdVEn0tYi8z0JB4RKrWIrpYfmeJAeqI/h8Q3qoKIuYSxd102OG0k6vWFwUseFpqtiTHvOlI+gBry2XBLIK3PJ1DcxzYWMb5T9rZPniwXsdeI+8rfCQU0w= ARC-Message-Signature: i=1; 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d="scan'208";a="219490597" IronPort-SDR: WKctnQsPGljMffycGJXgz7Qz74uEVSd/mxxNx8yBr42Ej7NJYiz6amxdJrGDCzaV6W6mjQdCxe RXchZVnRGY4BoI6NQK16/ZnPei61I/SfhiZw3AEiU+7wXMtq7q/WRQJRlRD6DXWFX8xn2tQHeO lW4G48nWNZteyVPfz96DzAs4Zc8LHEY7avwdT+rUZdUokVW/5XHbO+vUCYyeONpPgQpBl/uLkM FsvAYyhXyk2YW4BJ4alU8/PYsUTS/s4zosDkCms5qdL48VzXjKRWfiI4+UhIC6YKNm/gLT8fKR lSU4uGDKxItsOX3TJANgHInP IronPort-SDR: +2GHoSGSHbrKJ8tqSrajCQxOYT+GC1J6Mx2V8BqtgdK8C0KI2IsXrMwAfRQJC2i841z7l1kJtz QG80HQc4HYyZWKTIx5rvooKDjMTryRB11eLWJ/JXQL6o6yxpNqoy1ZdDtQBG2/8Wr+rFIw8jgm yUMeRJBeTbFtzAPCrTTlZwXUAyjeRTIw9cf1mNmO2hy0D4lJrlnKD4Jmg8qG10vI0EMmeOcyI6 o3OwBxhpbq46EG7xZuAagp8fDn2jodRX5hfSn2DaM66Y4Z9L0q396DL83PqBaXChh6QAtwDpBA MwQ= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 6/6] riscv/virt: Jump to pflash if specified Date: Thu, 19 Sep 2019 15:25:08 -0700 Message-Id: X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 68.232.143.124 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" If the user supplied pflash to QEMU then change the reset code to jump to the pflash base address instead of the DRAM base address. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ca002ecea7..ed25cc6761 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -441,6 +441,7 @@ static void riscv_virt_board_init(MachineState *machine) MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); char *plic_hart_config; size_t plic_hart_config_len; + target_ulong start_addr =3D memmap[VIRT_DRAM].base; int i; unsigned int smp_cpus =3D machine->smp.cpus; =20 @@ -487,6 +488,13 @@ static void riscv_virt_board_init(MachineState *machin= e) } } =20 + if (drive_get(IF_PFLASH, 0, 0)) { + /* Pflash was supplied, let's overwrite the address we jump to aft= er + * reset to the base of the flash. + */ + start_addr =3D virt_memmap[VIRT_FLASH].base; + } + /* reset vector */ uint32_t reset_vec[8] =3D { 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ @@ -499,7 +507,7 @@ static void riscv_virt_board_init(MachineState *machine) #endif 0x00028067, /* jr t0 */ 0x00000000, - memmap[VIRT_DRAM].base, /* start: .dword memmap[VIRT_DRAM].ba= se */ + start_addr, /* start: .dword */ 0x00000000, /* dtb: */ }; --=20 2.23.0