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charset="utf-8" Setting write permission on dirty PTEs results in userspace inside a Hypervisor guest (VU) becoming corrupted. This appears to be because it ends up with write permission in the second stage translation in cases where we aren't doing a store. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e32b6126af..f027be7f16 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -340,10 +340,8 @@ restart: if ((pte & PTE_X)) { *prot |=3D PAGE_EXEC; } - /* add write permission on stores or if the page is already di= rty, - so that we TLB miss on later writes to update the dirty bit= */ - if ((pte & PTE_W) && - (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_D))) { + /* add write permission on stores */ + if ((pte & PTE_W) && (access_type =3D=3D MMU_DATA_STORE)) { *prot |=3D PAGE_WRITE; } return TRANSLATE_SUCCESS; --=20 2.22.0 From nobody Mon May 6 23:50:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [PATCH v3 2/7] riscv: plic: Remove unused interrupt functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Signed-off-by: Alistair Francis Reviewed-by: Jonathan Behrens Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Chih-Min Chao Reviewed-by: Bin Meng --- hw/riscv/sifive_plic.c | 12 ------------ include/hw/riscv/sifive_plic.h | 3 --- 2 files changed, 15 deletions(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 0950e89e15..864a1bed42 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -161,18 +161,6 @@ static void sifive_plic_update(SiFivePLICState *plic) } } =20 -void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq) -{ - sifive_plic_set_pending(plic, irq, true); - sifive_plic_update(plic); -} - -void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq) -{ - sifive_plic_set_pending(plic, irq, false); - sifive_plic_update(plic); -} - static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid) { int i, j; diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h index ce8907f6aa..3b8a623919 100644 --- a/include/hw/riscv/sifive_plic.h +++ b/include/hw/riscv/sifive_plic.h @@ -69,9 +69,6 @@ typedef struct SiFivePLICState { uint32_t aperture_size; } SiFivePLICState; =20 -void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq); -void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq); - DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, uint32_t num_sources, uint32_t num_priorities, uint32_t priority_base, uint32_t pending_base, --=20 2.22.0 From nobody Mon May 6 23:50:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Thu, 15 Aug 2019 17:38:21 -0400 Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 16 Aug 2019 05:38:20 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2019 14:35:51 -0700 Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.58]) by uls-op-cesaip02.wdc.com with ESMTP; 15 Aug 2019 14:38:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1565905101; x=1597441101; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uwuM+Bgdl8OMIy2aZPhcFOR0tnj4yo5dn4bBCycd9KM=; b=GmV7xq+7LzHQjRo2mNmDRM5kjMM1sjP5mYwd3aj/x1YfJQXX3gXFtpTA RWJL81JskilnTaV2aI6z206/24sew3nWyx5q130LYzqCyoKIghc4d6Ajg CfxTvXzovVx6Ebp1G7sojIyOLxUARSaULU3/RWX7ShxSYqDxvEEJU0qde McsdJZtIJawtjGQ68lLlw2hRk4d56FaXtymhtxU4l6uLyO+M88xG4CbT7 SqST5ouvofHYVFr36xlOEfIvi0QKCqS45J/8MQupE5GoF3E+FOXyj5Y+j dU6gPbd10aHJeLlY6f0o2jSeopplwTWZVtxgLGalarAf9+KsDvjcYfHk8 Q==; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [PATCH v3 3/7] target/riscv: Create function to test if FP is enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Let's create a function that tests if floating point support is enabled. We can then protect all floating point operations based on if they are enabled. This patch so far doesn't change anything, it's just preparing for the Hypervisor support for floating point operations. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Christophe de Dinechin Reviewed-by: Chih-Min Chao Reviewed-by: Bin Meng --- target/riscv/cpu.h | 6 +++++- target/riscv/cpu_helper.c | 10 ++++++++++ target/riscv/csr.c | 20 +++++++++++--------- 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0adb307f32..2dc9b17678 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -255,6 +255,7 @@ void riscv_cpu_do_interrupt(CPUState *cpu); int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); +bool riscv_cpu_fp_enabled(CPURISCVState *env); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, @@ -298,7 +299,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState = *env, target_ulong *pc, #ifdef CONFIG_USER_ONLY *flags =3D TB_FLAGS_MSTATUS_FS; #else - *flags =3D cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); + *flags =3D cpu_mmu_index(env, 0); + if (riscv_cpu_fp_enabled(env)) { + *flags |=3D env->mstatus & MSTATUS_FS; + } #endif } =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f027be7f16..225e407cff 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -71,6 +71,16 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) =20 #if !defined(CONFIG_USER_ONLY) =20 +/* Return true is floating point support is currently enabled */ +bool riscv_cpu_fp_enabled(CPURISCVState *env) +{ + if (env->mstatus & MSTATUS_FS) { + return true; + } + + return false; +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env =3D &cpu->env; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e0d4586760..2789215b5e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -46,7 +46,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *o= ps) static int fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -108,7 +108,7 @@ static int pmp(CPURISCVState *env, int csrno) static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -119,7 +119,7 @@ static int read_fflags(CPURISCVState *env, int csrno, t= arget_ulong *val) static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } env->mstatus |=3D MSTATUS_FS; @@ -131,7 +131,7 @@ static int write_fflags(CPURISCVState *env, int csrno, = target_ulong val) static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -142,7 +142,7 @@ static int read_frm(CPURISCVState *env, int csrno, targ= et_ulong *val) static int write_frm(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } env->mstatus |=3D MSTATUS_FS; @@ -154,7 +154,7 @@ static int write_frm(CPURISCVState *env, int csrno, tar= get_ulong val) static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -166,7 +166,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, tar= get_ulong *val) static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } env->mstatus |=3D MSTATUS_FS; @@ -307,6 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) { target_ulong mstatus =3D env->mstatus; target_ulong mask =3D 0; + int dirty; =20 /* flush tlb on mstatus fields that affect VM */ if (env->priv_ver <=3D PRIV_VERSION_1_09_1) { @@ -340,8 +341,9 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) =20 mstatus =3D (mstatus & ~mask) | (val & mask); =20 - int dirty =3D ((mstatus & MSTATUS_FS) =3D=3D MSTATUS_FS) | - ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); + dirty =3D (riscv_cpu_fp_enabled(env) && + ((mstatus & MSTATUS_FS) =3D=3D MSTATUS_FS)) | + ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); mstatus =3D set_field(mstatus, MSTATUS_SD, dirty); env->mstatus =3D mstatus; =20 --=20 2.22.0 From nobody Mon May 6 23:50:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1565905279; cv=none; d=zoho.com; s=zohoarc; b=fsc25SvjFxZZurDWVug2kYiXt8DIB9r6oYkV6S7m6FNZR2OlF9/Cj3kDkDy8nzOV7//BTXWyWQmKQ9flEjHirVT7SxpJUtEb5nzIMuRxNL4Mk0KlWYmg8Plq4VYoefD8Jpd5kowDb61fdM20+0EumOAqesL89UZh5B+od+WGE7Y= ARC-Message-Signature: i=1; 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d="scan'208";a="116881532" IronPort-SDR: g1C7n/ZUIzoifQyFfrqgNy4/AP9uPfwMxq8mpZ3udurxoIdm8mo1Mgdbp2uD4pOcXJUkk+sf6E MWP4lihurj/tXYq5ZsN7Toqjq7+GVPL6b5Io69KHJYOzCOcrBu5iC+M6Jm0IR/uvrtunmLJ9E7 4QBZ8QICq1hbR9x9w5MP0Zpkh0XKlFHkkiz6gOV4TcsIfhsLnopSX6HulGOR9GZu7C2MTBjB5W 3j524YEYCAquo2c8UTA8PHrXeYKszXzEtlOuedZkNxZ9OKgSPrt8XqVETYyPtPUWTmdQdrVK2Y exoce7dkf3N6Noq6ILb7n/HM IronPort-SDR: O6zMu+gEITSx3YQ4MqSfRVaio/mRWu///LIrcCA1oxofnH9bvaKBUI/tIJFertnAw7Fwq8ogkt UmX5yYhKacAhiBb2pJche9rYgN9ztw0oHPM/qIV94pZ7tpDtu5Gt8ltYbW0KRQR0aqhhgysR+i 96jW2TYI8zXT4NDOgYT2kXRGD5e99XIW+pc9TPDwafZwIOOHk/lGPh0W2yoM+U963CVjuhDOz4 eKtDB7CzRRC8fqOydfY1lt1mhPrIF3HDi5UKuKtvNS1mPenXZP8o5VkzhAZQcHUCrWBvzp8lEH +LM= From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Thu, 15 Aug 2019 14:34:55 -0700 Message-Id: <59bed3d7342ef7513a60285e2711c162be5559fc.1565904855.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [PATCH v3 4/7] target/riscv: Update the Hypervisor CSRs to v0.4 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Update the Hypervisor CSR addresses to match the v0.4 spec. Signed-off-by: Alistair Francis Reviewed-by: Chih-Min Chao Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 11f971ad5d..e99834856c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -173,6 +173,24 @@ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 =20 +/* Hpervisor CSRs */ +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HCOUNTERNEN 0x606 +#define CSR_HGATP 0x680 + +#if defined(TARGET_RISCV32) +#define HGATP_MODE SATP32_MODE +#define HGATP_VMID SATP32_ASID +#define HGATP_PPN SATP32_PPN +#endif +#if defined(TARGET_RISCV64) +#define HGATP_MODE SATP64_MODE +#define HGATP_VMID SATP64_ASID +#define HGATP_PPN SATP64_PPN +#endif + /* Physical Memory Protection */ #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 @@ -206,23 +224,6 @@ #define CSR_DPC 0x7b1 #define CSR_DSCRATCH 0x7b2 =20 -/* Hpervisor CSRs */ -#define CSR_HSTATUS 0xa00 -#define CSR_HEDELEG 0xa02 -#define CSR_HIDELEG 0xa03 -#define CSR_HGATP 0xa80 - -#if defined(TARGET_RISCV32) -#define HGATP_MODE SATP32_MODE -#define HGATP_ASID SATP32_ASID -#define HGATP_PPN SATP32_PPN -#endif -#if defined(TARGET_RISCV64) -#define HGATP_MODE SATP64_MODE -#define HGATP_ASID SATP64_ASID -#define HGATP_PPN SATP64_PPN -#endif - /* Performance Counters */ #define CSR_MHPMCOUNTER3 0xb03 #define CSR_MHPMCOUNTER4 0xb04 --=20 2.22.0 From nobody Mon May 6 23:50:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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IronPort-SDR: 6b202trFfzjs9jZURU5lwymA2ZvutzcjLCrKvqipKjr3W6ZIRj9WyVS9a/Rn8LH4bVawQhhSzN q/YjWKPA+0tf41RnZ+Hbe7q4yYfTYj0Oe9/b5+gPvo5HVcT+8J33RDDUaHG7PFZEAsWYkqFMbi tGPf2RYDqVRGL9BAbBDaNaPkuTiW0Ui3+uMuJ/F7Sl15NCN9JVLQu1SVNbegJYwb3FbjT7u2in 9EnUFFDiFRckeukPtXrOywDNMcPc2bKOgNakRxvyBRuwcuC0qU7cupw/Ccm2UlhcS6mBDAqarw Wq8= X-IronPort-AV: E=Sophos;i="5.64,389,1559491200"; d="scan'208";a="116881534" IronPort-SDR: yJR1Pa9MBr/wJFMlUOUIJuhGb0BvCvetNhgU+i9FpYMmBr+wsF0PC5P3Y73CYJMRQyI9koXg6A er/vxE+yAnfeG0JiT8ZaEHgb+5lBgwOU1x1Ua5zSQlBvjKrTcm3/C+I+1dR/Wm7aivJFXp6SPW N0c5jlreHM+0SFczFNbH+jZW2jl1RgsZTIEgyj8pimmLL0WSh20zITd7aStQ/2lmL0MC7npdui IPqi3nrYxP4llG+vgtdnW66p4LfhdrEb4zO4Q9PlB8LQDG9PCI7oN+/vkl4M+Z3rDwOklbekcB Flm0xAuCnO9QIHn14OeYVFfK IronPort-SDR: V2vvTOk6ru8JxSH+sR112EuuW5S8h9s/4YFK6581kaJxrPM67zspPCDzyVgfR6Auy02rEcBbgi ei6O7O3I8DvZHtJQHSuNlaUp6Q5GpjrTl2b//TYr6iPHksEffQ5Do3XzW4k1u1ec5p3pGhQJhs 1MTZbXpqvb33XcVfUR+E7az+VFTFOYNUgNjF/e6Kb5ZJwOdpXNHzrfEFb+3u85nRJSVrtbNtDT fTn5sGvkLZ59BjgI5tUzgAkQny160yCpgHCSDPhCIhTcuP/EZnzLTM0ZjV9Df54fo+FiYVoK/A aZY= From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Thu, 15 Aug 2019 14:34:58 -0700 Message-Id: <4c3b0d0df95674ab0c049b75506f3ee3237ea14b.1565904855.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [PATCH v3 5/7] target/riscv: Use both register name and ABI name X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Atish Patra Use both the generic register name and ABI name for the general purpose registers and floating point registers. Signed-off-by: Atish Patra Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f8d07bd20a..60b95daf60 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -33,17 +33,20 @@ static const char riscv_exts[26] =3D "IEMAFDQCLBJTPVNSUHKORWXYZG"; =20 const char * const riscv_int_regnames[] =3D { - "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", - "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", - "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", - "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" + "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", + "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", + "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", + "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", + "x28/t3", "x29/t4", "x30/t5", "x31/t6" }; =20 const char * const riscv_fpr_regnames[] =3D { - "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", - "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", - "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", - "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" + "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", + "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", + "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", + "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", + "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", + "f30/ft10", "f31/ft11" }; =20 const char * const riscv_excp_names[] =3D { --=20 2.22.0 From nobody Mon May 6 23:50:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1565905280; cv=none; d=zoho.com; s=zohoarc; b=mf2gIrYyiY8bbe7j12wkzhpviwaxLi4aL5svpBx98I4Mxdx37DInfDGOqqBwHGnhLRySf/s4QUl+wC2jCfuToPjci1+ihDPCdSF9C2BqClKP320uTp+yQ57hc5CW9lgbsJU+lzqU0Swi3r9OqLOVFVev5vH9KaxJr5+lR80e5T8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565905280; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 2789215b5e..f767ad24be 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -335,7 +335,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) * RV32: MPV and MTL are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. */ - mask |=3D MSTATUS_MPP | MSTATUS_MPV; + mask |=3D MSTATUS_MTL | MSTATUS_MPV; #endif } =20 --=20 2.22.0 From nobody Mon May 6 23:50:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1565905443; cv=none; d=zoho.com; s=zohoarc; b=PO05fOlsrcYWb5SBlPHP2lTOoU4DjS8NGqbrbf4u4fRlQ569ZH5wUWgsOHN9OeYyeiskIQrLi9CG9RQMRJlBLMZIvyB7wWPpQ0uQsOhHVBO/eJyfvaKKJtGPPoY4L0K2ikAt6jsiyLj6H5ZAoQ1bc+M7NMwSJTQvluBsQIAS2KI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; 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d="scan'208";a="116881542" IronPort-SDR: m0A5vs/dSkhZpwa1MJBenFoZaUmjcunxwJyvHwUoWaTI1jxnREBj+RWdbS95g+KLs4u3U35xF1 ZGh/XlIbZsr8ehhJmcv8hNc04FOG5ebIakFHlNLGU7Of5IjqJLBX+/OE3r0WjLyRmwWoXP20Tg TD+Y3agbgFGLwtDJVqj4Kjh22OaZzdjzfOky88K4CVe1CE+bDJn3Z/fQ/srtUEvBDX2eK+H/B5 c+41YMPccrDIGUiEz8uBNcjEZVomiHIZutDVcf+4Hco3uS2ph+U+78NDf9pCnmHZNf/O/AFUN9 L/DsW85NF9fl8X7/Q6J6rGTH IronPort-SDR: 4HPxB2ojzz9R0wPEaoxKVEftqx7w39CUOQ78zDob1dWCJzsUuoBXmShxQ5bz1UzqoOP5mHBIQO bTnqN5TSyIVZncSRUZLnQ6TIirNfqOahvqJc0VdtbcHCpaVMe9f9fYR7mjzsZurWmvzp5Yojfg SOoao3SU9zQbydYU7WFxf8dRqeCHb5kMqikPyD96tTfL0v3WbDHDOm8wklccTzGgKRaeFZRlxj TsYBLrHNrjvss5qYFz4cG1LXqaQF8gGOAVBfiUW6dZrW9kQKhcZqa2d7wYouYhKv6sW5Y5VADh oC4= From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Thu, 15 Aug 2019 14:35:04 -0700 Message-Id: <7e476df36a8c2ba53162e9a5f62e9fa171da00ad.1565904855.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The mip register is an MXLEN-bit long register. Convert it to a target_ulong type instead of uint32_t. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2dc9b17678..0a7985c3f7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -130,7 +130,7 @@ struct CPURISCVState { * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-ze= ro. * mip is 32-bits to allow atomic_read on 32-bit hosts. */ - uint32_t mip; + target_ulong mip; uint32_t miclaim; =20 target_ulong mie; --=20 2.22.0