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charset="utf-8" Setting write permission on dirty PTEs results in userspace inside a Hypervisor guest (VU) becoming corrupted. This appears to be becuase it ends up with write permission in the second stage translation in cases where we aren't doing a store. Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e32b6126af..f027be7f16 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -340,10 +340,8 @@ restart: if ((pte & PTE_X)) { *prot |=3D PAGE_EXEC; } - /* add write permission on stores or if the page is already di= rty, - so that we TLB miss on later writes to update the dirty bit= */ - if ((pte & PTE_W) && - (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_D))) { + /* add write permission on stores */ + if ((pte & PTE_W) && (access_type =3D=3D MMU_DATA_STORE)) { *prot |=3D PAGE_WRITE; } return TRANSLATE_SUCCESS; --=20 2.22.0 From nobody Thu May 2 17:02:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" The privledge check based on the CSR address mask 0x300 doesn't work when using Hypervisor extensions so remove the check Signed-off-by: Alistair Francis --- target/riscv/csr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e0d4586760..af3b762c8b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -797,9 +797,8 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_u= long *ret_value, =20 /* check privileges and return -1 if check fails */ #if !defined(CONFIG_USER_ONLY) - int csr_priv =3D get_field(csrno, 0x300); int read_only =3D get_field(csrno, 0xC00) =3D=3D 3; - if ((write_mask && read_only) || (env->priv < csr_priv)) { + if (write_mask && read_only) { return -1; } #endif --=20 2.22.0 From nobody Thu May 2 17:02:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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IronPort-SDR: sx1mJopsky+qJZlGx+Y6zFilryfY8gaXmu8Vb2YDmtCsI+Lmgpax8x2eQpEYm5bw3OU9bZq2n1 HB1/dbUokGoO4y3SZeFmi+QXOGk6YgNdeFPbAxB7jjuyT/AogQ+WjoI0OoMAkTjx3N8quPjIGq BW7PaFahtSmLWNx6UZidW01+sIDxOqLtD68Hj7cdhsWQL5lIaaNIDOiRHbx0I2mFdylhDi2yPl sja6QKjalHkcrxdY6wvZFKgavOaEyEDgA0DbQcSDJLGWMe44mdLVJ8Cf9mAtJppLhwRmQH/qkq kBQ= X-IronPort-AV: E=Sophos;i="5.64,307,1559491200"; d="scan'208";a="220533146" IronPort-SDR: 99HHwb4xkZtL5/ni0EKtolBE9EMSV/IVhAcgybQaFUxXAKFs/GM+rqj0US19d/ROQzdpxwWYCO SBJoRpyitQKEZNPv7qqvfrsc+lKH6hrvoeHON7IL7xJGQxDXN1KICajkePwuupJnPcb0PVTbFf OmSZcxKeHd/XqAazqBGu7pcdYyFKMv0Sb48O4uxGfX4QXH6zP6sIZyksal7z5SwvB9MDBJBhHs AskGjYehkQMloMuYQ/uieNyGVongNqTVByWZo5NvwjGb9TLmSysGRXaeGMOKDvsscw38NKvm0w tBg0IuzeClDv+Lh0dWnZOrri IronPort-SDR: s8+XNtcn5cE//zb7iXmq1VV3grqsx0CFxxwZmbXymO89CoKnSBRljAW0CDlTbJtal3xZ8l7Bek RNK7B2JYr2L8kjc9WGwpoixRQ36+WSHLPd/3fgPPlLZ+ua3oAbfDNVdR7uU0Kz7aft1ZV/ivhJ i90tCx/J5KWV9xDBokSdJ+4RhDd08Kq5e9gjzckiZRL4VRQcz10TRCYx854A4BOlSMGWL8UcOe JOYTIftezUdh1AeTu+o6XE4DTtI8Q41vNE9Jc9zb7TrE62CfJoIvXoAtJhc0aa4zkwRFORzbeb MGQ= From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Thu, 25 Jul 2019 11:52:06 -0700 Message-Id: <50c1c6a3ace8b40f7b9d5395a2c3457cf1852721.1564080680.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [PATCH-4.2 v1 3/6] riscv: plic: Remove unused interrupt functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Chih-Min Chao Reviewed-by: Jonathan Behrens Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/sifive_plic.c | 12 ------------ include/hw/riscv/sifive_plic.h | 3 --- 2 files changed, 15 deletions(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 0950e89e15..864a1bed42 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -161,18 +161,6 @@ static void sifive_plic_update(SiFivePLICState *plic) } } =20 -void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq) -{ - sifive_plic_set_pending(plic, irq, true); - sifive_plic_update(plic); -} - -void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq) -{ - sifive_plic_set_pending(plic, irq, false); - sifive_plic_update(plic); -} - static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid) { int i, j; diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h index ce8907f6aa..3b8a623919 100644 --- a/include/hw/riscv/sifive_plic.h +++ b/include/hw/riscv/sifive_plic.h @@ -69,9 +69,6 @@ typedef struct SiFivePLICState { uint32_t aperture_size; } SiFivePLICState; =20 -void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq); -void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq); - DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, uint32_t num_sources, uint32_t num_priorities, uint32_t priority_base, uint32_t pending_base, --=20 2.22.0 From nobody Thu May 2 17:02:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1564080999; cv=none; d=zoho.com; s=zohoarc; b=JD9MVLZVfT5Z7B280q5qi2TLkwoppjTKfmip7f34ptBiRrcj6Payp5ywnGPBkmIhtN8SpZ3yFw5T0qXZkd0yX7LslZ226zKOY8bYIF4wZ83KdV+umm4MZ+9qE95LiLso5jEFGRl3JlEB4avViocIzk9yrFmd4q+24ZqMAG+ypJ8= ARC-Message-Signature: i=1; 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d="scan'208";a="220533152" IronPort-SDR: 6y2TJXBsXJqiEW7H0IRlq8Gskl5uch3EpqHnUox44uUXpuVjrMcgiSo/3M1oPeT9Yil5S4bXPH BR6IiuYvPTlyUtF2UuA/refABNY3h8vII2A07FOAd8tkz3SnkDzEkZoiJuAUO3gSbba2ElOej7 8gMKZAEenOh9WhkaTFLuMT3HhVY6Zi2uhdC6iVp8cNgi/GqRyuPqqinMrrQ5DaO/HFW/RhhJa/ qnG5l2CpicYwZSOATvE/zJ6c/Az/0PYd/ACH+uvuMnMhIrz903S9nhkZ770yR7PFrTE6YTLh+Y 94/EicYVH3pYdkyKZwlhBoXt IronPort-SDR: Qs4z0ii4JlUtoiuWAbDhT2dVcrzxC5KgxljZIBBHzsShmFcMNR1Svufr2yzwVE/wTPPlnV7NDb nyDLk5KKSUow65YgIdu0VAIOI9wRR3nhJ15ES7eLLAEs/LCK/rfaFUfX6oXCw9bG/T23XBucR3 WeEx4O6M+WgHVgdCvYZBVhbarjTLVIh38Pl/WQg+XGCf7wRQv2QZbd6/1EsUuDol67anLs06/S I8cDhV/dU3XA0+0+2+HbXN8VhZnyN/rBF+50LyYIJBSLER6unQgd1WoEEGji7vwN1Vu8jGDrHP Qpc= From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Thu, 25 Jul 2019 11:52:09 -0700 Message-Id: X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [PATCH-4.2 v1 4/6] target/riscv: Create function to test if FP is enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Let's creaate a function that tests if floating point support is enabled. We can then protect all floating point operations based on if they are enabled. This patch so far doesn't change anything, it's just preparing for the Hypervisor support for floating point operations. Signed-off-by: Alistair Francis Reviewed-by: Christophe de Dinechin Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 6 +++++- target/riscv/cpu_helper.c | 10 ++++++++++ target/riscv/csr.c | 19 ++++++++++--------- 3 files changed, 25 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0adb307f32..2dc9b17678 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -255,6 +255,7 @@ void riscv_cpu_do_interrupt(CPUState *cpu); int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); +bool riscv_cpu_fp_enabled(CPURISCVState *env); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, @@ -298,7 +299,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState = *env, target_ulong *pc, #ifdef CONFIG_USER_ONLY *flags =3D TB_FLAGS_MSTATUS_FS; #else - *flags =3D cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); + *flags =3D cpu_mmu_index(env, 0); + if (riscv_cpu_fp_enabled(env)) { + *flags |=3D env->mstatus & MSTATUS_FS; + } #endif } =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f027be7f16..225e407cff 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -71,6 +71,16 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) =20 #if !defined(CONFIG_USER_ONLY) =20 +/* Return true is floating point support is currently enabled */ +bool riscv_cpu_fp_enabled(CPURISCVState *env) +{ + if (env->mstatus & MSTATUS_FS) { + return true; + } + + return false; +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env =3D &cpu->env; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index af3b762c8b..7b73b73cf7 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -46,7 +46,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *o= ps) static int fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -108,7 +108,7 @@ static int pmp(CPURISCVState *env, int csrno) static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -119,7 +119,7 @@ static int read_fflags(CPURISCVState *env, int csrno, t= arget_ulong *val) static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } env->mstatus |=3D MSTATUS_FS; @@ -131,7 +131,7 @@ static int write_fflags(CPURISCVState *env, int csrno, = target_ulong val) static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -142,7 +142,7 @@ static int read_frm(CPURISCVState *env, int csrno, targ= et_ulong *val) static int write_frm(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } env->mstatus |=3D MSTATUS_FS; @@ -154,7 +154,7 @@ static int write_frm(CPURISCVState *env, int csrno, tar= get_ulong val) static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -166,7 +166,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, tar= get_ulong *val) static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } env->mstatus |=3D MSTATUS_FS; @@ -307,6 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) { target_ulong mstatus =3D env->mstatus; target_ulong mask =3D 0; + int dirty; =20 /* flush tlb on mstatus fields that affect VM */ if (env->priv_ver <=3D PRIV_VERSION_1_09_1) { @@ -340,8 +341,8 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) =20 mstatus =3D (mstatus & ~mask) | (val & mask); =20 - int dirty =3D ((mstatus & MSTATUS_FS) =3D=3D MSTATUS_FS) | - ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); + dirty =3D riscv_cpu_fp_enabled(env) | + ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); mstatus =3D set_field(mstatus, MSTATUS_SD, dirty); env->mstatus =3D mstatus; =20 --=20 2.22.0 From nobody Thu May 2 17:02:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1564080953; cv=none; d=zoho.com; s=zohoarc; b=Dl2HeazxNsPfBjlc2rnAqLYOjhk2qXo84QiECmRVGa75JWLEFNRqOJmY3LeiDVFt/2ETXghVJPCaTWsh6nF5Np6jEY+r5vJRs2ynRbBC48+pCTFEAiC/sJrq6mtEdBTArRvlB+5UP65UY5S4hW44fdWLh6oW9WyBJtRS14ZdEnA= ARC-Message-Signature: i=1; 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d="scan'208";a="220533155" IronPort-SDR: 5u5P+dfHlTtuVgL3H+lAQ7y6cBYlBhPe35WYmZSE8wjIENclUrmeU42EHHXUnB5brMkQ9a69+u FvQt18W+1BwqpKNFuE19EgCg7yODXOLbth0f4bqzzDh82XTnMSaI9CofVgts/j6oKRl4xRyVUz 7D8BU4+XNhCwx2loZC+pssb8FKNdndTbpd9SI8YFH4wKO6JCexRVtHY3fw04bQLBUmNWW0XoMr GgDMzQ6X8dyz5UKqldlg1wwkWASUdbyAWDnVheSNHirDOXl6ozf86uWbHPDHXABarA4SskHyC7 6oim8wlG1gR+njKG6YMcbMla IronPort-SDR: q+bikiQR1S/9+EoqdJTPVwPhULlr1b3s96U0jojqqRiXdQNiQtq+Y88KYkyYTOG/4e7TbFfy2z BvZd9EsYwOQAHFXoTc+KORdVAGUFM25Yc1XFK8z4i4Yx3l7MnLdrq+5ILaiN+i5esPxPuRwPGj 0Qs0ha+EKUnGxF+/fyr/z6WOAtZSjSNX16EyNp1vk9zO9yEtwzB5YXA1exQ8QXRrIvXty//Oba Mb7eD8AeqmWquGrahC2ku/QFkmXbArlqAUXlySJUfF74J2IVr21H6grBGeGAxqnytkl1mWKHWx myY= From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Thu, 25 Jul 2019 11:52:11 -0700 Message-Id: <10db21dad60854653b7b6272a44a63e2473af2b0.1564080680.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [PATCH-4.2 v1 5/6] target/riscv: Update the Hypervisor CSRs to v0.4 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Update the Hypervisor CSR addresses to match the v0.4 spec. Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 11f971ad5d..97b96c4e19 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -173,6 +173,24 @@ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 =20 +/* Hpervisor CSRs */ +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HCOUNTERNEN 0x606 +#define CSR_HGATP 0x680 + +#if defined(TARGET_RISCV32) +#define HGATP_MODE SATP32_MODE +#define HGATP_ASID SATP32_ASID +#define HGATP_PPN SATP32_PPN +#endif +#if defined(TARGET_RISCV64) +#define HGATP_MODE SATP64_MODE +#define HGATP_ASID SATP64_ASID +#define HGATP_PPN SATP64_PPN +#endif + /* Physical Memory Protection */ #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 @@ -206,23 +224,6 @@ #define CSR_DPC 0x7b1 #define CSR_DSCRATCH 0x7b2 =20 -/* Hpervisor CSRs */ -#define CSR_HSTATUS 0xa00 -#define CSR_HEDELEG 0xa02 -#define CSR_HIDELEG 0xa03 -#define CSR_HGATP 0xa80 - -#if defined(TARGET_RISCV32) -#define HGATP_MODE SATP32_MODE -#define HGATP_ASID SATP32_ASID -#define HGATP_PPN SATP32_PPN -#endif -#if defined(TARGET_RISCV64) -#define HGATP_MODE SATP64_MODE -#define HGATP_ASID SATP64_ASID -#define HGATP_PPN SATP64_PPN -#endif - /* Performance Counters */ #define CSR_MHPMCOUNTER3 0xb03 #define CSR_MHPMCOUNTER4 0xb04 --=20 2.22.0 From nobody Thu May 2 17:02:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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IronPort-SDR: 3U+L11vXi7BcPCiwhAK9ztxiKoMCv1n6Vzygnqiqj3Fkml5859yH39k6OI4yC9Uiq3MzuZWk5W VF0kn92SdVR+nRTi1zcO747qQvG9MfM+mTgdlpw7NHp+ciILVb9WnokNvh2AW7dGP1CCqiRx1L YMPC95ecQczW5Vj79o92BLcBVgbBYl0yrU+mIrG15YNfqp7KUwBuCBGniLqXQgSUgygLnuRUdv A5Enklz72dZaLfPCJvu9+1729eelrsNvNTgo30tvf6l/nTC1BodLP4QIkzHWWcLdSWSdEuMKUA olI= X-IronPort-AV: E=Sophos;i="5.64,307,1559491200"; d="scan'208";a="115109069" IronPort-SDR: lhXjGBIP1sEA8PwGoQ0oPABExk0ow3XaZdYB/pl1x1si3frnyg784YBQvec1AfMFtse4xovPx7 +7dBgUVPMz6aG+M54S08NAS3yFrPOVpi1zb2pBz12hU4mQGqNfe6a6xIlMwAXd59xqfI6CqRfz Vl2m00mDKF76+/LHgvl+QkP/hM98LWh2vw0YnfivXEkA6lGbv6vHn/JK3Y/b/CPxgn2r5mN9VQ GBoBYcFl47NzUuX/yEyQFc66PEU5gF3wcVa6gbDYcM/sEsXh2S/Wnxd49oCvzs9utu9POtOCxi J2XrSw+5cuRaVgmLav0STxo7 IronPort-SDR: E8ifU7kZm71V8FGinzNexRn2uMalZnkYLqnTQY6H2JALVJURBjQqSuzdCwUYmpcEFfEcEVxIUy 0iR8bTLGyR7a6SbT4KE42K/ku16IrDt/v5lIzNOIUYX7YLj/odEJtkEvUHPh5McDHjWL7mY3qP mgV5MnP50DaJjFKYyaYnWSK7zNv+T9z7O1urTVogGV3OXdUenRXcEpwZs09DcGK77KRQ6uZjMr ZxDPMyyurwEtAMEPoavogZkeHJIIRPCOzWaqAaFCrUdNYbXdvHUICKQcaK4VAAa8omV1QScliu RUs= From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Thu, 25 Jul 2019 11:52:14 -0700 Message-Id: <4116c27c037b5e7f4822cfd7199724450dc6b5da.1564080680.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [PATCH-4.2 v1 6/6] target/riscv: Fix Floating Point register names X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Atish Patra As per the RISC-V spec, Floating Point registers are named as f0..f31 so lets fix the register names accordingly. Signed-off-by: Atish Patra Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f8d07bd20a..af1e9b7690 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -40,10 +40,10 @@ const char * const riscv_int_regnames[] =3D { }; =20 const char * const riscv_fpr_regnames[] =3D { - "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", - "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", - "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", - "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" }; =20 const char * const riscv_excp_names[] =3D { --=20 2.22.0