From nobody Sun May 19 08:30:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1562152069; cv=none; d=zoho.com; s=zohoarc; b=STaMuvR7r1SqJpNfotez0+P7tzHnirzJqoAU/kMCAKVpTUvVh/iVP7o9fa+5HVLPDh+qvRnuZuI31RV4WGy7Rmf/Y1igIleZxoMTdplf6iave/tUJBdO+9Dx+W3z7cSwTvzYSnwUnNpzcCpRiorp5Chb9Dn28DIHvAtqJ9SlNH4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562152069; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=8M100xGr92RX0swSJ6YayKzQzfEcMCYqljsvK9HtFVU=; b=ba38VKfvcGFDMVIlMuycl2Ua3BQjXIc4YespXHKG0Uut12keerB5h+k42kv852VBZKImUXdO29wdduzDqfWy869KZ4iPpDn9b75fli3VYZHaMRkYXis5/e2BvMhM6ETJoxv+1CkTdII9xYM3hJ9IexhgMjW8HUIbmYmwRVnNLTc= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562152069803874.7115962906271; Wed, 3 Jul 2019 04:07:49 -0700 (PDT) Received: from localhost ([::1]:34912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hid76-0007S4-Qv for importer@patchew.org; Wed, 03 Jul 2019 07:07:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59961) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hid1E-0000mE-Og for qemu-devel@nongnu.org; Wed, 03 Jul 2019 07:01:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hid1D-0005EK-Bd for qemu-devel@nongnu.org; Wed, 03 Jul 2019 07:01:44 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:44208) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hid1C-00054V-RV for qemu-devel@nongnu.org; Wed, 03 Jul 2019 07:01:43 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 9E4787461AA; Wed, 3 Jul 2019 13:01:38 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 149AA7462AA; Wed, 3 Jul 2019 13:01:38 +0200 (CEST) Message-Id: <04b67ff483223d4722b0b044192558e7d17b36b5.1562151410.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Wed, 03 Jul 2019 12:56:50 +0200 MIME-Version: 1.0 To: qemu-devel@nongnu.org Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:738:2001:2001::2001 Subject: [Qemu-devel] [PATCH 1/3] ati-vga: Improve readability of ati_2d_blt function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Gerd Hoffmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Move common parts before the switch to remove code duplication and improve readibility. Signed-off-by: BALATON Zoltan --- hw/display/ati_2d.c | 80 ++++++++++++++++++++++---------------------------= ---- 1 file changed, 33 insertions(+), 47 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 2dbf53f039..c31142af6e 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -42,6 +42,8 @@ static int ati_bpp_from_datatype(ATIVGAState *s) } } =20 +#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CN= TL) + void ati_2d_blt(ATIVGAState *s) { /* FIXME it is probably more complex than this and may need to be */ @@ -51,6 +53,22 @@ void ati_2d_blt(ATIVGAState *s) s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), surface_bits_per_pixel(ds), (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); + int bpp =3D ati_bpp_from_datatype(s); + int dst_stride =3D DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_= pitch; + uint8_t *dst_bits =3D s->vga.vram_ptr + (DEFAULT_CNTL ? + s->regs.dst_offset : s->regs.default_offset); + + if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { + dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; + dst_stride *=3D bpp; + } + uint8_t *end =3D s->vga.vram_ptr + s->vga.vram_size; + if (dst_bits >=3D end || + dst_bits + s->regs.dst_x + (s->regs.dst_y + s->regs.dst_height) * + dst_stride >=3D end) { + qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); + return; + } DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d\n", s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset, s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch, @@ -59,41 +77,28 @@ void ati_2d_blt(ATIVGAState *s) switch (s->regs.dp_mix & GMC_ROP3_MASK) { case ROP3_SRCCOPY: { - uint8_t *src_bits, *dst_bits, *end; - int src_stride, dst_stride, bpp =3D ati_bpp_from_datatype(s); - src_bits =3D s->vga.vram_ptr + - (s->regs.dp_gui_master_cntl & GMC_SRC_PITCH_OFFSET_CNTL= ? - s->regs.src_offset : s->regs.default_offset); - dst_bits =3D s->vga.vram_ptr + - (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL= ? - s->regs.dst_offset : s->regs.default_offset); - src_stride =3D (s->regs.dp_gui_master_cntl & GMC_SRC_PITCH_OFFSET_= CNTL ? - s->regs.src_pitch : s->regs.default_pitch); - dst_stride =3D (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_= CNTL ? - s->regs.dst_pitch : s->regs.default_pitch); + int src_stride =3D DEFAULT_CNTL ? + s->regs.src_pitch : s->regs.default_pitch; + uint8_t *src_bits =3D s->vga.vram_ptr + (DEFAULT_CNTL ? + s->regs.src_offset : s->regs.default_offset); =20 if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { src_bits +=3D s->regs.crtc_offset & 0x07ffffff; - dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; src_stride *=3D bpp; - dst_stride *=3D bpp; } + if (src_bits >=3D end || + src_bits + s->regs.src_x + (s->regs.src_y + s->regs.dst_height= ) * + src_stride >=3D end) { + qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); + return; + } + src_stride /=3D sizeof(uint32_t); dst_stride /=3D sizeof(uint32_t); - DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d= )\n", src_bits, dst_bits, src_stride, dst_stride, bpp, bpp, s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y, s->regs.dst_width, s->regs.dst_height); - end =3D s->vga.vram_ptr + s->vga.vram_size; - if (src_bits >=3D end || dst_bits >=3D end || - src_bits + s->regs.src_x + (s->regs.src_y + s->regs.dst_height= ) * - src_stride * sizeof(uint32_t) >=3D end || - dst_bits + s->regs.dst_x + (s->regs.dst_y + s->regs.dst_height= ) * - dst_stride * sizeof(uint32_t) >=3D end) { - qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); - return; - } pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits, src_stride, dst_stride, bpp, bpp, s->regs.src_x, s->regs.src_y, @@ -115,20 +120,7 @@ void ati_2d_blt(ATIVGAState *s) case ROP3_BLACKNESS: case ROP3_WHITENESS: { - uint8_t *dst_bits, *end; - int dst_stride, bpp =3D ati_bpp_from_datatype(s); uint32_t filler =3D 0; - dst_bits =3D s->vga.vram_ptr + - (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL= ? - s->regs.dst_offset : s->regs.default_offset); - dst_stride =3D (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_= CNTL ? - s->regs.dst_pitch : s->regs.default_pitch); - - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; - dst_stride *=3D bpp; - } - dst_stride /=3D sizeof(uint32_t); =20 switch (s->regs.dp_mix & GMC_ROP3_MASK) { case ROP3_PATCOPY: @@ -144,22 +136,16 @@ void ati_2d_blt(ATIVGAState *s) break; } =20 + dst_stride /=3D sizeof(uint32_t); DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n", dst_bits, dst_stride, bpp, s->regs.dst_x, s->regs.dst_y, s->regs.dst_width, s->regs.dst_height, filler); - end =3D s->vga.vram_ptr + s->vga.vram_size; - if (dst_bits >=3D end || - dst_bits + s->regs.dst_x + (s->regs.dst_y + s->regs.dst_height= ) * - dst_stride * sizeof(uint32_t) >=3D end) { - qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); - return; - } pixman_fill((uint32_t *)dst_bits, dst_stride, bpp, - s->regs.dst_x, s->regs.dst_y, - s->regs.dst_width, s->regs.dst_height, - filler); + s->regs.dst_x, s->regs.dst_y, + s->regs.dst_width, s->regs.dst_height, + filler); if (dst_bits >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset= ) { --=20 2.13.7 From nobody Sun May 19 08:30:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1562152186; cv=none; d=zoho.com; s=zohoarc; b=LsgJqC5STu6xlw/Bz9EUI/XBPOM/6btzLlNEH219aWUiCeYuARIBmj17ck0P8FYxsODNfzCwJQsnNCe03ang1okF127MwLNRS9FnpwGSr3W5/tOFbK/x65CfOWrol+5FUeFKKiIOwVtaZrhTt4640MabaPMJqytfX2zD7NmIO7o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562152186; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=LwjGbyKdKcOMHj/EQXfTNHcGlG9Q1JiF9j8yag8oPxw=; b=Zv93DILmapCzRFuvulDNSPegYyg2mz5BR48XHtkmz4G9P62uZuGEpC1t2pNdpIEQ8jDeLoNReKXdHAJ3Flj2E7CWAqeammfdsYcMZXeA2dzpETLnzIZKwNuuC43VkT68XF5ehU4wZAHCBaa4bRlDU3uGj5ZAawZXuq3+LI40B70= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562152186219242.93596701806757; Wed, 3 Jul 2019 04:09:46 -0700 (PDT) Received: from localhost ([::1]:34930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hid8n-0001AL-Sx for importer@patchew.org; Wed, 03 Jul 2019 07:09:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59958) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hid1E-0000le-Gq for qemu-devel@nongnu.org; Wed, 03 Jul 2019 07:01:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hid1D-0005EF-As for qemu-devel@nongnu.org; Wed, 03 Jul 2019 07:01:44 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:44209) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hid1C-00054W-Ua for qemu-devel@nongnu.org; Wed, 03 Jul 2019 07:01:43 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 9FD097461AE; Wed, 3 Jul 2019 13:01:38 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 257447462BB; Wed, 3 Jul 2019 13:01:38 +0200 (CEST) Message-Id: <439aa85061f103446df7b42632d730971a372432.1562151410.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Wed, 03 Jul 2019 12:56:50 +0200 MIME-Version: 1.0 To: qemu-devel@nongnu.org Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:738:2001:2001::2001 Subject: [Qemu-devel] [PATCH 2/3] ati-vga: Fix frame buffer endianness for big endian target X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Gerd Hoffmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The extended mode frame buffer should be little endian even when emulating big endian machine (such as PPC). This fixes color problems with MorphOS. Signed-off-by: BALATON Zoltan --- hw/display/ati.c | 1 + hw/display/ati_2d.c | 10 +++++----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index c1d9d1518f..590362ea56 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -89,6 +89,7 @@ static void ati_vga_switch_mode(ATIVGAState *s) DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, = offs); vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED); + s->vga.big_endian_fb =3D false; /* reset VBE regs then set up mode */ s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] =3D h; s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] =3D v; diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index c31142af6e..b09753320a 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -124,15 +124,15 @@ void ati_2d_blt(ATIVGAState *s) =20 switch (s->regs.dp_mix & GMC_ROP3_MASK) { case ROP3_PATCOPY: - filler =3D bswap32(s->regs.dp_brush_frgd_clr); + filler =3D s->regs.dp_brush_frgd_clr; break; case ROP3_BLACKNESS: - filler =3D rgb_to_pixel32(s->vga.palette[0], s->vga.palette[1], - s->vga.palette[2]) << 8 | 0xff; + filler =3D 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[0], + s->vga.palette[1], s->vga.palette[2]); break; case ROP3_WHITENESS: - filler =3D rgb_to_pixel32(s->vga.palette[3], s->vga.palette[4], - s->vga.palette[5]) << 8 | 0xff; + filler =3D 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[3], + s->vga.palette[4], s->vga.palette[5]); break; } =20 --=20 2.13.7 From nobody Sun May 19 08:30:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1562152066; cv=none; d=zoho.com; s=zohoarc; b=ImLZWTInyDgXcCum9UlTUV7v8BpQuAzfAlnBrDj6h8Dicdx1L6MwHdFa8ojz/DjEUzaD42kN90faw+z8SGfFLHTmUR4FGRVJjQWCK7l8ZbKLhx5ZS4WJnEAcULuPaihqx3gKocCeO+3bkZTUecDrIeLGpFUohULkfNlyY0wOKrs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562152066; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=vn5VQ8+Pfpepz2r1wPFGt5Chd4MXS4kPanK0k1cKnW8=; b=lCv11PjbxodkNFjMVsCLXnP7MdAyPBb4Okpdpcf29U8yRv4lVzMJ1o8KFZjWK0QcMJrA85sSDeA0R3yNJWjXG9+RKWCIhR0WvbGlh/9I4kFzBx/D2iCky9drMNGSSmDoNHHQO3qj1Z61U/I8Iy/uejtBZdj6Be/h4wEqOW1xNk0= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562152066107576.2245036850252; Wed, 3 Jul 2019 04:07:46 -0700 (PDT) Received: from localhost ([::1]:34908 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hid72-0007ER-MX for importer@patchew.org; Wed, 03 Jul 2019 07:07:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59974) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hid1F-0000oX-Uo for qemu-devel@nongnu.org; Wed, 03 Jul 2019 07:01:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hid1D-0005ER-BT for qemu-devel@nongnu.org; Wed, 03 Jul 2019 07:01:44 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:44210) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hid1C-00054c-RV for qemu-devel@nongnu.org; Wed, 03 Jul 2019 07:01:43 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id A88937462B7; Wed, 3 Jul 2019 13:01:38 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 1FE477462B8; Wed, 3 Jul 2019 13:01:38 +0200 (CEST) Message-Id: <045b82d2c5167e0b2a23dfbf8a80085b0550e4ca.1562151410.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Wed, 03 Jul 2019 12:56:50 +0200 MIME-Version: 1.0 To: qemu-devel@nongnu.org Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:738:2001:2001::2001 Subject: [Qemu-devel] [PATCH 3/3] ati-vga: Fix reverse bit blts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Gerd Hoffmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The pixman library only supports blts with left to right, top to bottom order but the ATI VGA engine can also do different directions. Fix support for these via a temporary buffer for now. This fixes rendering issues related to such blts (such as moving windows) but some other glitches still remain. Signed-off-by: BALATON Zoltan --- hw/display/ati_2d.c | 53 ++++++++++++++++++++++++++++++++++++++-----------= ---- 1 file changed, 38 insertions(+), 15 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index b09753320a..07a776c31d 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -53,6 +53,10 @@ void ati_2d_blt(ATIVGAState *s) s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), surface_bits_per_pixel(ds), (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); + int dst_x =3D (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? + s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width); + int dst_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? + s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height); int bpp =3D ati_bpp_from_datatype(s); int dst_stride =3D DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_= pitch; uint8_t *dst_bits =3D s->vga.vram_ptr + (DEFAULT_CNTL ? @@ -63,20 +67,25 @@ void ati_2d_blt(ATIVGAState *s) dst_stride *=3D bpp; } uint8_t *end =3D s->vga.vram_ptr + s->vga.vram_size; - if (dst_bits >=3D end || - dst_bits + s->regs.dst_x + (s->regs.dst_y + s->regs.dst_height) * + if (dst_bits >=3D end || dst_bits + dst_x + (dst_y + s->regs.dst_heigh= t) * dst_stride >=3D end) { qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); return; } - DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d\n", + DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n", s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset, s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch, s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y, - s->regs.dst_width, s->regs.dst_height); + s->regs.dst_width, s->regs.dst_height, + (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'), + (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^')); switch (s->regs.dp_mix & GMC_ROP3_MASK) { case ROP3_SRCCOPY: { + int src_x =3D (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? + s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width= ); + int src_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? + s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_heigh= t); int src_stride =3D DEFAULT_CNTL ? s->regs.src_pitch : s->regs.default_pitch; uint8_t *src_bits =3D s->vga.vram_ptr + (DEFAULT_CNTL ? @@ -86,9 +95,8 @@ void ati_2d_blt(ATIVGAState *s) src_bits +=3D s->regs.crtc_offset & 0x07ffffff; src_stride *=3D bpp; } - if (src_bits >=3D end || - src_bits + s->regs.src_x + (s->regs.src_y + s->regs.dst_height= ) * - src_stride >=3D end) { + if (src_bits >=3D end || src_bits + src_x + + (src_y + s->regs.dst_height) * src_stride >=3D end) { qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); return; } @@ -97,19 +105,34 @@ void ati_2d_blt(ATIVGAState *s) dst_stride /=3D sizeof(uint32_t); DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d= )\n", src_bits, dst_bits, src_stride, dst_stride, bpp, bpp, - s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y, + src_x, src_y, dst_x, dst_y, s->regs.dst_width, s->regs.dst_height); - pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits, - src_stride, dst_stride, bpp, bpp, - s->regs.src_x, s->regs.src_y, - s->regs.dst_x, s->regs.dst_y, - s->regs.dst_width, s->regs.dst_height); + if (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT && + s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { + pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits, + src_stride, dst_stride, bpp, bpp, + src_x, src_y, dst_x, dst_y, + s->regs.dst_width, s->regs.dst_height); + } else { + /* FIXME: We only really need a temporary if src and dst overl= ap */ + uint32_t *tmp =3D g_malloc(src_stride * sizeof(uint32_t) * + s->regs.dst_height); + pixman_blt((uint32_t *)src_bits, tmp, + src_stride, src_stride, bpp, bpp, + src_x, src_y, 0, 0, + s->regs.dst_width, s->regs.dst_height); + pixman_blt(tmp, (uint32_t *)dst_bits, + src_stride, dst_stride, bpp, bpp, + 0, 0, dst_x, dst_y, + s->regs.dst_width, s->regs.dst_height); + g_free(tmp); + } if (dst_bits >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset= ) { memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + s->regs.dst_offset + - s->regs.dst_y * surface_stride(ds), + dst_y * surface_stride(ds), s->regs.dst_height * surface_stride(ds= )); } s->regs.dst_x +=3D s->regs.dst_width; @@ -151,7 +174,7 @@ void ati_2d_blt(ATIVGAState *s) s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset= ) { memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + s->regs.dst_offset + - s->regs.dst_y * surface_stride(ds), + dst_y * surface_stride(ds), s->regs.dst_height * surface_stride(ds= )); } s->regs.dst_y +=3D s->regs.dst_height; --=20 2.13.7