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[222.224.182.28]) by smtp.gmail.com with ESMTPSA id j186sm1074512pge.75.2017.08.22.22.57.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2017 22:57:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=E7Wj1Tk2j5xImTpkz4VJWpH6I7679DzUJ9y4ZTIJ7x0=; b=Rz+ZXx+uMbExUmzhIf/vAbS6Ww7zn0qVAQ2rvKaZPFHnA5Z06I5PnBBhJ5HuwxwJRT LeAuYkVU5s3dum58SgyLtRiB6Aze4dcCtKx2OCI1x3pgRBNOiF6dgOfOSxNJ/M3567bT 1JOL6qk2LG/z2swETOvytZvh1Ml51DzOXhMbvS9ennOc67qZ08Iene0DqPU5YD+YjKj7 7w4OsnST4Z6AItDhQpvO7wGoasozUyuRCMuqSUsrdqxl4aFeahp1J/QCwSOCDNJ1E0Yx 8LX6e951yAA2t1qdWwEpNJPr2T6aL3kUwdOuWo4sc+Qk87s+pfk4kQiRbsCDzxd6Twn6 7imw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=E7Wj1Tk2j5xImTpkz4VJWpH6I7679DzUJ9y4ZTIJ7x0=; b=Trd3sIUXWM716BznlDn2zHlDXeZx4Azhug6krBSA6GwjFRuBbLtKTbA2yhucJgDHai DciWimHd45M7FPA1kuflcQ4SJv4+twBLJVLpWgzogXRUIvi3qi52YHvKSOP7NY59k3Dw fYBxOB0UtnrvKR13seENvqsZEJvWIck8PbV87UZvczK7bitcokH8S+noLH57poA+YNT/ /uNZEaZxWeFQ9JZ+Mx24wGKqbRfn2q1UamfNNmKZRbrGQvc0swzlSGi5ZhOVPKeujL+F Yeox3DTD11nGpL5uBvBUsHDCbWa49+LVkOrD4ciNfRKNODVoVp9G6i7BnzFhkPVXszrn Aogw== X-Gm-Message-State: AHYfb5h2+XmRKIgh6h7aY5sa0QiaaIHbs6StVseUvVsl7S/rvR4/kugR UNJie8EZzUohfE9lcCZzGA== X-Received: by 10.84.210.206 with SMTP id a72mr1860963pli.218.1503467874803; Tue, 22 Aug 2017 22:57:54 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Wed, 23 Aug 2017 14:57:09 +0900 Message-Id: X-Mailer: git-send-email 2.13.5 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH 1/5] openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add OpenRISC Multicore PIC which handles inter processor interrupts (IPI) between cores. In OpenRISC all device interrupts are routed to each core enabling this device to be simple. Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- default-configs/or1k-softmmu.mak | 1 + hw/intc/Makefile.objs | 1 + hw/intc/ompic.c | 179 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 181 insertions(+) create mode 100644 hw/intc/ompic.c diff --git a/default-configs/or1k-softmmu.mak b/default-configs/or1k-softmm= u.mak index 10bfa7abb8..6f5824fd48 100644 --- a/default-configs/or1k-softmmu.mak +++ b/default-configs/or1k-softmmu.mak @@ -2,3 +2,4 @@ =20 CONFIG_SERIAL=3Dy CONFIG_OPENCORES_ETH=3Dy +CONFIG_OMPIC=3Dy diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index 78426a7daf..ae358569a1 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -43,3 +43,4 @@ obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_vic.o obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_cpuif.o obj-$(CONFIG_MIPS_CPS) +=3D mips_gic.o obj-$(CONFIG_NIOS2) +=3D nios2_iic.o +obj-$(CONFIG_OMPIC) +=3D ompic.o diff --git a/hw/intc/ompic.c b/hw/intc/ompic.c new file mode 100644 index 0000000000..c0e34d1268 --- /dev/null +++ b/hw/intc/ompic.c @@ -0,0 +1,179 @@ +/* + * This file is subject to the terms and conditions of the GNU General Pub= lic + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Authors: Stafford Horne + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "exec/memory.h" + +#define TYPE_OR1K_OMPIC "or1k-ompic" +#define OR1K_OMPIC(obj) OBJECT_CHECK(OR1KOMPICState, (obj), TYPE_OR1K_OMPI= C) + +#define OMPIC_CTRL_IRQ_ACK (1 << 31) +#define OMPIC_CTRL_IRQ_GEN (1 << 30) +#define OMPIC_CTRL_DST(cpu) (((cpu) >> 16) & 0x3fff) + +#define OMPIC_REG(addr) (((addr) >> 2) & 0x1) +#define OMPIC_SRC_CPU(addr) (((addr) >> 3) & 0x4f) +#define OMPIC_DST_CPU(addr) (((addr) >> 3) & 0x4f) + +#define OMPIC_STATUS_IRQ_PENDING (1 << 30) +#define OMPIC_STATUS_SRC(cpu) (((cpu) & 0x3fff) << 16) +#define OMPIC_STATUS_DATA(data) ((data) & 0xffff) + +#define OMPIC_CONTROL 0 +#define OMPIC_STATUS 1 + +#define OMPIC_MAX_CPUS 4 /* Real max is much higher, but dont waste memory= */ +#define OMPIC_ADDRSPACE_SZ (OMPIC_MAX_CPUS * 2 * 4) /* 2 32-bit regs per c= pu */ + +typedef struct OR1KOMPICState OR1KOMPICState; +typedef struct OR1KOMPICCPUState OR1KOMPICCPUState; + +struct OR1KOMPICCPUState { + qemu_irq irq; + uint32_t status; + uint32_t control; +}; + +struct OR1KOMPICState { + SysBusDevice parent_obj; + MemoryRegion mr; + + OR1KOMPICCPUState cpus[OMPIC_MAX_CPUS]; + + uint32_t num_cpus; +}; + +static uint64_t ompic_read(void *opaque, hwaddr addr, unsigned size) +{ + OR1KOMPICState *s =3D opaque; + int src_cpu =3D OMPIC_SRC_CPU(addr); + + /* We can only write to control control, write control + update status= */ + if (OMPIC_REG(addr) =3D=3D OMPIC_CONTROL) { + return s->cpus[src_cpu].control; + } else { + return s->cpus[src_cpu].status; + } + +} + +static void ompic_write(void *opaque, hwaddr addr, uint64_t data, unsigned= size) +{ + OR1KOMPICState *s =3D opaque; + /* We can only write to control control, write control + update status= */ + if (OMPIC_REG(addr) =3D=3D OMPIC_CONTROL) { + int src_cpu =3D OMPIC_SRC_CPU(addr); + + s->cpus[src_cpu].control =3D data; + + if (data & OMPIC_CTRL_IRQ_GEN) { + int dst_cpu =3D OMPIC_CTRL_DST(data); + + s->cpus[dst_cpu].status =3D OMPIC_STATUS_IRQ_PENDING | + OMPIC_STATUS_SRC(src_cpu) | + OMPIC_STATUS_DATA(data); + + qemu_irq_raise(s->cpus[dst_cpu].irq); + } + if (data & OMPIC_CTRL_IRQ_ACK) { + s->cpus[src_cpu].status &=3D ~OMPIC_STATUS_IRQ_PENDING; + qemu_irq_lower(s->cpus[src_cpu].irq); + } + } +} + +static const MemoryRegionOps ompic_ops =3D { + .read =3D ompic_read, + .write =3D ompic_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .max_access_size =3D 8, + }, +}; + +static void or1k_ompic_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + OR1KOMPICState *s =3D OR1K_OMPIC(obj); + + memory_region_init_io(&s->mr, OBJECT(s), &ompic_ops, s, + "or1k-ompic", OMPIC_ADDRSPACE_SZ); + sysbus_init_mmio(sbd, &s->mr); +} + +static void or1k_ompic_realize(DeviceState *dev, Error **errp) +{ + OR1KOMPICState *s =3D OR1K_OMPIC(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + int i; + + if (s->num_cpus > OMPIC_MAX_CPUS) { + error_setg(errp, "Exceeded maximum CPUs %d", s->num_cpus); + return; + } + /* Init IRQ sources for all CPUs */ + for (i =3D 0; i < s->num_cpus; i++) { + sysbus_init_irq(sbd, &s->cpus[i].irq); + } +} + +static Property or1k_ompic_properties[] =3D { + DEFINE_PROP_UINT32("num-cpus", OR1KOMPICState, num_cpus, 1), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_or1k_ompic_cpu =3D { + .name =3D "or1k_ompic_cpu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(status, OR1KOMPICCPUState), + VMSTATE_UINT32(control, OR1KOMPICCPUState), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_or1k_ompic =3D { + .name =3D TYPE_OR1K_OMPIC, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(cpus, OR1KOMPICState, OMPIC_MAX_CPUS, 1, + vmstate_or1k_ompic_cpu, OR1KOMPICCPUState), + VMSTATE_UINT32(num_cpus, OR1KOMPICState), + VMSTATE_END_OF_LIST() + } +}; + +static void or1k_ompic_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->props =3D or1k_ompic_properties; + dc->realize =3D or1k_ompic_realize; + dc->vmsd =3D &vmstate_or1k_ompic; +} + +static const TypeInfo or1k_ompic_info =3D { + .name =3D TYPE_OR1K_OMPIC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(OR1KOMPICState), + .instance_init =3D or1k_ompic_init, + .class_init =3D or1k_ompic_class_init, +}; + +static void or1k_ompic_register_types(void) +{ + type_register_static(&or1k_ompic_info); +} + +type_init(or1k_ompic_register_types) --=20 2.13.5 From nobody Mon May 6 16:39:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503468117258595.1673560561966; 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[222.224.182.28]) by smtp.gmail.com with ESMTPSA id r16sm1039606pgu.68.2017.08.22.22.57.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2017 22:57:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=zK0q0HUTbJkOnUOdJTbqcIUahIzwiWibg08FG2opNzk=; b=i+Z6n2+xYXLbERwo5SHXSIDaFoxwrrWaM9arZPSFu+aXHikmOOENUifFv0x4m2kgIO 3NH5TuqwkXYiXCR8QfHFXY8Tef6vSf4uvPwaFiZyxrmrsLjyNbBVIkNF9nD7NkgXipQy wT1f+TZx2tlVRM25VgoIgTWk3WVbVNv+3YDeJA/w5IRL8DUWzAx7mdcLP5XgnxLH/nMD YKhvsL389IJG52uAOZdoWwpNZmhk5knZDpnw/TqDkI0A9G7axBIFIF7QkAB7HFXwHwms pyOhsiViyk/is0tBZmZqXzOP9TAZ6T/uRSVpK5++qiSPi4kqZVAG97F8+MZ/dRl4/bPV jLpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=zK0q0HUTbJkOnUOdJTbqcIUahIzwiWibg08FG2opNzk=; b=KCgdcxWmgRLETf8vt9IH2AwX36FCYsa9oItW+Bh2+FFHOV/kkBREMq+lKUMojYZ/ca Y24JKEiaFlYPdRe62A+U8VVi73BJR99FTBpyGPPlsipGhAqj7DcHAzCx5eeV3ZBM9NQX NasPITJ3qjxMYGGDeau4CBLWi3XlcSo4uJMOwSmZmC8M1K0g05UyUpFm/oXB+IWEVEbI 8D54n9pg7VIsFWkF0DXtZofh9gBFEPeD3w9hBjCUGQw/cRVlIFuK6lwgftVn7XxoVo0v 7qTQ6jXHoyA35GQNcpIjYD2gmw7H4FMijgMcC9VhmfkNr42sgja+MDQJ8y54IxncLFrv GPEg== X-Gm-Message-State: AHYfb5iPGc33kB1m0AsJrQFdFGD67aQbu5aaZP589OyHfw55CWlBShBX aN9OZBQxj/ZiUNBQSZ9jsQ== X-Received: by 10.99.120.205 with SMTP id t196mr1567154pgc.35.1503467877582; Tue, 22 Aug 2017 22:57:57 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Wed, 23 Aug 2017 14:57:10 +0900 Message-Id: <88d5624e0d2f52db9072fcb36406baadf31d96bd.1503467674.git.shorne@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH 2/5] target/openrisc: Make coreid and numcores configurable in state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Previously coreid and numcores were hard coded as 0 and 1 respectively as OpenRISC QEMU did not have multicore support. Multicore support is now being added so these registers need to have configured values. Signed-off-by: Stafford Horne --- hw/openrisc/openrisc_sim.c | 3 +++ target/openrisc/cpu.h | 3 +++ target/openrisc/machine.c | 7 +++++-- target/openrisc/sys_helper.c | 4 ++-- 4 files changed, 13 insertions(+), 4 deletions(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index e1eeffc490..44a657753d 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -110,6 +110,9 @@ static void openrisc_sim_init(MachineState *machine) =20 for (n =3D 0; n < smp_cpus; n++) { cpu =3D cpu_openrisc_init(cpu_model); + cpu->env.coreid =3D n; + cpu->env.numcores =3D smp_cpus; + if (cpu =3D=3D NULL) { fprintf(stderr, "Unable to find CPU definition!\n"); exit(1); diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 2721432c4f..4a61e5abfc 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -319,7 +319,10 @@ typedef struct CPUOpenRISCState { =20 uint32_t picmr; /* Interrupt mask register */ uint32_t picsr; /* Interrupt contrl register*/ + uint32_t coreid; + uint32_t numcores; #endif + void *irq[32]; /* Interrupt irq input */ } CPUOpenRISCState; =20 diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index a20cce705d..a879b2b539 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -104,8 +104,8 @@ static const VMStateInfo vmstate_sr =3D { =20 static const VMStateDescription vmstate_env =3D { .name =3D "env", - .version_id =3D 6, - .minimum_version_id =3D 6, + .version_id =3D 7, + .minimum_version_id =3D 7, .post_load =3D env_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), @@ -152,6 +152,9 @@ static const VMStateDescription vmstate_env =3D { VMSTATE_UINT32(picmr, CPUOpenRISCState), VMSTATE_UINT32(picsr, CPUOpenRISCState), =20 + VMSTATE_UINT32(coreid, CPUOpenRISCState), + VMSTATE_UINT32(numcores, CPUOpenRISCState), + VMSTATE_END_OF_LIST() } }; diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index abdef5d6a5..e138bcf9db 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -249,10 +249,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, return env->esr; =20 case TO_SPR(0, 128): /* COREID */ - return 0; + return env->coreid; =20 case TO_SPR(0, 129): /* NUMCORES */ - return 1; + return env->numcores; =20 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ idx =3D (spr - 1024); --=20 2.13.5 From nobody Mon May 6 16:39:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150346811007762.80378424140645; Tue, 22 Aug 2017 23:01:50 -0700 (PDT) Received: from localhost ([::1]:41119 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkOjc-00079R-VM for importer@patchew.org; Wed, 23 Aug 2017 02:01:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40853) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkOfz-0004My-8U for qemu-devel@nongnu.org; Wed, 23 Aug 2017 01:58:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkOfx-0003WL-Uf for qemu-devel@nongnu.org; Wed, 23 Aug 2017 01:58:03 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:34845) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dkOfx-0003Va-MB for qemu-devel@nongnu.org; Wed, 23 Aug 2017 01:58:01 -0400 Received: by mail-pf0-x241.google.com with SMTP id k3so721345pfc.2 for ; Tue, 22 Aug 2017 22:58:01 -0700 (PDT) Received: from localhost (g28.222-224-182.ppp.wakwak.ne.jp. [222.224.182.28]) by smtp.gmail.com with ESMTPSA id z125sm1229429pfz.108.2017.08.22.22.57.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2017 22:58:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=6mTXQ0MEiBGKlNity0D+oItJai0tMkyFPWjMmzrlVd4=; b=MzLaKmlwvPrLcyweaJiLtqIUQydTtWeUrVCQNapDlE+sAC5UfvU85uPe+4iKeeG5jC uFw9mi3ttIc0SUlnHTvBPbaBnB4po9Djbzd5371sZ65kyUBbZT7Ev8ze3dgC8aa4FLL4 BMvG7WxXhj1CNAUUGhscBu0LV/X7sVn+AHTmJqihPFkJ9yi2IPxKZhjHMt6ovo0h/OUW B3BpVnL87SFuXKptkOZ4rrNvPkU3e/Bat8ho3RlZy1SRYAgFaCJNphixCuWJxxm3Kwnc G9V6Y6Ib8lrI4kEkZZ7Av9lZbXQt3MqeiT7EgUQTo4C12jCDbggML/KWLGhcDHLYJVkU q5GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=6mTXQ0MEiBGKlNity0D+oItJai0tMkyFPWjMmzrlVd4=; b=D6ovtcNQ9S+6lzo3KfSsyOoqfF9z0dTQUqAzoW9MkV+XhmURSbbGgEFCQwWT1pvMW9 yRYGM8jY6nQGOTWnHq/aXi2Z5TRklN3kembrJKb2dQ4LjoLSBuDmDL5yHsLmmwjgWjaq BngRx+7hKsHAs+sKQ0U1sAKKL1O4+JzvWnK+uEYlOfO8wxOTQaEKa3wa4sEfSRyYN8vs /HGO7NZnkZUkGXyBXzJWnJXvy25NakWAj0WETbyXFrduNVNhchSMEKSFc45Kf72rwDxa lqpOBhGQxr2QOwscT+8bwBTxuxCLcimHK8kyhDyVBRycT5Abcvqy0GaKb2ZkpVDF+A+y E5kg== X-Gm-Message-State: AHYfb5ihwUr5OaMBsuitMV0oOvU5h2taYkHglNlKddEnADbadioc8emr Stcww/bcQSUHhb4NHnX8CQ== X-Received: by 10.99.157.204 with SMTP id i195mr1563529pgd.101.1503467880485; Tue, 22 Aug 2017 22:58:00 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Wed, 23 Aug 2017 14:57:11 +0900 Message-Id: <9ff134a8c36d63ad667d94cacb5ef490e2227e1e.1503467674.git.shorne@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH 3/5] openrisc/cputimer: Perparation for Multicore X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In order to support multicore system we move some of the previously static state variables into the state of each core. On the other hand in order to allow timers to be synced between each code the ttcr (tick timer count register) is moved out of the core. This is not as per real hardware spec which has a separate timer counter per core, but it seems the most simple way to keep each clock in sync. Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- hw/openrisc/cputimer.c | 62 +++++++++++++++++++++++++++++++++-------= ---- target/openrisc/cpu.c | 1 - target/openrisc/cpu.h | 4 ++- target/openrisc/machine.c | 1 - target/openrisc/sys_helper.c | 4 +-- 5 files changed, 52 insertions(+), 20 deletions(-) diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c index febc469170..4c5415ff75 100644 --- a/hw/openrisc/cputimer.c +++ b/hw/openrisc/cputimer.c @@ -25,39 +25,56 @@ =20 #define TIMER_PERIOD 50 /* 50 ns period for 20 MHz timer */ =20 -/* The time when TTCR changes */ -static uint64_t last_clk; -static int is_counting; +/* Tick Timer global state to allow all cores to be in sync */ +typedef struct OR1KTimerState { + uint32_t ttcr; + uint64_t last_clk; +} OR1KTimerState; =20 +static OR1KTimerState *or1k_timer; + +void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val) +{ + or1k_timer->ttcr =3D val; +} + +uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu) +{ + return or1k_timer->ttcr; +} + +/* Add elapsed ticks to ttcr */ void cpu_openrisc_count_update(OpenRISCCPU *cpu) { uint64_t now; =20 - if (!is_counting) { + if (!cpu->env.is_counting) { return; } now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - cpu->env.ttcr +=3D (uint32_t)((now - last_clk) / TIMER_PERIOD); - last_clk =3D now; + or1k_timer->ttcr +=3D (uint32_t)((now - or1k_timer->last_clk) + / TIMER_PERIOD); + or1k_timer->last_clk =3D now; } =20 +/* Update the next timeout time as difference between ttmr and ttcr */ void cpu_openrisc_timer_update(OpenRISCCPU *cpu) { uint32_t wait; uint64_t now, next; =20 - if (!is_counting) { + if (!cpu->env.is_counting) { return; } =20 cpu_openrisc_count_update(cpu); - now =3D last_clk; + now =3D or1k_timer->last_clk; =20 - if ((cpu->env.ttmr & TTMR_TP) <=3D (cpu->env.ttcr & TTMR_TP)) { - wait =3D TTMR_TP - (cpu->env.ttcr & TTMR_TP) + 1; + if ((cpu->env.ttmr & TTMR_TP) <=3D (or1k_timer->ttcr & TTMR_TP)) { + wait =3D TTMR_TP - (or1k_timer->ttcr & TTMR_TP) + 1; wait +=3D cpu->env.ttmr & TTMR_TP; } else { - wait =3D (cpu->env.ttmr & TTMR_TP) - (cpu->env.ttcr & TTMR_TP); + wait =3D (cpu->env.ttmr & TTMR_TP) - (or1k_timer->ttcr & TTMR_TP); } next =3D now + (uint64_t)wait * TIMER_PERIOD; timer_mod(cpu->env.timer, next); @@ -66,7 +83,7 @@ void cpu_openrisc_timer_update(OpenRISCCPU *cpu) =20 void cpu_openrisc_count_start(OpenRISCCPU *cpu) { - is_counting =3D 1; + cpu->env.is_counting =3D 1; cpu_openrisc_count_update(cpu); } =20 @@ -74,7 +91,7 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu) { timer_del(cpu->env.timer); cpu_openrisc_count_update(cpu); - is_counting =3D 0; + cpu->env.is_counting =3D 0; } =20 static void openrisc_timer_cb(void *opaque) @@ -93,7 +110,7 @@ static void openrisc_timer_cb(void *opaque) case TIMER_NONE: break; case TIMER_INTR: - cpu->env.ttcr =3D 0; + or1k_timer->ttcr =3D 0; break; case TIMER_SHOT: cpu_openrisc_count_stop(cpu); @@ -105,9 +122,24 @@ static void openrisc_timer_cb(void *opaque) cpu_openrisc_timer_update(cpu); } =20 +static const VMStateDescription vmstate_or1k_timer =3D { + .name =3D "or1k_timer", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(ttcr, OR1KTimerState), + VMSTATE_UINT64(last_clk, OR1KTimerState), + VMSTATE_END_OF_LIST() + } +}; + void cpu_openrisc_clock_init(OpenRISCCPU *cpu) { cpu->env.timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &openrisc_timer_cb= , cpu); cpu->env.ttmr =3D 0x00000000; - cpu->env.ttcr =3D 0x00000000; + + if (or1k_timer =3D=3D NULL) { + or1k_timer =3D g_new0(OR1KTimerState, 1); + vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer); + } } diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 1d6330cbcc..0a46684987 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -61,7 +61,6 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.picsr =3D 0x00000000; =20 cpu->env.ttmr =3D 0x00000000; - cpu->env.ttcr =3D 0x00000000; #endif } =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 4a61e5abfc..265f48ca43 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -315,7 +315,7 @@ typedef struct CPUOpenRISCState { =20 QEMUTimer *timer; uint32_t ttmr; /* Timer tick mode register */ - uint32_t ttcr; /* Timer tick count register */ + int is_counting; =20 uint32_t picmr; /* Interrupt mask register */ uint32_t picsr; /* Interrupt contrl register*/ @@ -376,6 +376,8 @@ void cpu_openrisc_pic_init(OpenRISCCPU *cpu); =20 /* hw/openrisc_timer.c */ void cpu_openrisc_clock_init(OpenRISCCPU *cpu); +uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu); +void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val); void cpu_openrisc_count_update(OpenRISCCPU *cpu); void cpu_openrisc_timer_update(OpenRISCCPU *cpu); void cpu_openrisc_count_start(OpenRISCCPU *cpu); diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index a879b2b539..c6a945f0df 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -147,7 +147,6 @@ static const VMStateDescription vmstate_env =3D { =20 VMSTATE_TIMER_PTR(timer, CPUOpenRISCState), VMSTATE_UINT32(ttmr, CPUOpenRISCState), - VMSTATE_UINT32(ttcr, CPUOpenRISCState), =20 VMSTATE_UINT32(picmr, CPUOpenRISCState), VMSTATE_UINT32(picsr, CPUOpenRISCState), diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index e138bcf9db..35be44beff 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -188,7 +188,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, break; =20 case TO_SPR(10, 1): /* TTCR */ - env->ttcr =3D rb; + cpu_openrisc_count_set(cpu, rb); if (env->ttmr & TIMER_NONE) { return; } @@ -311,7 +311,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, =20 case TO_SPR(10, 1): /* TTCR */ cpu_openrisc_count_update(cpu); - return env->ttcr; + return cpu_openrisc_count_get(cpu); =20 default: break; --=20 2.13.5 From nobody Mon May 6 16:39:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503468205758192.70249732361344; Tue, 22 Aug 2017 23:03:25 -0700 (PDT) Received: from localhost ([::1]:41227 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkOlA-0008Cp-6q for importer@patchew.org; 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[222.224.182.28]) by smtp.gmail.com with ESMTPSA id g87sm1247588pfe.51.2017.08.22.22.58.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2017 22:58:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=pfdQ9xBQCWvpr5WSkAq61LpzzvurWqEsGpeXxR6Bwtw=; b=nW8pSR3tc3DCjpB7mUOFBo5bEakfTA53CXNglvnlwwkeTxNc/gwLzp0MWxqGMAJLcs WJjTN5VJ5Ivge1yTjOuWCcdvuVyExCQlv9ENTHGxhif8o3Kagu5VZ4RyPNWSFnfWQyeP SEMgKWsqv3jpO/Hz1CCKv1FN3mSFJ1tta93rzUdouYqy1mPnLvGdRXP5J9t6Lb/IHecF 2J/989xa4oJ1pJ9Jew6ceasloQthf33BroJNeD26TaTfeZTz1NU84FpPVh+Q6Hs/DbF5 /FylJ3YDVGwI/EsDElM2HdusVx/ALFVe/nDfOYGeZbubyYV4U50KvRa15JueMg0l9bEO nynQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=pfdQ9xBQCWvpr5WSkAq61LpzzvurWqEsGpeXxR6Bwtw=; b=J4N8uhueHuOVjmY0k/KAldCQpSwoXwjscX45bUd1VesIwGPhD5s8E4RpmlyPJCrDJs fv4inHzS5CCfqapzg4IFAwzxFCgm7w+qqUe2G1rBXEPEGe+a7O4tuDviik+BVDJfH99M 8HYs5XhuekozR4kGrF/PRGqhrnzdRIcY3vJDosFnh1zHNQrNAFEV4PqWmIrL2VZIjIFI eya5c1JWqggP6Sx9qAGqpD/P0Z/AGZ4E+aaqqRqiLkiut8Fw0h37KuLfaDD3XjpMsqJq 16gZB7hgR1pLyhX0dVpETMOybQTEGsxhAhh4k1vZnqELzxtANBFd9222G9vQmiYsGYM4 CzGg== X-Gm-Message-State: AHYfb5gQiEvb3TLFGzqmEp0re+Nyq9erkXnd0+a2Ja0I6CnPDl66Xd+m diQusjRpsyc4s58QM6TucA== X-Received: by 10.98.59.9 with SMTP id i9mr1615881pfa.330.1503467882746; Tue, 22 Aug 2017 22:58:02 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Wed, 23 Aug 2017 14:57:12 +0900 Message-Id: X-Mailer: git-send-email 2.13.5 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH 4/5] openrisc: Initial SMP support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Wire in ompic and add basic support for SMP. The OpenRISC is special in that interrupts for devices are routed to each core's PIC. This is achieved using the qemu_irq_split utility, but this currently limits OpenRISC to 2 cores. This models the reference architecture described in the OpenRISC spec 1.2 proposal. https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-= rev0.pdf The changes to the intialization of the sim include: CPU Reset o Reset each cpu to the bootstrap PC rather than only a single cpu as done before. o During Kernel loading the bootstrap PC is saved in a static global. Network Initialization o Connect the interrupt to each CPU o Use more simple sysbus_mmio_map() rather than memory_region_add_subregio= n() Sim Initialization o Initialize the pic and tick timer per cpu o Wire in the OMPIC if SMP is enabled o Wire the serial irq to each CPU using qemu_irq_split() Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- hw/openrisc/openrisc_sim.c | 84 +++++++++++++++++++++++++++++++++---------= ---- 1 file changed, 61 insertions(+), 23 deletions(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 44a657753d..f06a3e111b 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -35,36 +35,60 @@ =20 #define KERNEL_LOAD_ADDR 0x100 =20 +static struct openrisc_boot_info { + uint32_t bootstrap_pc; +} boot_info; + static void main_cpu_reset(void *opaque) { OpenRISCCPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); =20 cpu_reset(CPU(cpu)); + + cpu_set_pc(cs, boot_info.bootstrap_pc); } =20 -static void openrisc_sim_net_init(MemoryRegion *address_space, - hwaddr base, - hwaddr descriptors, - qemu_irq irq, NICInfo *nd) +static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors, + int num_cpus, qemu_irq **cpu_irqs, + int irq_pin, NICInfo *nd) { DeviceState *dev; SysBusDevice *s; + int i; =20 dev =3D qdev_create(NULL, "open_eth"); qdev_set_nic_properties(dev, nd); qdev_init_nofail(dev); =20 s =3D SYS_BUS_DEVICE(dev); - sysbus_connect_irq(s, 0, irq); - memory_region_add_subregion(address_space, base, - sysbus_mmio_get_region(s, 0)); - memory_region_add_subregion(address_space, descriptors, - sysbus_mmio_get_region(s, 1)); + for (i =3D 0; i < num_cpus; i++) { + sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]); + } + sysbus_mmio_map(s, 0, base); + sysbus_mmio_map(s, 1, descriptors); } =20 -static void cpu_openrisc_load_kernel(ram_addr_t ram_size, - const char *kernel_filename, - OpenRISCCPU *cpu) +static void openrisc_sim_ompic_init(hwaddr base, int num_cpus, + qemu_irq **cpu_irqs, int irq_pin) +{ + DeviceState *dev; + SysBusDevice *s; + int i; + + dev =3D qdev_create(NULL, "or1k-ompic"); + qdev_prop_set_uint32(dev, "num-cpus", num_cpus); + qdev_init_nofail(dev); + + s =3D SYS_BUS_DEVICE(dev); + for (i =3D 0; i < num_cpus; i++) { + sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]); + } + sysbus_mmio_map(s, 0, base); +} + +static void openrisc_load_kernel(ram_addr_t ram_size, + const char *kernel_filename) { long kernel_size; uint64_t elf_entry; @@ -83,6 +107,9 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size, kernel_size =3D load_image_targphys(kernel_filename, KERNEL_LOAD_ADDR, ram_size - KERNEL_LOAD_ADDR); + } + + if (entry <=3D 0) { entry =3D KERNEL_LOAD_ADDR; } =20 @@ -91,7 +118,7 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size, kernel_filename); exit(1); } - cpu->env.pc =3D entry; + boot_info.bootstrap_pc =3D entry; } } =20 @@ -102,6 +129,8 @@ static void openrisc_sim_init(MachineState *machine) const char *kernel_filename =3D machine->kernel_filename; OpenRISCCPU *cpu =3D NULL; MemoryRegion *ram; + qemu_irq *cpu_irqs[2]; + qemu_irq serial_irq; int n; =20 if (!cpu_model) { @@ -117,33 +146,42 @@ static void openrisc_sim_init(MachineState *machine) fprintf(stderr, "Unable to find CPU definition!\n"); exit(1); } + cpu_openrisc_pic_init(cpu); + cpu_irqs[n] =3D (qemu_irq *) cpu->env.irq; + + cpu_openrisc_clock_init(cpu); + qemu_register_reset(main_cpu_reset, cpu); - main_cpu_reset(cpu); } =20 ram =3D g_malloc(sizeof(*ram)); memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fat= al); memory_region_add_subregion(get_system_memory(), 0, ram); =20 - cpu_openrisc_pic_init(cpu); - cpu_openrisc_clock_init(cpu); + if (nd_table[0].used) { + openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus, + cpu_irqs, 4, nd_table); + } =20 - serial_mm_init(get_system_memory(), 0x90000000, 0, cpu->env.irq[2], - 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); + if (smp_cpus > 1) { + openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1); =20 - if (nd_table[0].used) { - openrisc_sim_net_init(get_system_memory(), 0x92000000, - 0x92000400, cpu->env.irq[4], nd_table); + serial_irq =3D qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]); + } else { + serial_irq =3D cpu_irqs[0][2]; } =20 - cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu); + serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq, + 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); + + openrisc_load_kernel(ram_size, kernel_filename); } =20 static void openrisc_sim_machine_init(MachineClass *mc) { mc->desc =3D "or1k simulation"; mc->init =3D openrisc_sim_init; - mc->max_cpus =3D 1; + mc->max_cpus =3D 2; mc->is_default =3D 1; } =20 --=20 2.13.5 From nobody Mon May 6 16:39:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150346804079522.214151457142407; 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X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH 5/5] openrisc: Only kick cpu on timeout, not on update X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Previously we were kicking the cpu on every update. This caused problems noticeable in SMP configurations where one CPU got pinned continuously servicing timer exceptions. Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- hw/openrisc/cputimer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c index 4c5415ff75..850f88761c 100644 --- a/hw/openrisc/cputimer.c +++ b/hw/openrisc/cputimer.c @@ -78,7 +78,6 @@ void cpu_openrisc_timer_update(OpenRISCCPU *cpu) } next =3D now + (uint64_t)wait * TIMER_PERIOD; timer_mod(cpu->env.timer, next); - qemu_cpu_kick(CPU(cpu)); } =20 void cpu_openrisc_count_start(OpenRISCCPU *cpu) @@ -120,6 +119,7 @@ static void openrisc_timer_cb(void *opaque) } =20 cpu_openrisc_timer_update(cpu); + qemu_cpu_kick(CPU(cpu)); } =20 static const VMStateDescription vmstate_or1k_timer =3D { --=20 2.13.5