From nobody Wed Nov 5 15:53:26 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496748610911785.3069658646128; Tue, 6 Jun 2017 04:30:10 -0700 (PDT) Received: from localhost ([::1]:37641 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICgW-0001bf-JH for importer@patchew.org; Tue, 06 Jun 2017 07:30:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43878) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICeq-0000TA-U7 for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dICem-0002jf-Rz for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:20 -0400 Received: from [59.151.112.132] (port=9198 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICem-0002g5-H4 for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:16 -0400 Received: from unknown (HELO cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 06 Jun 2017 19:27:55 +0800 Received: from G08CNEXCHPEKD02.g08.fujitsu.local (unknown [10.167.33.83]) by cn.fujitsu.com (Postfix) with ESMTP id C30DF47C7C69; Tue, 6 Jun 2017 19:27:52 +0800 (CST) Received: from maozy.g08.fujitsu.local (10.167.225.76) by G08CNEXCHPEKD02.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 6 Jun 2017 19:27:52 +0800 X-IronPort-AV: E=Sophos;i="5.22,518,1449504000"; d="scan'208";a="19716130" From: Mao Zhongyi To: Date: Tue, 6 Jun 2017 19:26:26 +0800 Message-ID: X-Mailer: git-send-email 2.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.225.76] X-yoursite-MailScanner-ID: C30DF47C7C69.A4CF4 X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: maozy.fnst@cn.fujitsu.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Subject: [Qemu-devel] [PATCH v3 1/7] pci: Clean up error checking in pci_add_capability() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On success, pci_add_capability2() returns a positive value. On failure, it sets an error and return a negative value. pci_add_capability() laboriously checks this behavior. No other caller does. Drop the checks from pci_add_capability(). Cc: mst@redhat.com Cc: marcel@redhat.com Signed-off-by: Mao Zhongyi Reviewed-by: Marcel Apfelbaum --- hw/pci/pci.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 98ccc27..53566b8 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2270,12 +2270,8 @@ int pci_add_capability(PCIDevice *pdev, uint8_t cap_= id, Error *local_err =3D NULL; =20 ret =3D pci_add_capability2(pdev, cap_id, offset, size, &local_err); - if (local_err) { - assert(ret < 0); + if (ret < 0) { error_report_err(local_err); - } else { - /* success implies a positive offset in config space */ - assert(ret > 0); } return ret; } --=20 2.9.3 From nobody Wed Nov 5 15:53:26 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496748671711742.5052462367295; Tue, 6 Jun 2017 04:31:11 -0700 (PDT) Received: from localhost ([::1]:37650 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICha-0002el-8l for importer@patchew.org; Tue, 06 Jun 2017 07:31:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43872) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICeq-0000Su-HP for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dICel-0002j3-OA for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:20 -0400 Received: from [59.151.112.132] (port=9198 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICel-0002g5-DG for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:15 -0400 Received: from unknown (HELO cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 06 Jun 2017 19:27:55 +0800 Received: from G08CNEXCHPEKD02.g08.fujitsu.local (unknown [10.167.33.83]) by cn.fujitsu.com (Postfix) with ESMTP id 7E55B47C7C83; Tue, 6 Jun 2017 19:27:53 +0800 (CST) Received: from maozy.g08.fujitsu.local (10.167.225.76) by G08CNEXCHPEKD02.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 6 Jun 2017 19:27:52 +0800 X-IronPort-AV: E=Sophos;i="5.22,518,1449504000"; d="scan'208";a="19716134" From: Mao Zhongyi To: Date: Tue, 6 Jun 2017 19:26:27 +0800 Message-ID: X-Mailer: git-send-email 2.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.225.76] X-yoursite-MailScanner-ID: 7E55B47C7C83.A10AE X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: maozy.fnst@cn.fujitsu.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Subject: [Qemu-devel] [PATCH v3 2/7] pci: Add comment for pci_add_capability2() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, armbru@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Comments for pci_add_capability2() to explain the return value. This may help to make a correct return value check for its callers. Cc: mst@redhat.com Cc: marcel@redhat.com Cc: armbru@redhat.com Suggested-by: Markus Armbruster Signed-off-by: Mao Zhongyi --- hw/pci/pci.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 53566b8..b73bfea 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2276,6 +2276,12 @@ int pci_add_capability(PCIDevice *pdev, uint8_t cap_= id, return ret; } =20 +/* + * On success, pci_add_capability2() returns a positive value + * that the offset of the pci capability. + * On failure, it sets an error and returns a negative error + * code. + */ int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, uint8_t offset, uint8_t size, Error **errp) --=20 2.9.3 From nobody Wed Nov 5 15:53:26 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496748741086283.7322368848561; Tue, 6 Jun 2017 04:32:21 -0700 (PDT) Received: from localhost ([::1]:37653 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICif-0003U1-NF for importer@patchew.org; Tue, 06 Jun 2017 07:32:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43877) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICeq-0000T9-TL for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dICen-0002kq-My for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:20 -0400 Received: from [59.151.112.132] (port=38614 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICen-0002jT-B0 for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:17 -0400 Received: from unknown (HELO cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 06 Jun 2017 19:27:55 +0800 Received: from G08CNEXCHPEKD02.g08.fujitsu.local (unknown [10.167.33.83]) by cn.fujitsu.com (Postfix) with ESMTP id 4C39C47C7C84; Tue, 6 Jun 2017 19:27:54 +0800 (CST) Received: from maozy.g08.fujitsu.local (10.167.225.76) by G08CNEXCHPEKD02.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 6 Jun 2017 19:27:53 +0800 X-IronPort-AV: E=Sophos;i="5.22,518,1449504000"; d="scan'208";a="19716133" From: Mao Zhongyi To: Date: Tue, 6 Jun 2017 19:26:28 +0800 Message-ID: <0d7a09056c63d112c6de0169352c82e5d4517080.1496746391.git.maozy.fnst@cn.fujitsu.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.225.76] X-yoursite-MailScanner-ID: 4C39C47C7C84.A3BDC X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: maozy.fnst@cn.fujitsu.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Subject: [Qemu-devel] [PATCH v3 3/7] pci: Fix the return value checking X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dmitry@daynix.com, jasowang@redhat.com, alex.williamson@redhat.com, kraxel@redhat.com, armbru@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" pci_add_capability returns a strictly positive value on success, correct asserts. Cc: dmitry@daynix.com Cc: jasowang@redhat.com Cc: kraxel@redhat.com Cc: alex.williamson@redhat.com Cc: armbru@redhat.com Signed-off-by: Mao Zhongyi --- hw/net/e1000e.c | 2 +- hw/net/eepro100.c | 2 +- hw/usb/hcd-xhci.c | 2 +- hw/vfio/pci.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index 6e23493..8259d67 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -374,7 +374,7 @@ e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offse= t, uint16_t pmc) { int ret =3D pci_add_capability(pdev, PCI_CAP_ID_PM, offset, PCI_PM_SIZ= EOF); =20 - if (ret >=3D 0) { + if (ret > 0) { pci_set_word(pdev->config + offset + PCI_PM_PMC, PCI_PM_CAP_VER_1_1 | pmc); diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c index 4bf71f2..da36816 100644 --- a/hw/net/eepro100.c +++ b/hw/net/eepro100.c @@ -571,7 +571,7 @@ static void e100_pci_reset(EEPRO100State * s) int cfg_offset =3D 0xdc; int r =3D pci_add_capability(&s->dev, PCI_CAP_ID_PM, cfg_offset, PCI_PM_SIZEOF); - assert(r >=3D 0); + assert(r > 0); pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21); #if 0 /* TODO: replace dummy code for power management emulation. */ /* TODO: Power Management Control / Status. */ diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index a0c7960..ab42f86 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -3417,7 +3417,7 @@ static void usb_xhci_realize(struct PCIDevice *dev, E= rror **errp) if (pci_bus_is_express(dev->bus) || xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) { ret =3D pcie_endpoint_cap_init(dev, 0xa0); - assert(ret >=3D 0); + assert(ret > 0); } =20 if (xhci->msix !=3D ON_OFF_AUTO_OFF) { diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 32aca77..5881968 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1744,7 +1744,7 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, i= nt pos, uint8_t size, } =20 pos =3D pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size); - if (pos >=3D 0) { + if (pos > 0) { vdev->pdev.exp.exp_cap =3D pos; } =20 --=20 2.9.3 From nobody Wed Nov 5 15:53:26 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496748743447171.559457152528; Tue, 6 Jun 2017 04:32:23 -0700 (PDT) Received: from localhost ([::1]:37654 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICij-0003XI-Tp for importer@patchew.org; Tue, 06 Jun 2017 07:32:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43881) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICeq-0000TB-UU for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dICen-0002kU-HI for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:20 -0400 Received: from [59.151.112.132] (port=55441 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICem-0002g4-Jk for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:17 -0400 Received: from unknown (HELO cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 06 Jun 2017 19:27:55 +0800 Received: from G08CNEXCHPEKD02.g08.fujitsu.local (unknown [10.167.33.83]) by cn.fujitsu.com (Postfix) with ESMTP id 0149747C7C85; Tue, 6 Jun 2017 19:27:55 +0800 (CST) Received: from maozy.g08.fujitsu.local (10.167.225.76) by G08CNEXCHPEKD02.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 6 Jun 2017 19:27:54 +0800 X-IronPort-AV: E=Sophos;i="5.22,518,1449504000"; d="scan'208";a="19716132" From: Mao Zhongyi To: Date: Tue, 6 Jun 2017 19:26:29 +0800 Message-ID: <8533d2df3734029324eec5b3edc546bd148dc3ef.1496746391.git.maozy.fnst@cn.fujitsu.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.225.76] X-yoursite-MailScanner-ID: 0149747C7C85.A2C77 X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: maozy.fnst@cn.fujitsu.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Subject: [Qemu-devel] [PATCH v3 4/7] net/eepro100: Fix code style X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jasowang@redhat.com, armbru@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It reports a code style problem(ERROR: "foo * bar" should be "foo *bar") when running checkpatch.pl. So fix it to conform to the coding standards. Cc: jasowang@redhat.com Cc: armbru@redhat.com Signed-off-by: Mao Zhongyi --- hw/net/eepro100.c | 62 +++++++++++++++++++++++++++------------------------= ---- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c index da36816..62e989c 100644 --- a/hw/net/eepro100.c +++ b/hw/net/eepro100.c @@ -405,7 +405,7 @@ enum scb_stat_ack { stat_ack_tx =3D (stat_ack_cu_idle | stat_ack_cu_cmd_done), }; =20 -static void disable_interrupt(EEPRO100State * s) +static void disable_interrupt(EEPRO100State *s) { if (s->int_stat) { TRACE(INT, logout("interrupt disabled\n")); @@ -414,7 +414,7 @@ static void disable_interrupt(EEPRO100State * s) } } =20 -static void enable_interrupt(EEPRO100State * s) +static void enable_interrupt(EEPRO100State *s) { if (!s->int_stat) { TRACE(INT, logout("interrupt enabled\n")); @@ -423,7 +423,7 @@ static void enable_interrupt(EEPRO100State * s) } } =20 -static void eepro100_acknowledge(EEPRO100State * s) +static void eepro100_acknowledge(EEPRO100State *s) { s->scb_stat &=3D ~s->mem[SCBAck]; s->mem[SCBAck] =3D s->scb_stat; @@ -432,7 +432,7 @@ static void eepro100_acknowledge(EEPRO100State * s) } } =20 -static void eepro100_interrupt(EEPRO100State * s, uint8_t status) +static void eepro100_interrupt(EEPRO100State *s, uint8_t status) { uint8_t mask =3D ~s->mem[SCBIntmask]; s->mem[SCBAck] |=3D status; @@ -449,52 +449,52 @@ static void eepro100_interrupt(EEPRO100State * s, uin= t8_t status) } } =20 -static void eepro100_cx_interrupt(EEPRO100State * s) +static void eepro100_cx_interrupt(EEPRO100State *s) { /* CU completed action command. */ /* Transmit not ok (82557 only, not in emulation). */ eepro100_interrupt(s, 0x80); } =20 -static void eepro100_cna_interrupt(EEPRO100State * s) +static void eepro100_cna_interrupt(EEPRO100State *s) { /* CU left the active state. */ eepro100_interrupt(s, 0x20); } =20 -static void eepro100_fr_interrupt(EEPRO100State * s) +static void eepro100_fr_interrupt(EEPRO100State *s) { /* RU received a complete frame. */ eepro100_interrupt(s, 0x40); } =20 -static void eepro100_rnr_interrupt(EEPRO100State * s) +static void eepro100_rnr_interrupt(EEPRO100State *s) { /* RU is not ready. */ eepro100_interrupt(s, 0x10); } =20 -static void eepro100_mdi_interrupt(EEPRO100State * s) +static void eepro100_mdi_interrupt(EEPRO100State *s) { /* MDI completed read or write cycle. */ eepro100_interrupt(s, 0x08); } =20 -static void eepro100_swi_interrupt(EEPRO100State * s) +static void eepro100_swi_interrupt(EEPRO100State *s) { /* Software has requested an interrupt. */ eepro100_interrupt(s, 0x04); } =20 #if 0 -static void eepro100_fcp_interrupt(EEPRO100State * s) +static void eepro100_fcp_interrupt(EEPRO100State *s) { /* Flow control pause interrupt (82558 and later). */ eepro100_interrupt(s, 0x01); } #endif =20 -static void e100_pci_reset(EEPRO100State * s) +static void e100_pci_reset(EEPRO100State *s) { E100PCIDeviceInfo *info =3D eepro100_get_class(s); uint32_t device =3D s->device; @@ -598,7 +598,7 @@ static void e100_pci_reset(EEPRO100State * s) #endif /* EEPROM_SIZE > 0 */ } =20 -static void nic_selective_reset(EEPRO100State * s) +static void nic_selective_reset(EEPRO100State *s) { size_t i; uint16_t *eeprom_contents =3D eeprom93xx_data(s->eeprom); @@ -669,7 +669,7 @@ static char *regname(uint32_t addr) *************************************************************************= ***/ =20 #if 0 -static uint16_t eepro100_read_command(EEPRO100State * s) +static uint16_t eepro100_read_command(EEPRO100State *s) { uint16_t val =3D 0xffff; TRACE(OTHER, logout("val=3D0x%04x\n", val)); @@ -694,27 +694,27 @@ enum commands { CmdTxFlex =3D 0x0008, /* Use "Flexible mode" for CmdTx command= . */ }; =20 -static cu_state_t get_cu_state(EEPRO100State * s) +static cu_state_t get_cu_state(EEPRO100State *s) { return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6); } =20 -static void set_cu_state(EEPRO100State * s, cu_state_t state) +static void set_cu_state(EEPRO100State *s, cu_state_t state) { s->mem[SCBStatus] =3D (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6); } =20 -static ru_state_t get_ru_state(EEPRO100State * s) +static ru_state_t get_ru_state(EEPRO100State *s) { return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2); } =20 -static void set_ru_state(EEPRO100State * s, ru_state_t state) +static void set_ru_state(EEPRO100State *s, ru_state_t state) { s->mem[SCBStatus] =3D (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2); } =20 -static void dump_statistics(EEPRO100State * s) +static void dump_statistics(EEPRO100State *s) { /* Dump statistical data. Most data is never changed by the emulation * and always 0, so we first just copy the whole block and then those @@ -962,7 +962,7 @@ static void action_command(EEPRO100State *s) /* List is empty. Now CU is idle or suspended. */ } =20 -static void eepro100_cu_command(EEPRO100State * s, uint8_t val) +static void eepro100_cu_command(EEPRO100State *s, uint8_t val) { cu_state_t cu_state; switch (val) { @@ -1036,7 +1036,7 @@ static void eepro100_cu_command(EEPRO100State * s, ui= nt8_t val) } } =20 -static void eepro100_ru_command(EEPRO100State * s, uint8_t val) +static void eepro100_ru_command(EEPRO100State *s, uint8_t val) { switch (val) { case RU_NOP: @@ -1084,7 +1084,7 @@ static void eepro100_ru_command(EEPRO100State * s, ui= nt8_t val) } } =20 -static void eepro100_write_command(EEPRO100State * s, uint8_t val) +static void eepro100_write_command(EEPRO100State *s, uint8_t val) { eepro100_ru_command(s, val & 0x0f); eepro100_cu_command(s, val & 0xf0); @@ -1106,7 +1106,7 @@ static void eepro100_write_command(EEPRO100State * s,= uint8_t val) #define EEPROM_DI 0x04 #define EEPROM_DO 0x08 =20 -static uint16_t eepro100_read_eeprom(EEPRO100State * s) +static uint16_t eepro100_read_eeprom(EEPRO100State *s) { uint16_t val =3D e100_read_reg2(s, SCBeeprom); if (eeprom93xx_read(s->eeprom)) { @@ -1170,7 +1170,7 @@ static const char *reg2name(uint8_t reg) } #endif /* DEBUG_EEPRO100 */ =20 -static uint32_t eepro100_read_mdi(EEPRO100State * s) +static uint32_t eepro100_read_mdi(EEPRO100State *s) { uint32_t val =3D e100_read_reg4(s, SCBCtrlMDI); =20 @@ -1302,7 +1302,7 @@ typedef struct { uint32_t st_result; /* Self Test Results */ } eepro100_selftest_t; =20 -static uint32_t eepro100_read_port(EEPRO100State * s) +static uint32_t eepro100_read_port(EEPRO100State *s) { return 0; } @@ -1340,7 +1340,7 @@ static void eepro100_write_port(EEPRO100State *s) * *************************************************************************= ***/ =20 -static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr) +static uint8_t eepro100_read1(EEPRO100State *s, uint32_t addr) { uint8_t val =3D 0; if (addr <=3D sizeof(s->mem) - sizeof(val)) { @@ -1393,7 +1393,7 @@ static uint8_t eepro100_read1(EEPRO100State * s, uint= 32_t addr) return val; } =20 -static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr) +static uint16_t eepro100_read2(EEPRO100State *s, uint32_t addr) { uint16_t val =3D 0; if (addr <=3D sizeof(s->mem) - sizeof(val)) { @@ -1421,7 +1421,7 @@ static uint16_t eepro100_read2(EEPRO100State * s, uin= t32_t addr) return val; } =20 -static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr) +static uint32_t eepro100_read4(EEPRO100State *s, uint32_t addr) { uint32_t val =3D 0; if (addr <=3D sizeof(s->mem) - sizeof(val)) { @@ -1453,7 +1453,7 @@ static uint32_t eepro100_read4(EEPRO100State * s, uin= t32_t addr) return val; } =20 -static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) +static void eepro100_write1(EEPRO100State *s, uint32_t addr, uint8_t val) { /* SCBStatus is readonly. */ if (addr > SCBStatus && addr <=3D sizeof(s->mem) - sizeof(val)) { @@ -1519,7 +1519,7 @@ static void eepro100_write1(EEPRO100State * s, uint32= _t addr, uint8_t val) } } =20 -static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) +static void eepro100_write2(EEPRO100State *s, uint32_t addr, uint16_t val) { /* SCBStatus is readonly. */ if (addr > SCBStatus && addr <=3D sizeof(s->mem) - sizeof(val)) { @@ -1565,7 +1565,7 @@ static void eepro100_write2(EEPRO100State * s, uint32= _t addr, uint16_t val) } } =20 -static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) +static void eepro100_write4(EEPRO100State *s, uint32_t addr, uint32_t val) { if (addr <=3D sizeof(s->mem) - sizeof(val)) { e100_write_reg4(s, addr, val); --=20 2.9.3 From nobody Wed Nov 5 15:53:26 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496748612824852.9128863052746; Tue, 6 Jun 2017 04:30:12 -0700 (PDT) Received: from localhost ([::1]:37643 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICga-0001e3-2r for importer@patchew.org; Tue, 06 Jun 2017 07:30:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43882) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICeq-0000TC-Ue for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dICeo-0002lR-I7 for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:20 -0400 Received: from [59.151.112.132] (port=9198 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICen-0002g5-LU for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:18 -0400 Received: from unknown (HELO cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 06 Jun 2017 19:27:55 +0800 Received: from G08CNEXCHPEKD02.g08.fujitsu.local (unknown [10.167.33.83]) by cn.fujitsu.com (Postfix) with ESMTP id E32EC47C7C86; Tue, 6 Jun 2017 19:27:55 +0800 (CST) Received: from maozy.g08.fujitsu.local (10.167.225.76) by G08CNEXCHPEKD02.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 6 Jun 2017 19:27:55 +0800 X-IronPort-AV: E=Sophos;i="5.22,518,1449504000"; d="scan'208";a="19716135" From: Mao Zhongyi To: Date: Tue, 6 Jun 2017 19:26:30 +0800 Message-ID: <3579e47c4bb41476406e26685292aaa9153fcc77.1496746391.git.maozy.fnst@cn.fujitsu.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.225.76] X-yoursite-MailScanner-ID: E32EC47C7C86.A7827 X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: maozy.fnst@cn.fujitsu.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Subject: [Qemu-devel] [PATCH v3 5/7] pci: Make errp the last parameter of pci_add_capability() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, mst@redhat.com, jasowang@redhat.com, armbru@redhat.com, marcel@redhat.com, alex.williamson@redhat.com, dmitry@daynix.com, pbonzini@redhat.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Error argument for pci_add_capability() to leverage the errp to pass info on errors. This way is helpful for its callers to make a better error handling when moving to 'realize'. Cc: pbonzini@redhat.com Cc: rth@twiddle.net Cc: ehabkost@redhat.com Cc: mst@redhat.com CC: dmitry@daynix.com Cc: jasowang@redhat.com Cc: marcel@redhat.com Cc: alex.williamson@redhat.com Cc: armbru@redhat.com Signed-off-by: Mao Zhongyi --- hw/i386/amd_iommu.c | 24 +++++++++++++++++------- hw/net/e1000e.c | 7 ++++++- hw/net/eepro100.c | 20 +++++++++++++++----- hw/pci-bridge/i82801b11.c | 1 + hw/pci/pci.c | 10 ++++------ hw/pci/pci_bridge.c | 7 ++++++- hw/pci/pcie.c | 10 ++++++++-- hw/pci/shpc.c | 5 ++++- hw/pci/slotid_cap.c | 7 ++++++- hw/vfio/pci.c | 3 ++- hw/virtio/virtio-pci.c | 19 ++++++++++++++----- include/hw/pci/pci.h | 3 ++- 12 files changed, 85 insertions(+), 31 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 7b6d4ea..d93ffc2 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1158,13 +1158,23 @@ static void amdvi_realize(DeviceState *dev, Error *= *err) x86_iommu->type =3D TYPE_AMD; qdev_set_parent_bus(DEVICE(&s->pci), &bus->qbus); object_property_set_bool(OBJECT(&s->pci), true, "realized", err); - s->capab_offset =3D pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC= , 0, - AMDVI_CAPAB_SIZE); - assert(s->capab_offset > 0); - ret =3D pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, AMDVI_CAPAB= _REG_SIZE); - assert(ret > 0); - ret =3D pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, AMDVI_CAPAB_= REG_SIZE); - assert(ret > 0); + ret =3D pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0, + AMDVI_CAPAB_SIZE, err); + if (ret < 0) { + return; + } + s->capab_offset =3D ret; + + ret =3D pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, + AMDVI_CAPAB_REG_SIZE, err); + if (ret < 0) { + return; + } + ret =3D pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, + AMDVI_CAPAB_REG_SIZE, err); + if (ret < 0) { + return; + } =20 /* set up MMIO */ memory_region_init_io(&s->mmio, OBJECT(s), &mmio_mem_ops, s, "amdvi-mm= io", diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index 8259d67..41430766 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -47,6 +47,7 @@ #include "e1000e_core.h" =20 #include "trace.h" +#include "qapi/error.h" =20 #define TYPE_E1000E "e1000e" #define E1000E(obj) OBJECT_CHECK(E1000EState, (obj), TYPE_E1000E) @@ -372,7 +373,9 @@ e1000e_gen_dsn(uint8_t *mac) static int e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc) { - int ret =3D pci_add_capability(pdev, PCI_CAP_ID_PM, offset, PCI_PM_SIZ= EOF); + Error *local_err =3D NULL; + int ret =3D pci_add_capability(pdev, PCI_CAP_ID_PM, offset, + PCI_PM_SIZEOF, &local_err); =20 if (ret > 0) { pci_set_word(pdev->config + offset + PCI_PM_PMC, @@ -386,6 +389,8 @@ e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offse= t, uint16_t pmc) =20 pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL, PCI_PM_CTRL_PME_STATUS); + } else { + error_report_err(local_err); } =20 return ret; diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c index 62e989c..0625839 100644 --- a/hw/net/eepro100.c +++ b/hw/net/eepro100.c @@ -48,6 +48,7 @@ #include "sysemu/sysemu.h" #include "sysemu/dma.h" #include "qemu/bitops.h" +#include "qapi/error.h" =20 /* QEMU sends frames smaller than 60 bytes to ethernet nics. * Such frames are rejected by real nics and their emulations. @@ -494,7 +495,7 @@ static void eepro100_fcp_interrupt(EEPRO100State *s) } #endif =20 -static void e100_pci_reset(EEPRO100State *s) +static void e100_pci_reset(EEPRO100State *s, Error **errp) { E100PCIDeviceInfo *info =3D eepro100_get_class(s); uint32_t device =3D s->device; @@ -570,9 +571,13 @@ static void e100_pci_reset(EEPRO100State *s) /* Power Management Capabilities */ int cfg_offset =3D 0xdc; int r =3D pci_add_capability(&s->dev, PCI_CAP_ID_PM, - cfg_offset, PCI_PM_SIZEOF); - assert(r > 0); - pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21); + cfg_offset, PCI_PM_SIZEOF, + errp); + if (r > 0) { + pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21); + } else { + return; + } #if 0 /* TODO: replace dummy code for power management emulation. */ /* TODO: Power Management Control / Status. */ pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000); @@ -1858,12 +1863,17 @@ static void e100_nic_realize(PCIDevice *pci_dev, Er= ror **errp) { EEPRO100State *s =3D DO_UPCAST(EEPRO100State, dev, pci_dev); E100PCIDeviceInfo *info =3D eepro100_get_class(s); + Error *local_err =3D NULL; =20 TRACE(OTHER, logout("\n")); =20 s->device =3D info->device; =20 - e100_pci_reset(s); + e100_pci_reset(s, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } =20 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM, * i82559 and later support 64 or 256 word EEPROM. */ diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c index 2404e7e..2c065c3 100644 --- a/hw/pci-bridge/i82801b11.c +++ b/hw/pci-bridge/i82801b11.c @@ -44,6 +44,7 @@ #include "qemu/osdep.h" #include "hw/pci/pci.h" #include "hw/i386/ich9.h" +#include "qapi/error.h" =20 =20 /*************************************************************************= ****/ diff --git a/hw/pci/pci.c b/hw/pci/pci.c index b73bfea..2bba37a 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2264,15 +2264,13 @@ static void pci_del_option_rom(PCIDevice *pdev) * in pci config space */ int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size) + uint8_t offset, uint8_t size, + Error **errp) { int ret; - Error *local_err =3D NULL; =20 - ret =3D pci_add_capability2(pdev, cap_id, offset, size, &local_err); - if (ret < 0) { - error_report_err(local_err); - } + ret =3D pci_add_capability2(pdev, cap_id, offset, size, errp); + return ret; } =20 diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 5118ef4..bb0f3a3 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -33,6 +33,7 @@ #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" #include "qemu/range.h" +#include "qapi/error.h" =20 /* PCI bridge subsystem vendor ID helper functions */ #define PCI_SSVID_SIZEOF 8 @@ -43,8 +44,12 @@ int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, uint16_t svid, uint16_t ssid) { int pos; - pos =3D pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SI= ZEOF); + Error *local_err =3D NULL; + + pos =3D pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, + PCI_SSVID_SIZEOF, &local_err); if (pos < 0) { + error_report_err(local_err); return pos; } =20 diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 18e634f..f187512 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -91,11 +91,14 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8= _t type, uint8_t port) /* PCIe cap v2 init */ int pos; uint8_t *exp_cap; + Error *local_err =3D NULL; =20 assert(pci_is_express(dev)); =20 - pos =3D pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER2_S= IZEOF); + pos =3D pci_add_capability(dev, PCI_CAP_ID_EXP, offset, + PCI_EXP_VER2_SIZEOF, &local_err); if (pos < 0) { + error_report_err(local_err); return pos; } dev->exp.exp_cap =3D pos; @@ -123,11 +126,14 @@ int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, = uint8_t type, { /* PCIe cap v1 init */ int pos; + Error *local_err =3D NULL; =20 assert(pci_is_express(dev)); =20 - pos =3D pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER1_S= IZEOF); + pos =3D pci_add_capability(dev, PCI_CAP_ID_EXP, offset, + PCI_EXP_VER1_SIZEOF, &local_err); if (pos < 0) { + error_report_err(local_err); return pos; } dev->exp.exp_cap =3D pos; diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c index 42fafac..d72d5e4 100644 --- a/hw/pci/shpc.c +++ b/hw/pci/shpc.c @@ -450,9 +450,12 @@ static int shpc_cap_add_config(PCIDevice *d) { uint8_t *config; int config_offset; + Error *local_err =3D NULL; config_offset =3D pci_add_capability(d, PCI_CAP_ID_SHPC, - 0, SHPC_CAP_LENGTH); + 0, SHPC_CAP_LENGTH, + &local_err); if (config_offset < 0) { + error_report_err(local_err); return config_offset; } config =3D d->config + config_offset; diff --git a/hw/pci/slotid_cap.c b/hw/pci/slotid_cap.c index aec1e91..bdca205 100644 --- a/hw/pci/slotid_cap.c +++ b/hw/pci/slotid_cap.c @@ -2,6 +2,7 @@ #include "hw/pci/slotid_cap.h" #include "hw/pci/pci.h" #include "qemu/error-report.h" +#include "qapi/error.h" =20 #define SLOTID_CAP_LENGTH 4 #define SLOTID_NSLOTS_SHIFT ctz32(PCI_SID_ESR_NSLOTS) @@ -11,6 +12,8 @@ int slotid_cap_init(PCIDevice *d, int nslots, unsigned offset) { int cap; + Error *local_err =3D NULL; + if (!chassis) { error_report("Bridge chassis not specified. Each bridge is require= d " "to be assigned a unique chassis id > 0."); @@ -21,8 +24,10 @@ int slotid_cap_init(PCIDevice *d, int nslots, return -EINVAL; } =20 - cap =3D pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, SLOTID_CAP_LE= NGTH); + cap =3D pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, + SLOTID_CAP_LENGTH, &local_err); if (cap < 0) { + error_report_err(local_err); return cap; } /* We make each chassis unique, this way each bridge is First in Chass= is */ diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 5881968..85cfe38 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1743,7 +1743,8 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, i= nt pos, uint8_t size, PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); } =20 - pos =3D pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size); + pos =3D pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size, + errp); if (pos > 0) { vdev->pdev.exp.exp_cap =3D pos; } diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index f9b7244..cca5276 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1161,9 +1161,14 @@ static int virtio_pci_add_mem_cap(VirtIOPCIProxy *pr= oxy, { PCIDevice *dev =3D &proxy->pci_dev; int offset; + Error *local_err =3D NULL; =20 - offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, 0, cap->cap_len); - assert(offset > 0); + offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, 0, + cap->cap_len, &local_err); + if (offset < 0) { + error_report_err(local_err); + abort(); + } =20 assert(cap->cap_len >=3D sizeof *cap); memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len, @@ -1810,9 +1815,13 @@ static void virtio_pci_realize(PCIDevice *pci_dev, E= rror **errp) pos =3D pcie_endpoint_cap_init(pci_dev, 0); assert(pos > 0); =20 - pos =3D pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEO= F); - assert(pos > 0); - pci_dev->exp.pm_cap =3D pos; + pos =3D pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, + PCI_PM_SIZEOF, errp); + if (pos > 0) { + pci_dev->exp.pm_cap =3D pos; + } else { + return; + } =20 /* * Indicates that this function complies with revision 1.2 of the diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index a37a2d5..fe52aa8 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -356,7 +356,8 @@ void pci_unregister_vga(PCIDevice *pci_dev); pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); =20 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size); + uint8_t offset, uint8_t size, + Error **errp); int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, uint8_t offset, uint8_t size, Error **errp); --=20 2.9.3 From nobody Wed Nov 5 15:53:26 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496748609132349.50581177136576; Tue, 6 Jun 2017 04:30:09 -0700 (PDT) Received: from localhost ([::1]:37642 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICgZ-0001dn-EY for importer@patchew.org; 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Tue, 6 Jun 2017 19:27:55 +0800 X-IronPort-AV: E=Sophos;i="5.22,518,1449504000"; d="scan'208";a="19716140" From: Mao Zhongyi To: Date: Tue, 6 Jun 2017 19:26:31 +0800 Message-ID: <8f3e1b8d3cde59ee1b4842bc0d5ccbcc3acf4df3.1496746391.git.maozy.fnst@cn.fujitsu.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.225.76] X-yoursite-MailScanner-ID: 9EB8847C7C61.A584B X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: maozy.fnst@cn.fujitsu.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Subject: [Qemu-devel] [PATCH v3 6/7] pci: Convert to realize X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, armbru@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The pci-birdge device i82801b11 and io3130_upstream/downstream still implements the old PCIDeviceClass .init() through *_init() instead of the new .realize(). All devices need to be converted to .realize(). So convert it and rename it to *_realize(). Cc: mst@redhat.com Cc: marcel@redhat.com Cc: armbru@redhat.com Signed-off-by: Mao Zhongyi --- hw/pci-bridge/i82801b11.c | 11 +++++------ hw/pci-bridge/pcie_root_port.c | 15 ++++++--------- hw/pci-bridge/xio3130_downstream.c | 20 +++++++++----------- hw/pci-bridge/xio3130_upstream.c | 20 +++++++++----------- hw/pci/pci_bridge.c | 7 +++---- hw/pci/pcie.c | 11 ++++++----- include/hw/pci/pci_bridge.h | 3 ++- include/hw/pci/pcie.h | 3 ++- 8 files changed, 42 insertions(+), 48 deletions(-) diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c index 2c065c3..2c1b747 100644 --- a/hw/pci-bridge/i82801b11.c +++ b/hw/pci-bridge/i82801b11.c @@ -59,24 +59,23 @@ typedef struct I82801b11Bridge { /*< public >*/ } I82801b11Bridge; =20 -static int i82801b11_bridge_initfn(PCIDevice *d) +static void i82801b11_bridge_realize(PCIDevice *d, Error **errp) { int rc; =20 pci_bridge_initfn(d, TYPE_PCI_BUS); =20 rc =3D pci_bridge_ssvid_init(d, I82801ba_SSVID_OFFSET, - I82801ba_SSVID_SVID, I82801ba_SSVID_SSID); + I82801ba_SSVID_SVID, I82801ba_SSVID_SSID, + errp); if (rc < 0) { goto err_bridge; } pci_config_set_prog_interface(d->config, PCI_CLASS_BRIDGE_PCI_INF_SUB); - return 0; + return; =20 err_bridge: pci_bridge_exitfn(d); - - return rc; } =20 static const VMStateDescription i82801b11_bridge_dev_vmstate =3D { @@ -96,7 +95,7 @@ static void i82801b11_bridge_class_init(ObjectClass *klas= s, void *data) k->vendor_id =3D PCI_VENDOR_ID_INTEL; k->device_id =3D PCI_DEVICE_ID_INTEL_82801BA_11; k->revision =3D ICH9_D2P_A2_REVISION; - k->init =3D i82801b11_bridge_initfn; + k->realize =3D i82801b11_bridge_realize; k->config_write =3D pci_bridge_write_config; dc->vmsd =3D &i82801b11_bridge_dev_vmstate; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index cf36318..00f0b1f 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -59,29 +59,27 @@ static void rp_realize(PCIDevice *d, Error **errp) PCIDeviceClass *dc =3D PCI_DEVICE_GET_CLASS(d); PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(d); int rc; - Error *local_err =3D NULL; =20 pci_config_set_interrupt_pin(d->config, 1); pci_bridge_initfn(d, TYPE_PCIE_BUS); pcie_port_init_reg(d); =20 - rc =3D pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, rpc-= >ssid); + rc =3D pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, + rpc->ssid, errp); if (rc < 0) { - error_setg(errp, "Can't init SSV ID, error %d", rc); goto err_bridge; } =20 if (rpc->interrupts_init) { - rc =3D rpc->interrupts_init(d, &local_err); + rc =3D rpc->interrupts_init(d, errp); if (rc < 0) { - error_propagate(errp, local_err); goto err_bridge; } } =20 - rc =3D pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT, p->po= rt); + rc =3D pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT, + p->port, errp); if (rc < 0) { - error_setg(errp, "Can't add Root Port capability, error %d", rc); goto err_int; } =20 @@ -98,9 +96,8 @@ static void rp_realize(PCIDevice *d, Error **errp) } =20 rc =3D pcie_aer_init(d, PCI_ERR_VER, rpc->aer_offset, - PCI_ERR_SIZEOF, &local_err); + PCI_ERR_SIZEOF, errp); if (rc < 0) { - error_propagate(errp, local_err); goto err; } pcie_aer_root_init(d); diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_dow= nstream.c index cfe8a36..e706f36 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -56,33 +56,33 @@ static void xio3130_downstream_reset(DeviceState *qdev) pci_bridge_reset(qdev); } =20 -static int xio3130_downstream_initfn(PCIDevice *d) +static void xio3130_downstream_realize(PCIDevice *d, Error **errp) { PCIEPort *p =3D PCIE_PORT(d); PCIESlot *s =3D PCIE_SLOT(d); int rc; - Error *err =3D NULL; =20 pci_bridge_initfn(d, TYPE_PCIE_BUS); pcie_port_init_reg(d); =20 rc =3D msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, - XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, &er= r); + XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, + errp); if (rc < 0) { assert(rc =3D=3D -ENOTSUP); - error_report_err(err); goto err_bridge; } =20 rc =3D pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, - XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); + XIO3130_SSVID_SVID, XIO3130_SSVID_SSID, + errp); if (rc < 0) { goto err_bridge; } =20 rc =3D pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, - p->port); + p->port, errp); if (rc < 0) { goto err_msi; } @@ -98,13 +98,12 @@ static int xio3130_downstream_initfn(PCIDevice *d) } =20 rc =3D pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET, - PCI_ERR_SIZEOF, &err); + PCI_ERR_SIZEOF, errp); if (rc < 0) { - error_report_err(err); goto err; } =20 - return 0; + return; =20 err: pcie_chassis_del_slot(s); @@ -114,7 +113,6 @@ err_msi: msi_uninit(d); err_bridge: pci_bridge_exitfn(d); - return rc; } =20 static void xio3130_downstream_exitfn(PCIDevice *d) @@ -181,7 +179,7 @@ static void xio3130_downstream_class_init(ObjectClass *= klass, void *data) k->is_express =3D 1; k->is_bridge =3D 1; k->config_write =3D xio3130_downstream_write_config; - k->init =3D xio3130_downstream_initfn; + k->realize =3D xio3130_downstream_realize; k->exit =3D xio3130_downstream_exitfn; k->vendor_id =3D PCI_VENDOR_ID_TI; k->device_id =3D PCI_DEVICE_ID_TI_XIO3130D; diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstr= eam.c index 401c784..a052224 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -53,32 +53,32 @@ static void xio3130_upstream_reset(DeviceState *qdev) pcie_cap_deverr_reset(d); } =20 -static int xio3130_upstream_initfn(PCIDevice *d) +static void xio3130_upstream_realize(PCIDevice *d, Error **errp) { PCIEPort *p =3D PCIE_PORT(d); int rc; - Error *err =3D NULL; =20 pci_bridge_initfn(d, TYPE_PCIE_BUS); pcie_port_init_reg(d); =20 rc =3D msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, - XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, &er= r); + XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, + errp); if (rc < 0) { assert(rc =3D=3D -ENOTSUP); - error_report_err(err); goto err_bridge; } =20 rc =3D pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, - XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); + XIO3130_SSVID_SVID, XIO3130_SSVID_SSID, + errp); if (rc < 0) { goto err_bridge; } =20 rc =3D pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, - p->port); + p->port, errp); if (rc < 0) { goto err_msi; } @@ -86,13 +86,12 @@ static int xio3130_upstream_initfn(PCIDevice *d) pcie_cap_deverr_init(d); =20 rc =3D pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET, - PCI_ERR_SIZEOF, &err); + PCI_ERR_SIZEOF, errp); if (rc < 0) { - error_report_err(err); goto err; } =20 - return 0; + return; =20 err: pcie_cap_exit(d); @@ -100,7 +99,6 @@ err_msi: msi_uninit(d); err_bridge: pci_bridge_exitfn(d); - return rc; } =20 static void xio3130_upstream_exitfn(PCIDevice *d) @@ -153,7 +151,7 @@ static void xio3130_upstream_class_init(ObjectClass *kl= ass, void *data) k->is_express =3D 1; k->is_bridge =3D 1; k->config_write =3D xio3130_upstream_write_config; - k->init =3D xio3130_upstream_initfn; + k->realize =3D xio3130_upstream_realize; k->exit =3D xio3130_upstream_exitfn; k->vendor_id =3D PCI_VENDOR_ID_TI; k->device_id =3D PCI_DEVICE_ID_TI_XIO3130U; diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index bb0f3a3..720119b 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -41,15 +41,14 @@ #define PCI_SSVID_SSID 6 =20 int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, - uint16_t svid, uint16_t ssid) + uint16_t svid, uint16_t ssid, + Error **errp) { int pos; - Error *local_err =3D NULL; =20 pos =3D pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, - PCI_SSVID_SIZEOF, &local_err); + PCI_SSVID_SIZEOF, errp); if (pos < 0) { - error_report_err(local_err); return pos; } =20 diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index f187512..05d091a 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -86,19 +86,19 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t = type, uint8_t version) pci_set_word(cmask + PCI_EXP_LNKSTA, 0); } =20 -int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t po= rt) +int pcie_cap_init(PCIDevice *dev, uint8_t offset, + uint8_t type, uint8_t port, + Error **errp) { /* PCIe cap v2 init */ int pos; uint8_t *exp_cap; - Error *local_err =3D NULL; =20 assert(pci_is_express(dev)); =20 pos =3D pci_add_capability(dev, PCI_CAP_ID_EXP, offset, - PCI_EXP_VER2_SIZEOF, &local_err); + PCI_EXP_VER2_SIZEOF, errp); if (pos < 0) { - error_report_err(local_err); return pos; } dev->exp.exp_cap =3D pos; @@ -147,6 +147,7 @@ static int pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_= size) { uint8_t type =3D PCI_EXP_TYPE_ENDPOINT; + Error *local_err =3D NULL; =20 /* * Windows guests will report Code 10, device cannot start, if @@ -159,7 +160,7 @@ pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t o= ffset, uint8_t cap_size) =20 return (cap_size =3D=3D PCI_EXP_VER1_SIZEOF) ? pcie_cap_v1_init(dev, offset, type, 0) - : pcie_cap_init(dev, offset, type, 0); + : pcie_cap_init(dev, offset, type, 0, &local_err); } =20 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index d5891cd..ff7cbaa 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -33,7 +33,8 @@ #define PCI_BRIDGE_DEV_PROP_SHPC "shpc" =20 int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, - uint16_t svid, uint16_t ssid); + uint16_t svid, uint16_t ssid, + Error **errp); =20 PCIDevice *pci_bridge_get_device(PCIBus *bus); PCIBus *pci_bridge_get_sec_bus(PCIBridge *br); diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 3d8f24b..b71e369 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -84,7 +84,8 @@ struct PCIExpressDevice { #define COMPAT_PROP_PCP "power_controller_present" =20 /* PCI express capability helper functions */ -int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t po= rt); +int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, + uint8_t port, Error **errp); int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port); int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset); --=20 2.9.3 From nobody Wed Nov 5 15:53:26 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 06 Jun 2017 07:28:18 -0400 Received: from unknown (HELO cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 06 Jun 2017 19:28:01 +0800 Received: from G08CNEXCHPEKD02.g08.fujitsu.local (unknown [10.167.33.83]) by cn.fujitsu.com (Postfix) with ESMTP id 56AAB47C7C69; Tue, 6 Jun 2017 19:27:57 +0800 (CST) Received: from maozy.g08.fujitsu.local (10.167.225.76) by G08CNEXCHPEKD02.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 6 Jun 2017 19:27:56 +0800 X-IronPort-AV: E=Sophos;i="5.22,518,1449504000"; d="scan'208";a="19716139" From: Mao Zhongyi To: Date: Tue, 6 Jun 2017 19:26:32 +0800 Message-ID: <4842dd61954d23862cf834a00847376bc54fb4da.1496746391.git.maozy.fnst@cn.fujitsu.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.225.76] X-yoursite-MailScanner-ID: 56AAB47C7C69.A4897 X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: maozy.fnst@cn.fujitsu.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Subject: [Qemu-devel] [PATCH v3 7/7] pci: Convert shpc_init() to Error X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, armbru@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to propagate error message better, convert shpc_init() to Error also convert the pci_bridge_dev_initfn() to realize. Cc: mst@redhat.com Cc: marcel@redhat.com Cc: armbru@redhat.com Signed-off-by: Mao Zhongyi --- hw/pci-bridge/pci_bridge_dev.c | 21 ++++++++------------- hw/pci/shpc.c | 11 +++++------ hw/pci/slotid_cap.c | 11 +++++------ include/hw/pci/shpc.h | 3 ++- include/hw/pci/slotid_cap.h | 3 ++- 5 files changed, 22 insertions(+), 27 deletions(-) diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index 5dbd933..30c4186 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -49,12 +49,11 @@ struct PCIBridgeDev { }; typedef struct PCIBridgeDev PCIBridgeDev; =20 -static int pci_bridge_dev_initfn(PCIDevice *dev) +static void pci_bridge_dev_realize(PCIDevice *dev, Error **errp) { PCIBridge *br =3D PCI_BRIDGE(dev); PCIBridgeDev *bridge_dev =3D PCI_BRIDGE_DEV(dev); int err; - Error *local_err =3D NULL; =20 pci_bridge_initfn(dev, TYPE_PCI_BUS); =20 @@ -62,7 +61,7 @@ static int pci_bridge_dev_initfn(PCIDevice *dev) dev->config[PCI_INTERRUPT_PIN] =3D 0x1; memory_region_init(&bridge_dev->bar, OBJECT(dev), "shpc-bar", shpc_bar_size(dev)); - err =3D shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0); + err =3D shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0, errp); if (err) { goto shpc_error; } @@ -71,7 +70,7 @@ static int pci_bridge_dev_initfn(PCIDevice *dev) bridge_dev->msi =3D ON_OFF_AUTO_OFF; } =20 - err =3D slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0); + err =3D slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0, errp); if (err) { goto slotid_error; } @@ -79,20 +78,18 @@ static int pci_bridge_dev_initfn(PCIDevice *dev) if (bridge_dev->msi !=3D ON_OFF_AUTO_OFF) { /* it means SHPC exists, because MSI is needed by SHPC */ =20 - err =3D msi_init(dev, 0, 1, true, true, &local_err); + err =3D msi_init(dev, 0, 1, true, true, errp); /* Any error other than -ENOTSUP(board's MSI support is broken) * is a programming error */ assert(!err || err =3D=3D -ENOTSUP); if (err && bridge_dev->msi =3D=3D ON_OFF_AUTO_ON) { /* Can't satisfy user's explicit msi=3Don request, fail */ - error_append_hint(&local_err, "You have to use msi=3Dauto (def= ault) " + error_append_hint(errp, "You have to use msi=3Dauto (default) " "or msi=3Doff with this machine type.\n"); - error_report_err(local_err); goto msi_error; } - assert(!local_err || bridge_dev->msi =3D=3D ON_OFF_AUTO_AUTO); + assert(bridge_dev->msi =3D=3D ON_OFF_AUTO_AUTO); /* With msi=3Dauto, we fall back to MSI off silently */ - error_free(local_err); } =20 if (shpc_present(dev)) { @@ -101,7 +98,7 @@ static int pci_bridge_dev_initfn(PCIDevice *dev) pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar); } - return 0; + return; =20 msi_error: slotid_cap_cleanup(dev); @@ -111,8 +108,6 @@ slotid_error: } shpc_error: pci_bridge_exitfn(dev); - - return err; } =20 static void pci_bridge_dev_exitfn(PCIDevice *dev) @@ -216,7 +211,7 @@ static void pci_bridge_dev_class_init(ObjectClass *klas= s, void *data) PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(klass); =20 - k->init =3D pci_bridge_dev_initfn; + k->realize =3D pci_bridge_dev_realize; k->exit =3D pci_bridge_dev_exitfn; k->config_write =3D pci_bridge_dev_write_config; k->vendor_id =3D PCI_VENDOR_ID_REDHAT; diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c index d72d5e4..69fc14b 100644 --- a/hw/pci/shpc.c +++ b/hw/pci/shpc.c @@ -446,16 +446,14 @@ static void shpc_cap_update_dword(PCIDevice *d) } =20 /* Add SHPC capability to the config space for the device. */ -static int shpc_cap_add_config(PCIDevice *d) +static int shpc_cap_add_config(PCIDevice *d, Error **errp) { uint8_t *config; int config_offset; - Error *local_err =3D NULL; config_offset =3D pci_add_capability(d, PCI_CAP_ID_SHPC, 0, SHPC_CAP_LENGTH, - &local_err); + errp); if (config_offset < 0) { - error_report_err(local_err); return config_offset; } config =3D d->config + config_offset; @@ -584,13 +582,14 @@ void shpc_device_hot_unplug_request_cb(HotplugHandler= *hotplug_dev, } =20 /* Initialize the SHPC structure in bridge's BAR. */ -int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned o= ffset) +int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, + unsigned offset, Error **errp) { int i, ret; int nslots =3D SHPC_MAX_SLOTS; /* TODO: qdev property? */ SHPCDevice *shpc =3D d->shpc =3D g_malloc0(sizeof(*d->shpc)); shpc->sec_bus =3D sec_bus; - ret =3D shpc_cap_add_config(d); + ret =3D shpc_cap_add_config(d, errp); if (ret) { g_free(d->shpc); return ret; diff --git a/hw/pci/slotid_cap.c b/hw/pci/slotid_cap.c index bdca205..36d021b 100644 --- a/hw/pci/slotid_cap.c +++ b/hw/pci/slotid_cap.c @@ -9,14 +9,14 @@ =20 int slotid_cap_init(PCIDevice *d, int nslots, uint8_t chassis, - unsigned offset) + unsigned offset, + Error **errp) { int cap; - Error *local_err =3D NULL; =20 if (!chassis) { - error_report("Bridge chassis not specified. Each bridge is require= d " - "to be assigned a unique chassis id > 0."); + error_setg(errp, "Bridge chassis not specified. Each bridge is req= uired" + " to be assigned a unique chassis id > 0."); return -EINVAL; } if (nslots < 0 || nslots > (PCI_SID_ESR_NSLOTS >> SLOTID_NSLOTS_SHIFT)= ) { @@ -25,9 +25,8 @@ int slotid_cap_init(PCIDevice *d, int nslots, } =20 cap =3D pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, - SLOTID_CAP_LENGTH, &local_err); + SLOTID_CAP_LENGTH, errp); if (cap < 0) { - error_report_err(local_err); return cap; } /* We make each chassis unique, this way each bridge is First in Chass= is */ diff --git a/include/hw/pci/shpc.h b/include/hw/pci/shpc.h index b208554..1ea88b1 100644 --- a/include/hw/pci/shpc.h +++ b/include/hw/pci/shpc.h @@ -39,7 +39,8 @@ struct SHPCDevice { =20 void shpc_reset(PCIDevice *d); int shpc_bar_size(PCIDevice *dev); -int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned= off); +int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, + unsigned off, Error **errp); void shpc_cleanup(PCIDevice *dev, MemoryRegion *bar); void shpc_free(PCIDevice *dev); void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int = len); diff --git a/include/hw/pci/slotid_cap.h b/include/hw/pci/slotid_cap.h index 70db047..a777ea0 100644 --- a/include/hw/pci/slotid_cap.h +++ b/include/hw/pci/slotid_cap.h @@ -5,7 +5,8 @@ =20 int slotid_cap_init(PCIDevice *dev, int nslots, uint8_t chassis, - unsigned offset); + unsigned offset, + Error **errp); void slotid_cap_cleanup(PCIDevice *dev); =20 #endif --=20 2.9.3