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[124.44.183.209]) by smtp.gmail.com with ESMTPSA id n85sm510569pfi.101.2017.05.03.17.53.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 May 2017 17:53:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-transfer-encoding; bh=hHxUOFAiwX7+DMZ8XogibcJIMTdjwTyPpfPjXB73tTs=; b=X0p3NXuqriyFf/ypp0TCbVnsd8b52PIjINL4O84pvjcxLlk3JD9bCJGVSPf3NV0Xrn jmIZxho/Wc7SHxpuViw1M/6zY9jzHmVY0GD3f+EkCC46kLXKk4bleEZMY/eY8Pig9XHn GvG+7Z/mgozxzCPMNHyrJSDk/45KZbtDFcezT+LptsfncQ4TxHaSZTCOOjWjlt+IkMGs iRxHcZQimw7yrFuQ12LEiWZO5IHyIY0XUeBfcNMBJ7NVgCiPGCnbgPmQqVrjwLYR9XLA BJ8GLA2NRqksM/BZpMQu68C+gmasMEYAl0QjBdD/dCWW6IJhOHbWUdY4nRQRp+43KKEA 614A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references:mime-version :content-transfer-encoding; bh=hHxUOFAiwX7+DMZ8XogibcJIMTdjwTyPpfPjXB73tTs=; b=VX6JNpwO6XldSPSACY6gX3j5VGei/I4LvJTDBnRMfkVrS9JNvho09m/SzQW+CISLn/ YEXH4YP9Ex/J5G3QLexYfCO39LJHzUbHSwrlJo4ba5Eme8lmI9sVfY90ZXlhRuNltrZn kcB2M+Tn8AOsEYCAf7cljrgStqFEl1gjMeeRxQ+7pcnUTrkrL9PInJnAuN/dfymYR0+c GoSDwjsaI2zF1VBibKOAmhVXMV0eLkkN7BjJRjye63sFdGz/s85gMP+nA4/8Y7dH4x8F 7t5Pq2jhsE3CsqXZ/wgv7dy+tQMbAGnJBrqZG2EMcsjsHaKrdb2yuAAMLNH9hgh4Y6jG ZYUg== X-Gm-Message-State: AN3rC/5WYlCTpVHoK6Jn7RI3Ko3mEVPs85tIoOnCpfUbJ5LjdCdXPB/p pDEgmwIY1/gOVw== X-Received: by 10.84.179.65 with SMTP id a59mr51016161plc.171.1493859222364; Wed, 03 May 2017 17:53:42 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Thu, 4 May 2017 09:53:16 +0900 Message-Id: <1d7cf18d79c85031998cc8e628414eac292ca694.1493858877.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL v2 01/11] MAINTAINERS: Add myself as openrisc maintainer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Jia has claimed he is no longer able to maintain. I have fixing bugs here and there and getting familiar with the code base. Orignal thread from Jia: https://lists.librecores.org/pipermail/openrisc/2017-January/000321.html Signed-off-by: Stafford Horne Reviewed-by: Alex Benn=C3=A9e --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index c60235e..21803ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -196,8 +196,8 @@ F: hw/nios2/ F: disas/nios2.c =20 OpenRISC -M: Jia Liu -S: Maintained +M: Stafford Horne +S: Odd Fixes F: target/openrisc/ F: hw/openrisc/ F: tests/tcg/openrisc/ --=20 2.9.3 From nobody Sun May 5 11:05:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149385961748451.9816708224688; Wed, 3 May 2017 18:00:17 -0700 (PDT) Received: from localhost ([::1]:39220 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d657w-0006mB-6N for importer@patchew.org; Wed, 03 May 2017 21:00:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56785) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d651f-0001EO-EF for qemu-devel@nongnu.org; Wed, 03 May 2017 20:53:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d651e-0005s7-9I for qemu-devel@nongnu.org; Wed, 03 May 2017 20:53:47 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:33672) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d651e-0005rk-2h for qemu-devel@nongnu.org; Wed, 03 May 2017 20:53:46 -0400 Received: by mail-pf0-x243.google.com with SMTP id b23so721510pfc.0 for ; Wed, 03 May 2017 17:53:45 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id d1sm505738pfa.56.2017.05.03.17.53.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 May 2017 17:53:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=B22Il4U+lW9qJRmIpKE7jAR5AR4P5G5MCstdmwVkA+0=; b=AnNcodeOw+83R2eiMMIEiGQr+fdNwZGCmcL1KiywrETgPi/ss8yOEfOAvQAsPx5cLb Nck1lbvqN66kVHEMAI5H3NVI8EJqdxA8cXfah9GVap/CPqpToDukRKeEli5Rq27kuzSt /R+KQ7CAQnRdYGW7g0C3vxBWlVKTG/L17p108OFdcaaXM4XqC5yw42dtr82LpkxoUkVp PeSw+Rx2FsPTylP9jWar+5FQVir+jTDkh6xeEINUlu4bgDjNvTtwU1lEdvnIUEgRyJYy 56T6DulRvUsVQkw4Yl3ZaQlUNbjrtmvqpUYQCy8wujo0z7Y3/BOW7nU2E+mcZtzo2URh 2DLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=B22Il4U+lW9qJRmIpKE7jAR5AR4P5G5MCstdmwVkA+0=; b=Ze4TdCJtqM8WgZpTZG5HyMgsguqbXM+duDP2mmn/FmmXTAvt3paJKnRT2yW2su87Mv k1XPl518uXGIX86E34gWGv61LLciTAMKpXjIElfbOItD9vVAuSShe6VSwhCHPuJeDH9u ng/EeyTBUZFo6g/ww3KkL0ujTizePEp5WWpH7IcUdDRRpZG/32DSaEB3cCd3IAI3qcS8 AhE95e8TOgvjv7HRZtNvPGyUf8xuDgr5FcvPaKObiNTJXilTgiqsBgK2v1PJ22YhRxQF jrJSuVOiLpg32h037H3JPfHUFUzi/gIOsvgoysrgG/mKucUyUkBkSEH68U6WmipPOPKE L2Eg== X-Gm-Message-State: AN3rC/7PKctK6NMmw2lHGf3ZXn4mgQIHss/q4TLC2DcY9BNWxrVjPZyQ TwFUHea/lfueqA== X-Received: by 10.98.94.69 with SMTP id s66mr7991147pfb.116.1493859225075; Wed, 03 May 2017 17:53:45 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Thu, 4 May 2017 09:53:17 +0900 Message-Id: <356a2db3c6f84e8e79e5afa3913514184bff5f50.1493858877.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PULL v2 02/11] target/openrisc: Implement EVBAR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , Stafford Horne , Tim 'mithro' Ansell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Tim 'mithro' Ansell Exception Vector Base Address Register (EVBAR) - This optional register can be used to apply an offset to the exception vector addresses. The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). Its presence is indicated by the EVBARP bit in the CPU Configuration Register (CPUCFGR). Signed-off-by: Tim 'mithro' Ansell Signed-off-by: Stafford Horne --- target/openrisc/cpu.c | 2 ++ target/openrisc/cpu.h | 7 +++++++ target/openrisc/interrupt.c | 6 +++++- target/openrisc/sys_helper.c | 7 +++++++ 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 7fd2b9a..1524ed9 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -134,6 +134,7 @@ static void or1200_initfn(Object *obj) =20 set_feature(cpu, OPENRISC_FEATURE_OB32S); set_feature(cpu, OPENRISC_FEATURE_OF32S); + set_feature(cpu, OPENRISC_FEATURE_EVBAR); } =20 static void openrisc_any_initfn(Object *obj) @@ -141,6 +142,7 @@ static void openrisc_any_initfn(Object *obj) OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 set_feature(cpu, OPENRISC_FEATURE_OB32S); + set_feature(cpu, OPENRISC_FEATURE_EVBAR); } =20 typedef struct OpenRISCCPUInfo { diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 418a0e6..1958b72 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -111,6 +111,11 @@ enum { CPUCFGR_OF32S =3D (1 << 7), CPUCFGR_OF64S =3D (1 << 8), CPUCFGR_OV64S =3D (1 << 9), + /* CPUCFGR_ND =3D (1 << 10), */ + /* CPUCFGR_AVRP =3D (1 << 11), */ + CPUCFGR_EVBARP =3D (1 << 12), + /* CPUCFGR_ISRP =3D (1 << 13), */ + /* CPUCFGR_AECSRP =3D (1 << 14), */ }; =20 /* DMMU configure register */ @@ -200,6 +205,7 @@ enum { OPENRISC_FEATURE_OF32S =3D (1 << 7), OPENRISC_FEATURE_OF64S =3D (1 << 8), OPENRISC_FEATURE_OV64S =3D (1 << 9), + OPENRISC_FEATURE_EVBAR =3D (1 << 12), }; =20 /* Tick Timer Mode Register */ @@ -289,6 +295,7 @@ typedef struct CPUOpenRISCState { uint32_t dmmucfgr; /* DMMU configure register */ uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ + uint32_t evbar; /* Exception vector base address register */ uint32_t fpcsr; /* Float register */ float_status fp_status; =20 diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index a2eec6f..78f0ba9 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -65,7 +65,11 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->lock_addr =3D -1; =20 if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { - env->pc =3D (cs->exception_index << 8); + hwaddr vect_pc =3D cs->exception_index << 8; + if (env->cpucfgr & CPUCFGR_EVBARP) { + vect_pc |=3D env->evbar; + } + env->pc =3D vect_pc; } else { cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 60c3193..6ba8162 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -39,6 +39,10 @@ void HELPER(mtspr)(CPUOpenRISCState *env, env->vr =3D rb; break; =20 + case TO_SPR(0, 11): /* EVBAR */ + env->evbar =3D rb; + break; + case TO_SPR(0, 16): /* NPC */ cpu_restore_state(cs, GETPC()); /* ??? Mirror or1ksim in not trashing delayed branch state @@ -206,6 +210,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 4): /* IMMUCFGR */ return env->immucfgr; =20 + case TO_SPR(0, 11): /* EVBAR */ + return env->evbar; + case TO_SPR(0, 16): /* NPC (equals PC) */ cpu_restore_state(cs, GETPC()); return env->pc; --=20 2.9.3 From nobody Sun May 5 11:05:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493859345574638.6937022208583; Wed, 3 May 2017 17:55:45 -0700 (PDT) Received: from localhost ([::1]:39205 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d653W-0002fj-Vy for importer@patchew.org; Wed, 03 May 2017 20:55:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56798) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d651h-0001Fx-FT for qemu-devel@nongnu.org; Wed, 03 May 2017 20:53:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d651g-0005vJ-OE for qemu-devel@nongnu.org; Wed, 03 May 2017 20:53:49 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:35414) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d651g-0005uN-I1 for qemu-devel@nongnu.org; Wed, 03 May 2017 20:53:48 -0400 Received: by mail-pf0-x244.google.com with SMTP id o68so716105pfj.2 for ; Wed, 03 May 2017 17:53:48 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. 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X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL v2 03/11] target/openrisc: Implement EPH bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , Stafford Horne , Tim 'mithro' Ansell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Tim 'mithro' Ansell Exception Prefix High (EPH) control bit of the Supervision Register (SR). The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). If SR[EPH] is set, the vector offset is logically ORed with the offset 0xF0000000. This means if EPH is; * 0 - Exceptions vectors start at EVBAR * 1 - Exception vectors start at EVBAR | 0xF0000000 Signed-off-by: Tim 'mithro' Ansell Signed-off-by: Stafford Horne --- target/openrisc/interrupt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 78f0ba9..2c91fab 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -69,6 +69,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs) if (env->cpucfgr & CPUCFGR_EVBARP) { vect_pc |=3D env->evbar; } + if (env->sr & SR_EPH) { + vect_pc |=3D 0xf0000000; + } env->pc =3D vect_pc; } else { cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); --=20 2.9.3 From nobody Sun May 5 11:05:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493859353838559.9327773674516; Wed, 3 May 2017 17:55:53 -0700 (PDT) Received: from localhost ([::1]:39206 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d653g-0002no-7a for importer@patchew.org; Wed, 03 May 2017 20:55:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56811) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d651n-0001KZ-BS for qemu-devel@nongnu.org; Wed, 03 May 2017 20:53:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d651k-0005wf-8o for qemu-devel@nongnu.org; Wed, 03 May 2017 20:53:55 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:35418) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d651k-0005wO-3c for qemu-devel@nongnu.org; Wed, 03 May 2017 20:53:52 -0400 Received: by mail-pf0-x244.google.com with SMTP id o68so716235pfj.2 for ; Wed, 03 May 2017 17:53:51 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id r18sm495219pfk.109.2017.05.03.17.53.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 May 2017 17:53:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=9mCr71zRIanCxE320hbzHVdcvw954RnaCnMU5tfyVf8=; b=uXFaWGE18qltRrk5JWjArvjcYDMnzTUJX6LhvAFEfu3W/FACAnql9T18u+rynQyhLT eJDO7zyAMN11+xFw8t0jT3at0Y3oiFIW8ZAQaaiVIW9JxbMyO38XkVqCsosGHDO46Kqo 0wukTzI7TVltJ+ALmapZGCF9mRoB2lmQDZDyBQRvhVahsTo/MTWNOeVvT6cfu6tUvgR/ vtjcAi+ToGgOPMfin8z9fEbgSMRG13mR1r/9RlHB2syTDPwqr9coJrvKQqe7eZCO+fh5 zSceTZk8Okz2hc+rk4lifT4iCrcC9BUAHkHyou5EuhM1sqr2Wv0z0SLQMVOPIiKD7dVA t7qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=9mCr71zRIanCxE320hbzHVdcvw954RnaCnMU5tfyVf8=; b=DQwSheLfXZd4uEQVxTFuMBghHHg4/Gf041HWtAnfyQRvjRkYviNuAQEMmUzb5JU2hQ XsS3ENHi9MeVfWYtpQUF6eH6yqM32e43ePs3ZF+6xNj2L0Ro7VtNckXUHiJOofwLMKP7 bN1YzPPvdl/+c/ioKGZJ8c5QnxTfnDvG9MWxG1V/L4jPG4Z1nyuBhr7FHE6+eG9nH5A1 Z8Y17sGwC58LO2CS6WDBZ1thi7h/fCOBbbAYwmUVPhnttAGU5PQcMATBF1fAIFH2PmNi s6J7T+38pq9Py1RgfgPewzC8jUwQWp0dEhbPPxs02IyfTvPdrqVyNIBdoK/bCT/BbUAk ndQw== X-Gm-Message-State: AN3rC/5VDyD/gcihPDrJIrCt/k7rh1RJfsqUf7kL4zwTPTULrRkYzc5I r6ni3xY2h077Hw== X-Received: by 10.84.198.3 with SMTP id o3mr51952785pld.45.1493859231251; Wed, 03 May 2017 17:53:51 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Thu, 4 May 2017 09:53:19 +0900 Message-Id: <461a4b944f7e036b2f6bd1fce83ad4fe09e5e2bc.1493858877.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL v2 04/11] target/openrisc: Fixes for memory debugging X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When debugging in gdb you might want to inspect instructions in mapped pages or in exception vectors like 0x800 etc. This was previously not possible in qemu since the *get_phys_page_debug() routine only looked into the data tlb. Change to fall back to look into instruction tlb and plain physical pages. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/mmu.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 56b11d3..ce2a29d 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -124,7 +124,7 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu, { int ret =3D TLBRET_MATCH; =20 - if (rw =3D=3D 2) { /* ITLB */ + if (rw =3D=3D MMU_INST_FETCH) { /* ITLB */ *physical =3D 0; ret =3D cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical, prot, address, r= w); @@ -221,12 +221,28 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs,= vaddr addr) OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); hwaddr phys_addr; int prot; + int miss; =20 - if (cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0)) { - return -1; + /* Check memory for any kind of address, since during debug the + gdb can ask for anything, check data tlb for address */ + miss =3D cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0); + + /* Check instruction tlb */ + if (miss) { + miss =3D cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, + MMU_INST_FETCH); + } + + /* Last, fall back to a plain address */ + if (miss) { + miss =3D cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr,= 0); } =20 - return phys_addr; + if (miss) { + return -1; + } else { + return phys_addr; + } } =20 void cpu_openrisc_mmu_init(OpenRISCCPU *cpu) --=20 2.9.3 From nobody Sun May 5 11:05:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493859355006187.6354199176858; Wed, 3 May 2017 17:55:55 -0700 (PDT) Received: from localhost ([::1]:39207 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d653h-0002oD-JY for importer@patchew.org; Wed, 03 May 2017 20:55:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56823) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d651o-0001NH-Dl for qemu-devel@nongnu.org; Wed, 03 May 2017 20:53:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d651n-0005y6-GS for qemu-devel@nongnu.org; Wed, 03 May 2017 20:53:56 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:35422) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d651n-0005xn-AV for qemu-devel@nongnu.org; Wed, 03 May 2017 20:53:55 -0400 Received: by mail-pf0-x242.google.com with SMTP id o68so716375pfj.2 for ; Wed, 03 May 2017 17:53:55 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id l62sm501595pfb.91.2017.05.03.17.53.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 May 2017 17:53:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=dkFGGmR2gcm5Xi/ekdDkUxK5HozEtZKrS7V8dnqBy5M=; b=UYaOe1AIuZsQ9Y18/irBd8D7ziTcjiBx2issdWIRT+f36HlI8wKczZwIEKPPJNNlmk dBrFgsvNF+PPwt2lxjmYwphfjRtO0sDzJ0FWcLA5fhXv220d8Y3ofI/O1gIjDKGPrlkR QV6z/axjXFG3RrGpMUrHNeMzl9s9wupaL4pHMtlrTsdmsjvFC7W/1CPDogAeYPmRiBw9 oTVsF2IOPJZmu67/N4fLKbDoB/yuuq0/1vlR1IwFGqvRz8t7fr7xdoj7GgbR5x03pd1x GKikHPXl1zg3nKUV+z5zUb3cuX0vC3u96lvQDyt6cJ3+/R0q78yAtt//LmWMe/P1FNKp J3rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=dkFGGmR2gcm5Xi/ekdDkUxK5HozEtZKrS7V8dnqBy5M=; b=f5ubl28mnlmE8eXpIex/hM/bwnMzHancKo9QxHJ0m5P7YI9MhVeizYZxiVsdWj0PB5 wbCgRfTIF3J1ot6+7vmKco2svr16D/sJr+08nwRm4D+u+PLO0N4mptSohiVpoijLFcm9 67CutYJ9HMUS9s+2naSvDozrB7AON9JGACnbJd0g0qpSAI12KRENfkJYGhIF2xdnZCDo 1EcUnwIUCqLO6IouMG8XKfttmmzuoDmhP+Zc1WJYoWDmVWRsNNhvB4xrU/6Fsr7TShf5 at/W9OsTBGOwxuhM3fvZb/Hl0Df9ifKwFEyWdZGVNBVlS5hORi/gg1tUMvao89tTz60N KY4Q== X-Gm-Message-State: AN3rC/7gQawZjATzc5D7G2K6lzLZXRurk7nR4iGuHyiX81VYWwufWL83 cPr43EckXB86GzYZ X-Received: by 10.98.196.207 with SMTP id h76mr7711152pfk.265.1493859234176; Wed, 03 May 2017 17:53:54 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Thu, 4 May 2017 09:53:20 +0900 Message-Id: X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL v2 05/11] target/openrisc: add numcores and coreid support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These are used to identify the processor in SMP system. Their definition has been defined in verilog cores but it not yet part of the spec but it will be soon. The proposal for this is available: https://openrisc.io/proposals/core-identifier-and-number-of-cores Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/sys_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 6ba8162..e13666b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -233,6 +233,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 64): /* ESR */ return env->esr; =20 + case TO_SPR(0, 128): /* COREID */ + return 0; + + case TO_SPR(0, 129): /* NUMCORES */ + return 1; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); return env->tlb->dtlb[0][idx].mr; --=20 2.9.3 From nobody Sun May 5 11:05:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493859510791301.2414480938887; Wed, 3 May 2017 17:58:30 -0700 (PDT) Received: from localhost ([::1]:39215 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d656D-0005AL-I2 for importer@patchew.org; Wed, 03 May 2017 20:58:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56838) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d651s-0001UP-QM for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d651s-0005zw-4B for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:00 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:33750) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d651r-0005zZ-Ud for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:00 -0400 Received: by mail-pg0-x243.google.com with SMTP id s62so797835pgc.0 for ; Wed, 03 May 2017 17:53:59 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id o62sm506804pfj.87.2017.05.03.17.53.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 May 2017 17:53:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=+4Icp+M0RQj6v24329W16eXLptpcG7P4F8rWNRb6XDQ=; b=iWmRMv5tUVnW8NqWRY8QxIoY8ybo4n47lLq2/aFrK1NpiC39mYYVHkbX6aMOlNJPRc OppRRy6Le1vbZBCWMQdkLwBZ+Z0Mb6HcaxO22qYPLWuzDFDCbuISVuhn/n6zur7cTZij nYzjKtUZk4F6n5LGK8EUdUhEzkRiZOh2rQinQBBFBYwTEHi4SXc4PcJL/Q7ZsY4Cc7No o8kXFM72hbEu1eX9DYe+gGtYXO0MJgcPhNBUV7yUfVEQOp6o7b60yeVeAKtQauZyqIuC n3oL+JTFL3VRbXNM1bqTaLvp3vX0o5WFZc/d5gMyl4xcgyv9wsYzfLcO3+sKGgghUkYB 0M4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=+4Icp+M0RQj6v24329W16eXLptpcG7P4F8rWNRb6XDQ=; b=MKsT/uD7+PSXJWnxPLrtDkiaguEOdEyUFuz0RxOvHPpUEJLo/CGG+x2GCfkeJ5sXMU wrBpAXI/pXKnHElNFnEOXo3VJnEZhQNCDSXDB2MVroIO6F4MfZR8sC9metvR2IY0A2oN KQnKCQAeuRDl1tztT3r/s7lXewW8xjTrjVEvLPBxuD0aFs8dDd0pWJ5LDyZxEgPnfMCI msj5XZjnv+FlT0IHR0T7EPC/lsnDXMDMPNCl5NoeFjAs6Ca2BYhLfQrlG7TgmrxmAu2G TXSceh77Hgyj3kcy/wZe7Y1z8EXr10EoRz5RgmUmf8hp3vm7AzWR9sbaX8Q3AbBu/Wqq ew9Q== X-Gm-Message-State: AN3rC/7my32D7FgvMWFA1fB0wfO+6tOOfyYZPRnEit4Ty1uSlUd9BT4M GogZ6nWGpvbaYHZ/ X-Received: by 10.99.60.21 with SMTP id j21mr27406914pga.99.1493859238794; Wed, 03 May 2017 17:53:58 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Thu, 4 May 2017 09:53:21 +0900 Message-Id: <4597992f624c015ceb51fedb4628b3fdb1e5bbaa.1493858877.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL v2 06/11] migration: Add VMSTATE_UINTTL_2DARRAY() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In openRISC we are implementing the shadow registers as a 2d array. Using this target long method rather than direct 32-bit alternatives is consistent with the rest of our vm state serialization logic. Signed-off-by: Stafford Horne --- include/migration/cpu.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/migration/cpu.h b/include/migration/cpu.h index f3d5dfc..a40bd35 100644 --- a/include/migration/cpu.h +++ b/include/migration/cpu.h @@ -18,6 +18,8 @@ VMSTATE_UINT64_EQUAL_V(_f, _s, _v) #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v) +#define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v) \ + VMSTATE_UINT64_2DARRAY_V(_f, _s, _n1, _n2, _v) #define VMSTATE_UINTTL_TEST(_f, _s, _t) \ VMSTATE_UINT64_TEST(_f, _s, _t) #define vmstate_info_uinttl vmstate_info_uint64 @@ -37,6 +39,8 @@ VMSTATE_UINT32_EQUAL_V(_f, _s, _v) #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v) +#define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v) \ + VMSTATE_UINT32_2DARRAY_V(_f, _s, _n1, _n2, _v) #define VMSTATE_UINTTL_TEST(_f, _s, _t) \ VMSTATE_UINT32_TEST(_f, _s, _t) #define vmstate_info_uinttl vmstate_info_uint32 @@ -48,5 +52,8 @@ VMSTATE_UINTTL_EQUAL_V(_f, _s, 0) #define VMSTATE_UINTTL_ARRAY(_f, _s, _n) \ VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, 0) +#define VMSTATE_UINTTL_2DARRAY(_f, _s, _n1, _n2) \ + VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, 0) + =20 #endif --=20 2.9.3 From nobody Sun May 5 11:05:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493859747193927.192908022625; Wed, 3 May 2017 18:02:27 -0700 (PDT) Received: from localhost ([::1]:39235 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d65A1-00006v-IO for importer@patchew.org; Wed, 03 May 2017 21:02:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56855) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d651w-0001VT-F8 for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d651u-00060k-MH for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:04 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:36152) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d651u-00060X-Do for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:02 -0400 Received: by mail-pf0-x243.google.com with SMTP id v14so712853pfd.3 for ; Wed, 03 May 2017 17:54:02 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id s68sm485428pfj.77.2017.05.03.17.54.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 May 2017 17:54:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=zlR4M8UtjiFSlXqd5GXGyVLQ5PnpuU1AfnCkjt6DOBU=; b=ELQ+/9D7QF2WldVQe2ED9n/dFYgZ76uKioDendI6aFdcsMPiCDsigi0FaB0zSoQlT3 ObPi8txC2bAXAaQdBALOu5tDjo2era76dhCN7a8uKAVEkpnQkLtL2fTCMuHO6zGPlAPr HvtOEJBSvqG+IpGO/b80ExGYbxAuFrKBbxR+g6leUtB0hQBGVDmq71dbluHubqd2tgB0 NNk+Ag6CRN9qAf6htS0qnGn0oo29RarX+iieUE1TdfBDPgAvLhf47J7wEYf7MuxR4qAJ U8EYS75AREET6pSscpXDjKQvNZa+STBLlMT+KF6+3skXGRUm7kj9or6gZx88+FO+3InN FDgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=zlR4M8UtjiFSlXqd5GXGyVLQ5PnpuU1AfnCkjt6DOBU=; b=eae3Q791jXFBKA3VAZ0IcqeZEvbt56jZl2JevQbXXBG4xu0rD9c4UXpuyEVD6bMrIp v/2DLoC0vkdgKUml3oYiGmQ5FIp3hHRWdOJ8jCpMsplaL6shsxxD1TjbbdeD0KdmwV+3 2/R/kBAvI55K0hFX7QmraZjKYb/HP4O+Yrivcg9poDxmZSmM5SQ1zMrZao4zpIjKU411 AHfl2IQ9r7Rf9ryp+/ezjSTe+MpXckfEQ9Gc5GtJMS7lJu+J6plemiassu2YZ5320E1L yVZAr0zPUgCMGHa9dfNQINLH494EMLnUfeyuUxdr4OJtUizAxDVIs87NqH6Flf6ZyFQf Anzg== X-Gm-Message-State: AN3rC/71R9CbN3q4XPq0SiiVKBHroXwX7iFnZjFXU2RIBo5SioYASbZ+ lNzoji3THP+/9mLz X-Received: by 10.84.196.100 with SMTP id k91mr53188370pld.165.1493859241233; Wed, 03 May 2017 17:54:01 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Thu, 4 May 2017 09:53:22 +0900 Message-Id: X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PULL v2 07/11] target/openrisc: implement shadow registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Shadow registers are part of the openrisc spec along with sr[cid], as part of the fast context switching feature. When exceptions occur, instead of having to save registers to the stack if enabled the CID will increment and a new set of registers will be available. This patch only implements shadow registers which can be used as extra scratch registers via the mfspr and mtspr if required. This is implemented in a way where it would be easy to add on the fast context switching, currently cid is hardcoded to 0. This is need for openrisc linux smp kernels to boot correctly. Signed-off-by: Stafford Horne --- linux-user/elfload.c | 2 +- linux-user/main.c | 18 +++++++++--------- linux-user/openrisc/target_cpu.h | 6 +++--- linux-user/openrisc/target_signal.h | 2 +- linux-user/signal.c | 17 +++++++++-------- target/openrisc/cpu.c | 4 +++- target/openrisc/cpu.h | 15 +++++++++++++-- target/openrisc/gdbstub.c | 4 ++-- target/openrisc/machine.c | 6 +++--- target/openrisc/sys_helper.c | 9 +++++++++ target/openrisc/translate.c | 5 +++-- 11 files changed, 56 insertions(+), 32 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f520d77..ce77317 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1052,7 +1052,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *= regs, int i; =20 for (i =3D 0; i < 32; i++) { - (*regs)[i] =3D tswapreg(env->gpr[i]); + (*regs)[i] =3D tswapreg(cpu_get_gpr(env, i)); } (*regs)[32] =3D tswapreg(env->pc); (*regs)[33] =3D tswapreg(cpu_get_sr(env)); diff --git a/linux-user/main.c b/linux-user/main.c index 10a3bb3..79d621b 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2590,17 +2590,17 @@ void cpu_loop(CPUOpenRISCState *env) case EXCP_SYSCALL: env->pc +=3D 4; /* 0xc00; */ ret =3D do_syscall(env, - env->gpr[11], /* return value */ - env->gpr[3], /* r3 - r7 are params */ - env->gpr[4], - env->gpr[5], - env->gpr[6], - env->gpr[7], - env->gpr[8], 0, 0); + cpu_get_gpr(env, 11), /* return value */ + cpu_get_gpr(env, 3), /* r3 - r7 are params */ + cpu_get_gpr(env, 4), + cpu_get_gpr(env, 5), + cpu_get_gpr(env, 6), + cpu_get_gpr(env, 7), + cpu_get_gpr(env, 8), 0, 0); if (ret =3D=3D -TARGET_ERESTARTSYS) { env->pc -=3D 4; } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - env->gpr[11] =3D ret; + cpu_set_gpr(env, 11, ret); } break; case EXCP_DPF: @@ -4765,7 +4765,7 @@ int main(int argc, char **argv, char **envp) int i; =20 for (i =3D 0; i < 32; i++) { - env->gpr[i] =3D regs->gpr[i]; + cpu_set_gpr(env, i, regs->gpr[i]); } env->pc =3D regs->pc; cpu_set_sr(env, regs->sr); diff --git a/linux-user/openrisc/target_cpu.h b/linux-user/openrisc/target_= cpu.h index f283d96..606ad6f 100644 --- a/linux-user/openrisc/target_cpu.h +++ b/linux-user/openrisc/target_cpu.h @@ -23,14 +23,14 @@ static inline void cpu_clone_regs(CPUOpenRISCState *env, target_ulong news= p) { if (newsp) { - env->gpr[1] =3D newsp; + cpu_set_gpr(env, 1, newsp); } - env->gpr[11] =3D 0; + cpu_set_gpr(env, 11, 0); } =20 static inline void cpu_set_tls(CPUOpenRISCState *env, target_ulong newtls) { - env->gpr[10] =3D newtls; + cpu_set_gpr(env, 10, newtls); } =20 #endif diff --git a/linux-user/openrisc/target_signal.h b/linux-user/openrisc/targ= et_signal.h index 9f2c493..95a733e 100644 --- a/linux-user/openrisc/target_signal.h +++ b/linux-user/openrisc/target_signal.h @@ -20,7 +20,7 @@ typedef struct target_sigaltstack { =20 static inline abi_ulong get_sp_from_cpustate(CPUOpenRISCState *state) { - return state->gpr[1]; + return cpu_get_gpr(state, 1); } =20 =20 diff --git a/linux-user/signal.c b/linux-user/signal.c index a67db04..3d18d1b 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -4411,7 +4411,7 @@ static void setup_sigcontext(struct target_sigcontext= *sc, CPUOpenRISCState *regs, unsigned long mask) { - unsigned long usp =3D regs->gpr[1]; + unsigned long usp =3D cpu_get_gpr(regs, 1); =20 /* copy the regs. they are first in sc so we can use sc directly */ =20 @@ -4436,7 +4436,7 @@ static inline abi_ulong get_sigframe(struct target_si= gaction *ka, CPUOpenRISCState *regs, size_t frame_size) { - unsigned long sp =3D regs->gpr[1]; + unsigned long sp =3D cpu_get_gpr(regs, 1); int onsigstack =3D on_sig_stack(sp); =20 /* redzone */ @@ -4489,7 +4489,8 @@ static void setup_rt_frame(int sig, struct target_sig= action *ka, __put_user(0, &frame->uc.tuc_link); __put_user(target_sigaltstack_used.ss_sp, &frame->uc.tuc_stack.ss_sp); - __put_user(sas_ss_flags(env->gpr[1]), &frame->uc.tuc_stack.ss_flags); + __put_user(sas_ss_flags(cpu_get_gpr(env, 1)), + &frame->uc.tuc_stack.ss_flags); __put_user(target_sigaltstack_used.ss_size, &frame->uc.tuc_stack.ss_size); setup_sigcontext(&frame->sc, env, set->sig[0]); @@ -4512,13 +4513,13 @@ static void setup_rt_frame(int sig, struct target_s= igaction *ka, =20 /* Set up registers for signal handler */ env->pc =3D (unsigned long)ka->_sa_handler; /* what we enter NOW */ - env->gpr[9] =3D (unsigned long)return_ip; /* what we enter LATER */ - env->gpr[3] =3D (unsigned long)sig; /* arg 1: signo */ - env->gpr[4] =3D (unsigned long)&frame->info; /* arg 2: (siginfo_t*) */ - env->gpr[5] =3D (unsigned long)&frame->uc; /* arg 3: ucontext */ + cpu_set_gpr(env, 9, (unsigned long)return_ip); /* what we enter LA= TER */ + cpu_set_gpr(env, 3, (unsigned long)sig); /* arg 1: signo */ + cpu_set_gpr(env, 4, (unsigned long)&frame->info); /* arg 2: (siginfo_= t*) */ + cpu_set_gpr(env, 5, (unsigned long)&frame->uc); /* arg 3: ucontext = */ =20 /* actually move the usp to reflect the stacked frame */ - env->gpr[1] =3D (unsigned long)frame; + cpu_set_gpr(env, 1, (unsigned long)frame); =20 return; =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 1524ed9..6c1ed07 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -52,7 +52,7 @@ static void openrisc_cpu_reset(CPUState *s) s->exception_index =3D -1; =20 cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; - cpu->env.cpucfgr =3D CPUCFGR_OB32S | CPUCFGR_OF32S; + cpu->env.cpucfgr =3D CPUCFGR_OB32S | CPUCFGR_OF32S | CPUCFGR_NSGF; cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 <= < 2)); cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 <= < 2)); =20 @@ -132,6 +132,7 @@ static void or1200_initfn(Object *obj) { OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 + set_feature(cpu, OPENRISC_FEATURE_NSGF); set_feature(cpu, OPENRISC_FEATURE_OB32S); set_feature(cpu, OPENRISC_FEATURE_OF32S); set_feature(cpu, OPENRISC_FEATURE_EVBAR); @@ -141,6 +142,7 @@ static void openrisc_any_initfn(Object *obj) { OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 + set_feature(cpu, OPENRISC_FEATURE_NSGF); set_feature(cpu, OPENRISC_FEATURE_OB32S); set_feature(cpu, OPENRISC_FEATURE_EVBAR); } diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 1958b72..e159b22 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -275,7 +275,8 @@ typedef struct CPUOpenRISCTLBContext { #endif =20 typedef struct CPUOpenRISCState { - target_ulong gpr[32]; /* General registers */ + target_ulong shadow_gpr[16][32]; /* Shadow registers */ + target_ulong pc; /* Program counter */ target_ulong ppc; /* Prev PC */ target_ulong jmp_pc; /* Jump PC */ @@ -399,6 +400,16 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, #define TB_FLAGS_R0_0 2 #define TB_FLAGS_OVE SR_OVE =20 +static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i) +{ + return env->shadow_gpr[0][i]; +} + +static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val) +{ + env->shadow_gpr[0][i] =3D val; +} + static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *f= lags) @@ -406,7 +417,7 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCStat= e *env, *pc =3D env->pc; *cs_base =3D 0; *flags =3D (env->dflag - | (env->gpr[0] =3D=3D 0 ? TB_FLAGS_R0_0 : 0) + | (cpu_get_gpr(env, 0) =3D=3D 0 ? TB_FLAGS_R0_0 : 0) | (env->sr & SR_OVE)); } =20 diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index b18c7e9..f9af650 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -28,7 +28,7 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t = *mem_buf, int n) CPUOpenRISCState *env =3D &cpu->env; =20 if (n < 32) { - return gdb_get_reg32(mem_buf, env->gpr[n]); + return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n)); } else { switch (n) { case 32: /* PPC */ @@ -61,7 +61,7 @@ int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t= *mem_buf, int n) tmp =3D ldl_p(mem_buf); =20 if (n < 32) { - env->gpr[n] =3D tmp; + cpu_set_gpr(env, n, tmp); } else { switch (n) { case 32: /* PPC */ diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 686eaa3..2bf71c3 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -47,10 +47,10 @@ static const VMStateInfo vmstate_sr =3D { =20 static const VMStateDescription vmstate_env =3D { .name =3D "env", - .version_id =3D 4, - .minimum_version_id =3D 4, + .version_id =3D 5, + .minimum_version_id =3D 5, .fields =3D (VMStateField[]) { - VMSTATE_UINTTL_ARRAY(gpr, CPUOpenRISCState, 32), + VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), VMSTATE_UINTTL(pc, CPUOpenRISCState), VMSTATE_UINTTL(ppc, CPUOpenRISCState), VMSTATE_UINTTL(jmp_pc, CPUOpenRISCState), diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index e13666b..fa3d6a4 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -92,6 +92,11 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(0, 64): /* ESR */ env->esr =3D rb; break; + + case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ + idx =3D (spr - 1024); + env->shadow_gpr[idx / 32][idx % 32] =3D rb; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); if (!(rb & 1)) { @@ -239,6 +244,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 129): /* NUMCORES */ return 1; =20 + case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ + idx =3D (spr - 1024); + return env->shadow_gpr[idx / 32][idx % 32]; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); return env->tlb->dtlb[0][idx].mr; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7c4cbf2..e49518e 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -107,7 +107,8 @@ void openrisc_translate_init(void) "mac"); for (i =3D 0; i < 32; i++) { cpu_R[i] =3D tcg_global_mem_new(cpu_env, - offsetof(CPUOpenRISCState, gpr[i]), + offsetof(CPUOpenRISCState, + shadow_gpr[0][i]), regnames[i]); } cpu_R0 =3D cpu_R[0]; @@ -1662,7 +1663,7 @@ void openrisc_cpu_dump_state(CPUState *cs, FILE *f, =20 cpu_fprintf(f, "PC=3D%08x\n", env->pc); for (i =3D 0; i < 32; ++i) { - cpu_fprintf(f, "R%02d=3D%08x%c", i, env->gpr[i], + cpu_fprintf(f, "R%02d=3D%08x%c", i, cpu_get_gpr(env, i), (i % 4) =3D=3D 3 ? '\n' : ' '); } } --=20 2.9.3 From nobody Sun May 5 11:05:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493859501754554.0175357004142; Wed, 3 May 2017 17:58:21 -0700 (PDT) Received: from localhost ([::1]:39213 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d6564-00051X-E5 for importer@patchew.org; Wed, 03 May 2017 20:58:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56865) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d651x-0001WX-Bs for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d651w-00061e-Ms for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:05 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:34722) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d651w-00061G-Gy for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:04 -0400 Received: by mail-pf0-x242.google.com with SMTP id d1so720583pfe.1 for ; Wed, 03 May 2017 17:54:04 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id p90sm487849pfa.119.2017.05.03.17.54.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 May 2017 17:54:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=hU1jGZmFTTYIW7x4xlhS9QjPIudVQLVMDBIoTvmEol0=; b=Fe8owwuZo4YeuxK700SVhviWTQiBbACRUjnH4/M5FRnG/zlOa62nqeu3WYUz/Kk0cw l6qL4oh1VtyLHrFpsruPXMQO4u7cYDnICiydjuvLBVi/ao8hfxJ4v1+RO8NwNhlOxjPP 1NaArVVAXrWgckBIgy6XTyzADXypZ7Rx39O1pyBsdVRYd/pbvCCluq0/Phho+1KZMg9I uapLagLYpgRm7IMEB+AuvLm3MfdjMZilDgADncsNH8D3a3mvQJNjyeRe9cq5eImVJfjF aBGOCcjdKeUxcaIWQMZfqgkoqBBdec48zLX83w62AruYt5AR2U6ZcHvYqlvRaxz3yCP7 pNqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=hU1jGZmFTTYIW7x4xlhS9QjPIudVQLVMDBIoTvmEol0=; b=V5NlZzfExKfM1oU32orbsXQ7dwqO7RsoEaQRMVlltxxOT8C0Yp9v74cFGdemZWia3/ M1qBK4qgdasecmUjhIDXkj789Lr4jBYOifzwdRiGtHN1phloc7ppT02ZYEez92OYUXkg u72y41+BZWj0+s0shSbOy6ZQgnohagA7rX4Bv3KXDzO9FSGX2eQN7IyeSSHEY8qgzdTC JznGjY5j0nCZyiIxcCqe304AwjmbeXeUGpM5Y3bP3U5eIXx1OJATROISKKsllA12RsAs PDpSZZwd1i65emSyfSvFWfzm/qUI+G3f6s044CW6RXy1OTBgX4csbgn56stTqsHSrH87 TIPQ== X-Gm-Message-State: AN3rC/50L1eGC80IDdXzPG0WdiQcGFe8/2BLGzJcC2hLFw/46sWIgYyv BRaI1Y2Hn1NggA== X-Received: by 10.99.127.89 with SMTP id p25mr13334221pgn.92.1493859243632; Wed, 03 May 2017 17:54:03 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Thu, 4 May 2017 09:53:23 +0900 Message-Id: X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL v2 08/11] migration: Add VMSTATE_STRUCT_2DARRAY() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For openrisc we implement tlb state as a 2d array of tlb entry structs. This is added to allow easy storing of state of 2d arrays. Signed-off-by: Stafford Horne --- include/migration/vmstate.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index f2dbf84..4834e55 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -499,6 +499,19 @@ extern const VMStateInfo vmstate_info_qtailq; .offset =3D vmstate_offset_array(_state, _field, _type, _num),\ } =20 +#define VMSTATE_STRUCT_2DARRAY_TEST(_field, _state, _n1, _n2, _test, \ + _version, _vmsd, _type) { \ + .name =3D (stringify(_field)), \ + .num =3D (_n1) * (_n2), \ + .field_exists =3D (_test), \ + .version_id =3D (_version), \ + .vmsd =3D &(_vmsd), \ + .size =3D sizeof(_type), \ + .flags =3D VMS_STRUCT | VMS_ARRAY, \ + .offset =3D vmstate_offset_2darray(_state, _field, _type, \ + _n1, _n2), \ +} + #define VMSTATE_STRUCT_VARRAY_UINT8(_field, _state, _field_num, _version, = _vmsd, _type) { \ .name =3D (stringify(_field)), \ .num_offset =3D vmstate_offset_value(_state, _field_num, uint8_t), \ @@ -746,6 +759,11 @@ extern const VMStateInfo vmstate_info_qtailq; VMSTATE_STRUCT_ARRAY_TEST(_field, _state, _num, NULL, _version, \ _vmsd, _type) =20 +#define VMSTATE_STRUCT_2DARRAY(_field, _state, _n1, _n2, _version, \ + _vmsd, _type) \ + VMSTATE_STRUCT_2DARRAY_TEST(_field, _state, _n1, _n2, NULL, \ + _version, _vmsd, _type) + #define VMSTATE_BUFFER_UNSAFE_INFO(_field, _state, _version, _info, _size)= \ VMSTATE_BUFFER_UNSAFE_INFO_TEST(_field, _state, NULL, _version, _info,= \ _size) --=20 2.9.3 From nobody Sun May 5 11:05:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493859637797760.3285028889842; Wed, 3 May 2017 18:00:37 -0700 (PDT) Received: from localhost ([::1]:39227 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d658G-00077N-Cs for importer@patchew.org; Wed, 03 May 2017 21:00:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56885) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d651z-0001dC-Uj for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d651z-00062i-47 for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:08 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:36757) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d651y-00062P-UQ for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:07 -0400 Received: by mail-pg0-x243.google.com with SMTP id v1so783211pgv.3 for ; Wed, 03 May 2017 17:54:06 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id e71sm502419pgc.17.2017.05.03.17.54.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 May 2017 17:54:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=aLPISuS5eSd812PwiN7tjAxR9Wk2P1U1KxqUk+A/dp4=; b=UqJv0ulBiqCp3sdKb6KQXOEgInyt4xYWCpP8OLy/jo63CEzvb+wDdyGdVn02FFclww k0WeorZlnarPgCGObeiMQjrY5bvFlGUTiyE31/ErnL7acXYulBPu/2TbqJWwYCUtWAST xlex5AdNbhdkEocP+P/qPmnqHhIx/Sv1Niht/sg9AzZAgoQr2XBKgCV6xs40k/KR27SJ EywoxvKEHPlrrQf3zds9zTyS9LNZIKXuNxzDGjcfTNU9UVdBttn2uRmXTRzvHZ3mjxCp WnA+pmLuFg+hcv2D91RNw238ZP/Jn23OP1LlAr3NfezgAJk9+RvEMcoEAq7kfLbK8L7v XM+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=aLPISuS5eSd812PwiN7tjAxR9Wk2P1U1KxqUk+A/dp4=; b=sxGKqML5+oT3m1CkAaAV0BhhBFbqqP8m3jNRYprXdMX5ZzRwo3LmFu/g2AMpAaQnao 7TgH/JePj2FxcaD8kRRAsHdWXZciZdcwIgizCnhzxvRw1JL99Ls2gwImXQplZfuTw0b9 m5jj86HfDfCSorJdoESfzH5Y1e4DUDEuynamg2/D+7uVGcb9ioyyaO9xdazzUT2+bsJ6 jF0gaoSC5XhL3qzzUOOrhcKBy6mTySzt1WSDwtagskcGTVPV1XA+NPGzDYq4doH8Wue6 /vWUPbFYgxI8KR2YzpZB6OS5YjhCNFDQ0kcpw2phW5YL7cuWLjQ9m2j5gtPgHQZWIwTo HVXw== X-Gm-Message-State: AN3rC/5cwaT56HyGyYCSiXZhVZZ5tkyymmMJWTfV1NIEGYz/ebj3y+Yw R1IfSxEo9XTXdw== X-Received: by 10.84.224.77 with SMTP id a13mr32785955plt.132.1493859246040; Wed, 03 May 2017 17:54:06 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Thu, 4 May 2017 09:53:24 +0900 Message-Id: X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL v2 09/11] target/openrisc: Implement full vmstate serialization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Previously serialization did not persist the tlb, timer, pic and other key state items. This meant snapshotting and restoring a running os would crash. After adding these I am able to take snapshots of a running linux os and restore at a later time. I am currently not trying to maintain capatibility with older versions as I do not believe this really worked before or anyone used it. Signed-off-by: Stafford Horne --- target/openrisc/machine.c | 73 +++++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 71 insertions(+), 2 deletions(-) diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 2bf71c3..a82be62 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -24,6 +24,63 @@ #include "hw/boards.h" #include "migration/cpu.h" =20 +static int env_post_load(void *opaque, int version_id) +{ + CPUOpenRISCState *env =3D opaque; + + /* Restore MMU handlers */ + if (env->sr & SR_DME) { + env->tlb->cpu_openrisc_map_address_data =3D + &cpu_openrisc_get_phys_data; + } else { + env->tlb->cpu_openrisc_map_address_data =3D + &cpu_openrisc_get_phys_nommu; + } + + if (env->sr & SR_IME) { + env->tlb->cpu_openrisc_map_address_code =3D + &cpu_openrisc_get_phys_code; + } else { + env->tlb->cpu_openrisc_map_address_code =3D + &cpu_openrisc_get_phys_nommu; + } + + + return 0; +} + +static const VMStateDescription vmstate_tlb_entry =3D { + .name =3D "tlb_entry", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(mr, OpenRISCTLBEntry), + VMSTATE_UINTTL(tr, OpenRISCTLBEntry), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_cpu_tlb =3D { + .name =3D "cpu_tlb", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT_2DARRAY(itlb, CPUOpenRISCTLBContext, + ITLB_WAYS, ITLB_SIZE, 0, + vmstate_tlb_entry, OpenRISCTLBEntry), + VMSTATE_STRUCT_2DARRAY(dtlb, CPUOpenRISCTLBContext, + DTLB_WAYS, DTLB_SIZE, 0, + vmstate_tlb_entry, OpenRISCTLBEntry), + VMSTATE_END_OF_LIST() + } +}; + +#define VMSTATE_CPU_TLB(_f, _s) \ + VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_tlb, CPUOpenRISCTLBContext) + + static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField *fi= eld) { CPUOpenRISCState *env =3D opaque; @@ -47,8 +104,9 @@ static const VMStateInfo vmstate_sr =3D { =20 static const VMStateDescription vmstate_env =3D { .name =3D "env", - .version_id =3D 5, - .minimum_version_id =3D 5, + .version_id =3D 6, + .minimum_version_id =3D 6, + .post_load =3D env_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), VMSTATE_UINTTL(pc, CPUOpenRISCState), @@ -79,9 +137,20 @@ static const VMStateDescription vmstate_env =3D { VMSTATE_UINT32(cpucfgr, CPUOpenRISCState), VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState), VMSTATE_UINT32(immucfgr, CPUOpenRISCState), + VMSTATE_UINT32(evbar, CPUOpenRISCState), VMSTATE_UINT32(esr, CPUOpenRISCState), VMSTATE_UINT32(fpcsr, CPUOpenRISCState), VMSTATE_UINT64(mac, CPUOpenRISCState), + + VMSTATE_CPU_TLB(tlb, CPUOpenRISCState), + + VMSTATE_TIMER_PTR(timer, CPUOpenRISCState), + VMSTATE_UINT32(ttmr, CPUOpenRISCState), + VMSTATE_UINT32(ttcr, CPUOpenRISCState), + + VMSTATE_UINT32(picmr, CPUOpenRISCState), + VMSTATE_UINT32(picsr, CPUOpenRISCState), + VMSTATE_END_OF_LIST() } }; --=20 2.9.3 From nobody Sun May 5 11:05:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149385950990151.603263662152926; Wed, 3 May 2017 17:58:29 -0700 (PDT) Received: from localhost ([::1]:39214 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d656C-00059d-LW for importer@patchew.org; Wed, 03 May 2017 20:58:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56911) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d6525-0001iO-DQ for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d6522-00063u-8f for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:13 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:33759) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d6522-00063d-2n for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:10 -0400 Received: by mail-pg0-x243.google.com with SMTP id s62so798242pgc.0 for ; Wed, 03 May 2017 17:54:09 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id q24sm498994pgn.58.2017.05.03.17.54.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 May 2017 17:54:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=ZSRaRZ7Gpo/Gz2A0pzY4GEBaKCItT05/PrKrzTgD0LE=; b=YTKPmCkmh6SQ5xQOVTEoItpcFLtUj5K6MSUL9U4NiWSsY5MfLejYejHJNtIJq8WyPZ UyR4QuesVPr/oUb3rfO8YmONqFzJz+XvMbwmuNzdv7sTMCqk76Rf5wXF8nag+nU7zYRm YXRM/UHCWx0400Xor0lbr/zFZRYPxpARKDHJUgEpEks1smIG8BYY0tOQjH/fFoDSfQzO OaO70+A34TGJ+bHA3s8WGVnOXl+RZogrHYGUMz6Xe2eY7Z4Cy0zlNyRFrP3mCCaTLLXx thcoDk8gPH2gRgK6+j5w16WrMT2m9w5awZeod7fkYhdeQB4uKqaUCzlgo5EfZ3+tVKgD h7nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=ZSRaRZ7Gpo/Gz2A0pzY4GEBaKCItT05/PrKrzTgD0LE=; b=gGrmcwpaMfQwPXPVmymbleerXKcgVPO+sm6NZJqwZRVbR7/zrisGn5HEFVDDc089Bn EJHwVQsqOVd+oKq9S1yxgjOaNW0Y1ZHa05Scy+3rKN4HheQoQIjflGmkuvVYv3dPVPeS /IxY4ijQdN9JDH/QQ9c+dklB0cdYEoyTlfKkTwVuudfFDFWwO35CWuzHHtD30jZiCAXs DJbCmzsNDYqerb3VdBmDCIfo0Qwwu8BJdBdunVkpIm8FYaFT0cTrhXkbLnK5ORZSkybx 8fvsRRe7X+7q4+vPQEyw9HywRQFdwNt1Mlz/6Jma+/ME3QqAjnwXYK0Vt/ZyHsK8yW4t LBiw== X-Gm-Message-State: AN3rC/6D7oK/BczTYKXAhk8eP3hUCwECjmm4kIPUZQWUsaQkdasq4TYb v5nkY/basdKwJdoS X-Received: by 10.98.41.7 with SMTP id p7mr7696358pfp.155.1493859248916; Wed, 03 May 2017 17:54:08 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Thu, 4 May 2017 09:53:25 +0900 Message-Id: <48a1b62baaf45e4d8d5ffac77647f7e898d7f7f1.1493858877.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL v2 10/11] target/openrisc: Remove duplicate features property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The features property has stored the exact same thing as the cpucfgr spr. Remove the feature enum and property as it is not needed. In order to preserve the behavior or keeping features accross reset this patch moves cpucfgr into the non reset region of the state struct. Since the cpucfgr is read only this means we only need to sset cpucfgr once during class init. Signed-off-by: Stafford Horne --- target/openrisc/cpu.c | 17 +++-------------- target/openrisc/cpu.h | 16 ++-------------- 2 files changed, 5 insertions(+), 28 deletions(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 6c1ed07..c9b3f22 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -52,7 +52,6 @@ static void openrisc_cpu_reset(CPUState *s) s->exception_index =3D -1; =20 cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; - cpu->env.cpucfgr =3D CPUCFGR_OB32S | CPUCFGR_OF32S | CPUCFGR_NSGF; cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 <= < 2)); cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 <= < 2)); =20 @@ -65,12 +64,6 @@ static void openrisc_cpu_reset(CPUState *s) #endif } =20 -static inline void set_feature(OpenRISCCPU *cpu, int feature) -{ - cpu->feature |=3D feature; - cpu->env.cpucfgr =3D cpu->feature; -} - static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -132,19 +125,15 @@ static void or1200_initfn(Object *obj) { OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 - set_feature(cpu, OPENRISC_FEATURE_NSGF); - set_feature(cpu, OPENRISC_FEATURE_OB32S); - set_feature(cpu, OPENRISC_FEATURE_OF32S); - set_feature(cpu, OPENRISC_FEATURE_EVBAR); + cpu->env.cpucfgr =3D CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | + CPUCFGR_EVBARP; } =20 static void openrisc_any_initfn(Object *obj) { OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 - set_feature(cpu, OPENRISC_FEATURE_NSGF); - set_feature(cpu, OPENRISC_FEATURE_OB32S); - set_feature(cpu, OPENRISC_FEATURE_EVBAR); + cpu->env.cpucfgr =3D CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP; } =20 typedef struct OpenRISCCPUInfo { diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index e159b22..938ccc3 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -196,18 +196,6 @@ enum { SR_SCE =3D (1 << 17), }; =20 -/* OpenRISC Hardware Capabilities */ -enum { - OPENRISC_FEATURE_NSGF =3D (15 << 0), - OPENRISC_FEATURE_CGF =3D (1 << 4), - OPENRISC_FEATURE_OB32S =3D (1 << 5), - OPENRISC_FEATURE_OB64S =3D (1 << 6), - OPENRISC_FEATURE_OF32S =3D (1 << 7), - OPENRISC_FEATURE_OF64S =3D (1 << 8), - OPENRISC_FEATURE_OV64S =3D (1 << 9), - OPENRISC_FEATURE_EVBAR =3D (1 << 12), -}; - /* Tick Timer Mode Register */ enum { TTMR_TP =3D (0xfffffff), @@ -292,7 +280,6 @@ typedef struct CPUOpenRISCState { uint32_t sr; /* Supervisor register, without SR_{F,CY,OV}= */ uint32_t vr; /* Version register */ uint32_t upr; /* Unit presence register */ - uint32_t cpucfgr; /* CPU configure register */ uint32_t dmmucfgr; /* DMMU configure register */ uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ @@ -311,6 +298,8 @@ typedef struct CPUOpenRISCState { CPU_COMMON =20 /* Fields from here on are preserved across CPU reset. */ + uint32_t cpucfgr; /* CPU configure register */ + #ifndef CONFIG_USER_ONLY CPUOpenRISCTLBContext * tlb; =20 @@ -337,7 +326,6 @@ typedef struct OpenRISCCPU { =20 CPUOpenRISCState env; =20 - uint32_t feature; /* CPU Capabilities */ } OpenRISCCPU; =20 static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env) --=20 2.9.3 From nobody Sun May 5 11:05:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493859636882333.3261202325565; Wed, 3 May 2017 18:00:36 -0700 (PDT) Received: from localhost ([::1]:39226 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d658F-00076g-3X for importer@patchew.org; Wed, 03 May 2017 21:00:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56920) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d6526-0001j6-7W for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d6525-00065B-5b for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:14 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:36764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d6524-00064r-UI for qemu-devel@nongnu.org; Wed, 03 May 2017 20:54:13 -0400 Received: by mail-pg0-x241.google.com with SMTP id v1so783465pgv.3 for ; Wed, 03 May 2017 17:54:12 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id u128sm510393pfb.55.2017.05.03.17.54.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 May 2017 17:54:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=9ZK/1O75svRsvUs5m9/Z7c3iaU+T/Tu7NOxwmmb8O5Y=; b=W+9IA7+JfqSoP442X7SYi476VfV/pJy7LqBAjYZGtOjb2n5KiCYSaaVTNWp06O+GyJ rNsnVtpOHwR4b2RyHxwmXvIkIKuJuLpCjvHyJrcEi3E91eRSeg5cpa0cccpzg9g798ur ss8H3IaPZ+qfWEiZ6xSTxL8W3ZzwPuTEt2XB3Fj5qjrs8wOt2MVfsYH5M48gHt3g3/Xo mI9X14JwArwHtA/THXacFclvfHd75MddVeWFgBHhRtjRrQ4/gdgacTUkjIR9bPaNBl6e Kmt3Se7btU9Hr5is3XKTHr+NumynUZmxcj2iDFGGNTHaIb3bnq7XWjPvu6rzo5R73zD7 AW2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=9ZK/1O75svRsvUs5m9/Z7c3iaU+T/Tu7NOxwmmb8O5Y=; b=cJOePqdWqRGxJkjqamC8ew35yXFmI/4dHosBTsVz1uEGEobqrOmu8o8Q9YSz/MItpK I8zGgBj442t5lLByRhPhk0PA3JMTNMBFQnsmIbfW57IF2Ng0HfwLVOBHriYxerzav9Y+ fNRgIeyQJ3HzbtEpMkiEtHbKPUQuKOS4RHXWTkf9PFVZPsd/+oXvzQTwlcl0gbM1cOPF W/KqipMnS1Gu01azJFcElDr2wyw3uqSum85Ui0/yhPsk0gUGrjzwnLwDagXeBdRLixv0 3bZh28yvMeAKUIfUT1K2J8JdSN6gUeIymUitWALfxz58XZMpg3AgObNlQxEBjB4y8EsC B7IA== X-Gm-Message-State: AN3rC/6mT4tPzjQI7Asr0gs9UPfgO/05+cdjnEwHdsogyrhfGHrtzAfS UIM++XN86+q9gO1c X-Received: by 10.84.217.215 with SMTP id d23mr20582645plj.114.1493859251800; Wed, 03 May 2017 17:54:11 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Thu, 4 May 2017 09:53:26 +0900 Message-Id: X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL v2 11/11] target/openrisc: Support non-busy idle state using PMR SPR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The OpenRISC architecture has the Power Management Register (PMR) special purpose register to manage cpu power states. The interesting modes are: * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt * Sleep Mode (SME) - Stop cpu and all units - wake on interrupt * Suspend Model (SUME) - Stop cpu and all units - wake on reset The linux kernel will set DME when idle. This patch implements the PMR SPR and halts the qemu cpu when there is a change to DME or SME. This means that openrisc qemu in no longer peggs a host cpu at 100%. In order for this to work we need to kick the CPU when timers are expired. Update the cpu timer to kick the cpu upon each timer event. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- hw/openrisc/cputimer.c | 1 + target/openrisc/cpu.c | 3 ++- target/openrisc/cpu.h | 10 ++++++++++ target/openrisc/interrupt.c | 2 ++ target/openrisc/machine.c | 1 + target/openrisc/sys_helper.c | 13 +++++++++++++ 6 files changed, 29 insertions(+), 1 deletion(-) diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c index a98c799..febc469 100644 --- a/hw/openrisc/cputimer.c +++ b/hw/openrisc/cputimer.c @@ -61,6 +61,7 @@ void cpu_openrisc_timer_update(OpenRISCCPU *cpu) } next =3D now + (uint64_t)wait * TIMER_PERIOD; timer_mod(cpu->env.timer, next); + qemu_cpu_kick(CPU(cpu)); } =20 void cpu_openrisc_count_start(OpenRISCCPU *cpu) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index c9b3f22..1d6330c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -51,7 +51,8 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.lock_addr =3D -1; s->exception_index =3D -1; =20 - cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; + cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | + UPR_PMP; cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 <= < 2)); cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 <= < 2)); =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 938ccc3..2721432 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -140,6 +140,15 @@ enum { IMMUCFGR_HTR =3D (1 << 11), }; =20 +/* Power management register */ +enum { + PMR_SDF =3D (15 << 0), + PMR_DME =3D (1 << 4), + PMR_SME =3D (1 << 5), + PMR_DCGE =3D (1 << 6), + PMR_SUME =3D (1 << 7), +}; + /* Float point control status register */ enum { FPCSR_FPEE =3D 1, @@ -284,6 +293,7 @@ typedef struct CPUOpenRISCState { uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ uint32_t evbar; /* Exception vector base address register */ + uint32_t pmr; /* Power Management Register */ uint32_t fpcsr; /* Float register */ float_status fp_status; =20 diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 2c91fab..3959671 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -60,6 +60,8 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr |=3D SR_SM; env->sr &=3D ~SR_IEE; env->sr &=3D ~SR_TEE; + env->pmr &=3D ~PMR_DME; + env->pmr &=3D ~PMR_SME; env->tlb->cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_nom= mu; env->tlb->cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_nom= mu; env->lock_addr =3D -1; diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index a82be62..a20cce7 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -138,6 +138,7 @@ static const VMStateDescription vmstate_env =3D { VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState), VMSTATE_UINT32(immucfgr, CPUOpenRISCState), VMSTATE_UINT32(evbar, CPUOpenRISCState), + VMSTATE_UINT32(pmr, CPUOpenRISCState), VMSTATE_UINT32(esr, CPUOpenRISCState), VMSTATE_UINT32(fpcsr, CPUOpenRISCState), VMSTATE_UINT64(mac, CPUOpenRISCState), diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index fa3d6a4..abdef5d 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "exception.h" =20 #define TO_SPR(group, number) (((group) << 11) + (number)) =20 @@ -141,6 +142,15 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(5, 2): /* MACHI */ env->mac =3D deposit64(env->mac, 32, 32, rb); break; + case TO_SPR(8, 0): /* PMR */ + env->pmr =3D rb; + if (env->pmr & PMR_DME || env->pmr & PMR_SME) { + cpu_restore_state(cs, GETPC()); + env->pc +=3D 4; + cs->halted =3D 1; + raise_exception(cpu, EXCP_HALTED); + } + break; case TO_SPR(9, 0): /* PICMR */ env->picmr |=3D rb; break; @@ -287,6 +297,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, return env->mac >> 32; break; =20 + case TO_SPR(8, 0): /* PMR */ + return env->pmr; + case TO_SPR(9, 0): /* PICMR */ return env->picmr; =20 --=20 2.9.3