From nobody Fri May 3 07:11:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493594207929517.4085737295968; Sun, 30 Apr 2017 16:16:47 -0700 (PDT) Received: from localhost ([::1]:46182 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y58-0002xy-GG for importer@patchew.org; Sun, 30 Apr 2017 19:16:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60333) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y3L-0001od-84 for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:14:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d4y3K-0006Rq-8x for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:14:55 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:33914) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d4y3K-0006RJ-31 for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:14:54 -0400 Received: by mail-pg0-x241.google.com with SMTP id t7so13879547pgt.1 for ; Sun, 30 Apr 2017 16:14:54 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id j65sm20631136pfc.86.2017.04.30.16.14.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 30 Apr 2017 16:14:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-transfer-encoding; bh=hHxUOFAiwX7+DMZ8XogibcJIMTdjwTyPpfPjXB73tTs=; b=vd2PBQQfb0Rr3elOlG9r/D/bY7mI+PI1KKDBG7RoGgciShHFVrHOIHZje3ynVZNuAW 0vp59S7tZepUJe4QSi1Lyu9nLOTxr599I6enG4+5stXZHMvWvEUlNOKCZEjifs8QMn7/ M1oCH6td6Q6bMpyg3XBvH7uGSD7PrTwvoMPS66hsSBMNbvPKUfPzO6vDxtaLfnB+IDTc h1HV+iQtiLN+s/L+nlJZziNu6qb/RLwtjhh/o2A4+2+3QrMR6CmsxAcuJnzWOFV0atb4 d4Bc7+pcQe8j2KcN3IcjBi0v0u1FD0c8zLsa6ksq66Fk3Jlge/ADEeJMJeKN0G4zSvdY +N1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references:mime-version :content-transfer-encoding; bh=hHxUOFAiwX7+DMZ8XogibcJIMTdjwTyPpfPjXB73tTs=; b=DMyKbPOjqA+szBDm51kIRY//RJgYchqQKGnsmkgzsN+Zo2EYUUvIH6GMPWcY4MqjmO h7uBEfv9oToG2N3fA5VAtITuuxCpGUS+VqM2wQA9huiAZoyvKE3P+yOHGzjvabs8AIGz FCtWIuaGY65NC0HRLl1IDGitfX6dtd6y4+i3ZR0p6PDSZsLVAt8aLXDeR3Ka8n3d2+sa OXQNXbGMRu0Hy13srVO/dBXKoWqOUzjohcp2bd5Y80ZibswnQT8UgQJKJTHOPnYiItoF d0hPTc3F3RM4O+YGKdYN5pAxnfNU5Zj0KCPP1WF50YZiXYfbzpqtUtyuV1/vQSTmV1mH Ihsg== X-Gm-Message-State: AN3rC/7bwqGkHFTSELqAotAdRv1NLsrs4qjqRz8wA+VJJZlUJnO/Kbbx xPTyAGXKmHoipw== X-Received: by 10.99.185.6 with SMTP id z6mr24055854pge.124.1493594093259; Sun, 30 Apr 2017 16:14:53 -0700 (PDT) From: Stafford Horne To: peter.maydell@linaro.org Date: Mon, 1 May 2017 08:14:15 +0900 Message-Id: <1d7cf18d79c85031998cc8e628414eac292ca694.1493593744.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 01/11] MAINTAINERS: Add myself as openrisc maintainer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , QEMU Development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Jia has claimed he is no longer able to maintain. I have fixing bugs here and there and getting familiar with the code base. Orignal thread from Jia: https://lists.librecores.org/pipermail/openrisc/2017-January/000321.html Signed-off-by: Stafford Horne Reviewed-by: Alex Benn=C3=A9e --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index c60235e..21803ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -196,8 +196,8 @@ F: hw/nios2/ F: disas/nios2.c =20 OpenRISC -M: Jia Liu -S: Maintained +M: Stafford Horne +S: Odd Fixes F: target/openrisc/ F: hw/openrisc/ F: tests/tcg/openrisc/ --=20 2.9.3 From nobody Fri May 3 07:11:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149359436316741.232059275088204; Sun, 30 Apr 2017 16:19:23 -0700 (PDT) Received: from localhost ([::1]:46194 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y7c-0004sq-N3 for importer@patchew.org; Sun, 30 Apr 2017 19:19:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60354) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y3N-0001qI-Or for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:14:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d4y3M-0006TC-K7 for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:14:57 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:34897) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d4y3M-0006Sn-Cd for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:14:56 -0400 Received: by mail-pf0-x244.google.com with SMTP id o68so6703497pfj.2 for ; Sun, 30 Apr 2017 16:14:56 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id d24sm20905519pfb.97.2017.04.30.16.14.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 30 Apr 2017 16:14:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=B22Il4U+lW9qJRmIpKE7jAR5AR4P5G5MCstdmwVkA+0=; b=mhrZrYvvGl3Menw0sskgZtSPqZjtewfFHzElGTSobuS4GQGKThCrQgmAGE6ZyUVShp VdXqHFyudFLtZhPR0KNmVZjqLdt3l7881Pz4QTR8XzYmWLjUQlHGPXCoFWd0cWzcetVM bYBmbfjZ8RxqcfBhbOYHxLCbo3mOzgQkY2l6x0FVCMkHu0M6jY+U4zlRphFnds0v6m2Q zg3mX/+pYeIRjdUYnREoCPVJF8jGSzc+NSNdmschwGA/fbkTBDFHSMd9kE5Hir8FdkMd 11i4fJFQ1V3PWzKNe/dDW+U5fBA4+KHFI3EDWnrrD5JNpXghzXwpa+rnTeYrrBZo4Kck VymQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=B22Il4U+lW9qJRmIpKE7jAR5AR4P5G5MCstdmwVkA+0=; b=PQrF5Md8I6xsBBk80XDVgNnZZj4Atmohd60UB5fw2ZK87LKnXh/9/rAjJorW9VDUmi N2q37K/UW4HrwXLjFh1JEOmO6uNkZ1yGU+PVL1ZKyRVqnQVQEY6ORW9jw8ajXfJjz1bw 8CORI9xcheiK9IxzWZBYXTVyuQSTTCSCsxYIh1PMub5WpBQTbYXuSUEvrfeRzP+s/Cmq AeXDOAwwG5983I0DC6XDi+/+0owF9UGlkilHQZqCR9Viv8OGr+aHDqXWsHL3PjJ0+HL2 DMMPcpSytqGox7i6VS21CDaG6y8LsKARKuBDcYAlv+n1INv63UvUWDmXASwZQ7I/mw2c 0Mcg== X-Gm-Message-State: AN3rC/71LtswDW+NNDBlV7gnBPYrSyFtoaltHTJjA+ByYjYrvTVI6LSz I7OD9HGojgP1GQ== X-Received: by 10.99.1.138 with SMTP id 132mr24476702pgb.236.1493594095532; Sun, 30 Apr 2017 16:14:55 -0700 (PDT) From: Stafford Horne To: peter.maydell@linaro.org Date: Mon, 1 May 2017 08:14:16 +0900 Message-Id: <356a2db3c6f84e8e79e5afa3913514184bff5f50.1493593744.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 02/11] target/openrisc: Implement EVBAR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , QEMU Development , Tim 'mithro' Ansell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Tim 'mithro' Ansell Exception Vector Base Address Register (EVBAR) - This optional register can be used to apply an offset to the exception vector addresses. The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). Its presence is indicated by the EVBARP bit in the CPU Configuration Register (CPUCFGR). Signed-off-by: Tim 'mithro' Ansell Signed-off-by: Stafford Horne --- target/openrisc/cpu.c | 2 ++ target/openrisc/cpu.h | 7 +++++++ target/openrisc/interrupt.c | 6 +++++- target/openrisc/sys_helper.c | 7 +++++++ 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 7fd2b9a..1524ed9 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -134,6 +134,7 @@ static void or1200_initfn(Object *obj) =20 set_feature(cpu, OPENRISC_FEATURE_OB32S); set_feature(cpu, OPENRISC_FEATURE_OF32S); + set_feature(cpu, OPENRISC_FEATURE_EVBAR); } =20 static void openrisc_any_initfn(Object *obj) @@ -141,6 +142,7 @@ static void openrisc_any_initfn(Object *obj) OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 set_feature(cpu, OPENRISC_FEATURE_OB32S); + set_feature(cpu, OPENRISC_FEATURE_EVBAR); } =20 typedef struct OpenRISCCPUInfo { diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 418a0e6..1958b72 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -111,6 +111,11 @@ enum { CPUCFGR_OF32S =3D (1 << 7), CPUCFGR_OF64S =3D (1 << 8), CPUCFGR_OV64S =3D (1 << 9), + /* CPUCFGR_ND =3D (1 << 10), */ + /* CPUCFGR_AVRP =3D (1 << 11), */ + CPUCFGR_EVBARP =3D (1 << 12), + /* CPUCFGR_ISRP =3D (1 << 13), */ + /* CPUCFGR_AECSRP =3D (1 << 14), */ }; =20 /* DMMU configure register */ @@ -200,6 +205,7 @@ enum { OPENRISC_FEATURE_OF32S =3D (1 << 7), OPENRISC_FEATURE_OF64S =3D (1 << 8), OPENRISC_FEATURE_OV64S =3D (1 << 9), + OPENRISC_FEATURE_EVBAR =3D (1 << 12), }; =20 /* Tick Timer Mode Register */ @@ -289,6 +295,7 @@ typedef struct CPUOpenRISCState { uint32_t dmmucfgr; /* DMMU configure register */ uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ + uint32_t evbar; /* Exception vector base address register */ uint32_t fpcsr; /* Float register */ float_status fp_status; =20 diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index a2eec6f..78f0ba9 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -65,7 +65,11 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->lock_addr =3D -1; =20 if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { - env->pc =3D (cs->exception_index << 8); + hwaddr vect_pc =3D cs->exception_index << 8; + if (env->cpucfgr & CPUCFGR_EVBARP) { + vect_pc |=3D env->evbar; + } + env->pc =3D vect_pc; } else { cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 60c3193..6ba8162 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -39,6 +39,10 @@ void HELPER(mtspr)(CPUOpenRISCState *env, env->vr =3D rb; break; =20 + case TO_SPR(0, 11): /* EVBAR */ + env->evbar =3D rb; + break; + case TO_SPR(0, 16): /* NPC */ cpu_restore_state(cs, GETPC()); /* ??? Mirror or1ksim in not trashing delayed branch state @@ -206,6 +210,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 4): /* IMMUCFGR */ return env->immucfgr; =20 + case TO_SPR(0, 11): /* EVBAR */ + return env->evbar; + case TO_SPR(0, 16): /* NPC (equals PC) */ cpu_restore_state(cs, GETPC()); return env->pc; --=20 2.9.3 From nobody Fri May 3 07:11:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493594538869842.2805028275118; Sun, 30 Apr 2017 16:22:18 -0700 (PDT) Received: from localhost ([::1]:46214 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4yAT-00079w-4a for importer@patchew.org; Sun, 30 Apr 2017 19:22:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60380) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y3S-0001uO-SX for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d4y3O-0006Uc-UN for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:02 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:33917) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d4y3O-0006UC-Oy for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:14:58 -0400 Received: by mail-pg0-x244.google.com with SMTP id t7so13879703pgt.1 for ; Sun, 30 Apr 2017 16:14:58 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id i73sm28024836pfi.131.2017.04.30.16.14.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 30 Apr 2017 16:14:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=T/5SyyeuyLbC6XdPnHSu/yu73YSFhxwg0LcKe5HXvxA=; b=DoKWzwyNJiNy1np6TlD0BvmtC8+hSt1aJ+C1LQYg1SmPLEWyXVfxYMWInZV9gOeqKA q3BK35Jongdd2gxrO6c5gfKPBFjfedSHqc+N8rGIpkIwut2oJLnF2YvZkvi1ZLqVeOvc Il28kMS2lK9E6VYDHIy+PiEdJnn62L/MCdYlHPplS1psxiTbLf3EwyRstRVS2PjTNePj bHnIimB/Lt4NulPkKXAcBDBt8ssEB8JfK953VzzjFUtpgQx3sIaqxsei7z1e/7x6un63 N4EPfFHSbjr/lQfIHAG9SRbv1fOkUs2pFVrEmIbzTyVPledwL6RJu28TreZk1wTNIm/h AwIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=T/5SyyeuyLbC6XdPnHSu/yu73YSFhxwg0LcKe5HXvxA=; b=KGccTR5Ucx83u1IU9eIN/CXL9eBCJoZ2GqMYV2u0pfv2AMpuRj0nVnP8RtjiBVIUEL 6QBotmpaTIPNs4K0k0vegNy4sORSK0vNSRzTpJ31GohU7JJZTVWDswf8PTNHsNxzSuDh og0+6Li0crk5cFnNOAIDor31iwYhTD2GEd+/C9sX9mvOd0o40ElDUbyOCu0MgEhncz23 qEI9wCWxdThR9dKEcbZHbgh8nALgetxjcLjoA9aFOb+oweIfljqPbR5USZOfIGWGHrYQ 5ElCnPcF0Xn9xAzJ7muyzWz8cuNNOSt2koOgSXbfopeBa1zo1owuY8lI76++9CHwv/cu 5k4A== X-Gm-Message-State: AN3rC/6NmTwNWhZfSyGimYLwN44o8yCvmpGtuPlzcXUzwdhcefmiB9t+ JBNFSBjVrZtadw== X-Received: by 10.99.48.71 with SMTP id w68mr23606448pgw.181.1493594097954; Sun, 30 Apr 2017 16:14:57 -0700 (PDT) From: Stafford Horne To: peter.maydell@linaro.org Date: Mon, 1 May 2017 08:14:17 +0900 Message-Id: <3fee028d1ea02cd16470dc5c65d54974ef85b673.1493593744.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PULL 03/11] target/openrisc: Implement EPH bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , QEMU Development , Tim 'mithro' Ansell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Tim 'mithro' Ansell Exception Prefix High (EPH) control bit of the Supervision Register (SR). The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). If SR[EPH] is set, the vector offset is logically ORed with the offset 0xF0000000. This means if EPH is; * 0 - Exceptions vectors start at EVBAR * 1 - Exception vectors start at EVBAR | 0xF0000000 Signed-off-by: Tim 'mithro' Ansell Signed-off-by: Stafford Horne --- target/openrisc/interrupt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 78f0ba9..2c91fab 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -69,6 +69,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs) if (env->cpucfgr & CPUCFGR_EVBARP) { vect_pc |=3D env->evbar; } + if (env->sr & SR_EPH) { + vect_pc |=3D 0xf0000000; + } env->pc =3D vect_pc; } else { cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); --=20 2.9.3 From nobody Fri May 3 07:11:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493594658720973.5625679429959; Sun, 30 Apr 2017 16:24:18 -0700 (PDT) Received: from localhost ([::1]:46224 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4yCP-0000Ke-GF for importer@patchew.org; Sun, 30 Apr 2017 19:24:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60381) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y3S-0001uP-Si for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d4y3R-0006Vp-4M for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:02 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:36471) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d4y3Q-0006VU-Uu for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:01 -0400 Received: by mail-pf0-x244.google.com with SMTP id v14so25734945pfd.3 for ; Sun, 30 Apr 2017 16:15:00 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id d1sm8472519pfa.56.2017.04.30.16.14.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 30 Apr 2017 16:14:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=yxHg3XOdD+A+57odxRvo3TC/7WsvaeDBVyL72alOQJg=; b=nPM3sU3y3EetgNZjfRscK8L98ykcBv7g44sPIxI3FUHiIyux2cFd2zpF+QIs5onFmw 5n+lYoCUNJzgMv1Q/vDAE4ZA9kkz6irCzTm2EozTP0iehmfs82R66QOpcMQWFsFlcZkk 3ugJ3GorHQnjMunxuRHCXkswNXtX8ghQL6kMn7VkDY0c3RXb29GqXPtD+efmYJ1wbwM3 qosw4OwXLAOuL4+BAB4XFP/Z+uaDN7GcJskxel67igu94dI1KD4QIqoGb2yAz3Nn5RUL 9fIbHQ4+V57URF6V6vETACP+Qz0S8v0bzkfWEXKGZADBfJ4RMc4cpLQfhzG+1PJgj/EC PZ/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=yxHg3XOdD+A+57odxRvo3TC/7WsvaeDBVyL72alOQJg=; b=SnJPBCHxN4DgpimG743GnU0NrCKx0FQ5dltAUe4bDHYBw9PQxPWeEbu36iYv8v3q/F hjs6e0qXQ9AJjKkorPgg8YsA0Ov0e6QzvsCFu5gwZCFZ/9BKLQxASyqTKkqAOJIqjzG9 guKXzCSLYFlqWljliwF1weqjwhQEdWXjN+myK+QY5DDXfs0zENtjgLp0WWMGiHXAdm8B IbgjHi2TDpCyWxu+mWqo2MMV84h+7KY9TsTR7ZnyAGVTg9XAePzQYxODWp4yR6MO3W3G 1nOBXbVGtzPTq+vrv4MZQs+6LAxPfpp+0ypa2NW5TmWbSmUD8Gu8i/LGtmH9DNiSJxkk w4hA== X-Gm-Message-State: AN3rC/6cE33it3uNCci3JL/XD8i4VJZPtBYy9uhynrUa6fXAnIUJmovL ty1AfwL9+kEbiv/t X-Received: by 10.98.153.216 with SMTP id t85mr23750830pfk.178.1493594100233; Sun, 30 Apr 2017 16:15:00 -0700 (PDT) From: Stafford Horne To: peter.maydell@linaro.org Date: Mon, 1 May 2017 08:14:18 +0900 Message-Id: X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 04/11] target/openrisc: Fixes for memory debugging X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , QEMU Development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When debugging in gdb you might want to inspect instructions in mapped pages or in exception vectors like 0x800 etc. This was previously not possible in qemu since the *get_phys_page_debug() routine only looked into the data tlb. Change to fall back to look into instruction tlb and plain physical pages. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/mmu.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 56b11d3..a6d7bcd 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -124,7 +124,7 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu, { int ret =3D TLBRET_MATCH; =20 - if (rw =3D=3D 2) { /* ITLB */ + if (rw =3D=3D MMU_INST_FETCH) { /* ITLB */ *physical =3D 0; ret =3D cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical, prot, address, r= w); @@ -221,12 +221,27 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs,= vaddr addr) OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); hwaddr phys_addr; int prot; + int miss; =20 - if (cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0)) { - return -1; + /* Check memory for any kind of address, since during debug the + gdb can ask for anything, check data tlb for address */ + miss =3D cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0); + + /* Check instruction tlb */ + if (miss) { + miss =3D cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, = MMU_INST_FETCH); + } + + /* Last, fall back to a plain address */ + if (miss) { + miss =3D cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr,= 0); } =20 - return phys_addr; + if (miss) { + return -1; + } else { + return phys_addr; + } } =20 void cpu_openrisc_mmu_init(OpenRISCCPU *cpu) --=20 2.9.3 From nobody Fri May 3 07:11:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493594227500734.0078612994275; Sun, 30 Apr 2017 16:17:07 -0700 (PDT) Received: from localhost ([::1]:46184 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y5R-00039x-O0 for importer@patchew.org; Sun, 30 Apr 2017 19:17:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60411) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y3U-0001vQ-6D for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d4y3T-0006XR-D1 for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:04 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:34172) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d4y3T-0006Wv-7E for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:03 -0400 Received: by mail-pf0-x244.google.com with SMTP id g23so25781357pfj.1 for ; Sun, 30 Apr 2017 16:15:03 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id q6sm19185777pfq.18.2017.04.30.16.15.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 30 Apr 2017 16:15:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=dkFGGmR2gcm5Xi/ekdDkUxK5HozEtZKrS7V8dnqBy5M=; b=gA75A40aoejN8RQefJsACddEJVxyXTEtvxb1HbtPf39/6iNWBBUewj9IhVLwOf1jhJ lOEImhK0t/wdgn6n6JCGjEZNiQtKUk5st3+NrylxXoZk39OF69dFMEFldQqd2rPGD1nW DHAdTpwKMObaezgQ5USPQaxy8aJ6JIvT+mlvyzbZ/Jsc78aXO8zLf5bFpuJ2PsY9fYlk VJ/qOdOcuRuG/NClJR+rshOjERVR2OvRvPHW6LFyDQdQd1OSynyadkJH6JtEylWqOHv9 faGfqUb4RIptCvmugquPxYrd2/ljHQ6+Xy6WkIDPQDcy/rtwtwPkt63x3/sjmibm0S7J 7I8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=dkFGGmR2gcm5Xi/ekdDkUxK5HozEtZKrS7V8dnqBy5M=; b=K3IGNroRA/nRltWl0J2lUqACzNPMl+HM59vg3W8xOxfG87UjeXmYMfL8JTk0Gn7xxD 97dRYo5ZlJCUryv+99vlCSeCADlFpYQgb3lA1zAxIfzcUhpFwXElhggsnCOPcz7lqNR5 boLI0OAYP3lQnNKiRLNH9zibeaOuZIw/V3U5008r9kLgFDebsT4oM4+2DgfpD3F2Nd9I rLRS64FaVdIPCXjOwKsy5ggm5dPsrVEzTkPhVzs4VfftDRLWCDOUtVe2x6kEwjALrSUC FVXj0Noy3g+sO3P349K7Qmy33ti/LTJunBSKC1c+EK/4Zx1aY39ezsaFpm1phanldNB7 BXpQ== X-Gm-Message-State: AN3rC/7bac7vfj/XLA6en8mTh2mHIxG6q2PewlPQ7VYOtcQVQLcjlWEe 8PX1TiP/Uq6KFaym X-Received: by 10.99.100.129 with SMTP id y123mr23442851pgb.217.1493594102518; Sun, 30 Apr 2017 16:15:02 -0700 (PDT) From: Stafford Horne To: peter.maydell@linaro.org Date: Mon, 1 May 2017 08:14:19 +0900 Message-Id: <4d3ebb3092f5ac66a58357cee15bd5432e77f2fe.1493593744.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 05/11] target/openrisc: add numcores and coreid support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , QEMU Development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These are used to identify the processor in SMP system. Their definition has been defined in verilog cores but it not yet part of the spec but it will be soon. The proposal for this is available: https://openrisc.io/proposals/core-identifier-and-number-of-cores Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/sys_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 6ba8162..e13666b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -233,6 +233,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 64): /* ESR */ return env->esr; =20 + case TO_SPR(0, 128): /* COREID */ + return 0; + + case TO_SPR(0, 129): /* NUMCORES */ + return 1; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); return env->tlb->dtlb[0][idx].mr; --=20 2.9.3 From nobody Fri May 3 07:11:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493594225860777.0328261951117; Sun, 30 Apr 2017 16:17:05 -0700 (PDT) Received: from localhost ([::1]:46183 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y5Q-00039O-9y for importer@patchew.org; Sun, 30 Apr 2017 19:17:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60429) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y3W-0001y9-JA for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d4y3V-0006Ys-RV for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:06 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:34908) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d4y3V-0006YT-LT for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:05 -0400 Received: by mail-pf0-x241.google.com with SMTP id o68so6703874pfj.2 for ; Sun, 30 Apr 2017 16:15:05 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id d82sm20223104pfl.124.2017.04.30.16.15.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 30 Apr 2017 16:15:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=+4Icp+M0RQj6v24329W16eXLptpcG7P4F8rWNRb6XDQ=; b=S1aVJSRVIhAVUPegKBHVV0uTxGHmfdg/e+0/i2AK1ujRq+iU2SIgoi44emhB4ETbpN FXJ5D08HJ3IB1+hY8ciaKrSBaKP1WawvQGNiOTKkYl41mDHdnFqj0Ip5Ux3u4S9zEpJF YySKoNiRHjQjyF+pg0FR7PRyrrBnXLJ+C/DyWv4i5Ns7+j75S7Osw/BqgavXXUAIGUbU slIkHSc2XeH7QJgcUkUBpsaAlCxpSpOj7bUKameCJv8C/VdyQl+BvAKaStfkrA2jcYH4 Hy6JL0gX+6hYBEjxs23lKEf1fj0mjCM8cIZY3rCtoLibl+SXGWgxCYf1JiuJupaUPhIv A8jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=+4Icp+M0RQj6v24329W16eXLptpcG7P4F8rWNRb6XDQ=; b=iaPNIOlFZsBj/UOulyfx/ahbxNnlwycAhndn6sxDR2rV29CA6YHvOz7HGnzb+A/RdX aD9LwmudB0TdaubOhgSYf6GFlldJXzAeJDUzIjOSBTl2Kf31sXs4HOqayZ9WDuvJKp89 fdIszE/+nm2hTt9Ulz3XDlUjq+234D+rRkE2SjVUvqxuS6fXtH2fbbf3kcQcq6qbFDvs CqDH8kunwY44TOU2wMdEXECJGmle5J3TXMKKaX0GCMmt7qxQKc/V48LCBSJEwXj4GTWf 64oS8GxAmB/EL+DovriA5Qk+tPFcG4fWcXfP8aA58mjPfiWKZKKkIzVeYTb2Lcw1Nprp geKw== X-Gm-Message-State: AN3rC/52w4QvYcmz5taFILtlVKlP8ShdIDXROf3vL1qYEf1ZmsmouG+7 rnjj+H8lrsPpZg== X-Received: by 10.99.150.17 with SMTP id c17mr24230783pge.160.1493594104844; Sun, 30 Apr 2017 16:15:04 -0700 (PDT) From: Stafford Horne To: peter.maydell@linaro.org Date: Mon, 1 May 2017 08:14:20 +0900 Message-Id: X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PULL 06/11] migration: Add VMSTATE_UINTTL_2DARRAY() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , QEMU Development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In openRISC we are implementing the shadow registers as a 2d array. Using this target long method rather than direct 32-bit alternatives is consistent with the rest of our vm state serialization logic. Signed-off-by: Stafford Horne --- include/migration/cpu.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/migration/cpu.h b/include/migration/cpu.h index f3d5dfc..a40bd35 100644 --- a/include/migration/cpu.h +++ b/include/migration/cpu.h @@ -18,6 +18,8 @@ VMSTATE_UINT64_EQUAL_V(_f, _s, _v) #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v) +#define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v) \ + VMSTATE_UINT64_2DARRAY_V(_f, _s, _n1, _n2, _v) #define VMSTATE_UINTTL_TEST(_f, _s, _t) \ VMSTATE_UINT64_TEST(_f, _s, _t) #define vmstate_info_uinttl vmstate_info_uint64 @@ -37,6 +39,8 @@ VMSTATE_UINT32_EQUAL_V(_f, _s, _v) #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v) +#define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v) \ + VMSTATE_UINT32_2DARRAY_V(_f, _s, _n1, _n2, _v) #define VMSTATE_UINTTL_TEST(_f, _s, _t) \ VMSTATE_UINT32_TEST(_f, _s, _t) #define vmstate_info_uinttl vmstate_info_uint32 @@ -48,5 +52,8 @@ VMSTATE_UINTTL_EQUAL_V(_f, _s, 0) #define VMSTATE_UINTTL_ARRAY(_f, _s, _n) \ VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, 0) +#define VMSTATE_UINTTL_2DARRAY(_f, _s, _n1, _n2) \ + VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, 0) + =20 #endif --=20 2.9.3 From nobody Fri May 3 07:11:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493594367998962.1366620527962; Sun, 30 Apr 2017 16:19:27 -0700 (PDT) Received: from localhost ([::1]:46196 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y7i-0004ww-8i for importer@patchew.org; Sun, 30 Apr 2017 19:19:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60466) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y3c-00025f-Fr for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d4y3Y-0006dX-Fn for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:12 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:34179) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d4y3Y-0006bn-6u for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:08 -0400 Received: by mail-pf0-x244.google.com with SMTP id g23so25781588pfj.1 for ; Sun, 30 Apr 2017 16:15:08 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id v12sm19716877pgn.5.2017.04.30.16.15.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 30 Apr 2017 16:15:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=uQCmnDtG3uspUhC/VPCTOH7VGCqVDNRqZ8bLg6VY2P8=; b=IeXxf+KFJvAOhWm+Uy7K49C/BW67L82C1IC2vuL78i0P5zP1wEtv4FhNjloFYaerjn Any7gPEIOSlIwmMgPaUEW0S9ozzwaI1nvyG2z37UAhDoLgHFitgr83VH4PLtp+CJkEKl jC93HPvdJ8f5L3wh5gWw4vI1L+3SlZGYKPWhwIX+b0f2cKzomJzo57W5hdaz8Bi6NG5Z 1dOohZs/4DsdiFi3tipTw7ZpVR1sB8pQhMI2vrxUebMW0nM+0Mu7vM0+rU2/UbhZo7V9 PLKLALCaFx3IAQ+Zi8qX5lc9JfRoWyGtMF19JudWRV4Sk8F+IJ3sPSLkqoDDNmOUXOok lTjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=uQCmnDtG3uspUhC/VPCTOH7VGCqVDNRqZ8bLg6VY2P8=; b=WuUNR1jlboB71KdsY6HTQ8SjWZ81DsoK1WwYr1V560C6QVkR/aco3dXp22TjEx0qb8 aC9R+XRcxqfCaET8vriPAMr+MkOKNsoR5P6wwnSqgs9Cw3lJhFGgeHoJrd8O34U3nMqf v5yUeKrE2IQMNq94rFA5ChcvbYA6zoI9JE0Us37csbyTTPBRAIORe/zkaLF+XN3fGP02 uAG28tOyfz22AJO2upeQldLAL4YttoEBYdhCl5nbRWCik/xIJu8m+xNsN4qUTGRWCApG Mwoq5HbjzbCrT+Y0BJ626WbeBBAMHvdpybzbjUf6Rcxi7Dw4LbpkYZ1s/jddR/8z/7nl 6XGw== X-Gm-Message-State: AN3rC/4+eVYcYWtd51Nn6+btemhbZmGHd3U19tVC4YRxMXf84iJ/ngKq XwLW/jdJLZN7uA== X-Received: by 10.98.197.194 with SMTP id j185mr23002338pfg.239.1493594107320; Sun, 30 Apr 2017 16:15:07 -0700 (PDT) From: Stafford Horne To: peter.maydell@linaro.org Date: Mon, 1 May 2017 08:14:21 +0900 Message-Id: <954c36a45feb9e2a8fac76ef2866b734d8eac91f.1493593744.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 07/11] target/openrisc: implement shadow registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , QEMU Development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Shadow registers are part of the openrisc spec along with sr[cid], as part of the fast context switching feature. When exceptions occur, instead of having to save registers to the stack if enabled the CID will increment and a new set of registers will be available. This patch only implements shadow registers which can be used as extra scratch registers via the mfspr and mtspr if required. This is implemented in a way where it would be easy to add on the fast context switching, currently cid is hardcoded to 0. This is need for openrisc linux smp kernels to boot correctly. Signed-off-by: Stafford Horne --- linux-user/elfload.c | 2 +- linux-user/main.c | 18 +++++++++--------- linux-user/openrisc/target_cpu.h | 6 +++--- linux-user/openrisc/target_signal.h | 2 +- linux-user/signal.c | 16 ++++++++-------- target/openrisc/cpu.c | 4 +++- target/openrisc/cpu.h | 15 +++++++++++++-- target/openrisc/gdbstub.c | 4 ++-- target/openrisc/machine.c | 6 +++--- target/openrisc/sys_helper.c | 9 +++++++++ target/openrisc/translate.c | 5 +++-- 11 files changed, 55 insertions(+), 32 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f520d77..ce77317 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1052,7 +1052,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *= regs, int i; =20 for (i =3D 0; i < 32; i++) { - (*regs)[i] =3D tswapreg(env->gpr[i]); + (*regs)[i] =3D tswapreg(cpu_get_gpr(env, i)); } (*regs)[32] =3D tswapreg(env->pc); (*regs)[33] =3D tswapreg(cpu_get_sr(env)); diff --git a/linux-user/main.c b/linux-user/main.c index 10a3bb3..79d621b 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2590,17 +2590,17 @@ void cpu_loop(CPUOpenRISCState *env) case EXCP_SYSCALL: env->pc +=3D 4; /* 0xc00; */ ret =3D do_syscall(env, - env->gpr[11], /* return value */ - env->gpr[3], /* r3 - r7 are params */ - env->gpr[4], - env->gpr[5], - env->gpr[6], - env->gpr[7], - env->gpr[8], 0, 0); + cpu_get_gpr(env, 11), /* return value */ + cpu_get_gpr(env, 3), /* r3 - r7 are params */ + cpu_get_gpr(env, 4), + cpu_get_gpr(env, 5), + cpu_get_gpr(env, 6), + cpu_get_gpr(env, 7), + cpu_get_gpr(env, 8), 0, 0); if (ret =3D=3D -TARGET_ERESTARTSYS) { env->pc -=3D 4; } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - env->gpr[11] =3D ret; + cpu_set_gpr(env, 11, ret); } break; case EXCP_DPF: @@ -4765,7 +4765,7 @@ int main(int argc, char **argv, char **envp) int i; =20 for (i =3D 0; i < 32; i++) { - env->gpr[i] =3D regs->gpr[i]; + cpu_set_gpr(env, i, regs->gpr[i]); } env->pc =3D regs->pc; cpu_set_sr(env, regs->sr); diff --git a/linux-user/openrisc/target_cpu.h b/linux-user/openrisc/target_= cpu.h index f283d96..606ad6f 100644 --- a/linux-user/openrisc/target_cpu.h +++ b/linux-user/openrisc/target_cpu.h @@ -23,14 +23,14 @@ static inline void cpu_clone_regs(CPUOpenRISCState *env, target_ulong news= p) { if (newsp) { - env->gpr[1] =3D newsp; + cpu_set_gpr(env, 1, newsp); } - env->gpr[11] =3D 0; + cpu_set_gpr(env, 11, 0); } =20 static inline void cpu_set_tls(CPUOpenRISCState *env, target_ulong newtls) { - env->gpr[10] =3D newtls; + cpu_set_gpr(env, 10, newtls); } =20 #endif diff --git a/linux-user/openrisc/target_signal.h b/linux-user/openrisc/targ= et_signal.h index 9f2c493..95a733e 100644 --- a/linux-user/openrisc/target_signal.h +++ b/linux-user/openrisc/target_signal.h @@ -20,7 +20,7 @@ typedef struct target_sigaltstack { =20 static inline abi_ulong get_sp_from_cpustate(CPUOpenRISCState *state) { - return state->gpr[1]; + return cpu_get_gpr(state, 1); } =20 =20 diff --git a/linux-user/signal.c b/linux-user/signal.c index a67db04..eb6cb9f 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -4411,7 +4411,7 @@ static void setup_sigcontext(struct target_sigcontext= *sc, CPUOpenRISCState *regs, unsigned long mask) { - unsigned long usp =3D regs->gpr[1]; + unsigned long usp =3D cpu_get_gpr(regs, 1); =20 /* copy the regs. they are first in sc so we can use sc directly */ =20 @@ -4436,7 +4436,7 @@ static inline abi_ulong get_sigframe(struct target_si= gaction *ka, CPUOpenRISCState *regs, size_t frame_size) { - unsigned long sp =3D regs->gpr[1]; + unsigned long sp =3D cpu_get_gpr(regs, 1); int onsigstack =3D on_sig_stack(sp); =20 /* redzone */ @@ -4489,7 +4489,7 @@ static void setup_rt_frame(int sig, struct target_sig= action *ka, __put_user(0, &frame->uc.tuc_link); __put_user(target_sigaltstack_used.ss_sp, &frame->uc.tuc_stack.ss_sp); - __put_user(sas_ss_flags(env->gpr[1]), &frame->uc.tuc_stack.ss_flags); + __put_user(sas_ss_flags(cpu_get_gpr(env, 1)), &frame->uc.tuc_stack.ss_= flags); __put_user(target_sigaltstack_used.ss_size, &frame->uc.tuc_stack.ss_size); setup_sigcontext(&frame->sc, env, set->sig[0]); @@ -4512,13 +4512,13 @@ static void setup_rt_frame(int sig, struct target_s= igaction *ka, =20 /* Set up registers for signal handler */ env->pc =3D (unsigned long)ka->_sa_handler; /* what we enter NOW */ - env->gpr[9] =3D (unsigned long)return_ip; /* what we enter LATER */ - env->gpr[3] =3D (unsigned long)sig; /* arg 1: signo */ - env->gpr[4] =3D (unsigned long)&frame->info; /* arg 2: (siginfo_t*) */ - env->gpr[5] =3D (unsigned long)&frame->uc; /* arg 3: ucontext */ + cpu_set_gpr(env, 9, (unsigned long)return_ip); /* what we enter LA= TER */ + cpu_set_gpr(env, 3, (unsigned long)sig); /* arg 1: signo */ + cpu_set_gpr(env, 4, (unsigned long)&frame->info); /* arg 2: (siginfo_= t*) */ + cpu_set_gpr(env, 5, (unsigned long)&frame->uc); /* arg 3: ucontext = */ =20 /* actually move the usp to reflect the stacked frame */ - env->gpr[1] =3D (unsigned long)frame; + cpu_set_gpr(env, 1, (unsigned long)frame); =20 return; =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 1524ed9..6c1ed07 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -52,7 +52,7 @@ static void openrisc_cpu_reset(CPUState *s) s->exception_index =3D -1; =20 cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; - cpu->env.cpucfgr =3D CPUCFGR_OB32S | CPUCFGR_OF32S; + cpu->env.cpucfgr =3D CPUCFGR_OB32S | CPUCFGR_OF32S | CPUCFGR_NSGF; cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 <= < 2)); cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 <= < 2)); =20 @@ -132,6 +132,7 @@ static void or1200_initfn(Object *obj) { OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 + set_feature(cpu, OPENRISC_FEATURE_NSGF); set_feature(cpu, OPENRISC_FEATURE_OB32S); set_feature(cpu, OPENRISC_FEATURE_OF32S); set_feature(cpu, OPENRISC_FEATURE_EVBAR); @@ -141,6 +142,7 @@ static void openrisc_any_initfn(Object *obj) { OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 + set_feature(cpu, OPENRISC_FEATURE_NSGF); set_feature(cpu, OPENRISC_FEATURE_OB32S); set_feature(cpu, OPENRISC_FEATURE_EVBAR); } diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 1958b72..e159b22 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -275,7 +275,8 @@ typedef struct CPUOpenRISCTLBContext { #endif =20 typedef struct CPUOpenRISCState { - target_ulong gpr[32]; /* General registers */ + target_ulong shadow_gpr[16][32]; /* Shadow registers */ + target_ulong pc; /* Program counter */ target_ulong ppc; /* Prev PC */ target_ulong jmp_pc; /* Jump PC */ @@ -399,6 +400,16 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, #define TB_FLAGS_R0_0 2 #define TB_FLAGS_OVE SR_OVE =20 +static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i) +{ + return env->shadow_gpr[0][i]; +} + +static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val) +{ + env->shadow_gpr[0][i] =3D val; +} + static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *f= lags) @@ -406,7 +417,7 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCStat= e *env, *pc =3D env->pc; *cs_base =3D 0; *flags =3D (env->dflag - | (env->gpr[0] =3D=3D 0 ? TB_FLAGS_R0_0 : 0) + | (cpu_get_gpr(env, 0) =3D=3D 0 ? TB_FLAGS_R0_0 : 0) | (env->sr & SR_OVE)); } =20 diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index b18c7e9..f9af650 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -28,7 +28,7 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t = *mem_buf, int n) CPUOpenRISCState *env =3D &cpu->env; =20 if (n < 32) { - return gdb_get_reg32(mem_buf, env->gpr[n]); + return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n)); } else { switch (n) { case 32: /* PPC */ @@ -61,7 +61,7 @@ int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t= *mem_buf, int n) tmp =3D ldl_p(mem_buf); =20 if (n < 32) { - env->gpr[n] =3D tmp; + cpu_set_gpr(env, n, tmp); } else { switch (n) { case 32: /* PPC */ diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 686eaa3..2bf71c3 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -47,10 +47,10 @@ static const VMStateInfo vmstate_sr =3D { =20 static const VMStateDescription vmstate_env =3D { .name =3D "env", - .version_id =3D 4, - .minimum_version_id =3D 4, + .version_id =3D 5, + .minimum_version_id =3D 5, .fields =3D (VMStateField[]) { - VMSTATE_UINTTL_ARRAY(gpr, CPUOpenRISCState, 32), + VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), VMSTATE_UINTTL(pc, CPUOpenRISCState), VMSTATE_UINTTL(ppc, CPUOpenRISCState), VMSTATE_UINTTL(jmp_pc, CPUOpenRISCState), diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index e13666b..fa3d6a4 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -92,6 +92,11 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(0, 64): /* ESR */ env->esr =3D rb; break; + + case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ + idx =3D (spr - 1024); + env->shadow_gpr[idx / 32][idx % 32] =3D rb; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); if (!(rb & 1)) { @@ -239,6 +244,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 129): /* NUMCORES */ return 1; =20 + case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ + idx =3D (spr - 1024); + return env->shadow_gpr[idx / 32][idx % 32]; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); return env->tlb->dtlb[0][idx].mr; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7c4cbf2..e49518e 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -107,7 +107,8 @@ void openrisc_translate_init(void) "mac"); for (i =3D 0; i < 32; i++) { cpu_R[i] =3D tcg_global_mem_new(cpu_env, - offsetof(CPUOpenRISCState, gpr[i]), + offsetof(CPUOpenRISCState, + shadow_gpr[0][i]), regnames[i]); } cpu_R0 =3D cpu_R[0]; @@ -1662,7 +1663,7 @@ void openrisc_cpu_dump_state(CPUState *cs, FILE *f, =20 cpu_fprintf(f, "PC=3D%08x\n", env->pc); for (i =3D 0; i < 32; ++i) { - cpu_fprintf(f, "R%02d=3D%08x%c", i, env->gpr[i], + cpu_fprintf(f, "R%02d=3D%08x%c", i, cpu_get_gpr(env, i), (i % 4) =3D=3D 3 ? '\n' : ' '); } } --=20 2.9.3 From nobody Fri May 3 07:11:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493594381729922.672665834244; Sun, 30 Apr 2017 16:19:41 -0700 (PDT) Received: from localhost ([::1]:46197 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y7u-00058B-7B for importer@patchew.org; Sun, 30 Apr 2017 19:19:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60465) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y3c-00025d-Fk for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d4y3b-0006g4-4p for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:12 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:34181) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d4y3a-0006fT-Vw for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:11 -0400 Received: by mail-pf0-x244.google.com with SMTP id g23so25781712pfj.1 for ; Sun, 30 Apr 2017 16:15:10 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id m4sm26341523pgm.25.2017.04.30.16.15.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 30 Apr 2017 16:15:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=1ULqFvCAucxpqTx+6eOt1U2rQEOVWS/jn5Ic4C9K95s=; b=ico4M/UqcNgvX0DRtcdMF0rTsSRDXyL4nY72zeR6LF3RT1Hjs68vEocDkI+FmtfQUY oiyKMxCRZooBgDOvbPFaKdExeADqTcVzYbzLZUAbZrujgP2RKZmR9bP97KXSGymWxFiF XRy1nG5gUQt7Cpq7LlDt5+qe0cNE1FSUyUfc1+EIhpp4EpcXasKIEtBvA0Cw+L0GFEwe qkS8LXMlIcdmPPLlYOgG8dU7kpQmRQYHnM5mXYtEcjEEe0r4wyGawrVo33CpXXZkyH/x PyF8VNOMKpQq9ByRrCbMjEOdyRz5Qd6BLfqQFwsw+cswDK87eIRDyr9l5A0ebVJ4xyRT mynw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=1ULqFvCAucxpqTx+6eOt1U2rQEOVWS/jn5Ic4C9K95s=; b=l8m67KDl+YeZK0NzD4xGh5mNUUf+3FKak/otjv3Q2lQBLr6LJQJ3ZOwESOyx9lwzCU rs0ebTHJ4cofzvzKliz6LpOS87n1i0F5m+TqH8z1NiRtsf+u7e3hTh0jUb+TZ2t6yDTt Zuck0pi/0gVABi69XwoMGt2QW55WlUMwgGLC7OsMAAnF4nqTO7UfnXP1lrDM74seAJea MxpKemxFg3mRkf0hrdEGoCD1XPwrOi2rXE+1pUrv42Dn6aWgAi6saaTrZk7qZGlHEz1M TjVhWoBrVTbrO+0TqfgaUtGsfZE6hJkKsBYSNenuOEI3qnM/DCMnYQu2Z+Znm6baXYGC 5xHw== X-Gm-Message-State: AN3rC/6COFdXlNnG2M6z1tmjW9EGSmXa7IyqDDyLRPO0kD8JAyDaJbuR 2IkpcqrpUuXXaLU3 X-Received: by 10.98.110.195 with SMTP id j186mr23907411pfc.25.1493594110240; Sun, 30 Apr 2017 16:15:10 -0700 (PDT) From: Stafford Horne To: peter.maydell@linaro.org Date: Mon, 1 May 2017 08:14:22 +0900 Message-Id: <565b9678ec7335762a290afce68f7062bdaf0ce9.1493593744.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 08/11] migration: Add VMSTATE_STRUCT_2DARRAY() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , QEMU Development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For openrisc we implement tlb state as a 2d array of tlb entry structs. This is added to allow easy storing of state of 2d arrays. Signed-off-by: Stafford Horne --- include/migration/vmstate.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index f2dbf84..9b7dcdc 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -499,6 +499,17 @@ extern const VMStateInfo vmstate_info_qtailq; .offset =3D vmstate_offset_array(_state, _field, _type, _num),\ } =20 +#define VMSTATE_STRUCT_2DARRAY_TEST(_field, _state, _n1, _n2, _test, _vers= ion, _vmsd, _type) { \ + .name =3D (stringify(_field)), = \ + .num =3D (_n1) * (_n2), = \ + .field_exists =3D (_test), = \ + .version_id =3D (_version), = \ + .vmsd =3D &(_vmsd), = \ + .size =3D sizeof(_type), = \ + .flags =3D VMS_STRUCT|VMS_ARRAY, = \ + .offset =3D vmstate_offset_2darray(_state, _field, _type, _n1, _= n2),\ +} + #define VMSTATE_STRUCT_VARRAY_UINT8(_field, _state, _field_num, _version, = _vmsd, _type) { \ .name =3D (stringify(_field)), \ .num_offset =3D vmstate_offset_value(_state, _field_num, uint8_t), \ @@ -746,6 +757,10 @@ extern const VMStateInfo vmstate_info_qtailq; VMSTATE_STRUCT_ARRAY_TEST(_field, _state, _num, NULL, _version, \ _vmsd, _type) =20 +#define VMSTATE_STRUCT_2DARRAY(_field, _state, _n1, _n2, _version, _vmsd, = _type) \ + VMSTATE_STRUCT_2DARRAY_TEST(_field, _state, _n1, _n2, NULL, _version, = \ + _vmsd, _type) + #define VMSTATE_BUFFER_UNSAFE_INFO(_field, _state, _version, _info, _size)= \ VMSTATE_BUFFER_UNSAFE_INFO_TEST(_field, _state, NULL, _version, _info,= \ _size) --=20 2.9.3 From nobody Fri May 3 07:11:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493594495214774.9864694312979; Sun, 30 Apr 2017 16:21:35 -0700 (PDT) Received: from localhost ([::1]:46212 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y9l-0006cw-Uk for importer@patchew.org; Sun, 30 Apr 2017 19:21:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60492) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y3e-00028v-H1 for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d4y3d-0006hY-FP for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:14 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:33578) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d4y3d-0006hC-9V for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:13 -0400 Received: by mail-pf0-x241.google.com with SMTP id b23so9853348pfc.0 for ; Sun, 30 Apr 2017 16:15:13 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id n7sm22031030pfn.0.2017.04.30.16.15.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 30 Apr 2017 16:15:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=aLPISuS5eSd812PwiN7tjAxR9Wk2P1U1KxqUk+A/dp4=; b=ubSfrKMNAJcb5FA6BrxmYXlfPQCIBFgC5shiKzPHnpmSVGZyR/Wd+BymDrpCsX40ci zQZt+2qaqHkbLKshzoB5u4T4G5cuJbjpZ+t/W3xbzuXo/MUaspzHg1o1XkohZN/4JeDK D3PJKhrmhUCm/cnPNHUGNHidpRiZrudNCQSaW4qF17Gs3QHZn3bKcE+1khEYgE64RDQl niwbNn2YSg6NPvewKzK1wOILCu4dEI8pr5F6pU1jMsQ9nO6DemFP0F874wGBoggPUy87 PO10+T4EHr6SjG4d6xZMUbjsAlqkuUgYcxnZntegC+IKiklhB9p1ka1QCLUdBuumLY8e mDsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=aLPISuS5eSd812PwiN7tjAxR9Wk2P1U1KxqUk+A/dp4=; b=Df3K9hgRDhVGvxtqQFYMvhjT6XfVmoMrH41gBgx8isp+Ugd8YVtXHZZEV9S9MS8PhE eSxx5DtS8hPkqB0J5XaIayU5UXxcXg6dfz/nJOAzjg/yA4VH89KobDR5nR/D67BtSQWu AZeSzQP5LWBaktwN/24FwNSNfoNQ6ODESf00iNdR+N9TYId8evNtmiQUVP9KyCzxbsUe D4wKfw6fG8OMp6ywYea7oXPVSL9eiIbBOR/Ppw36Vh2AW2IFoJNN+NtpDx2WRgPYU98e VfZaUew40fVJQGTvFd0GRZZatzTsiceMq4fFf2uKYUv1XUyQkW05LYnIVrNlaGGrLfAf ECeg== X-Gm-Message-State: AN3rC/4RWb/UypLQU3knewu5MF3AAtYfEe+f10leVqWRzb5sv+uwX42V A8JUCSFY4+pi+w== X-Received: by 10.84.254.67 with SMTP id a3mr30333639pln.185.1493594112570; Sun, 30 Apr 2017 16:15:12 -0700 (PDT) From: Stafford Horne To: peter.maydell@linaro.org Date: Mon, 1 May 2017 08:14:23 +0900 Message-Id: <76adf807304af127f81f0c11f29b610b059f3497.1493593744.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PULL 09/11] target/openrisc: Implement full vmstate serialization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , QEMU Development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Previously serialization did not persist the tlb, timer, pic and other key state items. This meant snapshotting and restoring a running os would crash. After adding these I am able to take snapshots of a running linux os and restore at a later time. I am currently not trying to maintain capatibility with older versions as I do not believe this really worked before or anyone used it. Signed-off-by: Stafford Horne --- target/openrisc/machine.c | 73 +++++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 71 insertions(+), 2 deletions(-) diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 2bf71c3..a82be62 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -24,6 +24,63 @@ #include "hw/boards.h" #include "migration/cpu.h" =20 +static int env_post_load(void *opaque, int version_id) +{ + CPUOpenRISCState *env =3D opaque; + + /* Restore MMU handlers */ + if (env->sr & SR_DME) { + env->tlb->cpu_openrisc_map_address_data =3D + &cpu_openrisc_get_phys_data; + } else { + env->tlb->cpu_openrisc_map_address_data =3D + &cpu_openrisc_get_phys_nommu; + } + + if (env->sr & SR_IME) { + env->tlb->cpu_openrisc_map_address_code =3D + &cpu_openrisc_get_phys_code; + } else { + env->tlb->cpu_openrisc_map_address_code =3D + &cpu_openrisc_get_phys_nommu; + } + + + return 0; +} + +static const VMStateDescription vmstate_tlb_entry =3D { + .name =3D "tlb_entry", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(mr, OpenRISCTLBEntry), + VMSTATE_UINTTL(tr, OpenRISCTLBEntry), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_cpu_tlb =3D { + .name =3D "cpu_tlb", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT_2DARRAY(itlb, CPUOpenRISCTLBContext, + ITLB_WAYS, ITLB_SIZE, 0, + vmstate_tlb_entry, OpenRISCTLBEntry), + VMSTATE_STRUCT_2DARRAY(dtlb, CPUOpenRISCTLBContext, + DTLB_WAYS, DTLB_SIZE, 0, + vmstate_tlb_entry, OpenRISCTLBEntry), + VMSTATE_END_OF_LIST() + } +}; + +#define VMSTATE_CPU_TLB(_f, _s) \ + VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_tlb, CPUOpenRISCTLBContext) + + static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField *fi= eld) { CPUOpenRISCState *env =3D opaque; @@ -47,8 +104,9 @@ static const VMStateInfo vmstate_sr =3D { =20 static const VMStateDescription vmstate_env =3D { .name =3D "env", - .version_id =3D 5, - .minimum_version_id =3D 5, + .version_id =3D 6, + .minimum_version_id =3D 6, + .post_load =3D env_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), VMSTATE_UINTTL(pc, CPUOpenRISCState), @@ -79,9 +137,20 @@ static const VMStateDescription vmstate_env =3D { VMSTATE_UINT32(cpucfgr, CPUOpenRISCState), VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState), VMSTATE_UINT32(immucfgr, CPUOpenRISCState), + VMSTATE_UINT32(evbar, CPUOpenRISCState), VMSTATE_UINT32(esr, CPUOpenRISCState), VMSTATE_UINT32(fpcsr, CPUOpenRISCState), VMSTATE_UINT64(mac, CPUOpenRISCState), + + VMSTATE_CPU_TLB(tlb, CPUOpenRISCState), + + VMSTATE_TIMER_PTR(timer, CPUOpenRISCState), + VMSTATE_UINT32(ttmr, CPUOpenRISCState), + VMSTATE_UINT32(ttcr, CPUOpenRISCState), + + VMSTATE_UINT32(picmr, CPUOpenRISCState), + VMSTATE_UINT32(picsr, CPUOpenRISCState), + VMSTATE_END_OF_LIST() } }; --=20 2.9.3 From nobody Fri May 3 07:11:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493594619015172.63351274553474; Sun, 30 Apr 2017 16:23:39 -0700 (PDT) Received: from localhost ([::1]:46222 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4yBl-0008Es-Hk for importer@patchew.org; Sun, 30 Apr 2017 19:23:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60507) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y3g-0002BO-Vv for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d4y3f-0006k3-Ra for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:17 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:34917) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d4y3f-0006ig-LE for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:15 -0400 Received: by mail-pf0-x241.google.com with SMTP id o68so6704297pfj.2 for ; Sun, 30 Apr 2017 16:15:15 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id x185sm20859981pfx.102.2017.04.30.16.15.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 30 Apr 2017 16:15:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=ZSRaRZ7Gpo/Gz2A0pzY4GEBaKCItT05/PrKrzTgD0LE=; b=Nnh+g6sGi7fakVSL1smS20YAoHrLOMDaLSMYuKbQkor/7Fc8t5OMY9Nr6Clh91l7Bb jZ56IViPDmDk8dRfeSfsAYko1VgEKyou+8cRIYYvvQD+a7JowgBau1SNY/y3lmzhGZio UAXj2FOUImK2CWpOxZEkm38jmHfkK0reXH615TGiJNlatIVYF1rYkOoXDVsNBNHZee/B k4yUWAMn7gRNOMJplN4Z7xF6Z/URMj4xYbehRLQ1mj9xpNIEtSVP8UIwbfSdhkrglBal JpLCLt00Z3w8/J+PTL/RSHVzrgMw+P0/dVQ3jowQA4acQx/2LhIsKrzkTnyrTWtOMaJM dttw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=ZSRaRZ7Gpo/Gz2A0pzY4GEBaKCItT05/PrKrzTgD0LE=; b=kIxmhWMzFX1j7clyePPXFUuieA6jrmD+NDGNP0acX5iZLHJyY651boweO3BVrN/r4t 2dHSAGWbxIOqVgUlfOzmnjMkXqnnLH+Cl94pDJ0Rj88AKYZQ0j6uKshl/JQZl3Uf6MF7 frN6LshHHDFh352knV5Cu0S9rKaiBH61otxpe9LCw49hM1EPWmlgxvBAWClYrPMy3Ayg 0fdCCuVGJhQ73MVTkD4PVyx7odiDl/mT5aiGfvNvOilZBVncm7HPAesrsdmk6QUXqbE1 vwlapwX7XeBkMmZHR1VW01mZ9qFYkxwlLfnCUfOvsVGSItHIrtm8pZno5+LOCxU9mMUd 0LaQ== X-Gm-Message-State: AN3rC/6tO12DoSVdhGFAvcyns+YtIlNf+VRzPPdcOEX9gXe2ORHOB5oq u/5q6TIECF/d1g== X-Received: by 10.84.224.206 with SMTP id k14mr1034302pln.162.1493594114917; Sun, 30 Apr 2017 16:15:14 -0700 (PDT) From: Stafford Horne To: peter.maydell@linaro.org Date: Mon, 1 May 2017 08:14:24 +0900 Message-Id: <5466599bfa21f03ae01741580c7e3fa0fdc6800d.1493593744.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PULL 10/11] target/openrisc: Remove duplicate features property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , QEMU Development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The features property has stored the exact same thing as the cpucfgr spr. Remove the feature enum and property as it is not needed. In order to preserve the behavior or keeping features accross reset this patch moves cpucfgr into the non reset region of the state struct. Since the cpucfgr is read only this means we only need to sset cpucfgr once during class init. Signed-off-by: Stafford Horne --- target/openrisc/cpu.c | 17 +++-------------- target/openrisc/cpu.h | 16 ++-------------- 2 files changed, 5 insertions(+), 28 deletions(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 6c1ed07..c9b3f22 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -52,7 +52,6 @@ static void openrisc_cpu_reset(CPUState *s) s->exception_index =3D -1; =20 cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; - cpu->env.cpucfgr =3D CPUCFGR_OB32S | CPUCFGR_OF32S | CPUCFGR_NSGF; cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 <= < 2)); cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 <= < 2)); =20 @@ -65,12 +64,6 @@ static void openrisc_cpu_reset(CPUState *s) #endif } =20 -static inline void set_feature(OpenRISCCPU *cpu, int feature) -{ - cpu->feature |=3D feature; - cpu->env.cpucfgr =3D cpu->feature; -} - static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -132,19 +125,15 @@ static void or1200_initfn(Object *obj) { OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 - set_feature(cpu, OPENRISC_FEATURE_NSGF); - set_feature(cpu, OPENRISC_FEATURE_OB32S); - set_feature(cpu, OPENRISC_FEATURE_OF32S); - set_feature(cpu, OPENRISC_FEATURE_EVBAR); + cpu->env.cpucfgr =3D CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | + CPUCFGR_EVBARP; } =20 static void openrisc_any_initfn(Object *obj) { OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 - set_feature(cpu, OPENRISC_FEATURE_NSGF); - set_feature(cpu, OPENRISC_FEATURE_OB32S); - set_feature(cpu, OPENRISC_FEATURE_EVBAR); + cpu->env.cpucfgr =3D CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP; } =20 typedef struct OpenRISCCPUInfo { diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index e159b22..938ccc3 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -196,18 +196,6 @@ enum { SR_SCE =3D (1 << 17), }; =20 -/* OpenRISC Hardware Capabilities */ -enum { - OPENRISC_FEATURE_NSGF =3D (15 << 0), - OPENRISC_FEATURE_CGF =3D (1 << 4), - OPENRISC_FEATURE_OB32S =3D (1 << 5), - OPENRISC_FEATURE_OB64S =3D (1 << 6), - OPENRISC_FEATURE_OF32S =3D (1 << 7), - OPENRISC_FEATURE_OF64S =3D (1 << 8), - OPENRISC_FEATURE_OV64S =3D (1 << 9), - OPENRISC_FEATURE_EVBAR =3D (1 << 12), -}; - /* Tick Timer Mode Register */ enum { TTMR_TP =3D (0xfffffff), @@ -292,7 +280,6 @@ typedef struct CPUOpenRISCState { uint32_t sr; /* Supervisor register, without SR_{F,CY,OV}= */ uint32_t vr; /* Version register */ uint32_t upr; /* Unit presence register */ - uint32_t cpucfgr; /* CPU configure register */ uint32_t dmmucfgr; /* DMMU configure register */ uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ @@ -311,6 +298,8 @@ typedef struct CPUOpenRISCState { CPU_COMMON =20 /* Fields from here on are preserved across CPU reset. */ + uint32_t cpucfgr; /* CPU configure register */ + #ifndef CONFIG_USER_ONLY CPUOpenRISCTLBContext * tlb; =20 @@ -337,7 +326,6 @@ typedef struct OpenRISCCPU { =20 CPUOpenRISCState env; =20 - uint32_t feature; /* CPU Capabilities */ } OpenRISCCPU; =20 static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env) --=20 2.9.3 From nobody Fri May 3 07:11:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493594504129250.36557713368563; Sun, 30 Apr 2017 16:21:44 -0700 (PDT) Received: from localhost ([::1]:46213 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y9u-0006kj-PQ for importer@patchew.org; Sun, 30 Apr 2017 19:21:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60561) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d4y3m-0002E7-9r for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d4y3i-0006km-Ah for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:22 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:33583) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d4y3i-0006kZ-2p for qemu-devel@nongnu.org; Sun, 30 Apr 2017 19:15:18 -0400 Received: by mail-pf0-x243.google.com with SMTP id b23so9853547pfc.0 for ; Sun, 30 Apr 2017 16:15:18 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id n85sm27215627pfi.101.2017.04.30.16.15.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 30 Apr 2017 16:15:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=9ZK/1O75svRsvUs5m9/Z7c3iaU+T/Tu7NOxwmmb8O5Y=; b=j1PqVoLA8v6TyeuJsUV20miEJOu28D+ya0qWtuGBIMWNIIkyLqjwCKlxNjmSU13wfj cpcxKMUxgNUTmN42uQb43ZUL+N81Ga24rFDuOMfHb5mThyfXUDjg8iS5hrnPG/qp5Usy DvMiiGgsD4X7V65LWBMkNAd2MgCCgYZi2wmwBppeIwelQAAEC4Vkb8VbdEQUSJX9C0rl RKp6q3WaYZSr9aiqkQmnvybMJ1kYK8Ys+duhCwJ6sf6zKTtQFUEBYvhL4yFUyLhAp+Yj aGxa1XJ5qIyvkLyaoRx0YE2XKo8Tit/iDmkQNMcgSiuC9VGaxLeFZgaeRQzEa59GAvoa +GoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=9ZK/1O75svRsvUs5m9/Z7c3iaU+T/Tu7NOxwmmb8O5Y=; b=JPo1RWxbduS+LrAZkIwEpUBHf3VsfHAcJ9blyqZ2bW1ONZ/0y2J35cILEB5ZrUCSoO iVyWx4jvwlb03g3xni0K6yAPmtDthER9vMWs1DW1pW6sO8w5/EX9i1eZn58KaYkX0yHX 41yt9wCMDDTcjzcDtuoljEbKAWhPnUzTaEEXZaUbCTfrk3Wg2wuo8J8BC3Ns3eyaNVpO 2hBPK6o/IPjhPcDNfbrHCjH0jk4mRg7h10TVl5BTLPvcdxW5rMeGlv4Mw/5hNjGbcPT3 cgZOlGBvVPzDvWhA5OzCd0p70MH2C7mOaJT314pwETkOytjf7XKm8Ej2ELmTEHQG1Tp0 CdxQ== X-Gm-Message-State: AN3rC/50KdhZQrgNO1t4P4xQQREaphU+NXrBfocwvgK8Ryw7UOw3Qy11 3j56WGA06FYYug== X-Received: by 10.84.192.37 with SMTP id b34mr30457815pld.174.1493594117353; Sun, 30 Apr 2017 16:15:17 -0700 (PDT) From: Stafford Horne To: peter.maydell@linaro.org Date: Mon, 1 May 2017 08:14:25 +0900 Message-Id: <700a330fbf023429a82222449a3f9bf0a884c767.1493593744.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PULL 11/11] target/openrisc: Support non-busy idle state using PMR SPR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , QEMU Development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The OpenRISC architecture has the Power Management Register (PMR) special purpose register to manage cpu power states. The interesting modes are: * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt * Sleep Mode (SME) - Stop cpu and all units - wake on interrupt * Suspend Model (SUME) - Stop cpu and all units - wake on reset The linux kernel will set DME when idle. This patch implements the PMR SPR and halts the qemu cpu when there is a change to DME or SME. This means that openrisc qemu in no longer peggs a host cpu at 100%. In order for this to work we need to kick the CPU when timers are expired. Update the cpu timer to kick the cpu upon each timer event. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- hw/openrisc/cputimer.c | 1 + target/openrisc/cpu.c | 3 ++- target/openrisc/cpu.h | 10 ++++++++++ target/openrisc/interrupt.c | 2 ++ target/openrisc/machine.c | 1 + target/openrisc/sys_helper.c | 13 +++++++++++++ 6 files changed, 29 insertions(+), 1 deletion(-) diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c index a98c799..febc469 100644 --- a/hw/openrisc/cputimer.c +++ b/hw/openrisc/cputimer.c @@ -61,6 +61,7 @@ void cpu_openrisc_timer_update(OpenRISCCPU *cpu) } next =3D now + (uint64_t)wait * TIMER_PERIOD; timer_mod(cpu->env.timer, next); + qemu_cpu_kick(CPU(cpu)); } =20 void cpu_openrisc_count_start(OpenRISCCPU *cpu) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index c9b3f22..1d6330c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -51,7 +51,8 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.lock_addr =3D -1; s->exception_index =3D -1; =20 - cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; + cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | + UPR_PMP; cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 <= < 2)); cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 <= < 2)); =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 938ccc3..2721432 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -140,6 +140,15 @@ enum { IMMUCFGR_HTR =3D (1 << 11), }; =20 +/* Power management register */ +enum { + PMR_SDF =3D (15 << 0), + PMR_DME =3D (1 << 4), + PMR_SME =3D (1 << 5), + PMR_DCGE =3D (1 << 6), + PMR_SUME =3D (1 << 7), +}; + /* Float point control status register */ enum { FPCSR_FPEE =3D 1, @@ -284,6 +293,7 @@ typedef struct CPUOpenRISCState { uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ uint32_t evbar; /* Exception vector base address register */ + uint32_t pmr; /* Power Management Register */ uint32_t fpcsr; /* Float register */ float_status fp_status; =20 diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 2c91fab..3959671 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -60,6 +60,8 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr |=3D SR_SM; env->sr &=3D ~SR_IEE; env->sr &=3D ~SR_TEE; + env->pmr &=3D ~PMR_DME; + env->pmr &=3D ~PMR_SME; env->tlb->cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_nom= mu; env->tlb->cpu_openrisc_map_address_code =3D &cpu_openrisc_get_phys_nom= mu; env->lock_addr =3D -1; diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index a82be62..a20cce7 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -138,6 +138,7 @@ static const VMStateDescription vmstate_env =3D { VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState), VMSTATE_UINT32(immucfgr, CPUOpenRISCState), VMSTATE_UINT32(evbar, CPUOpenRISCState), + VMSTATE_UINT32(pmr, CPUOpenRISCState), VMSTATE_UINT32(esr, CPUOpenRISCState), VMSTATE_UINT32(fpcsr, CPUOpenRISCState), VMSTATE_UINT64(mac, CPUOpenRISCState), diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index fa3d6a4..abdef5d 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "exception.h" =20 #define TO_SPR(group, number) (((group) << 11) + (number)) =20 @@ -141,6 +142,15 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(5, 2): /* MACHI */ env->mac =3D deposit64(env->mac, 32, 32, rb); break; + case TO_SPR(8, 0): /* PMR */ + env->pmr =3D rb; + if (env->pmr & PMR_DME || env->pmr & PMR_SME) { + cpu_restore_state(cs, GETPC()); + env->pc +=3D 4; + cs->halted =3D 1; + raise_exception(cpu, EXCP_HALTED); + } + break; case TO_SPR(9, 0): /* PICMR */ env->picmr |=3D rb; break; @@ -287,6 +297,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, return env->mac >> 32; break; =20 + case TO_SPR(8, 0): /* PMR */ + return env->pmr; + case TO_SPR(9, 0): /* PICMR */ return env->picmr; =20 --=20 2.9.3