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[124.44.184.64]) by smtp.gmail.com with ESMTPSA id a77sm26938403pfe.33.2017.04.23.15.41.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 23 Apr 2017 15:41:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=B22Il4U+lW9qJRmIpKE7jAR5AR4P5G5MCstdmwVkA+0=; b=nZkeRedOqBvyJwfWh0dOUxgJNykPohKYmpp9bgHC+5Nogzct+/AWzpaseEailrAvTU uy0h3iqg8jzpEHHukoftpAlB+tcQgge5aUwJwnOB34cRrExOIPypvw0tvNb7HXsTQXgA D2FZT3hF5P1qspvvpPz/ee5ShIH0uiHv+7LFlqAqYAgs0ZcyW1AosY7EAUgPvb41uPeH K8VOrafxjuW/uP2lBsCkOdQr6v0pejtLHlji6CTqgae33Zx6OAObfOi0SNcD+Ie4uRAo Y5445HY6Segx93DpNQ/F4MHycEGgpJMuK2SBrd3yoJDWcPsJjhUCO0ki3jhAv0dPmn2e Kk6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=B22Il4U+lW9qJRmIpKE7jAR5AR4P5G5MCstdmwVkA+0=; b=cupi1Bp05FfQSmoVgArZfGmtxwAKscw/SgyABHHPNbtjs5XzorxJimksaO0s6qQSSz 9SzG3nJQaQLOG5iSe149IGx2sDAysQKHpVVyLxclfLJo+xHYfwG76QDiZJTApFiCEmOU K8mGzIApAT8QF0mZcymuJSGFWZXCxdJaYTS/2C8Skh/D7GGEq2vlWJT4TcRhkCdAh9UM ZUE3idcNZGqyjxYum6bdMhAZFujUIiCLsJEm0GDaMdnvPCF4Yj/VF2C1dC8RndO9tEvt 464kQ+m0eMWmVLYyixLFH/2K62idEYcUC1x9WBQdRA73uH0QooqqAnZAbf0Sm2H+CM8F o3Yw== X-Gm-Message-State: AN3rC/4DBq6paUX/CO6Ea/Ef286bUdwWdnH9z41Lr0hJmu5Tv85QdFxO Nj0gaZgyGx0Q9g== X-Received: by 10.84.142.101 with SMTP id 92mr16615371plw.112.1492987275628; Sun, 23 Apr 2017 15:41:15 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Mon, 24 Apr 2017 07:40:49 +0900 Message-Id: <356a2db3c6f84e8e79e5afa3913514184bff5f50.1492986468.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH v2 1/9] target/openrisc: Implement EVBAR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , "Tim \\'mithro\\' Ansell" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Tim 'mithro' Ansell Exception Vector Base Address Register (EVBAR) - This optional register can be used to apply an offset to the exception vector addresses. The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). Its presence is indicated by the EVBARP bit in the CPU Configuration Register (CPUCFGR). Signed-off-by: Tim 'mithro' Ansell Signed-off-by: Stafford Horne --- target/openrisc/cpu.c | 2 ++ target/openrisc/cpu.h | 7 +++++++ target/openrisc/interrupt.c | 6 +++++- target/openrisc/sys_helper.c | 7 +++++++ 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 7fd2b9a..1524ed9 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -134,6 +134,7 @@ static void or1200_initfn(Object *obj) =20 set_feature(cpu, OPENRISC_FEATURE_OB32S); set_feature(cpu, OPENRISC_FEATURE_OF32S); + set_feature(cpu, OPENRISC_FEATURE_EVBAR); } =20 static void openrisc_any_initfn(Object *obj) @@ -141,6 +142,7 @@ static void openrisc_any_initfn(Object *obj) OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 set_feature(cpu, OPENRISC_FEATURE_OB32S); + set_feature(cpu, OPENRISC_FEATURE_EVBAR); } =20 typedef struct OpenRISCCPUInfo { diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 418a0e6..1958b72 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -111,6 +111,11 @@ enum { CPUCFGR_OF32S =3D (1 << 7), CPUCFGR_OF64S =3D (1 << 8), CPUCFGR_OV64S =3D (1 << 9), + /* CPUCFGR_ND =3D (1 << 10), */ + /* CPUCFGR_AVRP =3D (1 << 11), */ + CPUCFGR_EVBARP =3D (1 << 12), + /* CPUCFGR_ISRP =3D (1 << 13), */ + /* CPUCFGR_AECSRP =3D (1 << 14), */ }; =20 /* DMMU configure register */ @@ -200,6 +205,7 @@ enum { OPENRISC_FEATURE_OF32S =3D (1 << 7), OPENRISC_FEATURE_OF64S =3D (1 << 8), OPENRISC_FEATURE_OV64S =3D (1 << 9), + OPENRISC_FEATURE_EVBAR =3D (1 << 12), }; =20 /* Tick Timer Mode Register */ @@ -289,6 +295,7 @@ typedef struct CPUOpenRISCState { uint32_t dmmucfgr; /* DMMU configure register */ uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ + uint32_t evbar; /* Exception vector base address register */ uint32_t fpcsr; /* Float register */ float_status fp_status; =20 diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index a2eec6f..78f0ba9 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -65,7 +65,11 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->lock_addr =3D -1; =20 if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { - env->pc =3D (cs->exception_index << 8); + hwaddr vect_pc =3D cs->exception_index << 8; + if (env->cpucfgr & CPUCFGR_EVBARP) { + vect_pc |=3D env->evbar; + } + env->pc =3D vect_pc; } else { cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 60c3193..6ba8162 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -39,6 +39,10 @@ void HELPER(mtspr)(CPUOpenRISCState *env, env->vr =3D rb; break; =20 + case TO_SPR(0, 11): /* EVBAR */ + env->evbar =3D rb; + break; + case TO_SPR(0, 16): /* NPC */ cpu_restore_state(cs, GETPC()); /* ??? Mirror or1ksim in not trashing delayed branch state @@ -206,6 +210,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 4): /* IMMUCFGR */ return env->immucfgr; =20 + case TO_SPR(0, 11): /* EVBAR */ + return env->evbar; + case TO_SPR(0, 16): /* NPC (equals PC) */ cpu_restore_state(cs, GETPC()); return env->pc; --=20 2.9.3 From nobody Thu May 2 19:20:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492987523373881.2850119819462; Sun, 23 Apr 2017 15:45:23 -0700 (PDT) Received: from localhost ([::1]:40842 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QFu-0003YN-3v for importer@patchew.org; Sun, 23 Apr 2017 18:45:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55827) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QC0-0000QX-0t for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2QBz-0000Oe-Ax for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:20 -0400 Received: from mail-io0-x242.google.com ([2607:f8b0:4001:c06::242]:36481) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d2QBz-0000OT-5s for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:19 -0400 Received: by mail-io0-x242.google.com with SMTP id x86so43370900ioe.3 for ; Sun, 23 Apr 2017 15:41:19 -0700 (PDT) Received: from localhost (z64.124-44-184.ppp.wakwak.ne.jp. [124.44.184.64]) by smtp.gmail.com with ESMTPSA id u23sm26944039pfd.63.2017.04.23.15.41.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 23 Apr 2017 15:41:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=T/5SyyeuyLbC6XdPnHSu/yu73YSFhxwg0LcKe5HXvxA=; b=h2NVCIX1BBOr6e0lPGQkxqtvzwzi2QX2mCRs7eCtkExfSHvVDlURzFAwK5vDqOVEjK nQgG6mfVlwhr9IQJQIkEl66mj91KXZ8h57sm8b0WnhMBFbN1UbVI8vM86Y8EkFwKFbV9 j98Tcx7Da9TaB0SiBfOnSRi+rJ4TE7fUELFuVvw0gXibl30YFEOvuqWJswD9UIBgyQqn HFCJ4vzU0r+T/bkwzI3kJoXYIzWs6RKUUS8bmnnl2HXyF4t76hw2t33zVTCGBVd1hiTZ VnM+7FVaQaI9BWti47sUI5m0L7sXTx6Tx7sq+PIToHM0lb98tGHM4940O+2Q/8IRow2u nNSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=T/5SyyeuyLbC6XdPnHSu/yu73YSFhxwg0LcKe5HXvxA=; b=JjZpcHwYJZd6UUGXMqU5yCtQC7z7p6OW1YavQFHBuJRIH1T/FZI/mh6+gLRkg3vApx RFhB5rfxkvRc/yC8yBQOdX/XG3gYmwNJGhqUIfEMbDny2Ns3aKuXMpwnw8TGNx8dVgkL umQCa2Fo2Mlg+zUJ82VtkorNKV4DrqVs/Res0OoUDOrV+xqM/U1KqPjgdxEOntVFIz5o bCX9p+q0nNmGITDzYV8fAl1KaZSqIbf/PNDNcI0cDLcfC1wF8aje5Dp+zqa3C8bsPLAN 1kIAm0mdDM72xuFZQZX8w3BHj1ROrUioFw4BexRnyToXlV3xWyNsY0OSZ/u4IbiKLANx To2w== X-Gm-Message-State: AN3rC/794Vz9e6RLGdv1j+MRCo4RbwXYenZmDnZM8lyd7x6IxnMLbdJa eRYfU3W/auR+CQ== X-Received: by 10.98.31.90 with SMTP id f87mr9200149pff.264.1492987278500; Sun, 23 Apr 2017 15:41:18 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Mon, 24 Apr 2017 07:40:50 +0900 Message-Id: <3fee028d1ea02cd16470dc5c65d54974ef85b673.1492986468.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::242 Subject: [Qemu-devel] [PATCH v2 2/9] target/openrisc: Implement EPH bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , "Tim \\'mithro\\' Ansell" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Tim 'mithro' Ansell Exception Prefix High (EPH) control bit of the Supervision Register (SR). The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). If SR[EPH] is set, the vector offset is logically ORed with the offset 0xF0000000. This means if EPH is; * 0 - Exceptions vectors start at EVBAR * 1 - Exception vectors start at EVBAR | 0xF0000000 Signed-off-by: Tim 'mithro' Ansell Signed-off-by: Stafford Horne --- target/openrisc/interrupt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 78f0ba9..2c91fab 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -69,6 +69,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs) if (env->cpucfgr & CPUCFGR_EVBARP) { vect_pc |=3D env->evbar; } + if (env->sr & SR_EPH) { + vect_pc |=3D 0xf0000000; + } env->pc =3D vect_pc; } else { cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); --=20 2.9.3 From nobody Thu May 2 19:20:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492987386309131.75938083655046; Sun, 23 Apr 2017 15:43:06 -0700 (PDT) Received: from localhost ([::1]:40834 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QDg-0001ad-VR for importer@patchew.org; Sun, 23 Apr 2017 18:43:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55861) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QC2-0000SL-BP for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2QC1-0000QA-J4 for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:22 -0400 Received: from mail-it0-x243.google.com ([2607:f8b0:4001:c0b::243]:35134) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d2QC1-0000Q2-Dm for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:21 -0400 Received: by mail-it0-x243.google.com with SMTP id e132so11953230ite.2 for ; Sun, 23 Apr 2017 15:41:21 -0700 (PDT) Received: from localhost (z64.124-44-184.ppp.wakwak.ne.jp. [124.44.184.64]) by smtp.gmail.com with ESMTPSA id w17sm26887134pfg.75.2017.04.23.15.41.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 23 Apr 2017 15:41:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=yxHg3XOdD+A+57odxRvo3TC/7WsvaeDBVyL72alOQJg=; b=p5MU1PQUUdxtRgtFGKn4jrQCxv2Fh38DUxAnCoHOBbPyasZp+LXQfeSHDx9cbe3vLU mBQ3J4cV/3RVwPNeY8pMczWmjl3nZOXsR2DIqwxfg6K+pMWAAh6XmFj7PuynitGUaLxU DhrX0udiECWdZPVvnqOoEhPY7b+niR7yepQ0ADYReOtm3WqSSebJnOmJ4OB26Y35x4hN 1qLkCjwOyW4U0ymFspnE9XSU3Yo011LWjRfRD1fKQVz10T590vtUCI8rOWaKH4xqx6Xg nu/a5/Frv/X50ZOj5y5vgLOMLdVEsODaVQqpPsqnneIGsjwFnqWBwmCC868d33u3ir5L GHBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=yxHg3XOdD+A+57odxRvo3TC/7WsvaeDBVyL72alOQJg=; b=TfG+EPwMc3NJsg4YRoRMGQ3qt+xS4JMKHp4VNGZJPvqNbWkcDlLhFPnEqoCqTrl8H8 Gx24IOJT6A7Tg8RvuwqBODTNkzgbwSwXibctHifmenoV1k5tC5WHscclS65X+p0gmMx2 VFfY5wMSFZ1PqTInMsO5lygFCmvyj409TpNRMJsPDiH3nBucjEcudTMDro5f+sxmEcpz E7H1kHZFKes7Or0biF9I0GGMxroPkw5n9s5TiC8gX+otRfj3Hf1TmJx/87ouyL+Ql3a7 vBJvRJYDU4zE7nGPjSUKDJftDNDVdo80QwCWig9tL2zMIGKgXs/ZwC69ZzoP+OQeLSfI 6iPw== X-Gm-Message-State: AN3rC/7BKOskb+tpw8957RjAwdoRW8LgWlDwqTrg6v0TmsL9gbS7jUiW dbhd81VYJsGhtg== X-Received: by 10.99.141.199 with SMTP id z190mr21846763pgd.118.1492987280823; Sun, 23 Apr 2017 15:41:20 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Mon, 24 Apr 2017 07:40:51 +0900 Message-Id: X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH v2 3/9] target/openrisc: Fixes for memory debugging X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , "Tim \\'mithro\\' Ansell" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When debugging in gdb you might want to inspect instructions in mapped pages or in exception vectors like 0x800 etc. This was previously not possible in qemu since the *get_phys_page_debug() routine only looked into the data tlb. Change to fall back to look into instruction tlb and plain physical pages. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/mmu.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 56b11d3..a6d7bcd 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -124,7 +124,7 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu, { int ret =3D TLBRET_MATCH; =20 - if (rw =3D=3D 2) { /* ITLB */ + if (rw =3D=3D MMU_INST_FETCH) { /* ITLB */ *physical =3D 0; ret =3D cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical, prot, address, r= w); @@ -221,12 +221,27 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs,= vaddr addr) OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); hwaddr phys_addr; int prot; + int miss; =20 - if (cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0)) { - return -1; + /* Check memory for any kind of address, since during debug the + gdb can ask for anything, check data tlb for address */ + miss =3D cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0); + + /* Check instruction tlb */ + if (miss) { + miss =3D cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, = MMU_INST_FETCH); + } + + /* Last, fall back to a plain address */ + if (miss) { + miss =3D cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr,= 0); } =20 - return phys_addr; + if (miss) { + return -1; + } else { + return phys_addr; + } } =20 void cpu_openrisc_mmu_init(OpenRISCCPU *cpu) --=20 2.9.3 From nobody Thu May 2 19:20:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492987533106930.5536795686496; Sun, 23 Apr 2017 15:45:33 -0700 (PDT) Received: from localhost ([::1]:40848 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QG3-0003ja-QZ for importer@patchew.org; Sun, 23 Apr 2017 18:45:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55918) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QC5-0000Ui-IE for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2QC4-0000Rf-Dk for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:25 -0400 Received: from mail-io0-x241.google.com ([2607:f8b0:4001:c06::241]:34999) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d2QC4-0000RO-91 for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:24 -0400 Received: by mail-io0-x241.google.com with SMTP id d203so43489179iof.2 for ; Sun, 23 Apr 2017 15:41:24 -0700 (PDT) Received: from localhost (z64.124-44-184.ppp.wakwak.ne.jp. [124.44.184.64]) by smtp.gmail.com with ESMTPSA id c7sm27089316pgn.24.2017.04.23.15.41.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 23 Apr 2017 15:41:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=dkFGGmR2gcm5Xi/ekdDkUxK5HozEtZKrS7V8dnqBy5M=; b=EVOJ3u0nq3dSrv90f2dkOPo25aidjiLVI7bQ/JjNj/t1hzJF9gm3v0I4fZWBsjyKj1 bAdnPuvlxCLp7mhI8rGHzNNFnxcko0l0ER0BXWkLcrVpQxhbfVZU3JiczDUlYpiFPP9+ QjDH4AbMLydrThDsgumNdsSiKM/aiDy9ulZWAfVbxmo6tn/1cNuWw1bGMrODbVyS7uY6 DiKVEK+X0ASgD6peQZ9BwesKrPqb161Y1kPInngOl10m8tqoZ/QBR7ySdghdgnCJapp7 cpBVjNlwXsLXX64AvME43e1Bu7qC3xyP/31qoR1wZSbka6YTTbIkxBOWA1lxWRnWlmWI aAjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=dkFGGmR2gcm5Xi/ekdDkUxK5HozEtZKrS7V8dnqBy5M=; b=QfGhzX/WFh/5Oq96QAUPeRyOY9DRv6PTiY4pfKzNK3ici7oFRkrhp4BvMpqpeE6uPZ MocH9ETf5czvJMbH31jhdHsmaw/qFzVu3xL7nfaItaY2nXuNnpjjKMi0BVJih2jrfdzm MGgcqH4JERxSPyVtLKvTpRffhSh40vH1lkjTfUM8DmfKMCPcO6Yjxd7m9xIvjyEEI7sp zYtbKhV3CmGbXoT8yDfhrH54RGJnvON5n0qsXZq9osW/eE5dhbGDPGf4ljSFRz9ipgED ZkEloVmDCmkywx8fo3f4nk2bGVfkh4B7eM/3jm3wN0KzwQydZu6QHvnElwfxH19Kaw80 Ihcw== X-Gm-Message-State: AN3rC/4zWvFgMf9fxW4irEwZRGhTFGGBR4yO0N5ts7NxR0mWd98b6dRA MmIfqlIFHjiWHw== X-Received: by 10.98.217.80 with SMTP id s77mr22323840pfg.26.1492987283597; Sun, 23 Apr 2017 15:41:23 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Mon, 24 Apr 2017 07:40:52 +0900 Message-Id: <4d3ebb3092f5ac66a58357cee15bd5432e77f2fe.1492986468.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::241 Subject: [Qemu-devel] [PATCH v2 4/9] target/openrisc: add numcores and coreid support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , "Tim \\'mithro\\' Ansell" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These are used to identify the processor in SMP system. Their definition has been defined in verilog cores but it not yet part of the spec but it will be soon. The proposal for this is available: https://openrisc.io/proposals/core-identifier-and-number-of-cores Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/sys_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 6ba8162..e13666b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -233,6 +233,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 64): /* ESR */ return env->esr; =20 + case TO_SPR(0, 128): /* COREID */ + return 0; + + case TO_SPR(0, 129): /* NUMCORES */ + return 1; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); return env->tlb->dtlb[0][idx].mr; --=20 2.9.3 From nobody Thu May 2 19:20:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492987670233535.7968728572341; Sun, 23 Apr 2017 15:47:50 -0700 (PDT) Received: from localhost ([::1]:40856 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QIG-0005f1-VV for importer@patchew.org; Sun, 23 Apr 2017 18:47:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55977) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QC8-0000XQ-A7 for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2QC7-0000Th-9i for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:28 -0400 Received: from mail-it0-x244.google.com ([2607:f8b0:4001:c0b::244]:33562) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d2QC7-0000TA-3H for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:27 -0400 Received: by mail-it0-x244.google.com with SMTP id z67so11956163itb.0 for ; Sun, 23 Apr 2017 15:41:26 -0700 (PDT) Received: from localhost (z64.124-44-184.ppp.wakwak.ne.jp. [124.44.184.64]) by smtp.gmail.com with ESMTPSA id f124sm26911647pgc.43.2017.04.23.15.41.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 23 Apr 2017 15:41:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=+4Icp+M0RQj6v24329W16eXLptpcG7P4F8rWNRb6XDQ=; b=Ir25NzxCp/nzdqYo0LjtTWCZ+L8LwHVurT2FW8+GdST/xKEZJWWvMIieD8umYappj8 6w+m1lfRZD3GRk4rLyTlIfbkBtmhdhR38Gk4Y6ZY8qu9kICxaYi+n3+5D49GuPTebK6K XB71IREJJolmw23SFcbKftLTY8reE0e+Gi83VERtKcwRIAYezLfFARxcQt+IYEGlegaf jlvv+EBOI2haMKLAo/pBJuUPSxx1sZKNzNd3kedxKQT6GoV/aZYjXNwxkKaUKk44uEvW qmPt+VwMVIAWeBj3urFIpiXG75hDj9iHvouze2CQVZqZAENmPRaZJZskAUoZg0+eU2pu hlZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=+4Icp+M0RQj6v24329W16eXLptpcG7P4F8rWNRb6XDQ=; b=jUnCJsH1B2Syxo4iT/enrQK7un3VZE12DuK15yrghXORvc7SsVDkIuK7L6H3WEQlF9 mPuci0QCjg5Sqqlhk1TFwhXHJI+AI7Xk8Wch/E4Ee2F+CfSB7jNfUqvem1muaQC1HiiB TC+Jzkw9/2Dqau7lISTunn7teY5DhVN4Sz7Fa2EvNCLeDiI0nnVZH4KZK7Q1Q0c76KgZ lM6Pcmmgut+LckGgTglBs2drvNzuXRx7fIQAubxfTZ3eELqwBVt2b0B5+MjCxXbecKTe DEjpX/wCvbOZyH+5kd9w7FNi0ZXkd2qQaHS5Qu3v7u3DFrBAGeNrU25LBHMBMmAAQkS0 kaSQ== X-Gm-Message-State: AN3rC/7NW6zF1TMWlXAzUVKhFz6GN19Pouz5XaYw0xCMV9KjmhTXYMkT 6JtUn3BVJeYf4A== X-Received: by 10.99.166.18 with SMTP id t18mr15675225pge.109.1492987286371; Sun, 23 Apr 2017 15:41:26 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Mon, 24 Apr 2017 07:40:53 +0900 Message-Id: X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::244 Subject: [Qemu-devel] [PATCH v2 5/9] migration: Add VMSTATE_UINTTL_2DARRAY() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , "Tim \\'mithro\\' Ansell" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In openRISC we are implementing the shadow registers as a 2d array. Using this target long method rather than direct 32-bit alternatives is consistent with the rest of our vm state serialization logic. Signed-off-by: Stafford Horne --- include/migration/cpu.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/migration/cpu.h b/include/migration/cpu.h index f3d5dfc..a40bd35 100644 --- a/include/migration/cpu.h +++ b/include/migration/cpu.h @@ -18,6 +18,8 @@ VMSTATE_UINT64_EQUAL_V(_f, _s, _v) #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v) +#define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v) \ + VMSTATE_UINT64_2DARRAY_V(_f, _s, _n1, _n2, _v) #define VMSTATE_UINTTL_TEST(_f, _s, _t) \ VMSTATE_UINT64_TEST(_f, _s, _t) #define vmstate_info_uinttl vmstate_info_uint64 @@ -37,6 +39,8 @@ VMSTATE_UINT32_EQUAL_V(_f, _s, _v) #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v) +#define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v) \ + VMSTATE_UINT32_2DARRAY_V(_f, _s, _n1, _n2, _v) #define VMSTATE_UINTTL_TEST(_f, _s, _t) \ VMSTATE_UINT32_TEST(_f, _s, _t) #define vmstate_info_uinttl vmstate_info_uint32 @@ -48,5 +52,8 @@ VMSTATE_UINTTL_EQUAL_V(_f, _s, 0) #define VMSTATE_UINTTL_ARRAY(_f, _s, _n) \ VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, 0) +#define VMSTATE_UINTTL_2DARRAY(_f, _s, _n1, _n2) \ + VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, 0) + =20 #endif --=20 2.9.3 From nobody Thu May 2 19:20:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492987521051204.34163129624437; Sun, 23 Apr 2017 15:45:21 -0700 (PDT) Received: from localhost ([::1]:40841 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QFr-0003Ur-6u for importer@patchew.org; Sun, 23 Apr 2017 18:45:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56029) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QCC-0000aL-0T for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2QCA-0000WL-9h for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:32 -0400 Received: from mail-it0-x243.google.com ([2607:f8b0:4001:c0b::243]:36396) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d2QCA-0000VF-3m for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:30 -0400 Received: by mail-it0-x243.google.com with SMTP id x188so11177360itb.3 for ; Sun, 23 Apr 2017 15:41:29 -0700 (PDT) Received: from localhost (z64.124-44-184.ppp.wakwak.ne.jp. [124.44.184.64]) by smtp.gmail.com with ESMTPSA id d24sm26899980pfb.97.2017.04.23.15.41.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 23 Apr 2017 15:41:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=a8cdvnD5XgP1krOEfyyT2m1Gwo4mKEqfSkC1ya1HSF0=; b=cUM+7KVMvhDn4+nL8YV1M0FdJyA8Z/eIDMhbrNt1ecbUhuzSylDtbhR5Y9ZsMXLOru 6DLPVu77TqlTGvuCvk2cdOqUhw+068KGFwE2vvBcoCegykdoFZ5eH0JMywshxuR7znAK L9zi/v79x0FsdCyBXbna7zPEk+WUX65LUIUDqBj2JG6Ao+cBU2prP/RZkykKIs9mcQcU ObqvbeSmbEyjgb+NqslaefZNx8OwDcQ/2s4nwzR4RZ9VCUr9p8dy1g7O9m2t46d+Vl1h ZKbXsb/bnWwJz/kN8ObbrCR6Aa0xL0/iWf/qyR/9e8uKbklecRxNHUbHXpV6i4Hq8Ig2 8igg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=a8cdvnD5XgP1krOEfyyT2m1Gwo4mKEqfSkC1ya1HSF0=; b=YEfW91+gqDBa76mfgvLU0BiT+gGag346dm3p3g0bf97XYVDOYdDCbsh6aAn7OhL9Ke 8IR8pUtlyruYj0GptcI3qsRvzesXkteeG1SaMKuqw4bi4fT2Y+EXCx/cmNJaX36Uq+2I 0uhyc8/dk7Qo/9H1cGLqAshatqpf0tvDdI5HfozQWq3Wo4QFE3eLaY8sFRPYu9GKt4NO OwRZipocPSzC7HCaRnP2cqUaQNiaNMUHvyZN0MLX4ErqkCS0FHxmA8hQKDE7wX1dcGol ZNRHxVAW1YzbxQnOId2I7QIGPT420Ggq1WTtypHR7u2EECPiI9H4C4xQVIqqjGqLnOVl 02Bw== X-Gm-Message-State: AN3rC/6f2pDjcGVXX028HmUzhy60sfgplTBTnS64xUX9Z4msGFlwgmAa cuUpHk29Mr/2Whsi X-Received: by 10.84.224.12 with SMTP id r12mr28684803plj.69.1492987289267; Sun, 23 Apr 2017 15:41:29 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Mon, 24 Apr 2017 07:40:54 +0900 Message-Id: <954c36a45feb9e2a8fac76ef2866b734d8eac91f.1492986468.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH v2 6/9] target/openrisc: implement shadow registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , "Tim \\'mithro\\' Ansell" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Shadow registers are part of the openrisc spec along with sr[cid], as part of the fast context switching feature. When exceptions occur, instead of having to save registers to the stack if enabled the CID will increment and a new set of registers will be available. This patch only implements shadow registers which can be used as extra scratch registers via the mfspr and mtspr if required. This is implemented in a way where it would be easy to add on the fast context switching, currently cid is hardcoded to 0. This is need for openrisc linux smp kernels to boot correctly. Signed-off-by: Stafford Horne --- Changes since v1: o Use accessor functions cpu_get_gpr()/cpu_set_gpr() linux-user/elfload.c | 2 +- linux-user/main.c | 18 +++++++++--------- linux-user/openrisc/target_cpu.h | 6 +++--- linux-user/openrisc/target_signal.h | 2 +- linux-user/signal.c | 16 ++++++++-------- target/openrisc/cpu.c | 4 +++- target/openrisc/cpu.h | 15 +++++++++++++-- target/openrisc/gdbstub.c | 4 ++-- target/openrisc/machine.c | 6 +++--- target/openrisc/sys_helper.c | 9 +++++++++ target/openrisc/translate.c | 5 +++-- 11 files changed, 55 insertions(+), 32 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f520d77..ce77317 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1052,7 +1052,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *= regs, int i; =20 for (i =3D 0; i < 32; i++) { - (*regs)[i] =3D tswapreg(env->gpr[i]); + (*regs)[i] =3D tswapreg(cpu_get_gpr(env, i)); } (*regs)[32] =3D tswapreg(env->pc); (*regs)[33] =3D tswapreg(cpu_get_sr(env)); diff --git a/linux-user/main.c b/linux-user/main.c index 10a3bb3..79d621b 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2590,17 +2590,17 @@ void cpu_loop(CPUOpenRISCState *env) case EXCP_SYSCALL: env->pc +=3D 4; /* 0xc00; */ ret =3D do_syscall(env, - env->gpr[11], /* return value */ - env->gpr[3], /* r3 - r7 are params */ - env->gpr[4], - env->gpr[5], - env->gpr[6], - env->gpr[7], - env->gpr[8], 0, 0); + cpu_get_gpr(env, 11), /* return value */ + cpu_get_gpr(env, 3), /* r3 - r7 are params */ + cpu_get_gpr(env, 4), + cpu_get_gpr(env, 5), + cpu_get_gpr(env, 6), + cpu_get_gpr(env, 7), + cpu_get_gpr(env, 8), 0, 0); if (ret =3D=3D -TARGET_ERESTARTSYS) { env->pc -=3D 4; } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - env->gpr[11] =3D ret; + cpu_set_gpr(env, 11, ret); } break; case EXCP_DPF: @@ -4765,7 +4765,7 @@ int main(int argc, char **argv, char **envp) int i; =20 for (i =3D 0; i < 32; i++) { - env->gpr[i] =3D regs->gpr[i]; + cpu_set_gpr(env, i, regs->gpr[i]); } env->pc =3D regs->pc; cpu_set_sr(env, regs->sr); diff --git a/linux-user/openrisc/target_cpu.h b/linux-user/openrisc/target_= cpu.h index f283d96..606ad6f 100644 --- a/linux-user/openrisc/target_cpu.h +++ b/linux-user/openrisc/target_cpu.h @@ -23,14 +23,14 @@ static inline void cpu_clone_regs(CPUOpenRISCState *env, target_ulong news= p) { if (newsp) { - env->gpr[1] =3D newsp; + cpu_set_gpr(env, 1, newsp); } - env->gpr[11] =3D 0; + cpu_set_gpr(env, 11, 0); } =20 static inline void cpu_set_tls(CPUOpenRISCState *env, target_ulong newtls) { - env->gpr[10] =3D newtls; + cpu_set_gpr(env, 10, newtls); } =20 #endif diff --git a/linux-user/openrisc/target_signal.h b/linux-user/openrisc/targ= et_signal.h index 9f2c493..95a733e 100644 --- a/linux-user/openrisc/target_signal.h +++ b/linux-user/openrisc/target_signal.h @@ -20,7 +20,7 @@ typedef struct target_sigaltstack { =20 static inline abi_ulong get_sp_from_cpustate(CPUOpenRISCState *state) { - return state->gpr[1]; + return cpu_get_gpr(state, 1); } =20 =20 diff --git a/linux-user/signal.c b/linux-user/signal.c index a67db04..eb6cb9f 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -4411,7 +4411,7 @@ static void setup_sigcontext(struct target_sigcontext= *sc, CPUOpenRISCState *regs, unsigned long mask) { - unsigned long usp =3D regs->gpr[1]; + unsigned long usp =3D cpu_get_gpr(regs, 1); =20 /* copy the regs. they are first in sc so we can use sc directly */ =20 @@ -4436,7 +4436,7 @@ static inline abi_ulong get_sigframe(struct target_si= gaction *ka, CPUOpenRISCState *regs, size_t frame_size) { - unsigned long sp =3D regs->gpr[1]; + unsigned long sp =3D cpu_get_gpr(regs, 1); int onsigstack =3D on_sig_stack(sp); =20 /* redzone */ @@ -4489,7 +4489,7 @@ static void setup_rt_frame(int sig, struct target_sig= action *ka, __put_user(0, &frame->uc.tuc_link); __put_user(target_sigaltstack_used.ss_sp, &frame->uc.tuc_stack.ss_sp); - __put_user(sas_ss_flags(env->gpr[1]), &frame->uc.tuc_stack.ss_flags); + __put_user(sas_ss_flags(cpu_get_gpr(env, 1)), &frame->uc.tuc_stack.ss_= flags); __put_user(target_sigaltstack_used.ss_size, &frame->uc.tuc_stack.ss_size); setup_sigcontext(&frame->sc, env, set->sig[0]); @@ -4512,13 +4512,13 @@ static void setup_rt_frame(int sig, struct target_s= igaction *ka, =20 /* Set up registers for signal handler */ env->pc =3D (unsigned long)ka->_sa_handler; /* what we enter NOW */ - env->gpr[9] =3D (unsigned long)return_ip; /* what we enter LATER */ - env->gpr[3] =3D (unsigned long)sig; /* arg 1: signo */ - env->gpr[4] =3D (unsigned long)&frame->info; /* arg 2: (siginfo_t*) */ - env->gpr[5] =3D (unsigned long)&frame->uc; /* arg 3: ucontext */ + cpu_set_gpr(env, 9, (unsigned long)return_ip); /* what we enter LA= TER */ + cpu_set_gpr(env, 3, (unsigned long)sig); /* arg 1: signo */ + cpu_set_gpr(env, 4, (unsigned long)&frame->info); /* arg 2: (siginfo_= t*) */ + cpu_set_gpr(env, 5, (unsigned long)&frame->uc); /* arg 3: ucontext = */ =20 /* actually move the usp to reflect the stacked frame */ - env->gpr[1] =3D (unsigned long)frame; + cpu_set_gpr(env, 1, (unsigned long)frame); =20 return; =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 1524ed9..6c1ed07 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -52,7 +52,7 @@ static void openrisc_cpu_reset(CPUState *s) s->exception_index =3D -1; =20 cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; - cpu->env.cpucfgr =3D CPUCFGR_OB32S | CPUCFGR_OF32S; + cpu->env.cpucfgr =3D CPUCFGR_OB32S | CPUCFGR_OF32S | CPUCFGR_NSGF; cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 <= < 2)); cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 <= < 2)); =20 @@ -132,6 +132,7 @@ static void or1200_initfn(Object *obj) { OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 + set_feature(cpu, OPENRISC_FEATURE_NSGF); set_feature(cpu, OPENRISC_FEATURE_OB32S); set_feature(cpu, OPENRISC_FEATURE_OF32S); set_feature(cpu, OPENRISC_FEATURE_EVBAR); @@ -141,6 +142,7 @@ static void openrisc_any_initfn(Object *obj) { OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 + set_feature(cpu, OPENRISC_FEATURE_NSGF); set_feature(cpu, OPENRISC_FEATURE_OB32S); set_feature(cpu, OPENRISC_FEATURE_EVBAR); } diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 1958b72..e159b22 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -275,7 +275,8 @@ typedef struct CPUOpenRISCTLBContext { #endif =20 typedef struct CPUOpenRISCState { - target_ulong gpr[32]; /* General registers */ + target_ulong shadow_gpr[16][32]; /* Shadow registers */ + target_ulong pc; /* Program counter */ target_ulong ppc; /* Prev PC */ target_ulong jmp_pc; /* Jump PC */ @@ -399,6 +400,16 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, #define TB_FLAGS_R0_0 2 #define TB_FLAGS_OVE SR_OVE =20 +static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i) +{ + return env->shadow_gpr[0][i]; +} + +static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val) +{ + env->shadow_gpr[0][i] =3D val; +} + static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *f= lags) @@ -406,7 +417,7 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCStat= e *env, *pc =3D env->pc; *cs_base =3D 0; *flags =3D (env->dflag - | (env->gpr[0] =3D=3D 0 ? TB_FLAGS_R0_0 : 0) + | (cpu_get_gpr(env, 0) =3D=3D 0 ? TB_FLAGS_R0_0 : 0) | (env->sr & SR_OVE)); } =20 diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index b18c7e9..f9af650 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -28,7 +28,7 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t = *mem_buf, int n) CPUOpenRISCState *env =3D &cpu->env; =20 if (n < 32) { - return gdb_get_reg32(mem_buf, env->gpr[n]); + return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n)); } else { switch (n) { case 32: /* PPC */ @@ -61,7 +61,7 @@ int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t= *mem_buf, int n) tmp =3D ldl_p(mem_buf); =20 if (n < 32) { - env->gpr[n] =3D tmp; + cpu_set_gpr(env, n, tmp); } else { switch (n) { case 32: /* PPC */ diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 686eaa3..2bf71c3 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -47,10 +47,10 @@ static const VMStateInfo vmstate_sr =3D { =20 static const VMStateDescription vmstate_env =3D { .name =3D "env", - .version_id =3D 4, - .minimum_version_id =3D 4, + .version_id =3D 5, + .minimum_version_id =3D 5, .fields =3D (VMStateField[]) { - VMSTATE_UINTTL_ARRAY(gpr, CPUOpenRISCState, 32), + VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), VMSTATE_UINTTL(pc, CPUOpenRISCState), VMSTATE_UINTTL(ppc, CPUOpenRISCState), VMSTATE_UINTTL(jmp_pc, CPUOpenRISCState), diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index e13666b..fa3d6a4 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -92,6 +92,11 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(0, 64): /* ESR */ env->esr =3D rb; break; + + case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ + idx =3D (spr - 1024); + env->shadow_gpr[idx / 32][idx % 32] =3D rb; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); if (!(rb & 1)) { @@ -239,6 +244,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 129): /* NUMCORES */ return 1; =20 + case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ + idx =3D (spr - 1024); + return env->shadow_gpr[idx / 32][idx % 32]; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 = */ idx =3D spr - TO_SPR(1, 512); return env->tlb->dtlb[0][idx].mr; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7c4cbf2..e49518e 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -107,7 +107,8 @@ void openrisc_translate_init(void) "mac"); for (i =3D 0; i < 32; i++) { cpu_R[i] =3D tcg_global_mem_new(cpu_env, - offsetof(CPUOpenRISCState, gpr[i]), + offsetof(CPUOpenRISCState, + shadow_gpr[0][i]), regnames[i]); } cpu_R0 =3D cpu_R[0]; @@ -1662,7 +1663,7 @@ void openrisc_cpu_dump_state(CPUState *cs, FILE *f, =20 cpu_fprintf(f, "PC=3D%08x\n", env->pc); for (i =3D 0; i < 32; ++i) { - cpu_fprintf(f, "R%02d=3D%08x%c", i, env->gpr[i], + cpu_fprintf(f, "R%02d=3D%08x%c", i, cpu_get_gpr(env, i), (i % 4) =3D=3D 3 ? '\n' : ' '); } } --=20 2.9.3 From nobody Thu May 2 19:20:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492987662071307.38445326473413; Sun, 23 Apr 2017 15:47:42 -0700 (PDT) Received: from localhost ([::1]:40855 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QI8-0005Xb-Ok for importer@patchew.org; Sun, 23 Apr 2017 18:47:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56060) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QCF-0000cy-99 for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2QCC-0000Y4-SR for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:35 -0400 Received: from mail-it0-x241.google.com ([2607:f8b0:4001:c0b::241]:34182) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d2QCC-0000Xw-Nv for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:32 -0400 Received: by mail-it0-x241.google.com with SMTP id c26so4021211itd.1 for ; Sun, 23 Apr 2017 15:41:32 -0700 (PDT) Received: from localhost (z64.124-44-184.ppp.wakwak.ne.jp. [124.44.184.64]) by smtp.gmail.com with ESMTPSA id r86sm1777560pfb.24.2017.04.23.15.41.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 23 Apr 2017 15:41:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=1ULqFvCAucxpqTx+6eOt1U2rQEOVWS/jn5Ic4C9K95s=; b=ahOlOLT4sbk5ySP48uECFY4uuE8Oi4aaaGjMqns3Zt8TO/9vRIbv6dtxXTyr681oZ5 Bw2j2IKcVYnU1jUZoAK079OIZhWQj6coLs48O4BcYZ5WdAReY0/HnVTNPKoJeK8mLHBd o9KIHYBtiVnzYo/MAt9XyERFQ256X0jVnaVHZArO2C7/IRnQcBqdyGqrI9JYvctIWghq uHL0ILkjmMFr9Z8mMfHU2+WRkaTII0lXPZFHF7B4CgeCAg9+zFOtIk3fKcyyNHe28PVi fLUvArzQ6uThBQ8Ve/OmpGAsOZgoJz1KTqCvpN/u9+w0nWdJ4arsJscHZSkYvRwiWIUl xAIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=1ULqFvCAucxpqTx+6eOt1U2rQEOVWS/jn5Ic4C9K95s=; b=mhutDrCHHMqYsgPqpKes0Ble4SlrId7mgHooJ066r4ztu6Mo1IxIBtg2govjnnWJcn 0EymAmV71uBwFTka9NgFUxBwz8Gm/0Gy7YV7jPr1AA23BWzwLwDws4w3Lzx8vGy/szpO B21lJtNvkyObSW1967KoWquOy6AzPWW+Avu+zQBuEq4GhSgOPhkZ5+C8ipLcVyPUW84A LNvYP6lGZDlX9Q9EO6py8iIa+//5XgQ7jfMJkMdLMwnyKYIAakcXbKfd6dbrGfTgKdPX eACPPN5PtCjtDYEcVLq5AgPkArhpwHLl4AmlJOUT6zO9lTxkA2dqJqgAVr+NHZomP4BX 1ktw== X-Gm-Message-State: AN3rC/7BVOwFaDnqmWEK5YkqSydDxfyXy4/NjhPJZt715NKA95YOOGgI wzXVgm0Ub7zEYg== X-Received: by 10.84.168.131 with SMTP id f3mr28999633plb.160.1492987292036; Sun, 23 Apr 2017 15:41:32 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Mon, 24 Apr 2017 07:40:55 +0900 Message-Id: <565b9678ec7335762a290afce68f7062bdaf0ce9.1492986468.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::241 Subject: [Qemu-devel] [PATCH v2 7/9] migration: Add VMSTATE_STRUCT_2DARRAY() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , "Tim \\'mithro\\' Ansell" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For openrisc we implement tlb state as a 2d array of tlb entry structs. This is added to allow easy storing of state of 2d arrays. Signed-off-by: Stafford Horne --- include/migration/vmstate.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index f2dbf84..9b7dcdc 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -499,6 +499,17 @@ extern const VMStateInfo vmstate_info_qtailq; .offset =3D vmstate_offset_array(_state, _field, _type, _num),\ } =20 +#define VMSTATE_STRUCT_2DARRAY_TEST(_field, _state, _n1, _n2, _test, _vers= ion, _vmsd, _type) { \ + .name =3D (stringify(_field)), = \ + .num =3D (_n1) * (_n2), = \ + .field_exists =3D (_test), = \ + .version_id =3D (_version), = \ + .vmsd =3D &(_vmsd), = \ + .size =3D sizeof(_type), = \ + .flags =3D VMS_STRUCT|VMS_ARRAY, = \ + .offset =3D vmstate_offset_2darray(_state, _field, _type, _n1, _= n2),\ +} + #define VMSTATE_STRUCT_VARRAY_UINT8(_field, _state, _field_num, _version, = _vmsd, _type) { \ .name =3D (stringify(_field)), \ .num_offset =3D vmstate_offset_value(_state, _field_num, uint8_t), \ @@ -746,6 +757,10 @@ extern const VMStateInfo vmstate_info_qtailq; VMSTATE_STRUCT_ARRAY_TEST(_field, _state, _num, NULL, _version, \ _vmsd, _type) =20 +#define VMSTATE_STRUCT_2DARRAY(_field, _state, _n1, _n2, _version, _vmsd, = _type) \ + VMSTATE_STRUCT_2DARRAY_TEST(_field, _state, _n1, _n2, NULL, _version, = \ + _vmsd, _type) + #define VMSTATE_BUFFER_UNSAFE_INFO(_field, _state, _version, _info, _size)= \ VMSTATE_BUFFER_UNSAFE_INFO_TEST(_field, _state, NULL, _version, _info,= \ _size) --=20 2.9.3 From nobody Thu May 2 19:20:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492987786763797.1066630784463; Sun, 23 Apr 2017 15:49:46 -0700 (PDT) Received: from localhost ([::1]:40865 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QK9-0006y5-9s for importer@patchew.org; Sun, 23 Apr 2017 18:49:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56076) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QCG-0000dY-0o for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2QCF-0000Zw-52 for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:36 -0400 Received: from mail-it0-x242.google.com ([2607:f8b0:4001:c0b::242]:35163) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d2QCF-0000Zi-0H for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:35 -0400 Received: by mail-it0-x242.google.com with SMTP id e132so11954256ite.2 for ; Sun, 23 Apr 2017 15:41:34 -0700 (PDT) Received: from localhost (z64.124-44-184.ppp.wakwak.ne.jp. [124.44.184.64]) by smtp.gmail.com with ESMTPSA id u23sm26944455pfd.63.2017.04.23.15.41.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 23 Apr 2017 15:41:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=/WxVRlFqoj0VwAzTSjI+wvFg6QSZBT3MxAFpX4osKMQ=; b=F/2BO85tOPy+rJgC0bF5Z2i4c/1yXYOTrYmS80jcr0p71KRmG8YPxSnBTgIGaFMhxG R7DE0WMXF0jdNvj0aXhNxlCzPklZ6txIWH4M/AoyWYG85ZF1qp5Q014+d3/CgUs/P4Jo fM3DaTrQiJLjzM2s8LEAbryPIAdXDoHNDXcxVIgh8Bq9MB5cXm8NouznOovBF0ezg+kJ Xof4Xo18WnJV3wUEjiFH+ovbyc9muSXpjoU/2IoeVXfsio4uyomRpWzrdFdkSR3FsPvC RmuwQ/8hp0bRYUsAdEYdgUonk54LCii07YN/XBku7NgPFs0ICGH2cMU6E02/nuVRWjdO YEMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=/WxVRlFqoj0VwAzTSjI+wvFg6QSZBT3MxAFpX4osKMQ=; b=miuQ/AHvdpwqBw9cAzKS2aSH2w/21unhnxo8ePefuptZgArUuciRkTnXBDWLRycJsC xDYZ6U0SKeI+dTls9KCVabm0824HTQ/lYUf0Wlr8UxjkSGZRXVDySk36418v8UZzyEv5 5r6N6+B4HPFeR9A1iVHEWH+Nbyn3Eub3sjp1Ka78r1q+11No5USlF0ra8bZWeBDJVDV3 t5bD7AE9g906P2FDfLEJZ0YzHGEaXD9bgtH2DZ+Olm7QTVMEH2QTwfnkhwcY776XYRE4 9D6ca9AO8wrrcSynYxBMsvl8yWDZiuce5B39+bifCs0E6zXaJC6DlRMlVHVU4CXzC+BK zB9Q== X-Gm-Message-State: AN3rC/7M3w2iN9nOE23eIvJ7kxFlll1j0rghdeKm6W6ibCdQyCvFjIbo TDKa9CWXBRbNbQ== X-Received: by 10.99.232.69 with SMTP id a5mr21969644pgk.167.1492987294301; Sun, 23 Apr 2017 15:41:34 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Mon, 24 Apr 2017 07:40:56 +0900 Message-Id: <76adf807304af127f81f0c11f29b610b059f3497.1492986468.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::242 Subject: [Qemu-devel] [PATCH v2 8/9] target/openrisc: Implement full vmstate serialization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , "Tim \\'mithro\\' Ansell" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Previously serialization did not persist the tlb, timer, pic and other key state items. This meant snapshotting and restoring a running os would crash. After adding these I am able to take snapshots of a running linux os and restore at a later time. I am currently not trying to maintain capatibility with older versions as I do not believe this really worked before or anyone used it. Signed-off-by: Stafford Horne --- Changes since v1: o Added evbar o Bumped version on vmstate_env target/openrisc/machine.c | 73 +++++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 71 insertions(+), 2 deletions(-) diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 2bf71c3..a82be62 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -24,6 +24,63 @@ #include "hw/boards.h" #include "migration/cpu.h" =20 +static int env_post_load(void *opaque, int version_id) +{ + CPUOpenRISCState *env =3D opaque; + + /* Restore MMU handlers */ + if (env->sr & SR_DME) { + env->tlb->cpu_openrisc_map_address_data =3D + &cpu_openrisc_get_phys_data; + } else { + env->tlb->cpu_openrisc_map_address_data =3D + &cpu_openrisc_get_phys_nommu; + } + + if (env->sr & SR_IME) { + env->tlb->cpu_openrisc_map_address_code =3D + &cpu_openrisc_get_phys_code; + } else { + env->tlb->cpu_openrisc_map_address_code =3D + &cpu_openrisc_get_phys_nommu; + } + + + return 0; +} + +static const VMStateDescription vmstate_tlb_entry =3D { + .name =3D "tlb_entry", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(mr, OpenRISCTLBEntry), + VMSTATE_UINTTL(tr, OpenRISCTLBEntry), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_cpu_tlb =3D { + .name =3D "cpu_tlb", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT_2DARRAY(itlb, CPUOpenRISCTLBContext, + ITLB_WAYS, ITLB_SIZE, 0, + vmstate_tlb_entry, OpenRISCTLBEntry), + VMSTATE_STRUCT_2DARRAY(dtlb, CPUOpenRISCTLBContext, + DTLB_WAYS, DTLB_SIZE, 0, + vmstate_tlb_entry, OpenRISCTLBEntry), + VMSTATE_END_OF_LIST() + } +}; + +#define VMSTATE_CPU_TLB(_f, _s) \ + VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_tlb, CPUOpenRISCTLBContext) + + static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField *fi= eld) { CPUOpenRISCState *env =3D opaque; @@ -47,8 +104,9 @@ static const VMStateInfo vmstate_sr =3D { =20 static const VMStateDescription vmstate_env =3D { .name =3D "env", - .version_id =3D 5, - .minimum_version_id =3D 5, + .version_id =3D 6, + .minimum_version_id =3D 6, + .post_load =3D env_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), VMSTATE_UINTTL(pc, CPUOpenRISCState), @@ -79,9 +137,20 @@ static const VMStateDescription vmstate_env =3D { VMSTATE_UINT32(cpucfgr, CPUOpenRISCState), VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState), VMSTATE_UINT32(immucfgr, CPUOpenRISCState), + VMSTATE_UINT32(evbar, CPUOpenRISCState), VMSTATE_UINT32(esr, CPUOpenRISCState), VMSTATE_UINT32(fpcsr, CPUOpenRISCState), VMSTATE_UINT64(mac, CPUOpenRISCState), + + VMSTATE_CPU_TLB(tlb, CPUOpenRISCState), + + VMSTATE_TIMER_PTR(timer, CPUOpenRISCState), + VMSTATE_UINT32(ttmr, CPUOpenRISCState), + VMSTATE_UINT32(ttcr, CPUOpenRISCState), + + VMSTATE_UINT32(picmr, CPUOpenRISCState), + VMSTATE_UINT32(picsr, CPUOpenRISCState), + VMSTATE_END_OF_LIST() } }; --=20 2.9.3 From nobody Thu May 2 19:20:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492987405650334.29280362636973; Sun, 23 Apr 2017 15:43:25 -0700 (PDT) Received: from localhost ([::1]:40835 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QE0-0001rB-7w for importer@patchew.org; Sun, 23 Apr 2017 18:43:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56111) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2QCI-0000g3-Ml for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2QCH-0000cd-Rf for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:38 -0400 Received: from mail-io0-x244.google.com ([2607:f8b0:4001:c06::244]:36516) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d2QCH-0000cF-NT for qemu-devel@nongnu.org; Sun, 23 Apr 2017 18:41:37 -0400 Received: by mail-io0-x244.google.com with SMTP id x86so43372320ioe.3 for ; Sun, 23 Apr 2017 15:41:37 -0700 (PDT) Received: from localhost (z64.124-44-184.ppp.wakwak.ne.jp. [124.44.184.64]) by smtp.gmail.com with ESMTPSA id e24sm574846pfd.17.2017.04.23.15.41.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 23 Apr 2017 15:41:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=ZSRaRZ7Gpo/Gz2A0pzY4GEBaKCItT05/PrKrzTgD0LE=; b=ais6UksbiwFxMMzAuV4l87aOvWA+uyY0EOP2rre04dP0711QG7Lo/KBXNHrvrnhtnj ysicq9x4kv4V3mon/Ri1i3LCXqF/iFm8lUT9wZ2H+GF/YUku+SLYXFao/c0gXQermsd1 0e++DpY7qq3QIHjXSfgpYX8K4zuBVGulEVWv2i5KlsvoUn6aTKZeGGsNa47VNuXKhUi1 rlPa6WViXGeGkhub5HD25dc3IkLVHjvk5c67HS3Nm3jrbo4N4PW4G2GKhQeOIT5/G1qi dSnVCkDCtg6Glz3qoBtReewIl6jZVX3YVmP1JRX91vNTmy1qDLZXdC97Sfo44TfELJ3e uSWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=ZSRaRZ7Gpo/Gz2A0pzY4GEBaKCItT05/PrKrzTgD0LE=; b=RMz4aomg7+XdSejN3jX8jpC9OHhGca4XN0zXGV3bACB7y8oildGrjvxiuKdxGKHQ7N eGRxDilMez1NnoRq0sbORbgCTtAfmWzej0zr4c2FCQ8S492bFPS9yNtewYLHXKU1wxA/ Mvvst8kcToZtD1MzLxlMYexqO4eIhY3D5nZgrZCDQ5CEHqUz3RyzuRSulW3q4Wxci9Ix OfnPVDpYLEhvo2I8xUQs2jsDKVNn6wK81NFl/YX0r4wC+2Zh/PDjuG2/49fUKa4fFDIq jWpt0U8W9qkPDgBfFLRUUXRWggqSIaR3hnNhKvQQkdyRlU2pA6PzF/TTWS4EFJzmU4UH LmGQ== X-Gm-Message-State: AN3rC/4F9Tyktwmi7zwxu9O35ZU5QrxzEt+4/G8jVeSxXNmD0kTBAqT4 ydaHkhEq/FLSHA== X-Received: by 10.98.75.25 with SMTP id y25mr21735245pfa.157.1492987297064; Sun, 23 Apr 2017 15:41:37 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Mon, 24 Apr 2017 07:40:57 +0900 Message-Id: <5466599bfa21f03ae01741580c7e3fa0fdc6800d.1492986468.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::244 Subject: [Qemu-devel] [PATCH v2 9/9] target/openrisc: Remove duplicate features property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , "Tim \\'mithro\\' Ansell" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The features property has stored the exact same thing as the cpucfgr spr. Remove the feature enum and property as it is not needed. In order to preserve the behavior or keeping features accross reset this patch moves cpucfgr into the non reset region of the state struct. Since the cpucfgr is read only this means we only need to sset cpucfgr once during class init. Signed-off-by: Stafford Horne --- target/openrisc/cpu.c | 17 +++-------------- target/openrisc/cpu.h | 16 ++-------------- 2 files changed, 5 insertions(+), 28 deletions(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 6c1ed07..c9b3f22 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -52,7 +52,6 @@ static void openrisc_cpu_reset(CPUState *s) s->exception_index =3D -1; =20 cpu->env.upr =3D UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; - cpu->env.cpucfgr =3D CPUCFGR_OB32S | CPUCFGR_OF32S | CPUCFGR_NSGF; cpu->env.dmmucfgr =3D (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 <= < 2)); cpu->env.immucfgr =3D (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 <= < 2)); =20 @@ -65,12 +64,6 @@ static void openrisc_cpu_reset(CPUState *s) #endif } =20 -static inline void set_feature(OpenRISCCPU *cpu, int feature) -{ - cpu->feature |=3D feature; - cpu->env.cpucfgr =3D cpu->feature; -} - static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -132,19 +125,15 @@ static void or1200_initfn(Object *obj) { OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 - set_feature(cpu, OPENRISC_FEATURE_NSGF); - set_feature(cpu, OPENRISC_FEATURE_OB32S); - set_feature(cpu, OPENRISC_FEATURE_OF32S); - set_feature(cpu, OPENRISC_FEATURE_EVBAR); + cpu->env.cpucfgr =3D CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | + CPUCFGR_EVBARP; } =20 static void openrisc_any_initfn(Object *obj) { OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 - set_feature(cpu, OPENRISC_FEATURE_NSGF); - set_feature(cpu, OPENRISC_FEATURE_OB32S); - set_feature(cpu, OPENRISC_FEATURE_EVBAR); + cpu->env.cpucfgr =3D CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP; } =20 typedef struct OpenRISCCPUInfo { diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index e159b22..938ccc3 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -196,18 +196,6 @@ enum { SR_SCE =3D (1 << 17), }; =20 -/* OpenRISC Hardware Capabilities */ -enum { - OPENRISC_FEATURE_NSGF =3D (15 << 0), - OPENRISC_FEATURE_CGF =3D (1 << 4), - OPENRISC_FEATURE_OB32S =3D (1 << 5), - OPENRISC_FEATURE_OB64S =3D (1 << 6), - OPENRISC_FEATURE_OF32S =3D (1 << 7), - OPENRISC_FEATURE_OF64S =3D (1 << 8), - OPENRISC_FEATURE_OV64S =3D (1 << 9), - OPENRISC_FEATURE_EVBAR =3D (1 << 12), -}; - /* Tick Timer Mode Register */ enum { TTMR_TP =3D (0xfffffff), @@ -292,7 +280,6 @@ typedef struct CPUOpenRISCState { uint32_t sr; /* Supervisor register, without SR_{F,CY,OV}= */ uint32_t vr; /* Version register */ uint32_t upr; /* Unit presence register */ - uint32_t cpucfgr; /* CPU configure register */ uint32_t dmmucfgr; /* DMMU configure register */ uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ @@ -311,6 +298,8 @@ typedef struct CPUOpenRISCState { CPU_COMMON =20 /* Fields from here on are preserved across CPU reset. */ + uint32_t cpucfgr; /* CPU configure register */ + #ifndef CONFIG_USER_ONLY CPUOpenRISCTLBContext * tlb; =20 @@ -337,7 +326,6 @@ typedef struct OpenRISCCPU { =20 CPUOpenRISCState env; =20 - uint32_t feature; /* CPU Capabilities */ } OpenRISCCPU; =20 static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env) --=20 2.9.3