From nobody Tue Nov 18 10:40:12 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1609587017; cv=none; d=zohomail.com; s=zohoarc; b=jV04mUgDpAFLkWs7QNQx+lbBWWYU4wWGZuDvOA5aP4z4AR7bnTnaQ+PtoiDJ3IguCX863GTCATUwCR3QUzu3M2VxoC5/aT5HXR+E9uJ+I9la056agEOCKYCGjbR2sV7TcnztdJoGtZBfX0w18tfwkK7NwvD/GYkpTdRA2nXI5xw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609587017; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=wT66r+Q7+KutwCfpXIPrxcK4klP57N2Dhg4YF+7Y2zs=; b=lYVxtfRe64ePr1VmsRHBAYZTzBKtIw+sTP8dltqP/SXK/Or+9GHyPj3KthmQ9sp5tqWEXexwpN9Ch/hzIFu9cWqiL3tjWSgDFgrHlu+nwaNHHUmn93Zzk6hw79QC0ziH+69IGOxy8rDKGimTbWdVOcbmpUgf/xZzqiow7NHA3Zs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1609587017980315.52940319276354; Sat, 2 Jan 2021 03:30:17 -0800 (PST) Received: from localhost ([::1]:39484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kvf6u-0004sB-Ps for importer@patchew.org; Sat, 02 Jan 2021 06:30:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33336) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kverC-00013D-DV for qemu-devel@nongnu.org; Sat, 02 Jan 2021 06:14:02 -0500 Received: from zero.eik.bme.hu ([152.66.115.2]:56516) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kver2-00079e-T6 for qemu-devel@nongnu.org; Sat, 02 Jan 2021 06:14:02 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 16182747611; Sat, 2 Jan 2021 12:13:32 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 37A82747637; Sat, 2 Jan 2021 12:13:30 +0100 (CET) Message-Id: In-Reply-To: References: Subject: [PATCH 22/24] vt82c686: QOM-ify superio related functionality Date: Sat, 02 Jan 2021 11:43:35 +0100 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: BALATON Zoltan From: BALATON Zoltan via Content-Type: text/plain; charset="utf-8" Collect superio functionality and its controlling config registers handling in an abstract VIA_SUPERIO class that is a subclass of ISA_SUPERIO and put vt82c686b specific parts in a subclass of this abstract class. Signed-off-by: BALATON Zoltan --- hw/isa/vt82c686.c | 240 ++++++++++++++++++++++++-------------- include/hw/isa/vt82c686.h | 1 - 2 files changed, 150 insertions(+), 91 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 26db1a18e2..a755896b8e 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -249,12 +249,21 @@ static const TypeInfo vt8231_pm_info =3D { }; =20 =20 -typedef struct SuperIOConfig { +#define TYPE_VIA_SUPERIO "via-superio" +OBJECT_DECLARE_SIMPLE_TYPE(ViaSuperIOState, VIA_SUPERIO) + +struct ViaSuperIOState { + ISASuperIODevice superio; uint8_t regs[0x100]; + const MemoryRegionOps *io_ops; MemoryRegion io; - ISASuperIODevice *superio; MemoryRegion *serial_io[SUPERIO_MAX_SERIAL_PORTS]; -} SuperIOConfig; +}; + +static inline void via_superio_io_enable(ViaSuperIOState *s, bool enable) +{ + memory_region_set_enabled(&s->io, enable); +} =20 static MemoryRegion *find_subregion(ISADevice *d, MemoryRegion *parent, int offs) @@ -270,10 +279,76 @@ static MemoryRegion *find_subregion(ISADevice *d, Mem= oryRegion *parent, return mr; } =20 -static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data, - unsigned size) +static void via_superio_realize(DeviceState *d, Error **errp) +{ + ViaSuperIOState *s =3D VIA_SUPERIO(d); + ISASuperIOClass *ic =3D ISA_SUPERIO_GET_CLASS(s); + int i; + + assert(s->io_ops); + ic->parent_realize(d, errp); + if (*errp) { + return; + } + /* Grab io regions of serial devices so we can control them */ + for (i =3D 0; i < ic->serial.count; i++) { + ISADevice *sd =3D s->superio.serial[i]; + MemoryRegion *io =3D isa_address_space_io(sd); + MemoryRegion *mr =3D find_subregion(sd, io, sd->ioport_id); + if (!mr) { + error_setg(errp, "Could not get io region for serial %d", i); + return; + } + s->serial_io[i] =3D mr; + } + + memory_region_init_io(&s->io, OBJECT(d), s->io_ops, s, "via-superio", = 2); + memory_region_set_enabled(&s->io, false); + /* The floppy also uses 0x3f0 and 0x3f1 but this seems to work anyway = */ + memory_region_add_subregion(isa_address_space_io(ISA_DEVICE(s)), 0x3f0, + &s->io); +} + +static uint64_t via_superio_cfg_read(void *opaque, hwaddr addr, unsigned s= ize) +{ + ViaSuperIOState *sc =3D opaque; + uint8_t idx =3D sc->regs[0]; + uint8_t val =3D sc->regs[idx]; + + if (addr =3D=3D 0) { + return idx; + } + if (addr =3D=3D 1 && idx =3D=3D 0) { + val =3D 0; /* reading reg 0 where we store index value */ + } + trace_via_superio_read(idx, val); + return val; +} + +static void via_superio_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ISASuperIOClass *sc =3D ISA_SUPERIO_CLASS(klass); + + sc->parent_realize =3D dc->realize; + dc->realize =3D via_superio_realize; +} + +static const TypeInfo via_superio_info =3D { + .name =3D TYPE_VIA_SUPERIO, + .parent =3D TYPE_ISA_SUPERIO, + .instance_size =3D sizeof(ViaSuperIOState), + .class_size =3D sizeof(ISASuperIOClass), + .class_init =3D via_superio_class_init, + .abstract =3D true, +}; + +#define TYPE_VT82C686B_SUPERIO "vt82c686b-superio" + +static void vt82c686b_superio_cfg_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) { - SuperIOConfig *sc =3D opaque; + ViaSuperIOState *sc =3D opaque; uint8_t idx =3D sc->regs[0]; =20 if (addr =3D=3D 0) { /* config index register */ @@ -295,29 +370,29 @@ static void superio_cfg_write(void *opaque, hwaddr ad= dr, uint64_t data, case 0xfd ... 0xff: /* ignore write to read only registers */ return; - case 0xe2: + case 0xe2: /* Function select */ { data &=3D 0x1f; if (data & BIT(2)) { /* Serial port 1 enable */ - ISADevice *dev =3D sc->superio->serial[0]; + ISADevice *dev =3D sc->superio.serial[0]; if (!memory_region_is_mapped(sc->serial_io[0])) { memory_region_add_subregion(isa_address_space_io(dev), dev->ioport_id, sc->serial_io[= 0]); } } else { - MemoryRegion *io =3D isa_address_space_io(sc->superio->serial[= 0]); + MemoryRegion *io =3D isa_address_space_io(sc->superio.serial[0= ]); if (memory_region_is_mapped(sc->serial_io[0])) { memory_region_del_subregion(io, sc->serial_io[0]); } } if (data & BIT(3)) { /* Serial port 2 enable */ - ISADevice *dev =3D sc->superio->serial[1]; + ISADevice *dev =3D sc->superio.serial[1]; if (!memory_region_is_mapped(sc->serial_io[1])) { memory_region_add_subregion(isa_address_space_io(dev), dev->ioport_id, sc->serial_io[= 1]); } } else { - MemoryRegion *io =3D isa_address_space_io(sc->superio->serial[= 1]); + MemoryRegion *io =3D isa_address_space_io(sc->superio.serial[1= ]); if (memory_region_is_mapped(sc->serial_io[1])) { memory_region_del_subregion(io, sc->serial_io[1]); } @@ -327,7 +402,7 @@ static void superio_cfg_write(void *opaque, hwaddr addr= , uint64_t data, case 0xe7: /* Serial port 1 io base address */ { data &=3D 0xfe; - sc->superio->serial[0]->ioport_id =3D data << 2; + sc->superio.serial[0]->ioport_id =3D data << 2; if (memory_region_is_mapped(sc->serial_io[0])) { memory_region_set_address(sc->serial_io[0], data << 2); } @@ -336,7 +411,7 @@ static void superio_cfg_write(void *opaque, hwaddr addr= , uint64_t data, case 0xe8: /* Serial port 2 io base address */ { data &=3D 0xfe; - sc->superio->serial[1]->ioport_id =3D data << 2; + sc->superio.serial[1]->ioport_id =3D data << 2; if (memory_region_is_mapped(sc->serial_io[1])) { memory_region_set_address(sc->serial_io[1], data << 2); } @@ -350,25 +425,9 @@ static void superio_cfg_write(void *opaque, hwaddr add= r, uint64_t data, sc->regs[idx] =3D data; } =20 -static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size) -{ - SuperIOConfig *sc =3D opaque; - uint8_t idx =3D sc->regs[0]; - uint8_t val =3D sc->regs[idx]; - - if (addr =3D=3D 0) { - return idx; - } - if (addr =3D=3D 1 && idx =3D=3D 0) { - val =3D 0; /* reading reg 0 where we store index value */ - } - trace_via_superio_read(idx, val); - return val; -} - -static const MemoryRegionOps superio_cfg_ops =3D { - .read =3D superio_cfg_read, - .write =3D superio_cfg_write, +static const MemoryRegionOps vt82c686b_superio_cfg_ops =3D { + .read =3D via_superio_cfg_read, + .write =3D vt82c686b_superio_cfg_write, .endianness =3D DEVICE_NATIVE_ENDIAN, .impl =3D { .min_access_size =3D 1, @@ -376,13 +435,66 @@ static const MemoryRegionOps superio_cfg_ops =3D { }, }; =20 +static void vt82c686b_superio_reset(DeviceState *dev) +{ + ViaSuperIOState *s =3D VIA_SUPERIO(dev); + + memset(s->regs, 0, sizeof(s->regs)); + /* Device ID */ + vt82c686b_superio_cfg_write(s, 0, 0xe0, 1); + vt82c686b_superio_cfg_write(s, 1, 0x3c, 1); + /* Function select - all disabled */ + vt82c686b_superio_cfg_write(s, 0, 0xe2, 1); + vt82c686b_superio_cfg_write(s, 1, 0x03, 1); + /* Floppy ctrl base addr */ + vt82c686b_superio_cfg_write(s, 0, 0xe3, 1); + vt82c686b_superio_cfg_write(s, 1, 0xfc, 1); + /* Parallel port base addr */ + vt82c686b_superio_cfg_write(s, 0, 0xe6, 1); + vt82c686b_superio_cfg_write(s, 1, 0xde, 1); + /* Serial port 1 base addr */ + vt82c686b_superio_cfg_write(s, 0, 0xe7, 1); + vt82c686b_superio_cfg_write(s, 1, 0xfe, 1); + /* Serial port 2 base addr */ + vt82c686b_superio_cfg_write(s, 0, 0xe8, 1); + vt82c686b_superio_cfg_write(s, 1, 0xbe, 1); + + vt82c686b_superio_cfg_write(s, 0, 0, 1); +} + +static void vt82c686b_superio_init(Object *obj) +{ + VIA_SUPERIO(obj)->io_ops =3D &vt82c686b_superio_cfg_ops; +} + +static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ISASuperIOClass *sc =3D ISA_SUPERIO_CLASS(klass); + + dc->reset =3D vt82c686b_superio_reset; + sc->serial.count =3D 2; + sc->parallel.count =3D 1; + sc->ide.count =3D 0; /* emulated by via-ide */ + sc->floppy.count =3D 1; +} + +static const TypeInfo vt82c686b_superio_info =3D { + .name =3D TYPE_VT82C686B_SUPERIO, + .parent =3D TYPE_VIA_SUPERIO, + .instance_size =3D sizeof(ViaSuperIOState), + .instance_init =3D vt82c686b_superio_init, + .class_size =3D sizeof(ISASuperIOClass), + .class_init =3D vt82c686b_superio_class_init, +}; + =20 OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA) =20 struct VT82C686BISAState { PCIDevice dev; qemu_irq cpu_intr; - SuperIOConfig superio_cfg; + ViaSuperIOState *via_sio; }; =20 static void via_isa_request_i8259_irq(void *opaque, int irq, int level) @@ -400,7 +512,7 @@ static void vt82c686b_write_config(PCIDevice *d, uint32= _t addr, pci_default_write_config(d, addr, val, len); if (addr =3D=3D 0x85) { /* BIT(1): enable or disable superio config io ports */ - memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1)); + via_superio_io_enable(s->via_sio, val & BIT(1)); } } =20 @@ -432,13 +544,6 @@ static void vt82c686b_isa_reset(DeviceState *dev) pci_conf[0x5a] =3D 0x04; /* KBC/RTC Control*/ pci_conf[0x5f] =3D 0x04; pci_conf[0x77] =3D 0x10; /* GPIO Control 1/2/3/4 */ - - s->superio_cfg.regs[0xe0] =3D 0x3c; /* Device ID */ - s->superio_cfg.regs[0xe2] =3D 0x03; /* Function select */ - s->superio_cfg.regs[0xe3] =3D 0xfc; /* Floppy ctrl base addr */ - s->superio_cfg.regs[0xe6] =3D 0xde; /* Parallel port base addr */ - s->superio_cfg.regs[0xe7] =3D 0xfe; /* Serial port 1 base addr */ - s->superio_cfg.regs[0xe8] =3D 0xbe; /* Serial port 2 base addr */ } =20 static void vt82c686b_realize(PCIDevice *d, Error **errp) @@ -447,7 +552,6 @@ static void vt82c686b_realize(PCIDevice *d, Error **err= p) DeviceState *dev =3D DEVICE(d); ISABus *isa_bus; qemu_irq *isa_irq; - ISASuperIOClass *ic; int i; =20 qdev_init_gpio_out(dev, &s->cpu_intr, 1); @@ -457,9 +561,8 @@ static void vt82c686b_realize(PCIDevice *d, Error **err= p) isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq)); i8254_pit_init(isa_bus, 0x40, 0, NULL); i8257_dma_init(isa_bus, 0); - s->superio_cfg.superio =3D ISA_SUPERIO(isa_create_simple(isa_bus, - TYPE_VT82C686B_SUPER= IO)); - ic =3D ISA_SUPERIO_GET_CLASS(s->superio_cfg.superio); + s->via_sio =3D VIA_SUPERIO(isa_create_simple(isa_bus, + TYPE_VT82C686B_SUPERIO)); mc146818_rtc_init(isa_bus, 2000, NULL); =20 for (i =3D 0; i < PCI_CONFIG_HEADER_SIZE; i++) { @@ -467,31 +570,6 @@ static void vt82c686b_realize(PCIDevice *d, Error **er= rp) d->wmask[i] =3D 0; } } - - memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops, - &s->superio_cfg, "superio_cfg", 2); - memory_region_set_enabled(&s->superio_cfg.io, false); - /* - * The floppy also uses 0x3f0 and 0x3f1. - * But we do not emulate a floppy, so just set it here. - */ - memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, - &s->superio_cfg.io); - - /* Grab io regions of serial devices so we can control them */ - for (i =3D 0; i < ic->serial.count; i++) { - ISADevice *sd =3D s->superio_cfg.superio->serial[i]; - MemoryRegion *io =3D isa_address_space_io(sd); - MemoryRegion *mr =3D find_subregion(sd, io, sd->ioport_id); - if (!mr) { - error_setg(errp, "Could not get io region for serial %d", i); - return; - } - s->superio_cfg.serial_io[i] =3D mr; - if (memory_region_is_mapped(mr)) { - memory_region_del_subregion(io, mr); - } - } } =20 static void via_class_init(ObjectClass *klass, void *data) @@ -527,32 +605,14 @@ static const TypeInfo via_info =3D { }; =20 =20 -static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) -{ - ISASuperIOClass *sc =3D ISA_SUPERIO_CLASS(klass); - - sc->serial.count =3D 2; - sc->parallel.count =3D 1; - sc->ide.count =3D 0; - sc->floppy.count =3D 1; -} - -static const TypeInfo via_superio_info =3D { - .name =3D TYPE_VT82C686B_SUPERIO, - .parent =3D TYPE_ISA_SUPERIO, - .instance_size =3D sizeof(ISASuperIODevice), - .class_size =3D sizeof(ISASuperIOClass), - .class_init =3D vt82c686b_superio_class_init, -}; - - static void vt82c686b_register_types(void) { type_register_static(&via_pm_info); type_register_static(&vt82c686b_pm_info); type_register_static(&vt8231_pm_info); - type_register_static(&via_info); type_register_static(&via_superio_info); + type_register_static(&vt82c686b_superio_info); + type_register_static(&via_info); } =20 type_init(vt82c686b_register_types) diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h index 9b6d610e83..0692b9a527 100644 --- a/include/hw/isa/vt82c686.h +++ b/include/hw/isa/vt82c686.h @@ -2,7 +2,6 @@ #define HW_VT82C686_H =20 #define TYPE_VT82C686B_ISA "vt82c686b-isa" -#define TYPE_VT82C686B_SUPERIO "vt82c686b-superio" #define TYPE_VT82C686B_PM "vt82c686b-pm" #define TYPE_VT8231_PM "vt8231-pm" #define TYPE_VIA_AC97 "via-ac97" --=20 2.21.3