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IronPort-SDR: gzy9iNYFddtqeyYnTOAIqiUQ9WCu3nYP9qv3DZSz+PyEpjOtI9OpmsFCOpuM0sMntXTReflH15 DdoGs1aFtsoNIvFo7lpQhhwsXUaM/6b9hwnDfL/X7ErZVG8AtMmyBt/ykwsTpRMP7Y4Z2VOgGC +EP/55XM9Y3PfebuVkiJNa8p98Z5Fzl0QdvHjerzfHBMERdYS3CaR+aeYGiBY1Y5lWltFoKifg JKq1DY4zF3DtHlaPXXztgfZfXizB3Wq8lSEEnjH4zB3R/AgpfTS2MhTHDQzAZrYPmAhbHPoM4e E8c= X-IronPort-AV: E=Sophos;i="5.77,408,1596470400"; d="scan'208";a="151960182" IronPort-SDR: izfu8yR+CLTCf0+zAqdC9ltaSufhP6UBPEw9F/ECVp8ivsxNZca8AN7o91ebhrorAWNHDa2dMB /7Tt/tt9+eiE76+MJjFgrFmSlkMNa7RpRDCEfl0LK/LMJ5jqVfpV5rTEBuFrRR7F2z+PoadfYq bGbGI8GVKP+teMtyTB1oG//VOOYS3Qou2U56v71bU1TDUZ18ty2WR6xA2srFLVyw3QOHc94Fax /OUMXSUhcAHiW+R/pWkO0SjkfziuCVQg8WrdZZKszimK8C6irmiBOHz2qbWzqD3hX7/UEoiSry SqMmBMUnDgfTOKaPX601eRyo IronPort-SDR: XzTyfU6IdPRk8is2Opukr4FD1ubWonGCfqPowhLY67Hq5q8wb+BRjZvC06hJ0d4QobB3/xNV2j 6RM6SFbx7dmxFZorA/N5juzmKolh35xgLfEDNghR8AXfB3C6SF5SohL3Z8J37YBwTHAltcc9vw XfiYeCmpb1vyqC9We7W1U87vNPCqKvLriuHg8LJCIdsF3dmkyqr7Q35hRUv1xEoMs93fcTAOYx kb9Yjc2N0nEcpVKP6kKb+lwe8DaK90VU5dlfqUFmp71+u15/CPnfpWq18aK17OpRKConLiznLG xA4= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 16/16] target/riscv: Consolidate *statush registers Date: Fri, 23 Oct 2020 08:33:56 -0700 Message-Id: X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=558518344=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/23 11:44:34 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 24 ++++++++++++++--------- target/riscv/cpu_bits.h | 14 ++----------- target/riscv/cpu.c | 7 ++----- target/riscv/cpu_helper.c | 41 ++++++++++----------------------------- target/riscv/csr.c | 15 ++++++++------ target/riscv/op_helper.c | 11 ++++------- 6 files changed, 42 insertions(+), 70 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8bde15544d..de864a947b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -150,9 +150,11 @@ struct CPURISCVState { target_ulong resetvec; =20 target_ulong mhartid; - target_ulong mstatus; - /* This is RV32 only */ - target_ulong mstatush; + /* + * For RV32 this is 32-bit mstatus and 32-bit mstatush. + * For RV64 this is a 64-bit mstatus. + */ + uint64_t mstatus; =20 target_ulong mip; =20 @@ -187,15 +189,17 @@ struct CPURISCVState { uint64_t htimedelta; =20 /* Virtual CSRs */ - target_ulong vsstatus; target_ulong vstvec; target_ulong vsscratch; target_ulong vsepc; target_ulong vscause; target_ulong vstval; target_ulong vsatp; - /* This is RV32 only */ - target_ulong vsstatush; + /* + * For RV32 this is 32-bit mstatus and 32-bit mstatush. + * For RV64 this is a 64-bit mstatus. + */ + uint64_t vsstatus; =20 target_ulong mtval2; target_ulong mtinst; @@ -207,9 +211,11 @@ struct CPURISCVState { target_ulong scause_hs; target_ulong stval_hs; target_ulong satp_hs; - target_ulong mstatus_hs; - /* This is RV32 only */ - target_ulong mstatush_hs; + /* + * For RV32 this is 32-bit mstatus and 32-bit mstatush. + * For RV64 this is a 64-bit mstatus. + */ + uint64_t mstatus_hs; =20 target_ulong scounteren; target_ulong mcounteren; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index db46739b1c..4b75d2766e 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -381,19 +381,9 @@ #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ -#if defined(TARGET_RISCV64) -#define MSTATUS_GVA 0x4000000000ULL -#define MSTATUS_MPV 0x8000000000ULL -#elif defined(TARGET_RISCV32) -#define MSTATUS_GVA 0x00000040 -#define MSTATUS_MPV 0x00000080 -#endif =20 -#ifdef TARGET_RISCV32 -# define MSTATUS_MPV_ISSET(env) get_field(env->mstatush, MSTATUS_MPV) -#else -# define MSTATUS_MPV_ISSET(env) get_field(env->mstatus, MSTATUS_MPV) -#endif +#define MSTATUS_GVA 0x4000000000ULL +#define MSTATUS_MPV 0x8000000000ULL =20 #define MSTATUS64_UXL 0x0000000300000000ULL #define MSTATUS64_SXL 0x0000000C00000000ULL diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c77687ccb2..74c5ac5777 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -245,13 +245,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *= f, int flags) qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); - if (riscv_cpu_is_32bit(env)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstat= ush); - } + qemu_fprintf(f, " %s %016lx\n", "mstatus ", env->mstatus); if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatu= s); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vssta= tus); + qemu_fprintf(f, " %s %016lx\n", "vsstatus ", env->vsstatus); } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 62aed24feb..b109529ace 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -110,27 +110,19 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) =20 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { - target_ulong mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | - MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; + uint64_t mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | + MSTATUS64_UXL; bool current_virt =3D riscv_cpu_virt_enabled(env); =20 g_assert(riscv_has_ext(env, RVH)); =20 -#if defined(TARGET_RISCV64) - mstatus_mask |=3D MSTATUS64_UXL; -#endif - if (current_virt) { /* Current V=3D1 and we are about to change to V=3D0 */ env->vsstatus =3D env->mstatus & mstatus_mask; env->mstatus &=3D ~mstatus_mask; env->mstatus |=3D env->mstatus_hs; =20 - if (riscv_cpu_is_32bit(env)) { - env->vsstatush =3D env->mstatush; - env->mstatush |=3D env->mstatush_hs; - } - env->vstvec =3D env->stvec; env->stvec =3D env->stvec_hs; =20 @@ -154,11 +146,6 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) env->mstatus &=3D ~mstatus_mask; env->mstatus |=3D env->vsstatus; =20 - if (riscv_cpu_is_32bit(env)) { - env->mstatush_hs =3D env->mstatush; - env->mstatush |=3D env->vsstatush; - } - env->stvec_hs =3D env->stvec; env->stvec =3D env->vstvec; =20 @@ -729,7 +716,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV) && - MSTATUS_MPV_ISSET(env)) { + get_field(env->mstatus, MSTATUS_MPV)) { riscv_cpu_set_two_stage_lookup(env, true); } =20 @@ -801,7 +788,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV) && - MSTATUS_MPV_ISSET(env)) { + get_field(env->mstatus, MSTATUS_MPV)) { riscv_cpu_set_two_stage_lookup(env, false); } =20 @@ -864,7 +851,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; bool force_hs_execp =3D riscv_cpu_force_hs_excep_enabled(env); - target_ulong s; + uint64_t s; =20 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide * so we mask off the MSB and separate into trap type and cause. @@ -997,18 +984,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_cpu_virt_enabled(env)) { riscv_cpu_swap_hypervisor_regs(env); } - if (riscv_cpu_is_32bit(env)) { - env->mstatush =3D set_field(env->mstatush, MSTATUS_MPV, - riscv_cpu_virt_enabled(env)); - if (riscv_cpu_virt_enabled(env) && tval) { - env->mstatush =3D set_field(env->mstatush, MSTATUS_GVA= , 1); - } - } else { - env->mstatus =3D set_field(env->mstatus, MSTATUS_MPV, - riscv_cpu_virt_enabled(env)); - if (riscv_cpu_virt_enabled(env) && tval) { - env->mstatus =3D set_field(env->mstatus, MSTATUS_GVA, = 1); - } + env->mstatus =3D set_field(env->mstatus, MSTATUS_MPV, + riscv_cpu_virt_enabled(env)); + if (riscv_cpu_virt_enabled(env) && tval) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_GVA, 1); } =20 mtval2 =3D env->guest_phys_fault_addr; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b153cdfec3..7132a9bcd0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -473,8 +473,8 @@ static int validate_vm(CPURISCVState *env, target_ulong= vm) =20 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong mstatus =3D env->mstatus; - target_ulong mask =3D 0; + uint64_t mstatus =3D env->mstatus; + uint64_t mask =3D 0; int dirty; =20 /* flush tlb on mstatus fields that affect VM */ @@ -507,19 +507,22 @@ static int write_mstatus(CPURISCVState *env, int csrn= o, target_ulong val) =20 static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mstatush; + *val =3D env->mstatus >> 32; return 0; } =20 static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val) { - if ((val ^ env->mstatush) & (MSTATUS_MPV)) { + uint64_t val64 =3D (uint64_t) val << 32; + + if ((val64 ^ env->mstatus) & (MSTATUS_MPV)) { tlb_flush(env_cpu(env)); } =20 - val &=3D MSTATUS_MPV | MSTATUS_GVA; + val64 &=3D MSTATUS_MPV | MSTATUS_GVA; =20 - env->mstatush =3D val; + env->mstatus &=3D 0xFFFFFFFF; + env->mstatus |=3D val64; =20 return 0; } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 4ce73575a7..f9361e3af8 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -78,7 +78,8 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulon= g src, =20 target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) { - target_ulong prev_priv, prev_virt, mstatus; + target_ulong prev_priv, prev_virt; + uint64_t mstatus; =20 if (!(env->priv >=3D PRV_S)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); @@ -147,18 +148,14 @@ target_ulong helper_mret(CPURISCVState *env, target_u= long cpu_pc_deb) riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); } =20 - target_ulong mstatus =3D env->mstatus; + uint64_t mstatus =3D env->mstatus; target_ulong prev_priv =3D get_field(mstatus, MSTATUS_MPP); - target_ulong prev_virt =3D MSTATUS_MPV_ISSET(env); + target_ulong prev_virt =3D !!get_field(env->mstatus, MSTATUS_MPV); mstatus =3D set_field(mstatus, MSTATUS_MIE, get_field(mstatus, MSTATUS_MPIE)); mstatus =3D set_field(mstatus, MSTATUS_MPIE, 1); mstatus =3D set_field(mstatus, MSTATUS_MPP, PRV_U); -#ifdef TARGET_RISCV32 - env->mstatush =3D set_field(env->mstatush, MSTATUS_MPV, 0); -#else mstatus =3D set_field(mstatus, MSTATUS_MPV, 0); -#endif env->mstatus =3D mstatus; riscv_cpu_set_mode(env, prev_priv); =20 --=20 2.28.0