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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Jonathan Cameron , Fan Ni Subject: [PULL 47/63] hw/cxl/mbox: Pull the CCI definition out of the CXLDeviceState Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1699352637717100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jonathan Cameron Enables having multiple CCIs per devices. Each CCI (mailbox) has it's own state and command list, so they can't share a single structure. Signed-off-by: Jonathan Cameron Message-Id: <20231023160806.13206-4-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/cxl/cxl_device.h | 35 ++++++++++---- hw/cxl/cxl-device-utils.c | 31 +++++++++--- hw/cxl/cxl-mailbox-utils.c | 94 ++++++++++++++++++++++--------------- hw/mem/cxl_type3.c | 5 +- 4 files changed, 109 insertions(+), 56 deletions(-) diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index d7a2c4009e..779ca85319 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -111,12 +111,13 @@ typedef enum { CXL_MBOX_MAX =3D 0x17 } CXLRetCode; =20 +typedef struct CXLCCI CXLCCI; typedef struct cxl_device_state CXLDeviceState; struct cxl_cmd; typedef CXLRetCode (*opcode_handler)(const struct cxl_cmd *cmd, uint8_t *payload_in, size_t len_in, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxl_dstate); + CXLCCI *cci); struct cxl_cmd { const char *name; opcode_handler handler; @@ -140,6 +141,21 @@ typedef struct CXLEventLog { QSIMPLEQ_HEAD(, CXLEvent) events; } CXLEventLog; =20 +typedef struct CXLCCI { + const struct cxl_cmd (*cxl_cmd_set)[256]; + struct cel_log { + uint16_t opcode; + uint16_t effect; + } cel_log[1 << 16]; + size_t cel_size; + + size_t payload_max; + /* Pointer to device hosting the CCI */ + DeviceState *d; + /* Pointer to the device hosting the protocol conversion */ + DeviceState *intf; +} CXLCCI; + typedef struct cxl_device_state { MemoryRegion device_registers; =20 @@ -173,11 +189,6 @@ typedef struct cxl_device_state { uint32_t mbox_reg_state32[CXL_MAILBOX_REGISTERS_LENGTH / 4]; uint64_t mbox_reg_state64[CXL_MAILBOX_REGISTERS_LENGTH / 8]; }; - struct cel_log { - uint16_t opcode; - uint16_t effect; - } cel_log[1 << 16]; - size_t cel_size; }; =20 struct { @@ -196,10 +207,12 @@ typedef struct cxl_device_state { } CXLDeviceState; =20 /* Initialize the register block for a device */ -void cxl_device_register_block_init(Object *obj, CXLDeviceState *dev); +void cxl_device_register_block_init(Object *obj, CXLDeviceState *dev, + CXLCCI *cci); =20 +typedef struct CXLType3Dev CXLType3Dev; /* Set up default values for the register block */ -void cxl_device_register_init_common(CXLDeviceState *dev); +void cxl_device_register_init_t3(CXLType3Dev *ct3d); =20 /* * CXL 2.0 - 8.2.8.1 including errata F4 @@ -245,8 +258,9 @@ CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MEMORY_DEVICE, CXL_DEVICE_CAP_HDR1_OFFSET + CXL_DEVICE_CAP_REG_SIZE * 2) =20 -void cxl_initialize_mailbox(CXLDeviceState *cxl_dstate); -void cxl_process_mailbox(CXLDeviceState *cxl_dstate); +void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload= _max); +void cxl_init_cci(CXLCCI *cci, size_t payload_max); +void cxl_process_mailbox(CXLCCI *cci); =20 #define cxl_device_cap_init(dstate, reg, cap_id, ver) = \ do { = \ @@ -347,6 +361,7 @@ struct CXLType3Dev { AddressSpace hostpmem_as; CXLComponentState cxl_cstate; CXLDeviceState cxl_dstate; + CXLCCI cci; /* Primary PCI mailbox CCI */ =20 /* DOE */ DOECap doe_cdat; diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c index eb7195272e..327949a805 100644 --- a/hw/cxl/cxl-device-utils.c +++ b/hw/cxl/cxl-device-utils.c @@ -62,7 +62,14 @@ static uint64_t dev_reg_read(void *opaque, hwaddr offset= , unsigned size) =20 static uint64_t mailbox_reg_read(void *opaque, hwaddr offset, unsigned siz= e) { - CXLDeviceState *cxl_dstate =3D opaque; + CXLDeviceState *cxl_dstate; + CXLCCI *cci =3D opaque; + + if (object_dynamic_cast(OBJECT(cci->intf), TYPE_CXL_TYPE3)) { + cxl_dstate =3D &CXL_TYPE3(cci->intf)->cxl_dstate; + } else { + return 0; + } =20 switch (size) { case 1: @@ -123,7 +130,14 @@ static void mailbox_mem_writeq(uint64_t *reg_state, hw= addr offset, static void mailbox_reg_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - CXLDeviceState *cxl_dstate =3D opaque; + CXLDeviceState *cxl_dstate; + CXLCCI *cci =3D opaque; + + if (object_dynamic_cast(OBJECT(cci->intf), TYPE_CXL_TYPE3)) { + cxl_dstate =3D &CXL_TYPE3(cci->intf)->cxl_dstate; + } else { + return; + } =20 if (offset >=3D A_CXL_DEV_CMD_PAYLOAD) { memcpy(cxl_dstate->mbox_reg_state + offset, &value, size); @@ -143,7 +157,7 @@ static void mailbox_reg_write(void *opaque, hwaddr offs= et, uint64_t value, =20 if (ARRAY_FIELD_EX32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTR= L, DOORBELL)) { - cxl_process_mailbox(cxl_dstate); + cxl_process_mailbox(cci); } } =20 @@ -223,7 +237,8 @@ static const MemoryRegionOps caps_ops =3D { }, }; =20 -void cxl_device_register_block_init(Object *obj, CXLDeviceState *cxl_dstat= e) +void cxl_device_register_block_init(Object *obj, CXLDeviceState *cxl_dstat= e, + CXLCCI *cci) { /* This will be a BAR, so needs to be rounded up to pow2 for PCI spec = */ memory_region_init(&cxl_dstate->device_registers, obj, "device-registe= rs", @@ -233,7 +248,7 @@ void cxl_device_register_block_init(Object *obj, CXLDev= iceState *cxl_dstate) "cap-array", CXL_CAPS_SIZE); memory_region_init_io(&cxl_dstate->device, obj, &dev_ops, cxl_dstate, "device-status", CXL_DEVICE_STATUS_REGISTERS_LEN= GTH); - memory_region_init_io(&cxl_dstate->mailbox, obj, &mailbox_ops, cxl_dst= ate, + memory_region_init_io(&cxl_dstate->mailbox, obj, &mailbox_ops, cci, "mailbox", CXL_MAILBOX_REGISTERS_LENGTH); memory_region_init_io(&cxl_dstate->memory_device, obj, &mdev_ops, cxl_dstate, "memory device caps", @@ -284,8 +299,9 @@ static void mailbox_reg_init_common(CXLDeviceState *cxl= _dstate) =20 static void memdev_reg_init_common(CXLDeviceState *cxl_dstate) { } =20 -void cxl_device_register_init_common(CXLDeviceState *cxl_dstate) +void cxl_device_register_init_t3(CXLType3Dev *ct3d) { + CXLDeviceState *cxl_dstate =3D &ct3d->cxl_dstate; uint64_t *cap_h =3D cxl_dstate->caps_reg_state64; const int cap_count =3D 3; =20 @@ -303,7 +319,8 @@ void cxl_device_register_init_common(CXLDeviceState *cx= l_dstate) cxl_device_cap_init(cxl_dstate, MEMORY_DEVICE, 0x4000, 1); memdev_reg_init_common(cxl_dstate); =20 - cxl_initialize_mailbox(cxl_dstate); + cxl_initialize_mailbox_t3(&ct3d->cci, DEVICE(ct3d), + CXL_MAILBOX_MAX_PAYLOAD_SIZE); } =20 uint64_t cxl_device_get_timestamp(CXLDeviceState *cxl_dstate) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index e5ddce37c7..5484dfbbf1 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -73,8 +73,9 @@ enum { static CXLRetCode cmd_events_get_records(const struct cxl_cmd *cmd, uint8_t *payload_in, size_t len_i= n, uint8_t *payload_out, size_t *len= _out, - CXLDeviceState *cxlds) + CXLCCI *cci) { + CXLDeviceState *cxlds =3D &CXL_TYPE3(cci->d)->cxl_dstate; CXLGetEventPayload *pl; uint8_t log_type; int max_recs; @@ -102,8 +103,9 @@ static CXLRetCode cmd_events_clear_records(const struct= cxl_cmd *cmd, size_t len_in, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxlds) + CXLCCI *cci) { + CXLDeviceState *cxlds =3D &CXL_TYPE3(cci->d)->cxl_dstate; CXLClearEventPayload *pl; =20 pl =3D (CXLClearEventPayload *)payload_in; @@ -116,8 +118,9 @@ static CXLRetCode cmd_events_get_interrupt_policy(const= struct cxl_cmd *cmd, size_t len_in, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxlds) + CXLCCI *cci) { + CXLDeviceState *cxlds =3D &CXL_TYPE3(cci->d)->cxl_dstate; CXLEventInterruptPolicy *policy; CXLEventLog *log; =20 @@ -159,8 +162,9 @@ static CXLRetCode cmd_events_set_interrupt_policy(const= struct cxl_cmd *cmd, size_t len_in, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxlds) + CXLCCI *cci) { + CXLDeviceState *cxlds =3D &CXL_TYPE3(cci->d)->cxl_dstate; CXLEventInterruptPolicy *policy; CXLEventLog *log; =20 @@ -205,8 +209,9 @@ static CXLRetCode cmd_firmware_update_get_info(const st= ruct cxl_cmd *cmd, size_t len, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxl_dstate) + CXLCCI *cci) { + CXLDeviceState *cxl_dstate =3D &CXL_TYPE3(cci->d)->cxl_dstate; struct { uint8_t slots_supported; uint8_t slot_info; @@ -242,8 +247,9 @@ static CXLRetCode cmd_timestamp_get(const struct cxl_cm= d *cmd, size_t len_in, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxl_dstate) + CXLCCI *cci) { + CXLDeviceState *cxl_dstate =3D &CXL_TYPE3(cci->d)->cxl_dstate; uint64_t final_time =3D cxl_device_get_timestamp(cxl_dstate); =20 stq_le_p(payload_out, final_time); @@ -258,8 +264,10 @@ static CXLRetCode cmd_timestamp_set(const struct cxl_c= md *cmd, size_t len_in, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxl_dstate) + CXLCCI *cci) { + CXLDeviceState *cxl_dstate =3D &CXL_TYPE3(cci->d)->cxl_dstate; + cxl_dstate->timestamp.set =3D true; cxl_dstate->timestamp.last_set =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUA= L); =20 @@ -281,7 +289,7 @@ static CXLRetCode cmd_logs_get_supported(const struct c= xl_cmd *cmd, size_t len_in, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxl_dstate) + CXLCCI *cci) { struct { uint16_t entries; @@ -295,7 +303,7 @@ static CXLRetCode cmd_logs_get_supported(const struct c= xl_cmd *cmd, =20 supported_logs->entries =3D 1; supported_logs->log_entries[0].uuid =3D cel_uuid; - supported_logs->log_entries[0].size =3D 4 * cxl_dstate->cel_size; + supported_logs->log_entries[0].size =3D 4 * cci->cel_size; =20 *len_out =3D sizeof(*supported_logs); return CXL_MBOX_SUCCESS; @@ -307,7 +315,7 @@ static CXLRetCode cmd_logs_get_log(const struct cxl_cmd= *cmd, size_t len_in, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxl_dstate) + CXLCCI *cci) { struct { QemuUUID uuid; @@ -330,7 +338,7 @@ static CXLRetCode cmd_logs_get_log(const struct cxl_cmd= *cmd, * the only possible failure would be if the mailbox itself isn't big * enough. */ - if (get_log->offset + get_log->length > cxl_dstate->payload_size) { + if (get_log->offset + get_log->length > cci->payload_max) { return CXL_MBOX_INVALID_INPUT; } =20 @@ -341,8 +349,7 @@ static CXLRetCode cmd_logs_get_log(const struct cxl_cmd= *cmd, /* Store off everything to local variables so we can wipe out the payl= oad */ *len_out =3D get_log->length; =20 - memmove(payload_out, cxl_dstate->cel_log + get_log->offset, - get_log->length); + memmove(payload_out, cci->cel_log + get_log->offset, get_log->length); =20 return CXL_MBOX_SUCCESS; } @@ -353,7 +360,7 @@ static CXLRetCode cmd_identify_memory_device(const stru= ct cxl_cmd *cmd, size_t len_in, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxl_dstate) + CXLCCI *cci) { struct { char fw_revision[0x10]; @@ -372,9 +379,9 @@ static CXLRetCode cmd_identify_memory_device(const stru= ct cxl_cmd *cmd, uint8_t qos_telemetry_caps; } QEMU_PACKED *id; QEMU_BUILD_BUG_ON(sizeof(*id) !=3D 0x43); - - CXLType3Dev *ct3d =3D container_of(cxl_dstate, CXLType3Dev, cxl_dstate= ); + CXLType3Dev *ct3d =3D CXL_TYPE3(cci->d); CXLType3Class *cvc =3D CXL_TYPE3_GET_CLASS(ct3d); + CXLDeviceState *cxl_dstate =3D &ct3d->cxl_dstate; =20 if ((!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, CXL_CAPACITY_MULTIPLIER))= || (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))= ) { @@ -407,8 +414,9 @@ static CXLRetCode cmd_ccls_get_partition_info(const str= uct cxl_cmd *cmd, size_t len_in, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxl_dstate) + CXLCCI *cci) { + CXLDeviceState *cxl_dstate =3D &CXL_TYPE3(cci->d)->cxl_dstate; struct { uint64_t active_vmem; uint64_t active_pmem; @@ -442,13 +450,13 @@ static CXLRetCode cmd_ccls_get_lsa(const struct cxl_c= md *cmd, size_t len_in, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxl_dstate) + CXLCCI *cci) { struct { uint32_t offset; uint32_t length; } QEMU_PACKED *get_lsa; - CXLType3Dev *ct3d =3D container_of(cxl_dstate, CXLType3Dev, cxl_dstate= ); + CXLType3Dev *ct3d =3D CXL_TYPE3(cci->d); CXLType3Class *cvc =3D CXL_TYPE3_GET_CLASS(ct3d); uint32_t offset, length; =20 @@ -470,7 +478,7 @@ static CXLRetCode cmd_ccls_set_lsa(const struct cxl_cmd= *cmd, size_t len_in, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxl_dstate) + CXLCCI *cci) { struct set_lsa_pl { uint32_t offset; @@ -478,7 +486,7 @@ static CXLRetCode cmd_ccls_set_lsa(const struct cxl_cmd= *cmd, uint8_t data[]; } QEMU_PACKED; struct set_lsa_pl *set_lsa_payload =3D (void *)payload_in; - CXLType3Dev *ct3d =3D container_of(cxl_dstate, CXLType3Dev, cxl_dstate= ); + CXLType3Dev *ct3d =3D CXL_TYPE3(cci->d); CXLType3Class *cvc =3D CXL_TYPE3_GET_CLASS(ct3d); const size_t hdr_len =3D offsetof(struct set_lsa_pl, data); =20 @@ -507,7 +515,7 @@ static CXLRetCode cmd_media_get_poison_list(const struc= t cxl_cmd *cmd, size_t len_in, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxl_dstate) + CXLCCI *cci) { struct get_poison_list_pl { uint64_t pa; @@ -529,7 +537,7 @@ static CXLRetCode cmd_media_get_poison_list(const struc= t cxl_cmd *cmd, =20 struct get_poison_list_pl *in =3D (void *)payload_in; struct get_poison_list_out_pl *out =3D (void *)payload_out; - CXLType3Dev *ct3d =3D container_of(cxl_dstate, CXLType3Dev, cxl_dstate= ); + CXLType3Dev *ct3d =3D CXL_TYPE3(cci->d); uint16_t record_count =3D 0, i =3D 0; uint64_t query_start, query_length; CXLPoisonList *poison_list =3D &ct3d->poison_list; @@ -586,9 +594,9 @@ static CXLRetCode cmd_media_inject_poison(const struct = cxl_cmd *cmd, size_t len_in, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxl_dstate) + CXLCCI *cci) { - CXLType3Dev *ct3d =3D container_of(cxl_dstate, CXLType3Dev, cxl_dstate= ); + CXLType3Dev *ct3d =3D CXL_TYPE3(cci->d); CXLPoisonList *poison_list =3D &ct3d->poison_list; CXLPoison *ent; struct inject_poison_pl { @@ -629,9 +637,10 @@ static CXLRetCode cmd_media_clear_poison(const struct = cxl_cmd *cmd, size_t len_in, uint8_t *payload_out, size_t *len_out, - CXLDeviceState *cxl_dstate) + CXLCCI *cci) { - CXLType3Dev *ct3d =3D container_of(cxl_dstate, CXLType3Dev, cxl_dstate= ); + CXLType3Dev *ct3d =3D CXL_TYPE3(cci->d); + CXLDeviceState *cxl_dstate =3D &ct3d->cxl_dstate; CXLPoisonList *poison_list =3D &ct3d->poison_list; CXLType3Class *cvc =3D CXL_TYPE3_GET_CLASS(ct3d); struct clear_poison_pl { @@ -745,12 +754,13 @@ static const struct cxl_cmd cxl_cmd_set[256][256] =3D= { cmd_media_clear_poison, 72, 0 }, }; =20 -void cxl_process_mailbox(CXLDeviceState *cxl_dstate) +void cxl_process_mailbox(CXLCCI *cci) { uint16_t ret =3D CXL_MBOX_SUCCESS; const struct cxl_cmd *cxl_cmd; uint64_t status_reg =3D 0; opcode_handler h; + CXLDeviceState *cxl_dstate =3D &CXL_TYPE3(cci->d)->cxl_dstate; uint64_t command_reg =3D cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBO= X_CMD]; =20 uint8_t set =3D FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_S= ET); @@ -767,12 +777,12 @@ void cxl_process_mailbox(CXLDeviceState *cxl_dstate) pl_in_copy =3D g_memdup2(pl, len_in); /* Avoid stale data - including from earlier commands */ memset(pl, 0, CXL_MAILBOX_MAX_PAYLOAD_SIZE); - cxl_cmd =3D &cxl_dstate->cxl_cmd_set[set][cmd]; + cxl_cmd =3D &cci->cxl_cmd_set[set][cmd]; h =3D cxl_cmd->handler; if (h) { if (len_in =3D=3D cxl_cmd->in || cxl_cmd->in =3D=3D ~0) { - ret =3D (*h)(cxl_cmd, pl_in_copy, len_in, pl, &len_out, cxl_ds= tate); - assert(len_out <=3D cxl_dstate->payload_size); + ret =3D (*h)(cxl_cmd, pl, len_in, pl, &len_out, cci); + assert(len_out <=3D cci->payload_max); } else { ret =3D CXL_MBOX_INVALID_PAYLOAD_LENGTH; } @@ -798,20 +808,30 @@ void cxl_process_mailbox(CXLDeviceState *cxl_dstate) DOORBELL, 0); } =20 -void cxl_initialize_mailbox(CXLDeviceState *cxl_dstate) +void cxl_init_cci(CXLCCI *cci, size_t payload_max) { - cxl_dstate->cxl_cmd_set =3D cxl_cmd_set; + cci->payload_max =3D payload_max; for (int set =3D 0; set < 256; set++) { for (int cmd =3D 0; cmd < 256; cmd++) { - if (cxl_dstate->cxl_cmd_set[set][cmd].handler) { - const struct cxl_cmd *c =3D &cxl_dstate->cxl_cmd_set[set][= cmd]; + if (cci->cxl_cmd_set[set][cmd].handler) { + const struct cxl_cmd *c =3D &cci->cxl_cmd_set[set][cmd]; struct cel_log *log =3D - &cxl_dstate->cel_log[cxl_dstate->cel_size]; + &cci->cel_log[cci->cel_size]; =20 log->opcode =3D (set << 8) | cmd; log->effect =3D c->effect; - cxl_dstate->cel_size++; + cci->cel_size++; } } } } + +void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload= _max) +{ + cci->cxl_cmd_set =3D cxl_cmd_set; + cci->d =3D d; + + /* No separation for PCI MB as protocol handled in PCI device */ + cci->intf =3D d; + cxl_init_cci(cci, payload_max); +} diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 18ad853f5b..0529745786 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -716,7 +716,8 @@ static void ct3_realize(PCIDevice *pci_dev, Error **err= p) pci_dev, CXL_COMPONENT_REG_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, mr); =20 - cxl_device_register_block_init(OBJECT(pci_dev), &ct3d->cxl_dstate); + cxl_device_register_block_init(OBJECT(pci_dev), &ct3d->cxl_dstate, + &ct3d->cci); pci_register_bar(pci_dev, CXL_DEVICE_REG_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, @@ -922,7 +923,7 @@ static void ct3d_reset(DeviceState *dev) uint32_t *write_msk =3D ct3d->cxl_cstate.crb.cache_mem_regs_write_mask; =20 cxl_component_register_init_common(reg_state, write_msk, CXL2_TYPE3_DE= VICE); - cxl_device_register_init_common(&ct3d->cxl_dstate); + cxl_device_register_init_t3(ct3d); } =20 static Property ct3_props[] =3D { --=20 MST