From nobody Mon Feb 9 08:33:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660405528897350.2190103421906; Sat, 13 Aug 2022 08:45:28 -0700 (PDT) Received: from localhost ([::1]:50680 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtKJ-0007bj-Pw for importer@patchew.org; Sat, 13 Aug 2022 11:45:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9r-0000D2-Om; Sat, 13 Aug 2022 11:34:40 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:28308) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9p-0006JE-HA; Sat, 13 Aug 2022 11:34:39 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 64716748196; Sat, 13 Aug 2022 17:34:32 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 3B12D748190; Sat, 13 Aug 2022 17:34:32 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 05/22] ppc/ppc405: QOM'ify GPIO MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:32 +0200 (CEST) X-Spam-Probability: 11% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660405529076100001 From: C=C3=A9dric Le Goater The GPIO controller is currently modeled as a simple SysBus device with a unique memory region. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 21 +++++++++++++++++++ hw/ppc/ppc405_uc.c | 50 ++++++++++++++++++++++----------------------- hw/ppc/trace-events | 1 - 3 files changed, 45 insertions(+), 27 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index a5b493d3e7..21f6cb3585 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,6 +63,26 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; =20 +/* GPIO */ +#define TYPE_PPC405_GPIO "ppc405-gpio" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO); +struct Ppc405GpioState { + SysBusDevice parent_obj; + + MemoryRegion io; + uint32_t or; + uint32_t tcr; + uint32_t osrh; + uint32_t osrl; + uint32_t tsrh; + uint32_t tsrl; + uint32_t odr; + uint32_t ir; + uint32_t rr1; + uint32_t isr1h; + uint32_t isr1l; +}; + /* On Chip Memory */ #define TYPE_PPC405_OCM "ppc405-ocm" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM); @@ -152,6 +172,7 @@ struct Ppc405SoCState { Ppc405CpcState cpc; Ppc405GptState gpt; Ppc405OcmState ocm; + Ppc405GpioState gpio; }; =20 /* PowerPC 405 core */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 2282cfcd18..7ed3cf7149 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -714,22 +714,6 @@ static void ppc405_dma_init(CPUPPCState *env, qemu_irq= irqs[4]) =20 /*************************************************************************= ****/ /* GPIO */ -typedef struct ppc405_gpio_t ppc405_gpio_t; -struct ppc405_gpio_t { - MemoryRegion io; - uint32_t or; - uint32_t tcr; - uint32_t osrh; - uint32_t osrl; - uint32_t tsrh; - uint32_t tsrl; - uint32_t odr; - uint32_t ir; - uint32_t rr1; - uint32_t isr1h; - uint32_t isr1l; -}; - static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) { trace_ppc405_gpio_read(addr, size); @@ -748,20 +732,22 @@ static const MemoryRegionOps ppc405_gpio_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -static void ppc405_gpio_reset (void *opaque) +static void ppc405_gpio_realize(DeviceState *dev, Error **errp) { + Ppc405GpioState *s =3D PPC405_GPIO(dev); + + memory_region_init_io(&s->io, OBJECT(s), &ppc405_gpio_ops, s, "gpio", + 0x38); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io); } =20 -static void ppc405_gpio_init(hwaddr base) +static void ppc405_gpio_class_init(ObjectClass *oc, void *data) { - ppc405_gpio_t *gpio; - - trace_ppc405_gpio_init(base); + DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - gpio =3D g_new0(ppc405_gpio_t, 1); - memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio",= 0x038); - memory_region_add_subregion(get_system_memory(), base, &gpio->io); - qemu_register_reset(&ppc405_gpio_reset, gpio); + dc->realize =3D ppc405_gpio_realize; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; } =20 /*************************************************************************= ****/ @@ -1411,6 +1397,8 @@ static void ppc405_soc_instance_init(Object *obj) object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT); =20 object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM); + + object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO); } =20 static void ppc405_reset(void *opaque) @@ -1489,8 +1477,13 @@ static void ppc405_soc_realize(DeviceState *dev, Err= or **errp) /* I2C controller */ sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, qdev_get_gpio_in(s->uic, 2)); + /* GPIO */ - ppc405_gpio_init(0xef600700); + sbd =3D SYS_BUS_DEVICE(&s->gpio); + if (!sysbus_realize(sbd, errp)) { + return; + } + sysbus_mmio_map(sbd, 0, 0xef600700); =20 /* Serial ports */ if (serial_hd(0) !=3D NULL) { @@ -1552,6 +1545,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { + .name =3D TYPE_PPC405_GPIO, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Ppc405GpioState), + .class_init =3D ppc405_gpio_class_init, + }, { .name =3D TYPE_PPC405_OCM, .parent =3D TYPE_PPC4xx_DCR_DEVICE, .instance_size =3D sizeof(Ppc405OcmState), diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index adb4500888..66fbf0e035 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -154,7 +154,6 @@ opba_init(uint64_t addr) "offet 0x%" PRIx64 =20 ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d" ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" P= RIx64 " size %d =3D 0x%" PRIx64 -ppc405_gpio_init(uint64_t addr) "offet 0x%" PRIx64 =20 ocm_update_mappings(uint32_t isarc, uint32_t isacntl, uint32_t dsarc, uint= 32_t dsacntl, uint32_t ocm_isarc, uint32_t ocm_isacntl, uint32_t ocm_dsarc,= uint32_t ocm_dsacntl) "OCM update ISA 0x%08" PRIx32 " 0x%08" PRIx32 " (0x%= 08" PRIx32" 0x%08" PRIx32 ") DSA 0x%08" PRIx32 " 0x%08" PRIx32" (0x%08" PRI= x32 " 0x%08" PRIx32 ")" ocm_map(const char* prefix, uint32_t isarc) "OCM map %s 0x%08" PRIx32 --=20 2.30.4