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Sat, 07 Mar 2026 23:19:23 -0800 (PST) From: Chao Liu To: Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Fabiano Rosas , Laurent Vivier Cc: tangtao1634@phytium.com.cn, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 09/28] target/riscv: track the exact watchpoint trigger hit Date: Sun, 8 Mar 2026 15:17:12 +0800 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1342; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-dy1-x1342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772954461717154100 Content-Type: text/plain; charset="utf-8" Extend trigger-hit tracking to CPU watchpoints so load and store triggers preserve the exact matching trigger index across exception delivery. This simplifies the watchpoint hit path for the same reason as the breakpoint case: the trigger programming code has already expanded the load/store bits, size, and address into the concrete QEMU watchpoint object stored in env->cpu_watchpoint[i]. When QEMU reports a watchpoint hit, matching that object back to the trigger slot is enough; there is no need to repeat the address and access-type comparisons in the debug exception handler. The remaining dynamic privilege and textra conditions are still revalidated before the trigger action is taken. This gives watchpoint-based debug entry the same precise trigger information that breakpoint triggers now carry in CPU state. Signed-off-by: Chao Liu --- target/riscv/debug.c | 103 +++++++++++++++++-------------------------- 1 file changed, 40 insertions(+), 63 deletions(-) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index ef2fafcbef..eb03f306b1 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -586,6 +586,29 @@ static int riscv_debug_find_breakpoint_trigger(CPUStat= e *cs) return -1; } =20 +static int riscv_debug_find_watchpoint_trigger(CPUState *cs, CPUWatchpoint= *wp) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + for (int i =3D 0; i < RV_MAX_TRIGGERS; i++) { + int trigger_type =3D get_trigger_type(env, i); + + if (!trigger_common_match(env, trigger_type, i)) { + continue; + } + + if (wp !=3D env->cpu_watchpoint[i]) { + continue; + } + + env->badaddr =3D wp->hitaddr; + return i; + } + + return -1; +} + static void type2_reg_write(CPURISCVState *env, target_ulong index, int tdata_index, target_ulong val) { @@ -1012,17 +1035,21 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) return; } =20 - if (cs->watchpoint_hit) { - if (cs->watchpoint_hit->flags & BP_CPU) { - do_trigger_action(env, DBG_ACTION_BP); - } - } else { - if (hit < 0) { - hit =3D riscv_debug_find_breakpoint_trigger(cs); - } - if (hit >=3D 0) { - do_trigger_action(env, hit); - } + if (hit < 0 && cs->watchpoint_hit && (cs->watchpoint_hit->flags & BP_C= PU)) { + hit =3D riscv_debug_find_watchpoint_trigger(cs, cs->watchpoint_hit= ); + } + + if (cs->watchpoint_hit && + (hit >=3D 0 || (cs->watchpoint_hit->flags & BP_CPU))) { + cs->watchpoint_hit =3D NULL; + } + + if (hit < 0) { + hit =3D riscv_debug_find_breakpoint_trigger(cs); + } + + if (hit >=3D 0) { + do_trigger_action(env, hit); } } =20 @@ -1039,59 +1066,9 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, = CPUWatchpoint *wp) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - target_ulong ctrl; - target_ulong addr; - int trigger_type; - int flags; - int i; - - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { - trigger_type =3D get_trigger_type(env, i); - - if (!trigger_common_match(env, trigger_type, i)) { - continue; - } - - switch (trigger_type) { - case TRIGGER_TYPE_AD_MATCH: - ctrl =3D env->tdata1[i]; - addr =3D env->tdata2[i]; - flags =3D 0; - - if (ctrl & TYPE2_LOAD) { - flags |=3D BP_MEM_READ; - } - if (ctrl & TYPE2_STORE) { - flags |=3D BP_MEM_WRITE; - } =20 - if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { - return true; - } - break; - case TRIGGER_TYPE_AD_MATCH6: - ctrl =3D env->tdata1[i]; - addr =3D env->tdata2[i]; - flags =3D 0; - - if (ctrl & TYPE6_LOAD) { - flags |=3D BP_MEM_READ; - } - if (ctrl & TYPE6_STORE) { - flags |=3D BP_MEM_WRITE; - } - - if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { - return true; - } - break; - default: - /* other trigger types are not supported */ - break; - } - } - - return false; + env->pending_trigger_hit =3D riscv_debug_find_watchpoint_trigger(cs, w= p); + return env->pending_trigger_hit >=3D 0; } =20 void riscv_trigger_realize(CPURISCVState *env) --=20 2.53.0