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IronPort-SDR: 008hFMgMIf2kAN/8JIxT9aQ83gAIygh9TmzoAXIYwuKwf+pKMeLvHeriJsxMit9VsCMHMms28N erupZOJWRGbL5gjIXSw/+4mWb80Hg8BnFH4w6tlPpzqfGQWyidVn0d50YFWHrQnvo8+Qv1MbAl 4GoD5FBrHZf/hcdvNRpvgQHL8Zai8QkcpBP6rHGJlBIDG0UPQaHn4itP2761jO+Si2bvxOT6+z pE7Rwd0qmoC0u4MbY21AyF+RvHRVEkgXDznkvZltX3/1MOJ0Fu5cA+nsNiSo/3werZhBcS01kD maE= X-IronPort-AV: E=Sophos;i="5.81,300,1610380800"; d="scan'208";a="168175379" IronPort-SDR: HL6HH8zOIbHTkovU3gkhVkzKAZByPM9y7ZYwZJl0gwGwKZ5Zazr4rirCpAlHnXaWShg2/td8J2 7FtISGAWw+FPx1SrZmdBFxgLcCGI2kyYbLLVJUBYO3jsEk24jRv3w3HAxrQlbMYN4jJaK0wFI8 SlSXb3KCuqAKiRA3mQZQXGl11n0eZndsLN1MidZYvOmqKhrbB7bDQzkw4xuxZkzzuiZWR4VNuV hzgDnqrnyylOQxFQYMF/cFbsITq/iM2jASBlyT9DT+ff7p4XdnVRPD3AgrQqiG7cQkwpyzYppy Ej9Y0Q6coJUlXnSm8T4nIxL7 IronPort-SDR: sfsmzfWzFrxF6GuNsUiNABR2jwpkcKqW0bXp9fypVDbWP1mHcBUeFKPXFyyaSJCzNWFH985cWa h2UM/31SQ3yR6DsTHB4R71/xOO7bjs+QHlICOjbNwkc5sPzI8Zdpda/01pTS/xeHcYt5N4Rm90 9HWWZ8TmamyvRHqIMgHO4N1Uf8cNjL1vgyJN1oIj66LtpjwNxO2SaZVYGaTK7Hmx81ImVTHoa8 zkkGVL4QNtx62tLvqkx3nbO7dvKSe6OLMovryFdED0gemtaS9ZDHHYefQiOkl7Z2KDFMF3L7lS bIw= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro Date: Fri, 2 Apr 2021 16:02:40 -0400 Message-Id: X-Mailer: git-send-email 2.31.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=7197bd837=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 11 ----------- target/riscv/cpu_helper.c | 30 +++++++++++++++++++++++------- target/riscv/csr.c | 33 ++++++++++++++++++++++++--------- target/riscv/monitor.c | 22 +++++++++++++++++----- 4 files changed, 64 insertions(+), 32 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index dd643d0f63..6a816ce9c2 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -452,17 +452,6 @@ #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL =20 -#if defined(TARGET_RISCV32) -#define SATP_MODE SATP32_MODE -#define SATP_ASID SATP32_ASID -#define SATP_PPN SATP32_PPN -#endif -#if defined(TARGET_RISCV64) -#define SATP_MODE SATP64_MODE -#define SATP_ASID SATP64_ASID -#define SATP_PPN SATP64_PPN -#endif - /* VM modes (mstatus.vm) privileged ISA 1.9.1 */ #define VM_1_09_MBARE 0 #define VM_1_09_MBB 1 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6446af5de0..7ae9352d80 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -403,11 +403,21 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, =20 if (first_stage =3D=3D true) { if (use_background) { - base =3D (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT; - vm =3D get_field(env->vsatp, SATP_MODE); + if (riscv_cpu_is_32bit(env)) { + base =3D (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSH= IFT; + vm =3D get_field(env->vsatp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSH= IFT; + vm =3D get_field(env->vsatp, SATP64_MODE); + } } else { - base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; - vm =3D get_field(env->satp, SATP_MODE); + if (riscv_cpu_is_32bit(env)) { + base =3D (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHI= FT; + vm =3D get_field(env->satp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHI= FT; + vm =3D get_field(env->satp, SATP64_MODE); + } } widened =3D 0; } else { @@ -622,9 +632,15 @@ static void raise_mmu_exception(CPURISCVState *env, ta= rget_ulong address, CPUState *cs =3D env_cpu(env); int page_fault_exceptions; if (first_stage) { - page_fault_exceptions =3D - get_field(env->satp, SATP_MODE) !=3D VM_1_10_MBARE && - !pmp_violation; + if (riscv_cpu_is_32bit(env)) { + page_fault_exceptions =3D + get_field(env->satp, SATP32_MODE) !=3D VM_1_10_MBARE && + !pmp_violation; + } else { + page_fault_exceptions =3D + get_field(env->satp, SATP64_MODE) !=3D VM_1_10_MBARE && + !pmp_violation; + } } else { if (riscv_cpu_is_32bit(env)) { page_fault_exceptions =3D diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6052b2d6e9..b0ebaa029e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -930,16 +930,31 @@ static int write_satp(CPURISCVState *env, int csrno, = target_ulong val) if (!riscv_feature(env, RISCV_FEATURE_MMU)) { return 0; } - if (validate_vm(env, get_field(val, SATP_MODE)) && - ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) - { - if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { - return -RISCV_EXCP_ILLEGAL_INST; - } else { - if ((val ^ env->satp) & SATP_ASID) { - tlb_flush(env_cpu(env)); + if (riscv_cpu_is_32bit(env)) { + if (validate_vm(env, get_field(val, SATP32_MODE)) && + ((val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN))) + { + if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_= TVM)) { + return -RISCV_EXCP_ILLEGAL_INST; + } else { + if ((val ^ env->satp) & SATP32_ASID) { + tlb_flush(env_cpu(env)); + } + env->satp =3D val; + } + } + } else { + if (validate_vm(env, get_field(val, SATP64_MODE)) && + ((val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN))) + { + if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_= TVM)) { + return -RISCV_EXCP_ILLEGAL_INST; + } else { + if ((val ^ env->satp) & SATP64_ASID) { + tlb_flush(env_cpu(env)); + } + env->satp =3D val; } - env->satp =3D val; } } return 0; diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index e51188f919..f7e6ea72b3 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -150,9 +150,14 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *= env) target_ulong last_size; int last_attr; =20 - base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; + if (riscv_cpu_is_32bit(env)) { + base =3D (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; + vm =3D get_field(env->satp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; + vm =3D get_field(env->satp, SATP64_MODE); + } =20 - vm =3D get_field(env->satp, SATP_MODE); switch (vm) { case VM_1_10_SV32: levels =3D 2; @@ -215,9 +220,16 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) return; } =20 - if (!(env->satp & SATP_MODE)) { - monitor_printf(mon, "No translation or protection\n"); - return; + if (riscv_cpu_is_32bit(env)) { + if (!(env->satp & SATP32_MODE)) { + monitor_printf(mon, "No translation or protection\n"); + return; + } + } else { + if (!(env->satp & SATP64_MODE)) { + monitor_printf(mon, "No translation or protection\n"); + return; + } } =20 mem_info_svxx(mon, env); --=20 2.31.0