From nobody Mon Feb 9 10:51:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1609637347; cv=none; d=zohomail.com; s=zohoarc; b=dt2XEBDbH9mKi/8QGmAq7Oqf51ltiDNgVeXHBPtIEdsFmUABBxWJ1RuA0kpR4VEeux3HWU04WEtCzENhaoTF56/s9jT/0WFzzJ4Cjfq+dTM7kgoQtNyAynZ8s8E8RFtbcQYNNGiFBW9FZ0WUC+QreVEZrmpvkJPph2PAwfN8sU0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609637347; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=4PdeBlvNfS3L6h0bHqSfZkTHfHTqZqQfUOocn58qfZ8=; b=ewCu091Qm7lVvdyhlSMKpa/swoV1cT43V93CvQGXyfx8KhbyWCQkGD9MTk5d+dUvMJERQPP3ogSXZ9z0DBpT7y7z1cbcNIc+YbskH7FFZvCIkgxHI41853BHFYbPi7J1Gc7RXTCikxxClibjDffPDvjJvLcdCVAYCAOECThMmNY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1609637347750433.9537914569099; Sat, 2 Jan 2021 17:29:07 -0800 (PST) Received: from localhost ([::1]:37060 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kvsCg-0000fR-OB for importer@patchew.org; Sat, 02 Jan 2021 20:29:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41532) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kvs8a-0004mi-LD; Sat, 02 Jan 2021 20:24:52 -0500 Received: from zero.eik.bme.hu ([152.66.115.2]:20376) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kvs8X-0000t8-7j; Sat, 02 Jan 2021 20:24:52 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 402B374760E; Sun, 3 Jan 2021 02:24:44 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id B3664747603; Sun, 3 Jan 2021 02:24:43 +0100 (CET) Message-Id: In-Reply-To: References: Subject: [PATCH v3 3/5] ppc440_pcix: Improve comment for IRQ mapping Date: Sun, 03 Jan 2021 02:09:33 +0100 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , f4bug@amsat.org, Guenter Roeck , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: BALATON Zoltan From: BALATON Zoltan via Content-Type: text/plain; charset="utf-8" The code mapping all PCI interrupts to a single CPU IRQ works but is not trivial so document it in a comment. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440_pcix.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c index ee952314c8..eb1290ffc8 100644 --- a/hw/ppc/ppc440_pcix.c +++ b/hw/ppc/ppc440_pcix.c @@ -415,8 +415,15 @@ static void ppc440_pcix_reset(DeviceState *dev) s->sts =3D 0; } =20 -/* All pins from each slot are tied to a single board IRQ. - * This may need further refactoring for other boards. */ +/* + * All four IRQ[ABCD] pins from all slots are tied to a single board + * IRQ, so our mapping function here maps everything to IRQ 0. + * The code in pci_change_irq_level() tracks the number of times + * the mapped IRQ is asserted and deasserted, so if multiple devices + * assert an IRQ at the same time the behaviour is correct. + * + * This may need further refactoring for boards that use multiple IRQ line= s. + */ static int ppc440_pcix_map_irq(PCIDevice *pci_dev, int irq_num) { trace_ppc440_pcix_map_irq(pci_dev->devfn, irq_num, 0); --=20 2.21.3