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x=1602113809; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R2nVtvjRrWvX24XxkUnh1oGyAnhgooAojvHlsrtud9s=; b=ldXPgJv3e/xif27u1itUm8NNcQ6T78cjeukZnN6k1Euu1QDVJCyka/7z z+23/QwvEU4l/wLCj9FB6uuN/HyWgejPj0h3cK+w4StJFh2ZhKzLRU4x1 v0JWOGVxeHT6DFb0eJ6+GivUHBiElGe4gZHMaCVpYcdLuukS6d3+Fcsdo SbuwBXluL0YKY75IzTE89uivq5879VWSuHvV372nBaOAVoFgxnkUTQvu6 F1aVMi6u0hjYeV/qOPhnbx+yM9JIwxGcTiarIaudg4jeM1EHOXfiTQEpe wrM/gkrDLxvpiIgC+o36ABh0q0botbrAQ5JIAwjc+wMjjre9LT/FtawLn A==; IronPort-SDR: nchJAm6MnHfj8WiV5M5KLxLyF65KRKQXwWFL3B8BbmROtZ6njuaLeLgVTI25qldXANa4RVc8Ft lAq8GiiFeB5NxwCGtWuDoSpiC9YKe8LEcNfzACD+FEQGPtvRrByDTXcvSDxzPRHGXb12XP7A1t QtBpSvGfURDSuwA16+GYNma1OmKZiGBunyUKbUCg03NErKNU5WOBS0r49JLcjf4o71HsBBIgWv k7/lFfAKU9Ss5zScXnqoICOb6zNdQBLY8fsLLqdzOR/Wf9+xD/pFzDdaIPZ1HAbcTFkVQ6Dg3X PKc= X-IronPort-AV: E=Sophos;i="5.67,273,1566835200"; d="scan'208";a="227059688" IronPort-SDR: DTKWztKd4F/qmR6XuFxQ6jaR4BQ1rqx2wyEljy2Br54L5ruJEyI8VTxLVH45hdnlbbvUkOYdvv xf8Zd23ENXKv4uHF0HFg2tpMHE7o9JQKQus/6HSIRugMwqwKnG0dCPslJ7fdnPyUCPgrMn+eQ3 3QDAcgHbvTLN5anBp+ivIHzXaVM73vnyg7835RTe3gjlxdU2eE5OTx0TlVxT11Gk9zkROAyWsQ HO/zpmoX3TO+UACZLc8ozS9sdpNssnRAOdUP5I3qCly/by/hFvAfxPCJ4kjkwmD+3GI48FPuOw BRaY1T8tYGazLa6Miq5Fz4so IronPort-SDR: ECxz0I8bL62xCodACoQwtBjhYuZ5XYq8Ikn5vAKiK6EfxwoM6IYDvFviOM2xtwwbinCEiuvnvI dXT7Ap3pwkxSYEKX5hqd6iOs0BVvk2oT3ASwUdXTccISrMHOLg6BMO5egACTcEJ19lwjZuUMTR HOR+Mk0md0srXE3xVKRT71JUu6KHvw/4oQzKDtHEonJGPmM2cS7xyYyw0wxw88EoO9n53pEKV2 h34RfBqKiBUC+Q5tTzUC4l2oJw93Q44jX8jQuHMrs0PowaV+lR+3gZFcflbY9AhlVJ3g43i6/m pLM= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 3/7] riscv/sifive_u: Manually define the machine Date: Tue, 8 Oct 2019 16:32:14 -0700 Message-Id: X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 68.232.141.245 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Instead of using the DEFINE_MACHINE() macro to define the machine let's do it manually. This allows us to specify machine properties. This patch is no functional change. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/riscv/sifive_u.c | 44 ++++++++++++++++++++++++++----------- include/hw/riscv/sifive_u.h | 7 +++++- 2 files changed, 37 insertions(+), 14 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index bc0e01242b..f5741e9a38 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -310,8 +310,7 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, static void riscv_sifive_u_init(MachineState *machine) { const struct MemmapEntry *memmap =3D sifive_u_memmap; - - SiFiveUState *s =3D g_new0(SiFiveUState, 1); + SiFiveUState *s =3D RISCV_U_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *flash0 =3D g_new(MemoryRegion, 1); @@ -433,6 +432,10 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_CADENCE_GEM); } =20 +static void riscv_sifive_u_machine_instance_init(Object *obj) +{ +} + static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); @@ -546,17 +549,6 @@ static void riscv_sifive_u_soc_realize(DeviceState *de= v, Error **errp) memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); } =20 -static void riscv_sifive_u_machine_init(MachineClass *mc) -{ - mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; - mc->init =3D riscv_sifive_u_init; - mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; - mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; - mc->default_cpus =3D mc->min_cpus; -} - -DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) - static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -580,3 +572,29 @@ static void riscv_sifive_u_soc_register_types(void) } =20 type_init(riscv_sifive_u_soc_register_types) + +static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; + mc->init =3D riscv_sifive_u_init; + mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; + mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; + mc->default_cpus =3D mc->min_cpus; +} + +static const TypeInfo riscv_sifive_u_machine_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("sifive_u"), + .parent =3D TYPE_MACHINE, + .class_init =3D riscv_sifive_u_machine_class_init, + .instance_init =3D riscv_sifive_u_machine_instance_init, + .instance_size =3D sizeof(SiFiveUState), +}; + +static void riscv_sifive_u_machine_init_register_types(void) +{ + type_register_static(&riscv_sifive_u_machine_typeinfo); +} + +type_init(riscv_sifive_u_machine_init_register_types) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 2a08e2a5db..a921079fbe 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -44,12 +44,17 @@ typedef struct SiFiveUSoCState { CadenceGEMState gem; } SiFiveUSoCState; =20 +#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") +#define RISCV_U_MACHINE(obj) \ + OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE) + typedef struct SiFiveUState { /*< private >*/ - SysBusDevice parent_obj; + MachineState parent_obj; =20 /*< public >*/ SiFiveUSoCState soc; + void *fdt; int fdt_size; } SiFiveUState; --=20 2.23.0