From nobody Mon Nov 25 11:15:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1715556879651314.9127361338127; Sun, 12 May 2024 16:34:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6IcW-0001qy-FK; Sun, 12 May 2024 19:28:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6IcM-0001fQ-5P; Sun, 12 May 2024 19:28:37 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6IcI-0000Nr-H5; Sun, 12 May 2024 19:28:32 -0400 Received: from zero.eik.bme.hu (localhost [127.0.0.1]) by zero.eik.bme.hu (Postfix) with ESMTP id 067944E6775; Mon, 13 May 2024 01:28:09 +0200 (CEST) Received: from zero.eik.bme.hu ([127.0.0.1]) by zero.eik.bme.hu (zero.eik.bme.hu [127.0.0.1]) (amavisd-new, port 10028) with ESMTP id AiXwUBwScgnN; Mon, 13 May 2024 01:28:07 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 16BE84E65C8; Mon, 13 May 2024 01:28:07 +0200 (CEST) X-Virus-Scanned: amavisd-new at eik.bme.hu Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v7 33/61] target/ppc: Add a function to check for page protection bit MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza Date: Mon, 13 May 2024 01:28:07 +0200 (CEST) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1715556881437100011 Content-Type: text/plain; charset="utf-8" Checking if a page protection bit is set for a given access type is a common operation. Add a function to avoid repeating the same check at multiple places. As this relies on access type and page protection bit values having certain relation also add an assert to ensure that this assumption holds. Signed-off-by: BALATON Zoltan --- target/ppc/cpu_init.c | 5 +++++ target/ppc/internal.h | 23 +++++------------------ target/ppc/mmu-hash32.c | 6 +++--- target/ppc/mmu-hash64.c | 2 +- target/ppc/mmu-radix64.c | 2 +- target/ppc/mmu_common.c | 26 +++++++++++++------------- 6 files changed, 28 insertions(+), 36 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 92c71b2a09..d3b92d9f0e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7388,6 +7388,11 @@ static void ppc_cpu_class_init(ObjectClass *oc, void= *data) #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &ppc_sysemu_ops; INTERRUPT_STATS_PROVIDER_CLASS(oc)->get_statistics =3D ppc_get_irq_sta= ts; + + /* check_prot_access_type relies on MMU access and PAGE bits relations= */ + qemu_build_assert(MMU_DATA_LOAD =3D=3D 0 && MMU_DATA_STORE =3D=3D 1 && + MMU_INST_FETCH =3D=3D 2 && PAGE_READ =3D=3D 1 && + PAGE_WRITE =3D=3D 2 && PAGE_EXEC =3D=3D 4); #endif =20 cc->gdb_num_core_regs =3D 71; diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 4a90dd2584..20fb2ec593 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -234,27 +234,14 @@ void destroy_ppc_opcodes(PowerPCCPU *cpu); void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *ppc); const gchar *ppc_gdb_arch_name(CPUState *cs); =20 -/** - * prot_for_access_type: - * @access_type: Access type - * - * Return the protection bit required for the given access type. - */ -static inline int prot_for_access_type(MMUAccessType access_type) +#ifndef CONFIG_USER_ONLY + +/* Check if permission bit required for the access_type is set in prot */ +static inline int check_prot_access_type(int prot, MMUAccessType access_ty= pe) { - switch (access_type) { - case MMU_INST_FETCH: - return PAGE_EXEC; - case MMU_DATA_LOAD: - return PAGE_READ; - case MMU_DATA_STORE: - return PAGE_WRITE; - } - g_assert_not_reached(); + return prot & (1 << access_type); } =20 -#ifndef CONFIG_USER_ONLY - /* PowerPC MMU emulation */ =20 bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 3abaf16e78..1e8f1df0f0 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -252,7 +252,7 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, ta= rget_ulong sr, } =20 *prot =3D key ? PAGE_READ | PAGE_WRITE : PAGE_READ; - if (*prot & prot_for_access_type(access_type)) { + if (check_prot_access_type(*prot, access_type)) { *raddr =3D eaddr; return true; } @@ -403,7 +403,7 @@ bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMU= AccessType access_type, if (env->nb_BATs !=3D 0) { raddr =3D ppc_hash32_bat_lookup(cpu, eaddr, access_type, protp, mm= u_idx); if (raddr !=3D -1) { - if (prot_for_access_type(access_type) & ~*protp) { + if (!check_prot_access_type(*protp, access_type)) { if (guest_visible) { if (access_type =3D=3D MMU_INST_FETCH) { cs->exception_index =3D POWERPC_EXCP_ISI; @@ -471,7 +471,7 @@ bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMU= AccessType access_type, =20 prot =3D ppc_hash32_pte_prot(mmu_idx, sr, pte); =20 - if (prot_for_access_type(access_type) & ~prot) { + if (!check_prot_access_type(prot, access_type)) { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); if (guest_visible) { diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 0966422a55..d9626f6aab 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1097,7 +1097,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, M= MUAccessType access_type, amr_prot =3D ppc_hash64_amr_prot(cpu, pte); prot =3D exec_prot & pp_prot & amr_prot; =20 - need_prot =3D prot_for_access_type(access_type); + need_prot =3D check_prot_access_type(PAGE_RWX, access_type); if (need_prot & ~prot) { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 395ce3b782..2c5ade5cea 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -209,7 +209,7 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMU= AccessType access_type, } =20 /* Check if requested access type is allowed */ - if (prot_for_access_type(access_type) & ~*prot) { + if (!check_prot_access_type(*prot, access_type)) { /* Page Protected for that Access */ *fault_cause |=3D access_type =3D=3D MMU_INST_FETCH ? SRR1_NOEXEC_= GUARD : DSISR_PROTFAULT; diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 69f98b7d0e..6746a8ff6b 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -114,11 +114,6 @@ static int pp_check(int key, int pp, int nx) return access; } =20 -static int check_prot(int prot, MMUAccessType access_type) -{ - return prot & prot_for_access_type(access_type) ? 0 : -2; -} - int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr, int way, int is_code) { @@ -165,13 +160,14 @@ static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, targe= t_ulong pte0, /* Keep the matching PTE information */ ctx->raddr =3D pte1; ctx->prot =3D access; - ret =3D check_prot(ctx->prot, access_type); - if (ret =3D=3D 0) { + if (check_prot_access_type(ctx->prot, access_type)) { /* Access granted */ qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); + ret =3D 0; } else { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); + ret =3D -2; } } } @@ -339,12 +335,14 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_= t *ctx, (virtual & 0x0001F000); /* Compute access rights */ ctx->prot =3D prot; - ret =3D check_prot(ctx->prot, access_type); - if (ret =3D=3D 0) { + if (check_prot_access_type(ctx->prot, access_type)) { qemu_log_mask(CPU_LOG_MMU, "BAT %d match: r " HWADDR_F= MT_plx " prot=3D%c%c\n", i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', ctx->prot & PAGE_WRITE ? 'W' : '-'); + ret =3D 0; + } else { + ret =3D -2; } break; } @@ -561,9 +559,11 @@ static int mmu40x_get_physical_address(CPUPPCState *en= v, hwaddr *raddr, check_perms: /* Check from TLB entry */ *prot =3D tlb->prot; - ret =3D check_prot(*prot, access_type); - if (ret =3D=3D -2) { + if (check_prot_access_type(*prot, access_type)) { + ret =3D 0; + } else { env->spr[SPR_40x_ESR] =3D 0; + ret =3D -2; } break; } @@ -621,7 +621,7 @@ static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_= tlb_t *tlb, } else { *prot =3D (tlb->prot >> 4) & 0xF; } - if (*prot & prot_for_access_type(access_type)) { + if (check_prot_access_type(*prot, access_type)) { qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__); return 0; } @@ -823,7 +823,7 @@ found_tlb: *prot |=3D PAGE_EXEC; } } - if (*prot & prot_for_access_type(access_type)) { + if (check_prot_access_type(*prot, access_type)) { qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__); return 0; } --=20 2.30.9