From nobody Mon Feb 9 20:36:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686870298309264.3859122280387; Thu, 15 Jun 2023 16:04:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9w01-0002Wm-JI; Thu, 15 Jun 2023 19:03:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9vzz-0002Qk-QR; Thu, 15 Jun 2023 19:03:27 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9vzy-0007jf-4D; Thu, 15 Jun 2023 19:03:27 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 202C3748A5B; Fri, 16 Jun 2023 01:03:19 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 01FFB748A56; Fri, 16 Jun 2023 01:03:19 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v3 09/14] target/ppc: Move patching nip from exception handler to helper_scv MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Greg Kurz , Daniel Henrique Barboza , Nicholas Piggin Date: Fri, 16 Jun 2023 01:03:19 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686870299380100003 Content-Type: text/plain; charset="utf-8" From: Nicholas Piggin Unlike sc, for scv a facility unavailable interrupt must be generated if FSCR[SCV]=3D0 so we can't raise the exception with nip set to next instruction but we can move advancing nip if the FSCR check passes to helper_scv so the exception handler does not need to change it. [balaton: added commit message] Signed-off-by: BALATON Zoltan --- This needs SoB from Nick target/ppc/excp_helper.c | 2 +- target/ppc/translate.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 903216c2a6..ef363b0285 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1304,7 +1304,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception = */ lev =3D env->error_code; dump_syscall(env); - env->nip +=3D 4; new_msr |=3D env->msr & ((target_ulong)1 << MSR_EE); new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); =20 @@ -2410,6 +2409,7 @@ void helper_ppc_maybe_interrupt(CPUPPCState *env) void helper_scv(CPUPPCState *env, uint32_t lev) { if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) { + env->nip +=3D 4; raise_exception_err(env, POWERPC_EXCP_SYSCALL_VECTORED, lev); } else { raise_exception_err(env, POWERPC_EXCP_FU, FSCR_IC_SCV); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4260d3d66f..0360a17fb3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4433,7 +4433,11 @@ static void gen_scv(DisasContext *ctx) { uint32_t lev =3D (ctx->opcode >> 5) & 0x7F; =20 - /* Set the PC back to the faulting instruction. */ + /* + * Set the PC back to the scv instruction (unlike sc), because a facil= ity + * unavailable interrupt must be generated if FSCR[SCV]=3D0. The helper + * advances nip if the FSCR check passes. + */ gen_update_nip(ctx, ctx->cia); gen_helper_scv(cpu_env, tcg_constant_i32(lev)); =20 --=20 2.30.9