From nobody Sun Feb 8 11:07:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663157577435628.2312428123429; Wed, 14 Sep 2022 05:12:57 -0700 (PDT) Received: from localhost ([::1]:54212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYRGC-00045s-08 for importer@patchew.org; Wed, 14 Sep 2022 08:12:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42512) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYQex-0004K2-Em; Wed, 14 Sep 2022 07:34:27 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:42865) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYQev-0005Zw-DN; Wed, 14 Sep 2022 07:34:26 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id D260274637F; Wed, 14 Sep 2022 13:34:23 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 9296174632B; Wed, 14 Sep 2022 13:34:23 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v4 10/21] ppc440_sdram: Implement enable bit in the DDR2 SDRAM MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Wed, 14 Sep 2022 13:34:23 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663157578555100001 Content-Type: text/plain; charset="utf-8" To allow removing the do_init hack we need to improve the DDR2 SDRAM controller model to handle the enable/disable bit that it ignored so far. Signed-off-by: BALATON Zoltan --- v4: Add define for enable bit v2: replace 0x08000000 with BIT(27) hw/ppc/ppc440_uc.c | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 01184e717b..aa09534abb 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -23,6 +23,7 @@ #include "sysemu/reset.h" #include "ppc440.h" #include "qom/object.h" +#include "trace.h" =20 /*************************************************************************= ****/ /* L2 Cache as SRAM */ @@ -484,6 +485,7 @@ void ppc4xx_sdr_init(CPUPPCState *env) /* SDRAM controller */ typedef struct ppc440_sdram_t { uint32_t addr; + uint32_t mcopt2; int nbanks; Ppc4xxSdramBank bank[4]; } ppc440_sdram_t; @@ -581,12 +583,15 @@ static void sdram_set_bcr(ppc440_sdram_t *sdram, int = i, { if (sdram->bank[i].bcr & 1) { /* First unmap RAM if enabled */ + trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr), + sdram_size(sdram->bank[i].bcr)); sdram_bank_unmap(&sdram->bank[i]); } sdram->bank[i].bcr =3D bcr & 0xffe0ffc1; sdram->bank[i].base =3D sdram_base(bcr); sdram->bank[i].size =3D sdram_size(bcr); if (enabled && (bcr & 1)) { + trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr)); sdram_bank_map(&sdram->bank[i]); } } @@ -596,7 +601,7 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram) int i; =20 for (i =3D 0; i < sdram->nbanks; i++) { - if (sdram->bank[i].size !=3D 0) { + if (sdram->bank[i].size) { sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base, sdram->bank[i].size), 1); } else { @@ -605,6 +610,17 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram) } } =20 +static void sdram_unmap_bcr(ppc440_sdram_t *sdram) +{ + int i; + + for (i =3D 0; i < sdram->nbanks; i++) { + if (sdram->bank[i].size) { + sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0); + } + } +} + static uint32_t dcr_read_sdram(void *opaque, int dcrn) { ppc440_sdram_t *sdram =3D opaque; @@ -636,7 +652,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn) ret =3D 0x80000000; break; case 0x21: /* SDRAM_MCOPT2 */ - ret =3D 0x08000000; + ret =3D sdram->mcopt2; break; case 0x40: /* SDRAM_MB0CF */ ret =3D 0x00008001; @@ -658,6 +674,8 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn) return ret; } =20 +#define SDRAM_DDR2_MCOPT2_DCEN BIT(27) + static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val) { ppc440_sdram_t *sdram =3D opaque; @@ -680,6 +698,21 @@ static void dcr_write_sdram(void *opaque, int dcrn, ui= nt32_t val) switch (sdram->addr) { case 0x00: /* B0CR */ break; + case 0x21: /* SDRAM_MCOPT2 */ + if (!(sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) && + (val & SDRAM_DDR2_MCOPT2_DCEN)) { + trace_ppc4xx_sdram_enable("enable"); + /* validate all RAM mappings */ + sdram_map_bcr(sdram); + sdram->mcopt2 |=3D SDRAM_DDR2_MCOPT2_DCEN; + } else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) && + !(val & SDRAM_DDR2_MCOPT2_DCEN)) { + trace_ppc4xx_sdram_enable("disable"); + /* invalidate all RAM mappings */ + sdram_unmap_bcr(sdram); + sdram->mcopt2 &=3D ~SDRAM_DDR2_MCOPT2_DCEN; + } + break; default: break; } @@ -694,6 +727,7 @@ static void sdram_reset(void *opaque) ppc440_sdram_t *sdram =3D opaque; =20 sdram->addr =3D 0; + sdram->mcopt2 =3D SDRAM_DDR2_MCOPT2_DCEN; } =20 void ppc440_sdram_init(CPUPPCState *env, int nbanks, --=20 2.30.4